Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

20 files changed, 1957 insertions, 0 deletions

diff --git a/roms/u-boot/board/armltd/integrator/MAINTAINERS b/roms/u-boot/board/armltd/integrator/MAINTAINERS
new file mode 100644
index 000000000..8af765eae
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/MAINTAINERS
@@ -0,0 +1,14 @@
+INTEGRATOR BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	board/armltd/integrator/
+F:	include/configs/integratorcp.h
+F:	configs/integratorcp_cm1136_defconfig
+F:	include/configs/integratorap.h
+F:	configs/integratorap_cm720t_defconfig
+F:	configs/integratorap_cm920t_defconfig
+F:	configs/integratorcp_cm920t_defconfig
+F:	configs/integratorap_cm926ejs_defconfig
+F:	configs/integratorcp_cm926ejs_defconfig
+F:	configs/integratorap_cm946es_defconfig
+F:	configs/integratorcp_cm946es_defconfig
diff --git a/roms/u-boot/board/armltd/integrator/Makefile b/roms/u-boot/board/armltd/integrator/Makefile
new file mode 100644
index 000000000..8c906e3f0
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+
+obj-y	:= lowlevel_init.o
+
+obj-y	+= integrator.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += timer.o
diff --git a/roms/u-boot/board/armltd/integrator/README b/roms/u-boot/board/armltd/integrator/README
new file mode 100644
index 000000000..af9dcc1f4
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/README
@@ -0,0 +1,108 @@
+
+		U-Boot for ARM Integrator Development Platforms
+
+			Peter Pearse, ARM Ltd.
+			peter.pearse@arm.com
+			     www.arm.com
+
+Manuals available from :-
+http://www.arm.com/products/DevTools/Hardware_Platforms.html
+
+Overview :
+--------
+There are two Integrator variants - Integrator/AP and Integrator/CP.
+Each may be fitted with a variety of core modules (CMs).
+Each CM consists of a ARM processor core and associated hardware e.g
+	FPGA implementing various controllers and/or register
+	SSRAM
+	SDRAM
+	RAM controllers
+	clock generators etc.
+CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
+
+Boot Methods :
+------------
+Integrator platforms can be configured to use U-Boot in at least three ways :-
+a) Run ARM boot monitor, manually run U-Boot image from flash
+b) Run ARM boot monitor, automatically run U-Boot image from flash
+c) Run U-Boot image direct from flash.
+
+In cases a) and b) the ARM boot monitor will have configured the CM and mapped
+writeable memory to 0x00000000 in the Integrator address space.
+U-Boot has to carry out minimal configration before standard code is run.
+
+In case c) it may be necessary for U-Boot to perform CM dependent initialization.
+
+Configuring U-Boot :
+------------------
+	The makefile contains targets for Integrator platforms of both types
+fitted with all current variants of CM.
+
+	There are also targets independent of CM. These may not be suitable for
+boot process c) above. They have been preserved for backward compatibility with
+existing build processes.
+
+Code Hierarchy Applied :
+----------------------
+Code specific to initialization of a particular ARM processor has been placed in
+cpu/arm<>/start.S so that it may be used by other boards.
+
+However, to avoid duplicating code through all processor files, a generic core
+for ARM Integrator CMs has been added
+
+	arch/arm/cpu/arm_intcm
+
+Otherwise. for example,  the standard CM reset via the CM control register would
+need placing in each CM processor file......
+
+Code specific to the initialization of the CM, rather than the cpu, and initialization
+of the Integrator board itself, has been placed in
+
+	board/integrator<>/platform.S
+	board/integrator<>/integrator<>.c
+
+Targets
+=======
+The U-Boot make targets map to the available core modules as below.
+
+Integrator/AP is no longer available from ARM.
+Core modules marked ** are also no longer available.
+
+ap720t_config		** CM720T
+ap920t_config		** CM920T
+ap926ejs_config	Integrator Core Module for ARM926EJ-STM
+ap946es_config		Integrator Core Module for ARM946E-STM
+cp920t_config		** CM920T
+cp926ejs_config	Integrator Core Module for ARM926EJ-STM
+cp946es_config		Integrator Core Module for ARM946E-STM
+cp1136_config		Integrator Core Module ARM1136JF-S  TM
+
+The final groups of targets are for core modules where no explicit cpu
+code has yet been added to U-Boot i.e. they all use the same U-Boot binary
+using the generic "arm_intcm" core:
+
+ap966_config			Integrator Core Module for ARM966E-S TM
+ap922_config			Integrator Core Module for ARM922T TM with ETM
+ap922_XA10_config		Integrator Core Module for ARM922T using Altera Excalibur
+ap7_config			** CM7TDMI
+integratorap_config
+ap_config
+
+
+cp966_config			Integrator Core Module for ARM966E-S TM
+cp922_config			Integrator Core Module for ARM922T TM with ETM
+cp922_XA10_config		Integrator Core Module for ARM922T using Altera Excalibur
+cp1026_config			Integrator Core Module ARM1026EJ-S TM
+integratorcp_config
+cp_config
+
+The Makefile targets call board/integrator<>/split_by_variant.sh
+to configure various defines in include/configs/integrator<>.h
+to indicate the core module & core configuration and ensure that
+board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image.
+
+*********************************
+Because of this mechanism
+> make clean
+must be run before each change in configuration
+*********************************
diff --git a/roms/u-boot/board/armltd/integrator/arm-ebi.h b/roms/u-boot/board/armltd/integrator/arm-ebi.h
new file mode 100644
index 000000000..6b1a96d8a
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/arm-ebi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE		0x12000000
+
+#define EBI_CSR0_REG		0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG		0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG		0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG		0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK	0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK	0xF7
+#define EBI_CSR_ASYNC		0x00
+#define EBI_CSR_SYNC		0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK	0xFB
+#define EBI_CSR_WREN_DISABLE	0x00
+#define EBI_CSR_WREN_ENABLE	0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK	0xFC
+#define EBI_CSR_MEMSIZE_8BIT	0x00
+#define EBI_CSR_MEMSIZE_16BIT	0x01
+#define EBI_CSR_MEMSIZE_32BIT	0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG		0x20
+#define EBI_UNLOCK_MAGIC	0xA05F
+
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/integrator-sc.h b/roms/u-boot/board/armltd/integrator/integrator-sc.h
new file mode 100644
index 000000000..42d90b118
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/integrator-sc.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the System Controller (SC) and
+ * the similar "CP Controller" found in the ARM Integrator/AP and
+ * Integrator/CP reference designs
+ */
+
+#ifndef __ARM_SC_H
+#define __ARM_SC_H
+
+#define SC_BASE			0x11000000
+
+/*
+ * The system controller registers
+ */
+#define SC_ID_OFFSET		0x00
+#define SC_OSC_OFFSET		0x04
+/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
+#define SC_OSC_DIVXY		(1 << 8)
+#define SC_CTRLS_OFFSET		0x08
+#define SC_CTRLC_OFFSET		0x0C
+/* Set bits by writing CTRLS, clear bits by writing CTRLC */
+#define SC_CTRL_SOFTRESET	(1 << 0)
+#define SC_CTRL_FLASHVPP	(1 << 1)
+#define SC_CTRL_FLASHWP		(1 << 2)
+#define SC_CTRL_UART1DTR	(1 << 4)
+#define SC_CTRL_UART1RTS	(1 << 5)
+#define SC_CTRL_UART0DTR	(1 << 6)
+#define SC_CTRL_UART0RTS	(1 << 7)
+#define SC_DEC_OFFSET		0x10
+#define SC_ARB_OFFSET		0x14
+#define SC_PCI_OFFSET		0x18
+#define SC_PCI_PCIEN		(1 << 0)
+#define SC_PCI_PCIBINT_CLR	(1 << 1)
+#define SC_LOCK_OFFSET		0x1C
+#define SC_LBFADDR_OFFSET	0x20
+#define SC_LBFCODE_OFFSET	0x24
+
+#define SC_ID (SC_BASE + SC_ID_OFFSET)
+#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
+#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
+#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
+#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
+#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
+#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
+#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
+#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
+#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
+
+/*
+ * The Integrator/CP as a smaller set of registers, at a different
+ * offset - probably not to disturb old software.
+ */
+
+#define CP_BASE			0xCB000000
+
+#define CP_IDFIELD_OFFSET	0x00
+#define CP_FLASHPROG_OFFSET	0x04
+#define CP_FLASHPROG_FLVPPEN	(1 << 0)
+#define CP_FLASHPROG_FLWREN	(1 << 1)
+#define CP_FLASHPROG_FLASHSIZE	(1 << 2)
+#define CP_FLASHPROG_EXTRABANK	(1 << 3)
+#define CP_INTREG_OFFSET	0x08
+#define CP_DECODE_OFFSET	0x0C
+
+#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
+#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
+#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
+#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
+
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/integrator.c b/roms/u-boot/board/armltd/integrator/integrator.c
new file mode 100644
index 000000000..3e864e8e7
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/integrator.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+
+#include <common.h>
+#include <bootstage.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include "arm-ebi.h"
+#include "integrator-sc.h"
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = 0x16000000,
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	.type = TYPE_PL011,
+	.clock = 14745600,
+#else
+	.type = TYPE_PL010,
+	.clock = 0, /* Not used for PL010 */
+#endif
+};
+
+U_BOOT_DRVINFO(integrator_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	u32 val;
+
+	/* arch number of Integrator Board */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+#else
+	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#endif
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	/*
+	 * Flash protection on the Integrator/CP is in a simple register
+	 */
+	val = readl(CP_FLASHPROG);
+	val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
+	writel(val, CP_FLASHPROG);
+#else
+	/*
+	 * The Integrator/AP has some special protection mechanisms
+	 * for the external memories, first the External Bus Interface (EBI)
+	 * then the system controller (SC).
+	 *
+	 * The system comes up with the flash memory non-writable and
+	 * configuration locked. If we want U-Boot to be used for flash
+	 * access we cannot have the flash memory locked.
+	 */
+	writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+	val = readl(EBI_BASE + EBI_CSR1_REG);
+	val &= EBI_CSR_WREN_MASK;
+	val |= EBI_CSR_WREN_ENABLE;
+	writel(val, EBI_BASE + EBI_CSR1_REG);
+	writel(0, EBI_BASE + EBI_LOCK_REG);
+
+	/*
+	 * Set up the system controller to remove write protection from
+	 * the flash memory and enable Vpp
+	 */
+	writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
+#endif
+
+	icache_enable();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	env_set("verify", "n");
+	return (0);
+}
+
+/*
+ * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
+ * from there, which means we cannot test the RAM underneath the ROM at this
+ * point. It will be unmapped later on, when we are executing from the
+ * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
+ * RAM on higher addresses works fine.
+ */
+#define REMAPPED_FLASH_SZ 0x40000
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+#ifdef CONFIG_CM_SPD_DETECT
+	{
+extern void dram_query(void);
+	u32 cm_reg_sdram;
+	u32 sdram_shift;
+
+	dram_query();	/* Assembler accesses to CM registers */
+			/* Queries the SPD values	      */
+
+	/* Obtain the SDRAM size from the CM SDRAM register */
+
+	cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
+	/*   Register	      SDRAM size
+	 *
+	 *   0xXXXXXXbbb000bb	 16 MB
+	 *   0xXXXXXXbbb001bb	 32 MB
+	 *   0xXXXXXXbbb010bb	 64 MB
+	 *   0xXXXXXXbbb011bb	128 MB
+	 *   0xXXXXXXbbb100bb	256 MB
+	 *
+	 */
+	sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+				    REMAPPED_FLASH_SZ,
+				    0x01000000 << sdram_shift);
+	}
+#else
+	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+				    REMAPPED_FLASH_SZ,
+				    PHYS_SDRAM_1_SIZE);
+#endif /* CM_SPD_DETECT */
+	/* We only have one bank of RAM, set it to whatever was detected */
+	gd->bd->bi_dram[0].size	 = gd->ram_size;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+	rc += pci_eth_init(bis);
+	return rc;
+}
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/lowlevel_init.S b/roms/u-boot/board/armltd/integrator/lowlevel_init.S
new file mode 100644
index 000000000..1a1cb580b
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/lowlevel_init.S
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+
+#include <config.h>
+
+	/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+	mov	r0, #CM_BASE
+	ldr	r1,[r0,#OS_CTRL]
+	orr	r1,r1,#CMMASK_RESET
+	str	r1,[r0,#OS_CTRL]
+
+reset_failed:
+	b	reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	/* If U-Boot has been run after the ARM boot monitor
+	 * then all the necessary actions have been done
+	 * otherwise we are running from user flash mapped to 0x00000000
+	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+	 * Changes to the (possibly soft) reset defaults of the processor
+	 * itself should be performed in cpu/arm<>/start.S
+	 * This function affects only the core module or board settings
+	 */
+
+#ifdef CONFIG_CM_INIT
+	/* CM has an initialization register
+	 * - bits in it are wired into test-chip pins to force
+	 *   reset defaults
+	 * - may need to change its contents for U-Boot
+	 */
+
+	/* set the desired CM specific value */
+	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+	orr	r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+     !defined (CONFIG_CM940T)
+
+#ifdef	CONFIG_CM_MULTIPLE_SSRAM
+	/* set simple mapping			*/
+	and	r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
+
+#ifdef	CONFIG_CM_TCRAM
+	/* disable TCRAM			*/
+	and	r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM		*/
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+     defined (CONFIG_CM1136JF_S)
+
+	and	r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+	orr	r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+	/* read CM_INIT		 */
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_INIT]
+	/* check against desired bit setting */
+	and	r3,r1,r2
+	cmp	r3,r2
+	beq	init_reg_OK
+
+	/* lock for change */
+	mov	r3, #CMVAL_LOCK1
+	add	r3,r3,#CMVAL_LOCK2
+	str	r3, [r0, #OS_LOCK]
+	/* set desired value */
+	orr	r1,r1,r2
+	/* write & relock CM_INIT */
+	str	r1, [r0, #OS_INIT]
+	mov	r1, #CMVAL_UNLOCK
+	str	r1, [r0, #OS_LOCK]
+
+	/* soft reset so new values used */
+	b	reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+	mov	pc, lr
+
+#ifdef	CONFIG_CM_SPD_DETECT
+	/* Fast memory is available for the DRAM data
+	 * - ensure it has been transferred, then summarize the data
+	 *   into a CM register
+	 */
+.globl dram_query
+dram_query:
+	stmfd	r13!,{r4-r6,lr}
+	/* set up SDRAM info					*/
+	/* - based on example code from the CM User Guide */
+	mov	r0, #CM_BASE
+
+readspdbit:
+	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register	*/
+	and	r1, r1, #0x20		/* mask SPD bit (5)		*/
+	cmp	r1, #0x20		/* test if set			*/
+	bne	readspdbit
+
+setupsdram:
+	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
+	ldrb	r1, [r0, #3]		/* number of row address lines		*/
+	ldrb	r2, [r0, #4]		/* number of column address lines	*/
+	ldrb	r3, [r0, #5]		/* number of banks			*/
+	ldrb	r4, [r0, #31]		/* module bank density			*/
+	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
+	mov	r5, r5, ASL#2		/* size in MB				*/
+	mov	r0, #CM_BASE		/* reload for later code		*/
+	cmp	r5, #0x10		/* is it 16MB?				*/
+	bne	not16
+	mov	r6, #0x2		/* store size and CAS latency of 2	*/
+	b	writesize
+
+not16:
+	cmp	r5, #0x20		/* is it  32MB? */
+	bne	not32
+	mov	r6, #0x6
+	b	writesize
+
+not32:
+	cmp	r5, #0x40		/* is it  64MB? */
+	bne	not64
+	mov	r6, #0xa
+	b	writesize
+
+not64:
+	cmp	r5, #0x80		/* is it 128MB? */
+	bne	not128
+	mov	r6, #0xe
+	b	writesize
+
+not128:
+	/* if it is none of these sizes then it is either 256MB, or
+	 * there is no SDRAM fitted so default to 256MB
+	 */
+	mov	r6, #0x12
+
+writesize:
+	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
+	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
+	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
+	orr	r6, r6, r3		/* OR in size and CAS latency	 */
+	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
+
+#ifdef	CONFIG_CM_REMAP
+	/* CM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 */
+.globl cm_remap
+cm_remap:
+	stmfd	r13!,{r4-r10,lr}
+
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_CTRL]
+	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
+	str	r1, [r0, #OS_CTRL]
+
+	/* Now 0x00000000 is writeable, replace the vectors	*/
+	ldr	r0, =_start	/* r0 <- start of vectors	*/
+	add	r2, r0, #64	/* r2 <- past vectors	*/
+	sub	r1,r1,r1		/* destination 0x00000000	*/
+
+copy_vec:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
+	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
+	cmp	r0, r2			/* until source end address [r2]	*/
+	ble	copy_vec
+
+	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/roms/u-boot/board/armltd/integrator/pci.c b/roms/u-boot/board/armltd/integrator/pci.c
new file mode 100644
index 000000000..28efc33f1
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/pci.c
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ */
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include "integrator-sc.h"
+#include "pci_v3.h"
+
+#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
+#define INTEGRATOR_HDR0_SDRAM_BASE	0x80000000
+
+/*
+ * These are in the physical addresses on the CPU side, i.e.
+ * where we read and write stuff - you don't want to try to
+ * move these around
+ */
+#define PHYS_PCI_MEM_BASE	0x40000000
+#define PHYS_PCI_IO_BASE	0x60000000	/* PCI I/O space base */
+#define PHYS_PCI_CONFIG_BASE	0x61000000
+#define PHYS_PCI_V3_BASE	0x62000000	/* V360EPC registers */
+#define SZ_256M			0x10000000
+
+/*
+ * These are in the PCI BUS address space
+ * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
+ * we follow the example of the kernel, because that is the address
+ * range that devices actually use - what would they be doing at
+ * 0x40000000?
+ */
+#define PCI_BUS_NONMEM_START	0x00000000
+#define PCI_BUS_NONMEM_SIZE	SZ_256M
+
+#define PCI_BUS_PREMEM_START	(PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
+#define PCI_BUS_PREMEM_SIZE	SZ_256M
+
+#if PCI_BUS_NONMEM_START & 0x000fffff
+#error PCI_BUS_NONMEM_START must be megabyte aligned
+#endif
+#if PCI_BUS_PREMEM_START & 0x000fffff
+#error PCI_BUS_PREMEM_START must be megabyte aligned
+#endif
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+#define PCI_ENET0_IOADDR	0x60000000 /* First card in PCI I/O space */
+#define PCI_ENET0_MEMADDR	0x40000000 /* First card in PCI memory space */
+static struct pci_config_table pci_integrator_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif /* CONFIG_PCI_PNP */
+
+/* V3 access routines */
+#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readb(o)    (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readw(o)    (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readl(o)    (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
+{
+	unsigned int address, mapaddress;
+	unsigned int busnr = PCI_BUS(bdf);
+	unsigned int devfn = PCI_FUNC(bdf);
+
+	/*
+	 * Trap out illegal values
+	 */
+	if (offset > 255)
+		BUG();
+	if (busnr > 255)
+		BUG();
+	if (devfn > 255)
+		BUG();
+
+	if (busnr == 0) {
+		/*
+		 * Linux calls the thing U-Boot calls "DEV" "SLOT"
+		 * instead, but it's the same 5 bits
+		 */
+		int slot = PCI_DEV(bdf);
+
+		/*
+		 * local bus segment so need a type 0 config cycle
+		 *
+		 * build the PCI configuration "address" with one-hot in
+		 * A31-A11
+		 *
+		 * mapaddress:
+		 *  3:1 = config cycle (101)
+		 *  0   = PCI A1 & A0 are 0 (0)
+		 */
+		address = PCI_FUNC(bdf) << 8;
+		mapaddress = V3_LB_MAP_TYPE_CONFIG;
+
+		if (slot > 12)
+			/*
+			 * high order bits are handled by the MAP register
+			 */
+			mapaddress |= 1 << (slot - 5);
+		else
+			/*
+			 * low order bits handled directly in the address
+			 */
+			address |= 1 << (slot + 11);
+	} else {
+		/*
+		 * not the local bus segment so need a type 1 config cycle
+		 *
+		 * address:
+		 *  23:16 = bus number
+		 *  15:11 = slot number (7:3 of devfn)
+		 *  10:8  = func number (2:0 of devfn)
+		 *
+		 * mapaddress:
+		 *  3:1 = config cycle (101)
+		 *  0   = PCI A1 & A0 from host bus (1)
+		 */
+		mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
+		address = (busnr << 16) | (devfn << 8);
+	}
+
+	/*
+	 * Set up base0 to see all 512Mbytes of memory space (not
+	 * prefetchable), this frees up base1 for re-use by
+	 * configuration memory
+	 */
+	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+			V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
+
+	/*
+	 * Set up base1/map1 to point into configuration space.
+	 */
+	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
+			V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP1, mapaddress);
+
+	return PHYS_PCI_CONFIG_BASE + address + offset;
+}
+
+static void v3_close_config_window(void)
+{
+	/*
+	 * Reassign base1 for use by prefetchable PCI memory
+	 */
+	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
+			V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+			V3_LB_MAP_TYPE_MEM_MULTIPLE);
+
+	/*
+	 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
+	 */
+	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
+}
+
+static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
+				    int offset, unsigned char *val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	*val = __raw_readb(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_read__word(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned short *val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	*val = __raw_readw(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_read_dword(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned int *val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	*val = __raw_readl(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_write_byte(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned char val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	__raw_writeb((u8)val, addr);
+	__raw_readb(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_write_word(struct pci_controller *hose,
+				     pci_dev_t bdf, int offset,
+				     unsigned short val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	__raw_writew((u8)val, addr);
+	__raw_readw(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+static int pci_integrator_write_dword(struct pci_controller *hose,
+				      pci_dev_t bdf, int offset,
+				      unsigned int val)
+{
+	unsigned long addr;
+
+	addr = v3_open_config_window(bdf, offset);
+	__raw_writel((u8)val, addr);
+	__raw_readl(addr);
+	v3_close_config_window();
+	return 0;
+}
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	struct pci_controller *hose = &integrator_hose;
+	u16 val;
+
+	/* setting this register will take the V3 out of reset */
+	__raw_writel(SC_PCI_PCIEN, SC_PCI);
+
+	/* Wait for 230 ms (from spec) before accessing any V3 registers */
+	mdelay(230);
+
+	/* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
+	v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
+
+	/* Wait for the mailbox to settle */
+	do {
+		v3_writeb(V3_MAIL_DATA, 0xAA);
+		v3_writeb(V3_MAIL_DATA + 4, 0x55);
+	} while (v3_readb(V3_MAIL_DATA) != 0xAA ||
+		 v3_readb(V3_MAIL_DATA + 4) != 0x55);
+
+	/* Make sure that V3 register access is not locked, if it is, unlock it */
+	if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
+		v3_writew(V3_SYSTEM, 0xA05F);
+
+	/*
+	 * Ensure that the slave accesses from PCI are disabled while we
+	 * setup memory windows
+	 */
+	val = v3_readw(V3_PCI_CMD);
+	val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+	v3_writew(V3_PCI_CMD, val);
+
+	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+	val = v3_readw(V3_SYSTEM);
+	val &= ~V3_SYSTEM_M_RST_OUT;
+	v3_writew(V3_SYSTEM, val);
+
+	/* Make all accesses from PCI space retry until we're ready for them */
+	val = v3_readw(V3_PCI_CFG);
+	val |= V3_PCI_CFG_M_RETRY_EN;
+	v3_writew(V3_PCI_CFG, val);
+
+	/*
+	 * Set up any V3 PCI Configuration Registers that we absolutely have to.
+	 * LB_CFG controls Local Bus protocol.
+	 * Enable LocalBus byte strobes for READ accesses too.
+	 * set bit 7 BE_IMODE and bit 6 BE_OMODE
+	 */
+	val = v3_readw(V3_LB_CFG);
+	val |= 0x0C0;
+	v3_writew(V3_LB_CFG, val);
+
+	/* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
+	val = v3_readw(V3_PCI_CMD);
+	val |= V3_COMMAND_M_MASTER_EN;
+	v3_writew(V3_PCI_CMD, val);
+
+	/*
+	 * PCI_MAP0 controls where the PCI to CPU memory window is on
+	 * Local Bus
+	 */
+	v3_writel(V3_PCI_MAP0,
+		  (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
+						V3_PCI_MAP_M_REG_EN |
+						V3_PCI_MAP_M_ENABLE));
+
+	/* PCI_BASE0 is the PCI address of the start of the window */
+	v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
+
+	/* PCI_MAP1 is LOCAL address of the start of the window */
+	v3_writel(V3_PCI_MAP1,
+		  (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
+						  V3_PCI_MAP_M_REG_EN |
+						  V3_PCI_MAP_M_ENABLE));
+
+	/* PCI_BASE1 is the PCI address of the start of the window */
+	v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
+
+	/*
+	 * Set up memory the windows from local bus memory into PCI
+	 * configuration, I/O and Memory regions.
+	 * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
+	 */
+	v3_writew(V3_LB_BASE2,
+		  v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP2, 0);
+
+	/* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+	/*
+	 * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
+	 * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
+	 */
+	v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP0,
+		  v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
+
+	/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+	v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+			V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
+			V3_LB_BASE_ENABLE);
+	v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+			V3_LB_MAP_TYPE_MEM_MULTIPLE);
+
+	/* Dump PCI to local address space mappings */
+	debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
+	debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
+	debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
+	debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
+	debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
+	debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
+	debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
+
+	/*
+	 * Allow accesses to PCI Configuration space and set up A1, A0 for
+	 * type 1 config cycles
+	 */
+	val = v3_readw(V3_PCI_CFG);
+	val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
+	val |= V3_PCI_CFG_M_AD_LOW0;
+	v3_writew(V3_PCI_CFG, val);
+
+	/* now we can allow incoming PCI MEMORY accesses */
+	val = v3_readw(V3_PCI_CMD);
+	val |= V3_COMMAND_M_MEM_EN;
+	v3_writew(V3_PCI_CMD, val);
+
+	/*
+	 * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
+	 * now initialise.
+	 */
+	val = v3_readw(V3_SYSTEM);
+	val |= V3_SYSTEM_M_RST_OUT;
+	v3_writew(V3_SYSTEM, val);
+
+	/*  Lock the V3 system register so that no one else can play with it */
+	val = v3_readw(V3_SYSTEM);
+	val |= V3_SYSTEM_M_LOCK;
+	v3_writew(V3_SYSTEM, val);
+
+	/*
+	 * Configure and register the PCI hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System memory space, window 0 256 MB non-prefetchable */
+	pci_set_region(hose->regions + 0,
+		       PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
+		       SZ_256M,
+		       PCI_REGION_MEM);
+
+	/* System memory space, window 1 256 MB prefetchable */
+	pci_set_region(hose->regions + 1,
+		       PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
+		       SZ_256M,
+		       PCI_REGION_MEM |
+		       PCI_REGION_PREFETCH);
+
+	/* PCI I/O space */
+	pci_set_region(hose->regions + 2,
+		       0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
+		       PCI_REGION_IO);
+
+	/* PCI Memory - config space */
+	pci_set_region(hose->regions + 3,
+		       0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
+		       PCI_REGION_MEM);
+	/* PCI V3 regs */
+	pci_set_region(hose->regions + 4,
+		       0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
+		       PCI_REGION_MEM);
+
+	hose->region_count = 5;
+
+	pci_set_ops(hose,
+		    pci_integrator_read_byte,
+		    pci_integrator_read__word,
+		    pci_integrator_read_dword,
+		    pci_integrator_write_byte,
+		    pci_integrator_write_word,
+		    pci_integrator_write_dword);
+
+	pci_register_hose(hose);
+
+	pciauto_config_init(hose);
+	pciauto_config_device(hose, 0);
+
+	hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/roms/u-boot/board/armltd/integrator/pci_v3.h b/roms/u-boot/board/armltd/integrator/pci_v3.h
new file mode 100644
index 000000000..8d09e6966
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/pci_v3.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  arch/arm/include/asm/hardware/pci_v3.h
+ *
+ *  Internal header file PCI V3 chip
+ *
+ *  Copyright (C) ARM Limited
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
+ */
+#ifndef ASM_ARM_HARDWARE_PCI_V3_H
+#define ASM_ARM_HARDWARE_PCI_V3_H
+
+/* -------------------------------------------------------------------------------
+ *  V3 Local Bus to PCI Bridge definitions
+ * -------------------------------------------------------------------------------
+ *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ *  All V3 register names are prefaced by V3_ to avoid clashing with any other
+ *  PCI definitions.  Their names match the user's manual.
+ *
+ *  I'm assuming that I20 is disabled.
+ *
+ */
+#define V3_PCI_VENDOR                   0x00000000
+#define V3_PCI_DEVICE                   0x00000002
+#define V3_PCI_CMD                      0x00000004
+#define V3_PCI_STAT                     0x00000006
+#define V3_PCI_CC_REV                   0x00000008
+#define V3_PCI_HDR_CFG                  0x0000000C
+#define V3_PCI_IO_BASE                  0x00000010
+#define V3_PCI_BASE0                    0x00000014
+#define V3_PCI_BASE1                    0x00000018
+#define V3_PCI_SUB_VENDOR               0x0000002C
+#define V3_PCI_SUB_ID                   0x0000002E
+#define V3_PCI_ROM                      0x00000030
+#define V3_PCI_BPARAM                   0x0000003C
+#define V3_PCI_MAP0                     0x00000040
+#define V3_PCI_MAP1                     0x00000044
+#define V3_PCI_INT_STAT                 0x00000048
+#define V3_PCI_INT_CFG                  0x0000004C
+#define V3_LB_BASE0                     0x00000054
+#define V3_LB_BASE1                     0x00000058
+#define V3_LB_MAP0                      0x0000005E
+#define V3_LB_MAP1                      0x00000062
+#define V3_LB_BASE2                     0x00000064
+#define V3_LB_MAP2                      0x00000066
+#define V3_LB_SIZE                      0x00000068
+#define V3_LB_IO_BASE                   0x0000006E
+#define V3_FIFO_CFG                     0x00000070
+#define V3_FIFO_PRIORITY                0x00000072
+#define V3_FIFO_STAT                    0x00000074
+#define V3_LB_ISTAT                     0x00000076
+#define V3_LB_IMASK                     0x00000077
+#define V3_SYSTEM                       0x00000078
+#define V3_LB_CFG                       0x0000007A
+#define V3_PCI_CFG                      0x0000007C
+#define V3_DMA_PCI_ADR0                 0x00000080
+#define V3_DMA_PCI_ADR1                 0x00000090
+#define V3_DMA_LOCAL_ADR0               0x00000084
+#define V3_DMA_LOCAL_ADR1               0x00000094
+#define V3_DMA_LENGTH0                  0x00000088
+#define V3_DMA_LENGTH1                  0x00000098
+#define V3_DMA_CSR0                     0x0000008B
+#define V3_DMA_CSR1                     0x0000009B
+#define V3_DMA_CTLB_ADR0                0x0000008C
+#define V3_DMA_CTLB_ADR1                0x0000009C
+#define V3_DMA_DELAY                    0x000000E0
+#define V3_MAIL_DATA                    0x000000C0
+#define V3_PCI_MAIL_IEWR                0x000000D0
+#define V3_PCI_MAIL_IERD                0x000000D2
+#define V3_LB_MAIL_IEWR                 0x000000D4
+#define V3_LB_MAIL_IERD                 0x000000D6
+#define V3_MAIL_WR_STAT                 0x000000D8
+#define V3_MAIL_RD_STAT                 0x000000DA
+#define V3_QBA_MAP                      0x000000DC
+
+/*  PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+
+/*  SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+
+/*  PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN		(1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS		(1 << 14)
+#define V3_PCI_CFG_M_IO_DIS		(1 << 13)
+#define V3_PCI_CFG_M_EN3V		(1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+
+/*  PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
+#define V3_PCI_BASE_M_TYPE              (3 << 1)
+#define V3_PCI_BASE_M_IO                (1 << 0)
+
+/*  PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
+#define V3_PCI_MAP_M_SWAP               (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+
+#define V3_PCI_MAP_M_ADR_SIZE_1MB	(0 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_2MB	(1 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_4MB	(2 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_8MB	(3 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_16MB	(4 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_32MB	(5 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_64MB	(6 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_128MB	(7 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_256MB	(8 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_512MB	(9 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_1GB	(10 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_2GB	(11 << 4)
+
+/*
+ *  LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE		0xfff00000
+#define V3_LB_BASE_SWAP			(3 << 8)
+#define V3_LB_BASE_ADR_SIZE		(15 << 4)
+#define V3_LB_BASE_PREFETCH		(1 << 3)
+#define V3_LB_BASE_ENABLE		(1 << 0)
+
+#define V3_LB_BASE_ADR_SIZE_1MB		(0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB		(1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB		(2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB		(3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB	(4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB	(5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB	(6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB	(7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB	(8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB	(9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB		(10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB		(11 << 4)
+
+#define v3_addr_to_lb_base(a)	((a) & V3_LB_BASE_ADR_BASE)
+
+/*
+ *  LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR		0xfff0
+#define V3_LB_MAP_TYPE			(7 << 1)
+#define V3_LB_MAP_AD_LOW_EN		(1 << 0)
+
+#define V3_LB_MAP_TYPE_IACK		(0 << 1)
+#define V3_LB_MAP_TYPE_IO		(1 << 1)
+#define V3_LB_MAP_TYPE_MEM		(3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG		(5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE	(6 << 1)
+
+/* PCI MAP register bits (PCI -> Local bus) */
+#define v3_addr_to_lb_map(a)	(((a) >> 16) & V3_LB_MAP_MAP_ADR)
+
+/*
+ *  LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE		0xff00
+#define V3_LB_BASE2_SWAP		(3 << 6)
+#define V3_LB_BASE2_ENABLE		(1 << 0)
+
+#define v3_addr_to_lb_base2(a)	(((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+
+/*
+ *  LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR		0xff00
+
+#define v3_addr_to_lb_map2(a)	(((a) >> 16) & V3_LB_MAP2_MAP_ADR)
+
+#endif
diff --git a/roms/u-boot/board/armltd/integrator/timer.c b/roms/u-boot/board/armltd/integrator/timer.c
new file mode 100644
index 000000000..d220b877d
--- /dev/null
+++ b/roms/u-boot/board/armltd/integrator/timer.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <time.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+#define DIV_CLOCK_INIT	1
+#define TIMER_LOAD_VAL	0xFFFFFFFFL
+#else
+#define DIV_CLOCK_INIT	256
+#define TIMER_LOAD_VAL	0x0000FFFFL
+#endif
+/* The Integrator/CP timer1 is clocked at 1MHz
+ * can be divided by 16 or 256
+ * and can be set up as a 32-bit timer
+ */
+/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
+/* Keep total timer count to avoid losing decrements < div_timer */
+static unsigned long long total_count = 0;
+static unsigned long long lastdec;	 /* Timer reading at last call	   */
+/* Divisor applied to timer clock */
+static unsigned long long div_clock = DIV_CLOCK_INIT;
+static unsigned long long div_timer = 1; /* Divisor to convert timer reading
+					  * change to U-Boot ticks
+					  */
+/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
+static ulong timestamp;		/* U-Boot ticks since startup */
+
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
+
+/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
+ *  - unless otherwise stated
+ */
+
+/* starts up a counter
+ * - the Integrator/CP timer can be set up to issue an interrupt */
+int timer_init (void)
+{
+	/* Load timer with initial value */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	/* Set timer to be
+	 *	enabled		 1
+	 *	periodic	 1
+	 *	no interrupts	 0
+	 *	X		 0
+	 *	divider 1	00 == less rounding error
+	 *	32 bit		 1
+	 *	wrapping	 0
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+#else
+	/* Set timer to be
+	 *	enabled		 1
+	 *	free-running	 0
+	 *	XX		00
+	 *	divider 256	10
+	 *	XX		00
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+#endif
+
+	/* init the timestamp */
+	total_count = 0ULL;
+	/* capure current decrementer value    */
+	lastdec	  = READ_TIMER;
+	/* start "advancing" time stamp from 0 */
+	timestamp = 0L;
+
+	div_timer = CONFIG_SYS_HZ_CLOCK;
+	do_div(div_timer, CONFIG_SYS_HZ);
+	do_div(div_timer, div_clock);
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+/* converts the timer reading to U-Boot ticks	       */
+/* the timestamp is the number of ticks since reset    */
+static ulong get_timer_masked (void)
+{
+	/* get current count */
+	unsigned long long now = READ_TIMER;
+
+	if(now > lastdec) {
+		/* Must have wrapped */
+		total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+	} else {
+		total_count += lastdec - now;
+	}
+	lastdec	= now;
+
+	/* Reuse "now" */
+	now = total_count;
+	do_div(now, div_timer);
+	timestamp = now;
+
+	return timestamp;
+}
+
+ulong get_timer (ulong base_ticks)
+{
+	return get_timer_masked () - base_ticks;
+}
+
+/* delay usec useconds */
+void __udelay(unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* Convert to U-Boot ticks */
+	tmo  = usec * CONFIG_SYS_HZ;
+	tmo /= (1000000L);
+
+	tmp  = get_timer_masked();	/* get current timestamp */
+	tmo += tmp;			/* form target timestamp */
+
+	while (get_timer_masked () < tmo) {/* loop till event */
+		/*NOP*/;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk(void)
+{
+	unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+
+	do_div(tmp, div_clock);
+
+	return tmp;
+}
diff --git a/roms/u-boot/board/armltd/total_compute/Kconfig b/roms/u-boot/board/armltd/total_compute/Kconfig
new file mode 100644
index 000000000..62e6e6f4a
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TOTAL_COMPUTE
+
+config SYS_BOARD
+	default "total_compute"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "total_compute"
+
+endif
diff --git a/roms/u-boot/board/armltd/total_compute/MAINTAINERS b/roms/u-boot/board/armltd/total_compute/MAINTAINERS
new file mode 100644
index 000000000..3dc1cd188
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/MAINTAINERS
@@ -0,0 +1,7 @@
+TOTAL_COMPUTE BOARD
+M:	Usama Arif <usama.arif@arm.com>
+S:	Maintained
+F:	board/armltd/total_compute/
+F:	include/configs/total_compute.h
+F:	configs/total_compute_defconfig
+F:	arch/arm/dts/total_compute.dts
diff --git a/roms/u-boot/board/armltd/total_compute/Makefile b/roms/u-boot/board/armltd/total_compute/Makefile
new file mode 100644
index 000000000..8b1045843
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 Arm Limited
+# Usama Arif <usama.arif@arm.com>
+
+obj-y	:= total_compute.o
diff --git a/roms/u-boot/board/armltd/total_compute/total_compute.c b/roms/u-boot/board/armltd/total_compute/total_compute.c
new file mode 100644
index 000000000..b7eaab085
--- /dev/null
+++ b/roms/u-boot/board/armltd/total_compute/total_compute.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Arm Limited
+ * Usama Arif <usama.arif@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = UART0_BASE,
+	.type = TYPE_PL011,
+	.clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(total_compute_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+static struct mm_region total_compute_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = total_compute_mem_map;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/* Nothing to be done here as handled by PSCI interface */
+void reset_cpu(void)
+{
+}
diff --git a/roms/u-boot/board/armltd/vexpress64/Kconfig b/roms/u-boot/board/armltd/vexpress64/Kconfig
new file mode 100644
index 000000000..1d13f542e
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
+
+config SYS_BOARD
+	default "vexpress64"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "vexpress_aemv8a"
+
+config JUNO_DTB_PART
+	string "NOR flash partition holding DTB"
+	default "board.dtb"
+	help
+	  The ARM partition name in the NOR flash memory holding the
+	  device tree blob to configure U-Boot.
+
+endif
diff --git a/roms/u-boot/board/armltd/vexpress64/MAINTAINERS b/roms/u-boot/board/armltd/vexpress64/MAINTAINERS
new file mode 100644
index 000000000..0ba044d7f
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/MAINTAINERS
@@ -0,0 +1,16 @@
+VEXPRESS64 BOARD
+M:	David Feng <fenghua@phytium.com.cn>
+S:	Maintained
+F:	board/armltd/vexpress64/
+F:	include/configs/vexpress_aemv8a.h
+F:	configs/vexpress_aemv8a_defconfig
+
+VEXPRESS_AEMV8A_SEMI BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	configs/vexpress_aemv8a_semi_defconfig
+
+JUNO DEVELOPMENT PLATFORM BOARD
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	configs/vexpress_aemv8a_juno_defconfig
diff --git a/roms/u-boot/board/armltd/vexpress64/Makefile b/roms/u-boot/board/armltd/vexpress64/Makefile
new file mode 100644
index 000000000..868dc4f62
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= vexpress64.o
+obj-$(CONFIG_TARGET_VEXPRESS64_JUNO)	+= pcie.o
diff --git a/roms/u-boot/board/armltd/vexpress64/pcie.c b/roms/u-boot/board/armltd/vexpress64/pcie.c
new file mode 100644
index 000000000..733b190e5
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/pcie.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) ARM Ltd 2015
+ *
+ * Author: Liviu Dudau <Liviu.Dudau@arm.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <pci_ids.h>
+#include <linux/delay.h>
+#include "pcie.h"
+
+/* XpressRICH3 support */
+#define XR3_CONFIG_BASE			0x7ff30000
+#define XR3_RESET_BASE			0x7ff20000
+
+#define XR3_PCI_ECAM_START		0x40000000
+#define XR3_PCI_ECAM_SIZE		28	/* as power of 2 = 0x10000000 */
+#define XR3_PCI_IOSPACE_START		0x5f800000
+#define XR3_PCI_IOSPACE_SIZE		23	/* as power of 2 = 0x800000 */
+#define XR3_PCI_MEMSPACE_START		0x50000000
+#define XR3_PCI_MEMSPACE_SIZE		27	/* as power of 2 = 0x8000000 */
+#define XR3_PCI_MEMSPACE64_START	0x4000000000
+#define XR3_PCI_MEMSPACE64_SIZE		33	/* as power of 2 = 0x200000000 */
+
+#define JUNO_V2M_MSI_START		0x2c1c0000
+#define JUNO_V2M_MSI_SIZE		12	/* as power of 2 = 4096 */
+
+#define XR3PCI_BASIC_STATUS		0x18
+#define XR3PCI_BS_GEN_MASK		(0xf << 8)
+#define XR3PCI_BS_LINK_MASK		0xff
+
+#define XR3PCI_VIRTCHAN_CREDITS		0x90
+#define XR3PCI_BRIDGE_PCI_IDS		0x9c
+#define XR3PCI_PEX_SPC2			0xd8
+
+#define XR3PCI_ATR_PCIE_WIN0		0x600
+#define XR3PCI_ATR_PCIE_WIN1		0x700
+#define XR3PCI_ATR_AXI4_SLV0		0x800
+
+#define XR3PCI_ATR_TABLE_SIZE		0x20
+#define XR3PCI_ATR_SRC_ADDR_LOW		0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH	0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW	0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH	0xc
+#define XR3PCI_ATR_TRSL_PARAM		0x10
+
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_AXIDEVICE	(0x420004)
+#define XR3PCI_ATR_TRSLID_AXIMEMORY	(0x4e0004)  /* Write-through, read/write allocate */
+#define XR3PCI_ATR_TRSLID_PCIE_CONF	(0x000001)
+#define XR3PCI_ATR_TRSLID_PCIE_IO	(0x020000)
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY	(0x000000)
+
+#define XR3PCI_ECAM_OFFSET(b, d, o)	(((b) << 20) | \
+					(PCI_SLOT(d) << 15) | \
+					(PCI_FUNC(d) << 12) | o)
+
+#define JUNO_RESET_CTRL			0x1004
+#define JUNO_RESET_CTRL_PHY		BIT(0)
+#define JUNO_RESET_CTRL_RC		BIT(1)
+
+#define JUNO_RESET_STATUS		0x1008
+#define JUNO_RESET_STATUS_PLL		BIT(0)
+#define JUNO_RESET_STATUS_PHY		BIT(1)
+#define JUNO_RESET_STATUS_RC		BIT(2)
+#define JUNO_RESET_STATUS_MASK		(JUNO_RESET_STATUS_PLL | \
+					 JUNO_RESET_STATUS_PHY | \
+					 JUNO_RESET_STATUS_RC)
+
+static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+				 unsigned long trsl_addr, int window_size,
+				 int trsl_param)
+{
+	/* X3PCI_ATR_SRC_ADDR_LOW:
+	     - bit 0: enable entry,
+	     - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
+	     - bits 7-11: reserved
+	     - bits 12-31: start of source address
+	*/
+	writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
+	       base + XR3PCI_ATR_SRC_ADDR_LOW);
+	writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
+	writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
+	writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
+	writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
+
+	debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
+	       src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
+	       ((u64)1) << window_size, trsl_param);
+}
+
+static void xr3pci_setup_atr(void)
+{
+	/* setup PCIe to CPU address translation tables */
+	unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
+
+	/* forward all writes from PCIe to GIC V2M (used for MSI) */
+	xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
+			     JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* PCIe devices can write anywhere in memory */
+	xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
+			     31 /* grant access to all RAM under 4GB */,
+			     XR3PCI_ATR_TRSLID_AXIMEMORY);
+	base += XR3PCI_ATR_TABLE_SIZE;
+	xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
+			     XR3_PCI_MEMSPACE64_SIZE,
+			     XR3PCI_ATR_TRSLID_AXIMEMORY);
+
+
+	/* setup CPU to PCIe address translation table */
+	base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
+
+	/* setup ECAM space to bus configuration interface */
+	xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
+			     XR3PCI_ATR_TRSLID_PCIE_CONF);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* setup IO space translation */
+	xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
+			     XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* setup 32bit MEM space translation */
+	xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
+			     XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+
+	base += XR3PCI_ATR_TABLE_SIZE;
+
+	/* setup 64bit MEM space translation */
+	xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
+			     XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
+}
+
+static void xr3pci_init(void)
+{
+	u32 val;
+	int timeout = 200;
+
+	/* Initialise the XpressRICH3 PCIe host bridge */
+
+	/* add credits */
+	writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
+	writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
+	/* allow ECRC */
+	writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
+	/* setup the correct class code for the host bridge */
+	writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
+
+	/* reset phy and root complex */
+	writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
+	       XR3_RESET_BASE + JUNO_RESET_CTRL);
+
+	do {
+		mdelay(1);
+		val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
+	} while (--timeout &&
+		(val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
+
+	if (!timeout) {
+		printf("PCI XR3 Root complex reset timed out\n");
+		return;
+	}
+
+	/* Wait for the link to train */
+	mdelay(20);
+	timeout = 20;
+
+	do {
+		mdelay(1);
+		val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
+	} while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
+
+	if (!(val & XR3PCI_BS_LINK_MASK)) {
+		printf("Failed to negotiate a link!\n");
+		return;
+	}
+
+	printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
+	       val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
+
+	xr3pci_setup_atr();
+}
+
+void vexpress64_pcie_init(void)
+{
+	/* Initialise and configure the PCIe host bridge. */
+	xr3pci_init();
+
+	/* Register the now ECAM complaint PCIe host controller with U-Boot. */
+	pci_init();
+}
diff --git a/roms/u-boot/board/armltd/vexpress64/pcie.h b/roms/u-boot/board/armltd/vexpress64/pcie.h
new file mode 100644
index 000000000..14642f4f5
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/pcie.h
@@ -0,0 +1,6 @@
+#ifndef __VEXPRESS64_PCIE_H__
+#define __VEXPRESS64_PCIE_H__
+
+void vexpress64_pcie_init(void);
+
+#endif /* __VEXPRESS64_PCIE_H__ */
diff --git a/roms/u-boot/board/armltd/vexpress64/vexpress64.c b/roms/u-boot/board/armltd/vexpress64/vexpress64.c
new file mode 100644
index 000000000..2e4260286
--- /dev/null
+++ b/roms/u-boot/board/armltd/vexpress64/vexpress64.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include "pcie.h"
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = V2M_UART0,
+	.type = TYPE_PL011,
+	.clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(vexpress_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+static struct mm_region vexpress64_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = vexpress64_mem_map;
+
+/* This function gets replaced by platforms supporting PCIe.
+ * The replacement function, eg. on Juno, initialises the PCIe bus.
+ */
+__weak void vexpress64_pcie_init(void)
+{
+}
+
+int board_init(void)
+{
+	vexpress64_pcie_init();
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef PHYS_SDRAM_2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD
+#define JUNO_FLASH_SEC_SIZE	(256 * 1024)
+static phys_addr_t find_dtb_in_nor_flash(const char *partname)
+{
+	phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
+	int i;
+
+	for (i = 0;
+	     i < CONFIG_SYS_MAX_FLASH_SECT;
+	     i++, sector += JUNO_FLASH_SEC_SIZE) {
+		int len = strlen(partname) + 1;
+		int offs;
+		phys_addr_t imginfo;
+		u32 reg;
+
+		reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
+                /* This makes up the string "HSLFTOOF" flash footer */
+		if (reg != 0x464F4F54U)
+			continue;
+		reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
+                if (reg != 0x464C5348U)
+			continue;
+
+		for (offs = 0; offs < 32; offs += 4, len -= 4) {
+			reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
+			if (strncmp(partname + offs, (char *)&reg,
+			            len > 4 ? 4 : len))
+				break;
+
+			if (len > 4)
+				continue;
+
+			reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
+			imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
+			reg = readl(imginfo + 0x54);
+
+			return CONFIG_SYS_FLASH_BASE +
+			       reg * JUNO_FLASH_SEC_SIZE;
+		}
+	}
+
+	printf("No DTB found\n");
+
+	return ~0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
+
+	if (fdt_rom_addr == ~0UL)
+		return NULL;
+
+	return (void *)fdt_rom_addr;
+}
+#endif
+
+/* Actual reset is done via PSCI. */
+void reset_cpu(void)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(struct bd_info *bis)
+{
+	int rc = 0;
+#ifndef CONFIG_DM_ETH
+#ifdef CONFIG_SMC91111
+	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+#endif
+	return rc;
+}