Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

8 files changed, 166 insertions, 0 deletions

diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/.gitignore
new file mode 100644
index 000000000..6eb8a5481
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Kconfig
new file mode 100644
index 000000000..64692509f
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -0,0 +1,30 @@
+config SYS_BOARD
+	default "conga-qeval20-qa3-e3845"
+
+config SYS_VENDOR
+	default "congatec"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "conga-qeval20-qa3-e3845" if TARGET_CONGA_QEVAL20_QA3_E3845
+	default "theadorable-x86-conga-qa3-e3845" if TARGET_THEADORABLE_X86_CONGA_QA3_E3845
+
+config SYS_TEXT_BASE
+	default 0xfff00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_WINBOND
+	select SERIAL_RX_BUFFER
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
new file mode 100644
index 000000000..cceda4f49
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
@@ -0,0 +1,11 @@
+congatec EVAL20-QA3-E3845
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/congatec/conga-qeval20-qa3-e3845
+F:	include/configs/conga-qeval20-qa3-e3845.h
+F:	include/configs/theadorable-x86-conga-qa3-e3845.h
+F:	configs/conga-qeval20-qa3-e3845_defconfig
+F:	configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+F:	configs/theadorable-x86-conga-qa3-e3845_defconfig
+F:	configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+F:	arch/x86/dts/conga-qeval20-qa3-e3845.dts
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Makefile b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Makefile
new file mode 100644
index 000000000..451a4fcd6
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015, Google, Inc
+
+obj-y	+= conga-qeval20-qa3.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/README b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/README
new file mode 100644
index 000000000..98ff992a3
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/README
@@ -0,0 +1,23 @@
+------------------------------
+U-Boot console UART selection:
+------------------------------
+
+The U-Boot port for this congatec board currently supports two different
+configurations (defconfig files). The only difference is the UART that
+is used as the U-Boot console UART. The default defconfig file:
+
+conga-qeval20-qa3-e3845_defconfig
+
+provides this console on the UART0 which is provided via a Winbond
+Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier
+board (conga-QEVAL). This UART is the one provided with a SubD9
+connector on the mainboard (the low one). The 2nd defconfig file:
+
+conga-qeval20-qa3-e3845-internal-uart_defconfig
+
+provides the U-Boot console on the BayTrail internal legacy UART,
+which is routed from the QSeven SoM to the X300 connector on the
+baseboard. Here is called COM2. The baseboard already provides the
+RS232 level shifters. So a TTL-USB UART adapter does not work in
+this case. The signals need to get connected directly to the
+RS232 level signals of the PC UART via some adapter cable.
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
new file mode 100644
index 000000000..856960d5e
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
new file mode 100644
index 000000000..315b6dc54
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <winbond_w83627.h>
+#include <asm/gpio.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_INTERNAL_UART
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the Winbond one can be used.
+	 */
+	setup_internal_uart(0);
+
+	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
+	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
+			      UART0_BASE, UART0_IRQ);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+	u8 buf[8];
+	int ret;
+
+	/* Configure SMSC USB2513 USB Hub: 7bit address 0x2c */
+	ret = i2c_get_chip_for_busnum(0, 0x2c, 1, &dev);
+	if (ret) {
+		printf("Cannot find USB2513: %d\n", ret);
+		return 0;
+	}
+
+	/*
+	 * The first access to the USB Hub fails sometimes, so lets read
+	 * a dummy byte to be sure here
+	 */
+	dm_i2c_read(dev, 0x00, buf, 1);
+
+	/*
+	 * The SMSC hub is not visible on the I2C bus after the first
+	 * configuration at power-up. The following code deliberately
+	 * does not report upon failure of these I2C write calls.
+	 */
+	buf[0] = 0x93;
+	dm_i2c_write(dev, 0x06, buf, 1);
+
+	buf[0] = 0xaa;
+	dm_i2c_write(dev, 0xf8, buf, 1);
+
+	buf[0] = 0x0f;
+	dm_i2c_write(dev, 0xfa, buf, 1);
+
+	buf[0] = 0x01;
+	dm_i2c_write(dev, 0xff, buf, 1);
+
+	return 0;
+}
diff --git a/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
new file mode 100644
index 000000000..d2297ef59
--- /dev/null
+++ b/roms/u-boot/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}