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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/board/freescale/common/cadmus.c | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/board/freescale/common/cadmus.c')
-rw-r--r-- | roms/u-boot/board/freescale/common/cadmus.c | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/common/cadmus.c b/roms/u-boot/board/freescale/common/cadmus.c new file mode 100644 index 000000000..7e7394f33 --- /dev/null +++ b/roms/u-boot/board/freescale/common/cadmus.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2004, 2011 Freescale Semiconductor. + */ + + +#include <common.h> + + +/* + * CADMUS Board System Registers + */ +#ifndef CONFIG_SYS_CADMUS_BASE_REG +#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) +#endif + +typedef struct cadmus_reg { + u_char cm_ver; /* Board version */ + u_char cm_csr; /* General control/status */ + u_char cm_rst; /* Reset control */ + u_char cm_hsclk; /* High speed clock */ + u_char cm_hsxclk; /* High speed clock extended */ + u_char cm_led; /* LED data */ + u_char cm_pci; /* PCI control/status */ + u_char cm_dma; /* DMA control */ + u_char cm_reserved[248]; /* Total 256 bytes */ +} cadmus_reg_t; + + +unsigned int +get_board_version(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; + + return cadmus->cm_ver; +} + + +unsigned long +get_clock_freq(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; + + uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ + + if (pci1_speed == 0) { + return 33333333; + } else if (pci1_speed == 1) { + return 66666666; + } else { + /* Really, unknown. Be safe? */ + return 33333333; + } +} + + +unsigned int +get_pci_slot(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; + + /* + * PCI slot in USER bits CSR[6:7] by convention. + */ + return ((cadmus->cm_csr >> 6) & 0x3) + 1; +} + + +unsigned int +get_pci_dual(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; + + /* + * PCI DUAL in CM_PCI[3] + */ + return cadmus->cm_pci & 0x10; +} |