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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/board/freescale/t208xrdb/ddr.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/board/freescale/t208xrdb/ddr.h')
-rw-r--r-- | roms/u-boot/board/freescale/t208xrdb/ddr.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/roms/u-boot/board/freescale/t208xrdb/ddr.h b/roms/u-boot/board/freescale/t208xrdb/ddr.h new file mode 100644 index 000000000..c00f17816 --- /dev/null +++ b/roms/u-boot/board/freescale/t208xrdb/ddr.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, + {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif |