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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/board/imgtec/xilfpga/xilfpga.c | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/board/imgtec/xilfpga/xilfpga.c')
-rw-r--r-- | roms/u-boot/board/imgtec/xilfpga/xilfpga.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/roms/u-boot/board/imgtec/xilfpga/xilfpga.c b/roms/u-boot/board/imgtec/xilfpga/xilfpga.c new file mode 100644 index 000000000..6a836370e --- /dev/null +++ b/roms/u-boot/board/imgtec/xilfpga/xilfpga.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Imagination Technologies MIPSfpga platform code + * + * Copyright (C) 2016, Imagination Technologies Ltd. + * + * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> + * + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* initialize the DDR Controller and PHY */ +int dram_init(void) +{ + /* MIG IP block is smart and doesn't need SW + * to do any init */ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */ + + return 0; +} |