Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

5 files changed, 212 insertions, 0 deletions

diff --git a/roms/u-boot/board/kobol/helios4/Kconfig b/roms/u-boot/board/kobol/helios4/Kconfig
new file mode 100644
index 000000000..cad51c1cf
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/Kconfig
@@ -0,0 +1,24 @@
+menu "Helios4 configuration"
+	depends on TARGET_HELIOS4
+
+config ENV_SIZE
+	hex "Environment Size"
+	default 0x10000
+
+config ENV_OFFSET
+	hex "Environment offset"
+	default 0xF0000
+
+config ENV_SECT_SIZE
+	hex "Environment Sector-Size"
+	# Use SPI or SATA flash erase block size of 4 KiB
+	default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA
+	# Use optimistic 64 KiB erase block, will vary between actual media
+	default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART
+
+config SYS_SPI_U_BOOT_OFFS
+	hex "address of u-boot payload in SPI flash"
+	default 0x20000
+	depends on MVEBU_SPL_BOOT_DEVICE_SPI
+
+endmenu
diff --git a/roms/u-boot/board/kobol/helios4/MAINTAINERS b/roms/u-boot/board/kobol/helios4/MAINTAINERS
new file mode 100644
index 000000000..c9610deee
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/MAINTAINERS
@@ -0,0 +1,6 @@
+HELIOS4 BOARD
+M:	Dennis Gilmore <dgilmore@redhat.com>
+S:	Maintained
+F:	board/kobol/helios4/
+F:	include/configs/helios4.h
+F:	configs/helios4_defconfig
diff --git a/roms/u-boot/board/kobol/helios4/Makefile b/roms/u-boot/board/kobol/helios4/Makefile
new file mode 100644
index 000000000..63f079639
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
+
+obj-y	:= helios4.o
diff --git a/roms/u-boot/board/kobol/helios4/README b/roms/u-boot/board/kobol/helios4/README
new file mode 100644
index 000000000..749f04827
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/README
@@ -0,0 +1,46 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+Generate the U-Boot image with these commands:
+
+$ make helios4_defconfig
+$ make
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+Now all you need to do is copy this image on a SD card.
+For example with this command:
+
+$ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
+
+Please use the correct device node for your setup instead
+of "/dev/sdX" here!
+
+Boot selection:
+---------------
+
+Before powering up the board, boot selection should be done via the SW1 dip
+switch (0: OFF, 1: ON):
+
+ - SPI:     00010
+ - SD/eMMC: 00111
+ - SATA1:   11100
+ - UART:    11110
+
+Boot from UART:
+---------------
+
+Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
+to your host.
+
+Set the SW1 DIP switches to UART boot (see above).
+
+Run the following command to initiate U-Boot download:
+
+  ./tools/kwboot -p -b u-boot-spl.kwb /dev/ttyUSBX
+
+Use the correct UART device node for /dev/ttyUSBX.
+
+When download finishes start your favorite terminal emulator
+on /dev/ttyUSBX.
diff --git a/roms/u-boot/board/kobol/helios4/helios4.c b/roms/u-boot/board/kobol/helios4/helios4.c
new file mode 100644
index 000000000..9c5b687b3
--- /dev/null
+++ b/roms/u-boot/board/kobol/helios4/helios4.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
+ *  based on board/solidrun/clearfog/clearfog.c
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <init.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
+ */
+#define BOARD_GPP_OUT_ENA_LOW	0xffffffff
+#define BOARD_GPP_OUT_ENA_MID	0xffffffff
+
+#define BOARD_GPP_OUT_VAL_LOW	0x0
+#define BOARD_GPP_OUT_VAL_MID	0x0
+#define BOARD_GPP_POL_LOW	0x0
+#define BOARD_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map[] = {
+	{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct mv_ddr_topology_map board_topology_map = {
+	DEBUG_LEVEL_ERROR,
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    MV_DDR_DEV_WIDTH_16BIT,	/* memory_width */
+	    MV_DDR_DIE_CAP_8GBIT,	/* mem_size */
+	    MV_DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_wl cas_l */
+	    MV_DDR_TEMP_LOW,		/* temperature */
+	    MV_DDR_TIM_DEFAULT} },	/* timing */
+	BUS_MASK_32BIT_ECC,		/* Busses mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+	NOT_COMBINED,			/* ddr twin-die combined */
+	{ {0} },			/* raw spd data */
+	{0}				/* timing parameters */
+};
+
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x10400011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
+	writel(0x44400002, MVEBU_MPP_BASE + 0x10);
+	writel(0x41144004, MVEBU_MPP_BASE + 0x14);
+	writel(0x40333333, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Helios4\n");
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}