Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

9 files changed, 575 insertions, 0 deletions

diff --git a/roms/u-boot/board/kontron/sl28/Kconfig b/roms/u-boot/board/kontron/sl28/Kconfig
new file mode 100644
index 000000000..abcacc318
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/Kconfig
@@ -0,0 +1,61 @@
+if TARGET_SL28
+
+config SYS_BOARD
+	default "sl28"
+
+config SYS_VENDOR
+	default "kontron"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "kontron_sl28"
+
+config SYS_TEXT_BASE
+	default 0x96000000
+
+config SL28_SPL_LOADS_ATF_BL31
+	bool "SPL loads BL31 of the ARM Trusted Firmware"
+	select SPL_ATF
+	select SPL_ATF_LOAD_IMAGE_V2
+	select ARMV8_SEC_FIRMWARE_SUPPORT
+	select SEC_FIRMWARE_ARMV8_PSCI
+	help
+	  Enable this to load a BL31 image by the SPL. You have to
+	  provde a bl31.bin in u-boot's root directory.
+
+if SL28_SPL_LOADS_ATF_BL31
+
+config SL28_BL31_ENTRY_ADDR
+	hex "Entry point of the BL31 image"
+	default 0xfbe00000
+
+endif
+
+config SL28_SPL_LOADS_OPTEE_BL32
+	bool "SPL loads OP-TEE Trusted OS as BL32"
+	depends on SL28_SPL_LOADS_ATF_BL31
+	help
+	  Enable this to load a BL32 image by the SPL. You have to
+	  provde a tee.bin in u-boot's root directory.
+
+if SL28_SPL_LOADS_OPTEE_BL32
+
+config SL28_BL32_ENTRY_ADDR
+	hex "Entry point of the BL32 image"
+	default 0xfc000000
+
+endif
+
+config SL28_ENABLE_SER0_CONSOLE
+	bool "Enable console output on SER0"
+	select DM_SERIAL
+	select SPL_DM_SERIAL
+	select FSL_LPUART
+	help
+	  By default the console output of this board is on the second serial
+	  line (SER1). Sometimes it is desirable to enable output on the first
+	  serial line (SER0). For example, if you have a carrier which only
+	  supports the first serial port.
+endif
diff --git a/roms/u-boot/board/kontron/sl28/MAINTAINERS b/roms/u-boot/board/kontron/sl28/MAINTAINERS
new file mode 100644
index 000000000..a7b0fbbdd
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/MAINTAINERS
@@ -0,0 +1,7 @@
+Kontron SMARC-sAL28 board
+M:	Michael Walle <michael@walle.cc>
+S:	Maintained
+F:	arch/arm/dts/fsl-ls1028a-kontron-sl28-*
+F:	board/kontron/sl28/
+F:	configs/kontron_sl28_defconfig
+F:	include/configs/kontron_sl28.h
diff --git a/roms/u-boot/board/kontron/sl28/Makefile b/roms/u-boot/board/kontron/sl28/Makefile
new file mode 100644
index 000000000..5d220f074
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+ifndef CONFIG_SPL_BUILD
+obj-y += sl28.o cmds.o
+endif
+
+obj-y += common.o ddr.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_SPL_ATF) += spl_atf.o
+endif
diff --git a/roms/u-boot/board/kontron/sl28/cmds.c b/roms/u-boot/board/kontron/sl28/cmds.c
new file mode 100644
index 000000000..046d3b490
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/cmds.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * sl28 extension commands
+ *
+ * Copyright (c) 2020 Kontron Europe GmbH
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+#define CPLD_I2C_ADDR 0x4a
+#define REG_UFM_CTRL 0x02
+#define   UFM_CTRL_DCLK    BIT(1)
+#define   UFM_CTRL_DIN     BIT(2)
+#define   UFM_CTRL_PROGRAM BIT(3)
+#define   UFM_CTRL_ERASE   BIT(4)
+#define   UFM_CTRL_DSHIFT  BIT(5)
+#define   UFM_CTRL_DOUT    BIT(6)
+#define   UFM_CTRL_BUSY    BIT(7)
+
+static int ufm_shift_data(struct udevice *dev, u16 data_in, u16 *data_out)
+{
+	int i;
+	int ret;
+	u16 data = 0;
+
+	/* latch data */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, 0);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	/* assert drshift */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DSHIFT | UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	/* clock 16 data bits, reverse order */
+	for (i = 15; i >= 0; i--) {
+		u8 din = (data_in & (1 << i)) ? UFM_CTRL_DIN : 0;
+
+		ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DSHIFT
+				| din);
+		if (ret < 0)
+			return ret;
+		if (data_out) {
+			ret = dm_i2c_reg_read(dev, REG_UFM_CTRL);
+			if (ret < 0)
+				return ret;
+			if (ret & UFM_CTRL_DOUT)
+				data |= (1 << i);
+		}
+		ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+				       UFM_CTRL_DSHIFT | UFM_CTRL_DCLK | din);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* deassert drshift */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+
+	if (data_out)
+		*data_out = data;
+
+	return ret;
+}
+
+static int ufm_erase(struct udevice *dev)
+{
+	int ret;
+
+	/* erase, tEPMX is 500ms */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DCLK | UFM_CTRL_ERASE);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+	mdelay(500);
+
+	return 0;
+}
+
+static int ufm_program(struct udevice *dev)
+{
+	int ret;
+
+	/* program, tPPMX is 100us */
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL,
+			       UFM_CTRL_DCLK | UFM_CTRL_PROGRAM);
+	if (ret < 0)
+		return ret;
+	ret = dm_i2c_reg_write(dev, REG_UFM_CTRL, UFM_CTRL_DCLK);
+	if (ret < 0)
+		return ret;
+	udelay(100);
+
+	return 0;
+}
+
+static int ufm_write(struct udevice *dev, u16 data)
+{
+	int ret;
+
+	ret = ufm_shift_data(dev, data, NULL);
+	if (ret < 0)
+		return ret;
+
+	ret = ufm_erase(dev);
+	if (ret < 0)
+		return ret;
+
+	return ufm_program(dev);
+}
+
+static int ufm_read(struct udevice *dev, u16 *data)
+{
+	return ufm_shift_data(dev, 0, data);
+}
+
+static int do_sl28_nvm(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	struct udevice *dev;
+	u16 nvm;
+	int ret;
+	char *endp;
+
+	if (i2c_get_chip_for_busnum(0, CPLD_I2C_ADDR, 1, &dev))
+		return CMD_RET_FAILURE;
+
+	if (argc > 1) {
+		nvm = simple_strtoul(argv[1], &endp, 16);
+		if (*endp != '\0') {
+			printf("ERROR: argument is not a valid number\n");
+			ret = -EINVAL;
+			goto out;
+		}
+
+		/*
+		 * We swap all bits, because the a zero bit in hardware means the
+		 * feature is enabled. But this is hard for the user.
+		 */
+		nvm ^= 0xffff;
+
+		ret = ufm_write(dev, nvm);
+		if (ret)
+			goto out;
+		printf("New settings will be activated after the next power cycle!\n");
+	} else {
+		ret = ufm_read(dev, &nvm);
+		if (ret)
+			goto out;
+		nvm ^= 0xffff;
+
+		printf("%04hx\n", nvm);
+	}
+
+	return CMD_RET_SUCCESS;
+
+out:
+	printf("command failed (%d)\n", ret);
+	return CMD_RET_FAILURE;
+}
+
+static char sl28_help_text[] =
+	"nvm [<hex>] - display/set the 16 non-volatile bits\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(sl28, "SMARC-sAL28 specific", sl28_help_text,
+			U_BOOT_SUBCMD_MKENT(nvm, 2, 1, do_sl28_nvm));
diff --git a/roms/u-boot/board/kontron/sl28/common.c b/roms/u-boot/board/kontron/sl28/common.c
new file mode 100644
index 000000000..33c6843c3
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/common.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
+}
diff --git a/roms/u-boot/board/kontron/sl28/ddr.c b/roms/u-boot/board/kontron/sl28/ddr.c
new file mode 100644
index 000000000..41426996a
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/ddr.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <fsl_ddr_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DCFG_GPPORCR1 0x20
+
+#define GPPORCR1_MEM_MASK		(0x7 << 5)
+#define GPPORCR1_MEM_512MB_CS0		(0x0 << 5)
+#define GPPORCR1_MEM_1GB_CS0		(0x1 << 5)
+#define GPPORCR1_MEM_2GB_CS0		(0x2 << 5)
+#define GPPORCR1_MEM_4GB_CS0_1		(0x3 << 5)
+#define GPPORCR1_MEM_4GB_CS0_2		(0x4 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1_2_3	(0x5 << 5)
+#define GPPORCR1_MEM_8GB_CS0_1		(0x6 << 5)
+
+static fsl_ddr_cfg_regs_t __maybe_unused ddr_cfg_regs = {
+	.cs[0].bnds		= 0x0000007f,
+	.cs[0].config		= 0x80044402,
+	.cs[1].bnds		= 0x008000ff,
+	.cs[1].config		= 0x80004402,
+
+	.timing_cfg_0		= 0x9011010c,
+	.timing_cfg_3		= 0x010c1000,
+	.timing_cfg_1		= 0xbcb48c66,
+	.timing_cfg_2		= 0x0fc0d118,
+	.ddr_sdram_cfg		= 0xe70c000c,
+	.ddr_sdram_cfg_2	= 0x24401111,
+	.ddr_sdram_mode		= 0x00441c70,
+	.ddr_sdram_mode_3	= 0x00001c70,
+	.ddr_sdram_mode_5	= 0x00001c70,
+	.ddr_sdram_mode_7	= 0x00001c70,
+	.ddr_sdram_mode_2	= 0x00180000,
+	.ddr_sdram_mode_4	= 0x00180000,
+	.ddr_sdram_mode_6	= 0x00180000,
+	.ddr_sdram_mode_8	= 0x00180000,
+
+	.ddr_sdram_interval	= 0x0c30030c,
+	.ddr_data_init		= 0xdeadbeef,
+
+	.ddr_sdram_clk_cntl	= 0x02400000,
+
+	.timing_cfg_4		= 0x00000001,
+	.timing_cfg_5		= 0x04401400,
+
+	.ddr_zq_cntl		= 0x89080600,
+	.ddr_wrlvl_cntl		= 0x8675f606,
+	.ddr_wrlvl_cntl_2	= 0x04080700,
+	.ddr_wrlvl_cntl_3	= 0x00000009,
+
+	.ddr_cdr1		= 0x80040000,
+	.ddr_cdr2		= 0x0000bc01,
+};
+
+int fsl_initdram(void)
+{
+	u32 gpporcr1 = in_le32(DCFG_BASE + DCFG_GPPORCR1);
+	phys_size_t dram_size;
+
+	switch (gpporcr1 & GPPORCR1_MEM_MASK) {
+	case GPPORCR1_MEM_2GB_CS0:
+		dram_size = 0x80000000;
+		ddr_cfg_regs.cs[1].bnds = 0;
+		ddr_cfg_regs.cs[1].config = 0;
+		ddr_cfg_regs.cs[1].config_2 = 0;
+		break;
+	case GPPORCR1_MEM_4GB_CS0_1:
+		dram_size = 0x100000000ULL;
+		break;
+	case GPPORCR1_MEM_512MB_CS0:
+		dram_size = 0x20000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_1GB_CS0:
+		dram_size = 0x40000000;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_4GB_CS0_2:
+		dram_size = 0x100000000ULL;
+		fallthrough; /* for now */
+	case GPPORCR1_MEM_8GB_CS0_1:
+	case GPPORCR1_MEM_8GB_CS0_1_2_3:
+		dram_size = 0x200000000ULL;
+		fallthrough; /* for now */
+	default:
+		panic("Unsupported memory configuration (%08x)\n",
+		      gpporcr1 & GPPORCR1_MEM_MASK);
+		break;
+	}
+
+	if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD))
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kontron/sl28/sl28.c b/roms/u-boot/board/kontron/sl28/sl28.c
new file mode 100644
index 000000000..c8ed7ac81
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/sl28.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+int board_init(void)
+{
+	if (CONFIG_IS_ENABLED(FSL_CAAM))
+		sec_init();
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int checkboard(void)
+{
+	printf("EL:    %d\n", current_el());
+	return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+	print_ddr_info(0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int nbanks = CONFIG_NR_DRAM_BANKS;
+	int node;
+	int i;
+
+	ft_cpu_setup(blob, bd);
+
+	/* fixup DT for the two GPP DDR banks */
+	for (i = 0; i < nbanks; i++) {
+		base[i] = gd->bd->bi_dram[i].start;
+		size[i] = gd->bd->bi_dram[i].size;
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, nbanks);
+
+	fdt_fixup_icid(blob);
+
+	if (CONFIG_IS_ENABLED(SL28_SPL_LOADS_OPTEE_BL32)) {
+		node = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
+		if (node)
+			fdt_set_node_status(blob, node, FDT_STATUS_OKAY, 0);
+	}
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kontron/sl28/spl.c b/roms/u-boot/board/kontron/sl28/spl.c
new file mode 100644
index 000000000..0e6ad5f37
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/spl.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch-fsl-layerscape/fsl_serdes.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+
+#define DCFG_RCWSR25 0x160
+#define GPINFO_HW_VARIANT_MASK 0xff
+
+#define SERDES_LNDGCR0		0x1ea08c0
+#define   LNDGCR0_PROTS_MASK	GENMASK(11, 7)
+#define   LNDGCR0_PROTS_SATA	(0x2 << 7)
+#define SERDES_LNDGCR1		0x1ea08c4
+#define   LNDGCR1_RDAT_INV	BIT(31)
+
+/*
+ * On this board the SMARC PCIe lane D might be switched to SATA mode. This
+ * makes sense if this lane is connected to a Mini PCI slot and a mSATA card
+ * is plugged in. In this case, the RX pair is swapped and we need to invert
+ * the received data.
+ */
+static void fixup_sata_rx_polarity(void)
+{
+	u32 prot = in_le32(SERDES_LNDGCR0) & LNDGCR0_PROTS_MASK;
+	u32 tmp;
+
+	if (prot == LNDGCR0_PROTS_SATA) {
+		tmp = in_le32(SERDES_LNDGCR1);
+		tmp |= LNDGCR1_RDAT_INV;
+		out_le32(SERDES_LNDGCR1, tmp);
+	}
+}
+
+int sl28_variant(void)
+{
+	return in_le32(DCFG_BASE + DCFG_RCWSR25) & GPINFO_HW_VARIANT_MASK;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	int variant = sl28_variant();
+
+	switch (variant) {
+	case 1:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var1");
+	case 2:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var2");
+	case 3:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var3");
+	case 4:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28-var4");
+	default:
+		return strcmp(name, "fsl-ls1028a-kontron-sl28");
+	}
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_SPI;
+}
+
+int board_early_init_f(void)
+{
+	fixup_sata_rx_polarity();
+	fsl_lsch3_early_init_f();
+
+	return 0;
+}
diff --git a/roms/u-boot/board/kontron/sl28/spl_atf.c b/roms/u-boot/board/kontron/sl28/spl_atf.c
new file mode 100644
index 000000000..a9cd6850e
--- /dev/null
+++ b/roms/u-boot/board/kontron/sl28/spl_atf.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LS1028A TF-A calling support
+ *
+ * Copyright (c) 2020 Michael Walle <michael@walle.cc>
+ */
+
+#include <common.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <atf_common.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct region_info {
+	u64 addr;
+	u64 size;
+};
+
+struct dram_regions_info {
+	u64 num_dram_regions;
+	u64 total_dram_size;
+	struct region_info region[CONFIG_NR_DRAM_BANKS];
+};
+
+struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry,
+					      uintptr_t bl33_entry,
+					      uintptr_t fdt_addr)
+{
+	static struct dram_regions_info dram_regions_info = { 0 };
+	struct bl_params *bl_params;
+	struct bl_params_node *node;
+	void *dcfg_ccsr = (void *)DCFG_BASE;
+	int i;
+
+	dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start;
+		dram_regions_info.region[i].size = gd->bd->bi_dram[i].size;
+		dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size;
+	}
+
+	bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry,
+							fdt_addr);
+
+	for_each_bl_params_node(bl_params, node) {
+		if (node->image_id == ATF_BL31_IMAGE_ID) {
+			node->ep_info->args.arg3 = (uintptr_t)&dram_regions_info;
+			node->ep_info->args.arg4 = in_le32(dcfg_ccsr + DCFG_PORSR1);
+		}
+	}
+
+	return bl_params;
+}