diff options
| author |   Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
|---|---|---|
| committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
| commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
| tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/board/renesas/draak | |
| parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) | |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/board/renesas/draak')
| -rw-r--r-- | roms/u-boot/board/renesas/draak/Kconfig | 15 | ||||
| -rw-r--r-- | roms/u-boot/board/renesas/draak/MAINTAINERS | 6 | ||||
| -rw-r--r-- | roms/u-boot/board/renesas/draak/Makefile | 13 | ||||
| -rw-r--r-- | roms/u-boot/board/renesas/draak/draak.c | 81 |
4 files changed, 115 insertions, 0 deletions
diff --git a/roms/u-boot/board/renesas/draak/Kconfig b/roms/u-boot/board/renesas/draak/Kconfig new file mode 100644 index 000000000..9106387bb --- /dev/null +++ b/roms/u-boot/board/renesas/draak/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DRAAK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "draak" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "draak" + +endif diff --git a/roms/u-boot/board/renesas/draak/MAINTAINERS b/roms/u-boot/board/renesas/draak/MAINTAINERS new file mode 100644 index 000000000..1dbcc2811 --- /dev/null +++ b/roms/u-boot/board/renesas/draak/MAINTAINERS @@ -0,0 +1,6 @@ +DRAAK BOARD +M: Marek Vasut <marek.vasut+renesas@gmail.com> +S: Maintained +F: board/renesas/draak/ +F: include/configs/draak.h +F: configs/r8a77995_draak_defconfig diff --git a/roms/u-boot/board/renesas/draak/Makefile b/roms/u-boot/board/renesas/draak/Makefile new file mode 100644 index 000000000..1fc90d1da --- /dev/null +++ b/roms/u-boot/board/renesas/draak/Makefile @@ -0,0 +1,13 @@ +# +# board/renesas/draak/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := draak.o ../rcar-common/common.o +endif diff --git a/roms/u-boot/board/renesas/draak/draak.c b/roms/u-boot/board/renesas/draak/draak.c new file mode 100644 index 000000000..1d76f95ae --- /dev/null +++ b/roms/u-boot/board/renesas/draak/draak.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * board/renesas/draak/draak.c + * This file is Draak board support. + * + * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> + */ + +#include <common.h> +#include <cpu_func.h> +#include <hang.h> +#include <init.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <asm/global_data.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GSX_MSTP112 BIT(12) /* 3DG */ +#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ +#define DVFS_MSTP926 BIT(26) +#define HSUSB_MSTP704 BIT(4) /* HSUSB */ + +int board_early_init_f(void) +{ +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); +#endif + return 0; +} + +/* HSUSB block registers */ +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + + /* Configure the HSUSB block */ + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(void) +{ + writel(RST_CA53_CODE, RST_CA53RESCNT); +} |