Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

90 files changed, 92250 insertions, 0 deletions

diff --git a/roms/u-boot/board/xilinx/Kconfig b/roms/u-boot/board/xilinx/Kconfig
new file mode 100644
index 000000000..64507b5d8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/Kconfig
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2018, Luca Ceresoli <luca@lucaceresoli.net>
+
+if ARCH_ZYNQ || ARCH_ZYNQMP
+
+config XILINX_PS_INIT_FILE
+	string "Zynq/ZynqMP PS init file(s) location"
+	help
+	  On Zynq and ZynqMP U-Boot SPL (or U-Boot proper if
+	  ZYNQMP_PSU_INIT_ENABLED is set) is responsible for some
+	  basic initializations, such as enabling peripherals and
+	  configuring pinmuxes. The PS init file (called
+	  psu_init_gpl.c on ZynqMP, ps7_init_gpl.c for Zynq-7000)
+	  contains the code for such initializations.
+
+	  U-Boot contains PS init files for some boards, but each of
+	  them describes only one specific configuration. Users of a
+	  different board, or needing a different configuration, can
+	  generate custom files using the Xilinx development tools.
+
+	  There are three ways to give a PS init file to U-Boot:
+
+	  1. Set this variable to the path, either relative to the
+	     source tree or absolute, where the psu_init_gpl.c or
+	     ps7_init_gpl.c file is located. U-Boot will build this
+	     file.
+
+	  2. If you leave an empty string here, U-Boot will use
+	     board/xilinx/zynq/$(CONFIG_DEFAULT_DEVICE_TREE)/ps7_init_gpl.c
+	     for Zynq-7000, or
+	     board/xilinx/zynqmp/$(CONFIG_DEFAULT_DEVICE_TREE)/psu_init_gpl.c
+	     for ZynqMP.
+
+	  3. If the above file does not exist, U-Boot will use
+	     board/xilinx/zynq/ps7_init_gpl.c for Zynq-7000, or
+	     board/xilinx/zynqmp/psu_init_gpl.c for ZynqMP. This file
+	     is not provided by U-Boot, you have to copy it there
+	     before the build.
+
+endif
+
+config XILINX_OF_BOARD_DTB_ADDR
+	hex "Default DTB pickup address"
+	default 0x1000 if ARCH_VERSAL
+	default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
+	depends on OF_BOARD || OF_SEPARATE
+	help
+	  Offset in the memory where the board configuration DTB is placed.
+
+config BOOT_SCRIPT_OFFSET
+	hex "Boot script offset"
+	depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || MICROBLAZE
+	default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
+	default 0x3E80000 if ARCH_ZYNQMP
+	default 0x7F80000 if ARCH_VERSAL
+	help
+	   Specifies distro boot script offset in NAND/QSPI/NOR flash.
+
+config ZYNQ_MAC_IN_EEPROM
+	bool "Reading MAC address from EEPROM"
+	help
+	  Enable this option if your MAC address is saved in eeprom and
+	  xlnx,eeprom DT property in chosen node points to it.
+
+if ZYNQ_MAC_IN_EEPROM
+
+config ZYNQ_GEM_I2C_MAC_OFFSET
+	hex "Set the I2C MAC offset"
+	default 0x0
+	depends on DM_I2C
+	help
+	  Set the MAC offset for i2C.
+
+endif
+
+config CMD_FRU
+	bool "FRU information for product"
+	help
+	  This option enables FRU commands to capture and display FRU
+	  information present in the device. The FRU Information is used
+	  to primarily to provide "inventory" information about the boards
+	  that the FRU Information Device is located on.
diff --git a/roms/u-boot/board/xilinx/bootscripts/qspiboot.cmd b/roms/u-boot/board/xilinx/bootscripts/qspiboot.cmd
new file mode 100644
index 000000000..c10341c4d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/bootscripts/qspiboot.cmd
@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d qspiboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# fdt_addr, fdt_offset, fdt_size, kernel_addr, kernel_offset, kernel_size
+#
+sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && sf read $kernel_addr $kernel_offset $kernel_size && booti $kernel_addr - $fdt_addr
diff --git a/roms/u-boot/board/xilinx/bootscripts/sdboot.cmd b/roms/u-boot/board/xilinx/bootscripts/sdboot.cmd
new file mode 100644
index 000000000..0031900db
--- /dev/null
+++ b/roms/u-boot/board/xilinx/bootscripts/sdboot.cmd
@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d sdboot.cmd boot.scr
+#
+# It requires a list of environment variables used below to be defined
+# before load
+#
+mmc dev $devnum && mmcinfo && run uenvboot || run sdroot$devnum;load mmc $devnum:$partid $fdt_addr system.dtb && load mmc $devnum:$partid $kernel_addr Image && booti $kernel_addr - $fdt_addr
diff --git a/roms/u-boot/board/xilinx/common/Makefile b/roms/u-boot/board/xilinx/common/Makefile
new file mode 100644
index 000000000..212028478
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2020 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y	+= board.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_FRU) += fru.o fru_ops.o
+endif
diff --git a/roms/u-boot/board/xilinx/common/board.c b/roms/u-boot/board/xilinx/common/board.c
new file mode 100644
index 000000000..92b61d83c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/board.c
@@ -0,0 +1,442 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include "board.h"
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <net.h>
+#include <generated/dt.h>
+
+#include "fru.h"
+
+#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+	int ret = -EINVAL;
+	struct udevice *dev;
+	ofnode eeprom;
+
+	eeprom = ofnode_get_chosen_node("xlnx,eeprom");
+	if (!ofnode_valid(eeprom))
+		return -ENODEV;
+
+	debug("%s: Path to EEPROM %s\n", __func__,
+	      ofnode_read_chosen_string("xlnx,eeprom"));
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+	if (ret)
+		return ret;
+
+	ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6);
+	if (ret)
+		debug("%s: I2C EEPROM MAC address read failed\n", __func__);
+	else
+		debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
+
+	return ret;
+}
+#endif
+
+#define EEPROM_HEADER_MAGIC		0xdaaddeed
+#define EEPROM_HDR_MANUFACTURER_LEN	16
+#define EEPROM_HDR_NAME_LEN		16
+#define EEPROM_HDR_REV_LEN		8
+#define EEPROM_HDR_SERIAL_LEN		20
+#define EEPROM_HDR_NO_OF_MAC_ADDR	4
+#define EEPROM_HDR_ETH_ALEN		ETH_ALEN
+
+struct xilinx_board_description {
+	u32 header;
+	char manufacturer[EEPROM_HDR_MANUFACTURER_LEN + 1];
+	char name[EEPROM_HDR_NAME_LEN + 1];
+	char revision[EEPROM_HDR_REV_LEN + 1];
+	char serial[EEPROM_HDR_SERIAL_LEN + 1];
+	u8 mac_addr[EEPROM_HDR_NO_OF_MAC_ADDR][EEPROM_HDR_ETH_ALEN + 1];
+};
+
+static int highest_id = -1;
+static struct xilinx_board_description **board_info;
+
+#define XILINX_I2C_DETECTION_BITS	sizeof(struct fru_common_hdr)
+
+/* Variable which stores pointer to array which stores eeprom content */
+struct xilinx_legacy_format {
+	char board_sn[18]; /* 0x0 */
+	char unused0[14]; /* 0x12 */
+	char eth_mac[6]; /* 0x20 */
+	char unused1[170]; /* 0x26 */
+	char board_name[11]; /* 0xd0 */
+	char unused2[5]; /* 0xdc */
+	char board_revision[3]; /* 0xe0 */
+	char unused3[29]; /* 0xe3 */
+};
+
+static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size)
+{
+	int i;
+	char byte;
+
+	for (i = 0; i < size; i++) {
+		byte = eeprom[i];
+
+		/* Remove all ffs and spaces */
+		if (byte == 0xff || byte == ' ')
+			eeprom[i] = 0;
+
+		/* Convert strings to lower case */
+		if (byte >= 'A' && byte <= 'Z')
+			eeprom[i] = byte + 'a' - 'A';
+	}
+}
+
+static int xilinx_read_eeprom_legacy(struct udevice *dev, char *name,
+				     struct xilinx_board_description *desc)
+{
+	int ret, size;
+	struct xilinx_legacy_format *eeprom_content;
+	bool eth_valid = false;
+
+	size = sizeof(*eeprom_content);
+
+	eeprom_content = calloc(1, size);
+	if (!eeprom_content)
+		return -ENOMEM;
+
+	debug("%s: I2C EEPROM read pass data at %p\n", __func__,
+	      eeprom_content);
+
+	ret = dm_i2c_read(dev, 0, (uchar *)eeprom_content, size);
+	if (ret) {
+		debug("%s: I2C EEPROM read failed\n", __func__);
+		free(eeprom_content);
+		return ret;
+	}
+
+	xilinx_eeprom_legacy_cleanup((char *)eeprom_content, size);
+
+	printf("Xilinx I2C Legacy format at %s:\n", name);
+	printf(" Board name:\t%s\n", eeprom_content->board_name);
+	printf(" Board rev:\t%s\n", eeprom_content->board_revision);
+	printf(" Board SN:\t%s\n", eeprom_content->board_sn);
+
+	eth_valid = is_valid_ethaddr((const u8 *)eeprom_content->eth_mac);
+	if (eth_valid)
+		printf(" Ethernet mac:\t%pM\n", eeprom_content->eth_mac);
+
+	/* Terminating \0 chars ensure end of string */
+	strcpy(desc->name, eeprom_content->board_name);
+	strcpy(desc->revision, eeprom_content->board_revision);
+	strcpy(desc->serial, eeprom_content->board_sn);
+	if (eth_valid)
+		memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN);
+
+	desc->header = EEPROM_HEADER_MAGIC;
+
+	free(eeprom_content);
+
+	return ret;
+}
+
+static bool xilinx_detect_legacy(u8 *buffer)
+{
+	int i;
+	char c;
+
+	for (i = 0; i < XILINX_I2C_DETECTION_BITS; i++) {
+		c = buffer[i];
+
+		if (c < '0' || c > '9')
+			return false;
+	}
+
+	return true;
+}
+
+static int xilinx_read_eeprom_fru(struct udevice *dev, char *name,
+				  struct xilinx_board_description *desc)
+{
+	int ret, eeprom_size;
+	u8 *fru_content;
+
+	/* FIXME this is shortcut - if eeprom type is wrong it will fail */
+	eeprom_size = i2c_eeprom_size(dev);
+
+	fru_content = calloc(1, eeprom_size);
+	if (!fru_content)
+		return -ENOMEM;
+
+	debug("%s: I2C EEPROM read pass data at %p\n", __func__,
+	      fru_content);
+
+	ret = dm_i2c_read(dev, 0, (uchar *)fru_content,
+			  eeprom_size);
+	if (ret) {
+		debug("%s: I2C EEPROM read failed\n", __func__);
+		free(fru_content);
+		return ret;
+	}
+
+	printf("Xilinx I2C FRU format at %s:\n", name);
+	fru_capture((unsigned long)fru_content);
+	ret = fru_display(0);
+	if (ret) {
+		printf("FRU format decoding failed.\n");
+		return ret;
+	}
+
+	if (desc->header == EEPROM_HEADER_MAGIC) {
+		debug("Information already filled\n");
+		return -EINVAL;
+	}
+
+	/* It is clear that FRU was captured and structures were filled */
+	strncpy(desc->manufacturer, (char *)fru_data.brd.manufacturer_name,
+		sizeof(desc->manufacturer));
+	strncpy(desc->name, (char *)fru_data.brd.product_name,
+		sizeof(desc->name));
+	strncpy(desc->revision, (char *)fru_data.brd.rev,
+		sizeof(desc->revision));
+	strncpy(desc->serial, (char *)fru_data.brd.serial_number,
+		sizeof(desc->serial));
+	desc->header = EEPROM_HEADER_MAGIC;
+
+	return 0;
+}
+
+static bool xilinx_detect_fru(u8 *buffer)
+{
+	u8 checksum = 0;
+	int i;
+
+	checksum = fru_checksum((u8 *)buffer, sizeof(struct fru_common_hdr));
+	if (checksum) {
+		debug("%s Common header CRC FAIL\n", __func__);
+		return false;
+	}
+
+	bool all_zeros = true;
+	/* Checksum over all zeros is also zero that's why detect this case */
+	for (i = 0; i < sizeof(struct fru_common_hdr); i++) {
+		if (buffer[i] != 0)
+			all_zeros = false;
+	}
+
+	if (all_zeros)
+		return false;
+
+	debug("%s Common header CRC PASS\n", __func__);
+	return true;
+}
+
+static int xilinx_read_eeprom_single(char *name,
+				     struct xilinx_board_description *desc)
+{
+	int ret;
+	struct udevice *dev;
+	ofnode eeprom;
+	u8 buffer[XILINX_I2C_DETECTION_BITS];
+
+	eeprom = ofnode_get_aliases_node(name);
+	if (!ofnode_valid(eeprom))
+		return -ENODEV;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+	if (ret)
+		return ret;
+
+	ret = dm_i2c_read(dev, 0, buffer, sizeof(buffer));
+	if (ret) {
+		debug("%s: I2C EEPROM read failed\n", __func__);
+		return ret;
+	}
+
+	debug("%s: i2c memory detected: %s\n", __func__, name);
+
+	if (CONFIG_IS_ENABLED(CMD_FRU) && xilinx_detect_fru(buffer))
+		return xilinx_read_eeprom_fru(dev, name, desc);
+
+	if (xilinx_detect_legacy(buffer))
+		return xilinx_read_eeprom_legacy(dev, name, desc);
+
+	return -ENODEV;
+}
+
+__maybe_unused int xilinx_read_eeprom(void)
+{
+	int id, ret;
+	char name_buf[8]; /* 8 bytes should be enough for nvmem+number */
+	struct xilinx_board_description *desc;
+
+	highest_id = dev_read_alias_highest_id("nvmem");
+	/* No nvmem aliases present */
+	if (highest_id < 0)
+		return -EINVAL;
+
+	board_info = calloc(1, sizeof(desc) * highest_id);
+	if (!board_info)
+		return -ENOMEM;
+
+	debug("%s: Highest ID %d, board_info %p\n", __func__,
+	      highest_id, board_info);
+
+	for (id = 0; id <= highest_id; id++) {
+		snprintf(name_buf, sizeof(name_buf), "nvmem%d", id);
+
+		/* Alloc structure */
+		desc = board_info[id];
+		if (!desc) {
+			desc = calloc(1, sizeof(*desc));
+			if (!desc)
+				return -ENOMEM;
+
+			board_info[id] = desc;
+		}
+
+		/* Ignoring return value for supporting multiple chips */
+		ret = xilinx_read_eeprom_single(name_buf, desc);
+		if (ret) {
+			free(desc);
+			board_info[id] = NULL;
+		}
+	}
+
+	/*
+	 * Consider to clean board_info structure when board/cards are not
+	 * detected.
+	 */
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
+void *board_fdt_blob_setup(void)
+{
+	void *fdt_blob;
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+	    !IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
+	    !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
+		fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+
+		if (fdt_magic(fdt_blob) == FDT_MAGIC)
+			return fdt_blob;
+
+		debug("DTB is not passed via %p\n", fdt_blob);
+	}
+
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		/*
+		 * FDT is at end of BSS unless it is in a different memory
+		 * region
+		 */
+		if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
+			fdt_blob = (ulong *)&_image_binary_end;
+		else
+			fdt_blob = (ulong *)&__bss_end;
+	} else {
+		/* FDT is at end of image */
+		fdt_blob = (ulong *)&_end;
+	}
+
+	if (fdt_magic(fdt_blob) == FDT_MAGIC)
+		return fdt_blob;
+
+	debug("DTB is also not passed via %p\n", fdt_blob);
+
+	return NULL;
+}
+#endif
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+static int env_set_by_index(const char *name, int index, char *data)
+{
+	char var[32];
+
+	if (!index)
+		sprintf(var, "board_%s", name);
+	else
+		sprintf(var, "card%d_%s", index, name);
+
+	return env_set(var, data);
+}
+
+int board_late_init_xilinx(void)
+{
+	u32 ret = 0;
+	int i, id, macid = 0;
+	struct xilinx_board_description *desc;
+	phys_size_t bootm_size = gd->ram_size;
+
+	if (!CONFIG_IS_ENABLED(MICROBLAZE)) {
+		ulong scriptaddr;
+
+		scriptaddr = env_get_hex("scriptaddr", 0);
+		ret |= env_set_hex("scriptaddr", gd->ram_base + scriptaddr);
+	}
+
+	if (CONFIG_IS_ENABLED(ARCH_ZYNQ) || CONFIG_IS_ENABLED(MICROBLAZE))
+		bootm_size = min(bootm_size, (phys_size_t)(SZ_512M + SZ_256M));
+
+	ret |= env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
+
+	ret |= env_set_addr("bootm_low", (void *)gd->ram_base);
+	ret |= env_set_addr("bootm_size", (void *)bootm_size);
+
+	for (id = 0; id <= highest_id; id++) {
+		desc = board_info[id];
+		if (desc && desc->header == EEPROM_HEADER_MAGIC) {
+			if (desc->manufacturer[0])
+				ret |= env_set_by_index("manufacturer", id,
+							desc->manufacturer);
+			if (desc->name[0])
+				ret |= env_set_by_index("name", id,
+							desc->name);
+			if (desc->revision[0])
+				ret |= env_set_by_index("rev", id,
+							desc->revision);
+			if (desc->serial[0])
+				ret |= env_set_by_index("serial", id,
+							desc->serial);
+
+			if (!CONFIG_IS_ENABLED(NET))
+				continue;
+
+			for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) {
+				if (!desc->mac_addr[i])
+					continue;
+
+				if (is_valid_ethaddr((const u8 *)desc->mac_addr[i]))
+					ret |= eth_env_set_enetaddr_by_index("eth",
+							macid++, desc->mac_addr[i]);
+			}
+		}
+	}
+
+	if (ret)
+		printf("%s: Saving run time variables FAILED\n", __func__);
+
+	return 0;
+}
+#endif
+
+int __maybe_unused board_fit_config_name_match(const char *name)
+{
+	debug("%s: Check %s, default %s\n", __func__, name, DEVICE_TREE);
+
+	if (!strcmp(name, DEVICE_TREE))
+		return 0;
+
+	return -1;
+}
diff --git a/roms/u-boot/board/xilinx/common/board.h b/roms/u-boot/board/xilinx/common/board.h
new file mode 100644
index 000000000..69e642429
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/board.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#ifndef _BOARD_XILINX_COMMON_BOARD_H
+#define _BOARD_XILINX_COMMON_BOARD_H
+
+int board_late_init_xilinx(void);
+
+int xilinx_read_eeprom(void);
+
+#endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/roms/u-boot/board/xilinx/common/fru.c b/roms/u-boot/board/xilinx/common/fru.c
new file mode 100644
index 000000000..ccf48723f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/fru.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 - 2020 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdtdec.h>
+#include <malloc.h>
+
+#include "fru.h"
+
+static int do_fru_capture(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	unsigned long addr;
+	char *endp;
+
+	if (argc < cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], &endp, 16);
+	if (*argv[1] == 0 || *endp != 0)
+		return -1;
+
+	return fru_capture(addr);
+}
+
+static int do_fru_display(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	fru_display(1);
+	return CMD_RET_SUCCESS;
+}
+
+static int do_fru_generate(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	unsigned long addr;
+
+	if (argc < cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+
+	return fru_generate(addr, argv[3], argv[4], argv[5], argv[6], argv[7]);
+}
+
+static struct cmd_tbl cmd_fru_sub[] = {
+	U_BOOT_CMD_MKENT(capture, 3, 0, do_fru_capture, "", ""),
+	U_BOOT_CMD_MKENT(display, 2, 0, do_fru_display, "", ""),
+	U_BOOT_CMD_MKENT(board_gen, 8, 0, do_fru_generate, "", ""),
+};
+
+static int do_fru(struct cmd_tbl *cmdtp, int flag, int argc,
+		  char *const argv[])
+{
+	struct cmd_tbl *c;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	c = find_cmd_tbl(argv[1], &cmd_fru_sub[0],
+			 ARRAY_SIZE(cmd_fru_sub));
+	if (!c)
+		return CMD_RET_USAGE;
+
+	ret = c->cmd(c, flag, argc, argv);
+
+	return cmd_process_error(c, ret);
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char fru_help_text[] =
+	"capture <addr> - Parse and capture FRU table present at address.\n"
+	"fru display - Displays content of FRU table that was captured using\n"
+	"              fru capture command\n"
+	"fru board_gen <addr> <manufacturer> <board name> <serial number>\n"
+	"              <part number> <revision> - Generate FRU format with\n"
+	"              board info area filled based on parameters. <addr> is\n"
+	"              pointing to place where FRU is generated.\n"
+	;
+#endif
+
+U_BOOT_CMD(
+	fru, 8, 1, do_fru,
+	"FRU table info",
+	fru_help_text
+)
diff --git a/roms/u-boot/board/xilinx/common/fru.h b/roms/u-boot/board/xilinx/common/fru.h
new file mode 100644
index 000000000..e7284709d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/fru.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#ifndef __FRU_H
+#define __FRU_H
+
+struct fru_common_hdr {
+	u8 version;
+	u8 off_internal;
+	u8 off_chassis;
+	u8 off_board;
+	u8 off_product;
+	u8 off_multirec;
+	u8 pad;
+	u8 crc;
+};
+
+#define FRU_BOARD_MAX_LEN	32
+
+struct __packed fru_board_info_header {
+	u8 ver;
+	u8 len;
+	u8 lang_code;
+	u8 time[3];
+};
+
+struct __packed fru_board_info_member {
+	u8 type_len;
+	u8 *name;
+};
+
+struct fru_board_data {
+	u8 ver;
+	u8 len;
+	u8 lang_code;
+	u8 time[3];
+	u8 manufacturer_type_len;
+	u8 manufacturer_name[FRU_BOARD_MAX_LEN];
+	u8 product_name_type_len;
+	u8 product_name[FRU_BOARD_MAX_LEN];
+	u8 serial_number_type_len;
+	u8 serial_number[FRU_BOARD_MAX_LEN];
+	u8 part_number_type_len;
+	u8 part_number[FRU_BOARD_MAX_LEN];
+	u8 file_id_type_len;
+	u8 file_id[FRU_BOARD_MAX_LEN];
+	/* Xilinx custom fields */
+	u8 rev_type_len;
+	u8 rev[FRU_BOARD_MAX_LEN];
+	u8 pcie_type_len;
+	u8 pcie[FRU_BOARD_MAX_LEN];
+	u8 uuid_type_len;
+	u8 uuid[FRU_BOARD_MAX_LEN];
+};
+
+struct fru_table {
+	struct fru_common_hdr hdr;
+	struct fru_board_data brd;
+	bool captured;
+};
+
+#define FRU_TYPELEN_CODE_MASK	0xC0
+#define FRU_TYPELEN_LEN_MASK	0x3F
+#define FRU_COMMON_HDR_VER_MASK		0xF
+#define FRU_COMMON_HDR_LEN_MULTIPLIER	8
+#define FRU_LANG_CODE_ENGLISH		0
+#define FRU_LANG_CODE_ENGLISH_1		25
+#define FRU_TYPELEN_EOF			0xC1
+
+/* This should be minimum of fields */
+#define FRU_BOARD_AREA_TOTAL_FIELDS	5
+#define FRU_TYPELEN_TYPE_SHIFT		6
+#define FRU_TYPELEN_TYPE_BINARY		0
+#define FRU_TYPELEN_TYPE_ASCII8		3
+
+int fru_display(int verbose);
+int fru_capture(unsigned long addr);
+int fru_generate(unsigned long addr, char *manufacturer, char *board_name,
+		 char *serial_no, char *part_no, char *revision);
+u8 fru_checksum(u8 *addr, u8 len);
+
+extern struct fru_table fru_data;
+
+#endif /* FRU_H */
diff --git a/roms/u-boot/board/xilinx/common/fru_ops.c b/roms/u-boot/board/xilinx/common/fru_ops.c
new file mode 100644
index 000000000..6ed63bb7e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/common/fru_ops.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 - 2020 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include "fru.h"
+
+struct fru_table fru_data __section(".data");
+
+static u16 fru_cal_area_len(u8 len)
+{
+	return len * FRU_COMMON_HDR_LEN_MULTIPLIER;
+}
+
+static u8 fru_version(u8 ver)
+{
+	return ver & FRU_COMMON_HDR_VER_MASK;
+}
+
+static int fru_check_language(u8 code)
+{
+	if (code != FRU_LANG_CODE_ENGLISH && code != FRU_LANG_CODE_ENGLISH_1) {
+		printf("FRU_ERROR: Only English Language is supported\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+u8 fru_checksum(u8 *addr, u8 len)
+{
+	u8 checksum = 0;
+
+	while (len--) {
+		checksum += *addr;
+		addr++;
+	}
+
+	return checksum;
+}
+
+static int fru_check_type_len(u8 type_len, u8 language, u8 *type)
+{
+	int len;
+
+	if (type_len == FRU_TYPELEN_EOF)
+		return -EINVAL;
+
+	*type = (type_len & FRU_TYPELEN_CODE_MASK) >> FRU_TYPELEN_TYPE_SHIFT;
+
+	len = type_len & FRU_TYPELEN_LEN_MASK;
+
+	return len;
+}
+
+/* Return len */
+static u8 fru_gen_type_len(u8 *addr, char *name)
+{
+	int len = strlen(name);
+	struct fru_board_info_member *member;
+
+	member = (struct fru_board_info_member *)addr;
+	member->type_len = FRU_TYPELEN_TYPE_ASCII8 << FRU_TYPELEN_TYPE_SHIFT;
+	member->type_len |= len;
+
+	debug("%lx/%lx: Add %s to 0x%lx (len 0x%x)\n", (ulong)addr,
+	      (ulong)&member->type_len,  name, (ulong)&member->name, len);
+	memcpy(&member->name, name, len);
+
+	/* Add +1 for type_len parameter */
+	return 1 + len;
+}
+
+int fru_generate(unsigned long addr, char *manufacturer, char *board_name,
+		 char *serial_no, char *part_no, char *revision)
+{
+	struct fru_common_hdr *header = (struct fru_common_hdr *)addr;
+	struct fru_board_info_header *board_info;
+	u8 *member;
+	u8 len, pad, modulo;
+
+	header->version = 1; /* Only version 1.0 is supported now */
+	header->off_internal = 0; /* not present */
+	header->off_chassis = 0; /* not present */
+	header->off_board = (sizeof(*header)) / 8; /* Starting offset 8 */
+	header->off_product = 0; /* not present */
+	header->off_multirec = 0; /* not present */
+	header->pad = 0;
+	/*
+	 * This unsigned byte can be used to calculate a zero checksum
+	 * for the data area following the header. I.e. the modulo 256 sum of
+	 * the record data bytes plus the checksum byte equals zero.
+	 */
+	header->crc = 0; /* Clear before calculation */
+	header->crc = 0 - fru_checksum((u8 *)header, sizeof(*header));
+
+	/* board info is just right after header */
+	board_info = (void *)((u8 *)header + sizeof(*header));
+
+	debug("header %lx, board_info %lx\n", (ulong)header, (ulong)board_info);
+
+	board_info->ver = 1; /* 1.0 spec */
+	board_info->lang_code = 0; /* English */
+	board_info->time[0] = 0; /* unspecified */
+	board_info->time[1] = 0; /* unspecified */
+	board_info->time[2] = 0; /* unspecified */
+
+	/* Member fields are just after board_info header */
+	member = (u8 *)board_info + sizeof(*board_info);
+
+	len = fru_gen_type_len(member, manufacturer); /* Board Manufacturer */
+	member += len;
+	len = fru_gen_type_len(member, board_name); /* Board Product name */
+	member += len;
+	len = fru_gen_type_len(member, serial_no); /* Board Serial number */
+	member += len;
+	len = fru_gen_type_len(member, part_no); /* Board part number */
+	member += len;
+	len = fru_gen_type_len(member, "U-Boot generator"); /* File ID */
+	member += len;
+	len = fru_gen_type_len(member, revision); /* Revision */
+	member += len;
+
+	*member++ = 0xc1; /* Indication of no more fields */
+
+	len = member - (u8 *)board_info; /* Find current length */
+	len += 1; /* Add checksum there too for calculation */
+
+	modulo = len % 8;
+
+	if (modulo) {
+		/* Do not fill last item which is checksum */
+		for (pad = 0; pad < 8 - modulo; pad++)
+			*member++ = 0;
+
+		/* Increase structure size */
+		len += 8 - modulo;
+	}
+
+	board_info->len = len / 8; /* Size in multiples of 8 bytes */
+
+	*member = 0; /* Clear before calculation */
+	*member = 0 - fru_checksum((u8 *)board_info, len);
+
+	debug("checksum %x(addr %x)\n", *member, len);
+
+	env_set_hex("fru_addr", addr);
+	env_set_hex("filesize", (unsigned long)member - addr + 1);
+
+	return 0;
+}
+
+static int fru_parse_board(unsigned long addr)
+{
+	u8 i, type;
+	int len;
+	u8 *data, *term, *limit;
+
+	memcpy(&fru_data.brd.ver, (void *)addr, 6);
+	addr += 6;
+	data = (u8 *)&fru_data.brd.manufacturer_type_len;
+
+	/* Record max structure limit not to write data over allocated space */
+	limit = (u8 *)&fru_data.brd + sizeof(struct fru_board_data);
+
+	for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) {
+		len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code,
+					 &type);
+		/*
+		 * Stop cature if it end of fields
+		 */
+		if (len == -EINVAL)
+			break;
+
+		/* Stop when amount of chars is more then fields to record */
+		if (data + len > limit)
+			break;
+		/* This record type/len field */
+		*data++ = *(u8 *)addr;
+
+		/* Add offset to match data */
+		addr += 1;
+
+		/* If len is 0 it means empty field that's why skip writing */
+		if (!len)
+			continue;
+
+		/* Record data field */
+		memcpy(data, (u8 *)addr, len);
+		term = data + (u8)len;
+		*term = 0;
+		addr += len;
+	}
+
+	if (i < FRU_BOARD_AREA_TOTAL_FIELDS) {
+		printf("Board area require minimum %d fields\n",
+		       FRU_BOARD_AREA_TOTAL_FIELDS);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int fru_capture(unsigned long addr)
+{
+	struct fru_common_hdr *hdr;
+	u8 checksum = 0;
+
+	checksum = fru_checksum((u8 *)addr, sizeof(struct fru_common_hdr));
+	if (checksum) {
+		printf("%s Common header CRC error\n", __func__);
+		return -EINVAL;
+	}
+
+	hdr = (struct fru_common_hdr *)addr;
+
+	memcpy((void *)&fru_data, (void *)hdr,
+	       sizeof(struct fru_common_hdr));
+
+	fru_data.captured = true;
+
+	if (hdr->off_board) {
+		addr += fru_cal_area_len(hdr->off_board);
+		fru_parse_board(addr);
+	}
+
+	env_set_hex("fru_addr", addr);
+
+	return 0;
+}
+
+static int fru_display_board(struct fru_board_data *brd, int verbose)
+{
+	u32 time = 0;
+	u8 type;
+	int len;
+	u8 *data;
+	static const char * const typecode[] = {
+		"Binary/Unspecified",
+		"BCD plus",
+		"6-bit ASCII",
+		"8-bit ASCII",
+		"2-byte UNICODE"
+	};
+	static const char * const boardinfo[] = {
+		"Manufacturer Name",
+		"Product Name",
+		"Serial No",
+		"Part Number",
+		"File ID",
+		/* Xilinx spec */
+		"Revision Number",
+	};
+
+	if (verbose) {
+		printf("*****BOARD INFO*****\n");
+		printf("Version:%d\n", fru_version(brd->ver));
+		printf("Board Area Length:%d\n", fru_cal_area_len(brd->len));
+	}
+
+	if (fru_check_language(brd->lang_code))
+		return -EINVAL;
+
+	time = brd->time[2] << 16 | brd->time[1] << 8 |
+	       brd->time[0];
+
+	if (verbose)
+		printf("Time in Minutes from 0:00hrs 1/1/96: %d\n", time);
+
+	data = (u8 *)&brd->manufacturer_type_len;
+
+	for (u8 i = 0; i < (sizeof(boardinfo) / sizeof(*boardinfo)); i++) {
+		len = fru_check_type_len(*data++, brd->lang_code,
+					 &type);
+		if (len == -EINVAL) {
+			printf("**** EOF for Board Area ****\n");
+			break;
+		}
+
+		if (type <= FRU_TYPELEN_TYPE_ASCII8 &&
+		    (brd->lang_code == FRU_LANG_CODE_ENGLISH ||
+		     brd->lang_code == FRU_LANG_CODE_ENGLISH_1))
+			debug("Type code: %s\n", typecode[type]);
+		else
+			debug("Type code: %s\n", typecode[type + 1]);
+
+		if (!len) {
+			debug("%s not found\n", boardinfo[i]);
+			continue;
+		}
+
+		switch (type) {
+		case FRU_TYPELEN_TYPE_BINARY:
+			debug("Length: %d\n", len);
+			printf(" %s: 0x%x\n", boardinfo[i], *data);
+			break;
+		case FRU_TYPELEN_TYPE_ASCII8:
+			debug("Length: %d\n", len);
+			printf(" %s: %s\n", boardinfo[i], data);
+			break;
+		default:
+			debug("Unsupported type %x\n", type);
+		}
+
+		data += FRU_BOARD_MAX_LEN;
+	}
+
+	return 0;
+}
+
+static void fru_display_common_hdr(struct fru_common_hdr *hdr, int verbose)
+{
+	if (!verbose)
+		return;
+
+	printf("*****COMMON HEADER*****\n");
+	printf("Version:%d\n", fru_version(hdr->version));
+	if (hdr->off_internal)
+		printf("Internal Use Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_internal));
+	else
+		printf("*** No Internal Area ***\n");
+
+	if (hdr->off_chassis)
+		printf("Chassis Info Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_chassis));
+	else
+		printf("*** No Chassis Info Area ***\n");
+
+	if (hdr->off_board)
+		printf("Board Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_board));
+	else
+		printf("*** No Board Area ***\n");
+
+	if (hdr->off_product)
+		printf("Product Info Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_product));
+	else
+		printf("*** No Product Info Area ***\n");
+
+	if (hdr->off_multirec)
+		printf("MultiRecord Area Offset:%d\n",
+		       fru_cal_area_len(hdr->off_multirec));
+	else
+		printf("*** No MultiRecord Area ***\n");
+}
+
+int fru_display(int verbose)
+{
+	if (!fru_data.captured) {
+		printf("FRU data not available please run fru parse\n");
+		return -EINVAL;
+	}
+
+	fru_display_common_hdr(&fru_data.hdr, verbose);
+
+	return fru_display_board(&fru_data.brd, verbose);
+}
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/Kconfig b/roms/u-boot/board/xilinx/microblaze-generic/Kconfig
new file mode 100644
index 000000000..f2fa0f72b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/Kconfig
@@ -0,0 +1,41 @@
+if TARGET_MICROBLAZE_GENERIC
+
+config SYS_BOARD
+	default "microblaze-generic"
+
+config SYS_VENDOR
+	default "xilinx"
+
+config SYS_CONFIG_NAME
+	string "Board configuration name"
+	default "microblaze-generic"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
+
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+	int "USE_MSR_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+	int "USE_PCMP_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_BARREL
+	int "USE_BARREL range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_DIV
+	int "USE_DIV range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+	default 0
+
+config XILINX_MICROBLAZE0_HW_VER
+	string "Core version number"
+	default "7.10.d"
+
+endif
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/MAINTAINERS b/roms/u-boot/board/xilinx/microblaze-generic/MAINTAINERS
new file mode 100644
index 000000000..29ed32f78
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/MAINTAINERS
@@ -0,0 +1,7 @@
+MICROBLAZE-GENERIC BOARD
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	board/xilinx/microblaze-generic/
+F:	include/configs/microblaze-generic.h
+F:	configs/microblaze-generic_defconfig
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/Makefile b/roms/u-boot/board/xilinx/microblaze-generic/Makefile
new file mode 100644
index 000000000..cfd833752
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	= microblaze-generic.o
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/config.mk b/roms/u-boot/board/xilinx/microblaze-generic/config.mk
new file mode 100644
index 000000000..a9539776d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/config.mk
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2007 - 2016 Michal Simek
+#
+# Michal SIMEK <monstr@monstr.eu>
+
+CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+
+# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+
+CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+
+PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
diff --git a/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c b/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c
new file mode 100644
index 000000000..a427ac94a
--- /dev/null
+++ b/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007-2018 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+
+/*
+ * This is a board specific file.  It's OK to include board specific
+ * header files
+ */
+
+#include <common.h>
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <dm/lists.h>
+#include <fdtdec.h>
+#include <linux/sizes.h>
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+};
+
+int board_late_init(void)
+{
+	ulong max_size;
+	u32 status = 0;
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
+	int ret;
+
+	ret = device_bind_driver(gd->dm_root, "mb_soft_reset",
+				 "reset_soft", NULL);
+	if (ret)
+		printf("Warning: No reset driver: ret=%d\n", ret);
+#endif
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	max_size = gd->start_addr_sp - CONFIG_STACK_SIZE;
+	max_size = round_down(max_size, SZ_16M);
+
+	status |= env_set_hex("scriptaddr", max_size + SZ_2M);
+
+	status |= env_set_hex("pxefile_addr_r", max_size + SZ_1M);
+
+	status |= env_set_hex("kernel_addr_r", gd->ram_base + SZ_32M);
+
+	status |= env_set_hex("fdt_addr_r", gd->ram_base + SZ_32M - SZ_1M);
+
+	status |= env_set_hex("ramdisk_addr_r",
+			       gd->ram_base + SZ_32M + SZ_4M + SZ_2M);
+	if (IS_ENABLED(CONFIG_MTD_NOR_FLASH))
+		status |= env_set_hex("script_offset_nor",
+				       gd->bd->bi_flashstart +
+				       CONFIG_BOOT_SCRIPT_OFFSET);
+	if (status)
+		printf("%s: Saving run time variables FAILED\n", __func__);
+
+	return board_late_init_xilinx();
+}
diff --git a/roms/u-boot/board/xilinx/versal/Kconfig b/roms/u-boot/board/xilinx/versal/Kconfig
new file mode 100644
index 000000000..c0cccc206
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2020, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_VERSAL
+
+config CMD_VERSAL
+	bool "Enable Versal specific commands"
+	default y
+	depends on ZYNQMP_FIRMWARE
+	help
+	  Enable Versal specific commands.
+
+endif
diff --git a/roms/u-boot/board/xilinx/versal/MAINTAINERS b/roms/u-boot/board/xilinx/versal/MAINTAINERS
new file mode 100644
index 000000000..bbab05136
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/MAINTAINERS
@@ -0,0 +1,8 @@
+XILINX_VERSAL BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/versal*
+F:	board/xilinx/versal/
+F:	include/configs/xilinx_versal*
+F:	configs/xilinx_versal*
diff --git a/roms/u-boot/board/xilinx/versal/Makefile b/roms/u-boot/board/xilinx/versal/Makefile
new file mode 100644
index 000000000..4a46ca02d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y	:= board.o
+obj-$(CONFIG_CMD_VERSAL)	+= cmds.o
diff --git a/roms/u-boot/board/xilinx/versal/board.c b/roms/u-boot/board/xilinx/versal/board.c
new file mode 100644
index 000000000..6045eb2ba
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/board.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <env_internal.h>
+#include <log.h>
+#include <malloc.h>
+#include <time.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <versalpl.h>
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+#endif
+
+int board_init(void)
+{
+	printf("EL Level:\tEL%d\n", current_el());
+
+#if defined(CONFIG_FPGA_VERSALPL)
+	fpga_init();
+	fpga_add(fpga_xilinx, &versalpl);
+#endif
+
+	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+		xilinx_read_eeprom();
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	u32 val;
+
+	if (current_el() != 3)
+		return 0;
+
+	debug("iou_switch ctrl div0 %x\n",
+	      readl(&crlapb_base->iou_switch_ctrl));
+
+	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+	       &crlapb_base->iou_switch_ctrl);
+
+	/* Global timer init - Program time stamp reference clk */
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+	writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+	debug("ref ctrl 0x%x\n",
+	      readl(&crlapb_base->timestamp_ref_ctrl));
+
+	/* Clear reset of timestamp reg */
+	writel(0, &crlapb_base->rst_timestamp);
+
+	/*
+	 * Program freq register in System counter and
+	 * enable system counter.
+	 */
+	writel(COUNTER_FREQUENCY,
+	       &iou_scntr_secure->base_frequency_id_register);
+
+	debug("counter val 0x%x\n",
+	      readl(&iou_scntr_secure->base_frequency_id_register));
+
+	writel(IOU_SCNTRS_CONTROL_EN,
+	       &iou_scntr_secure->counter_control_register);
+
+	debug("scntrs control 0x%x\n",
+	      readl(&iou_scntr_secure->counter_control_register));
+	debug("timer 0x%llx\n", get_ticks());
+	debug("timer 0x%llx\n", get_ticks());
+
+	return 0;
+}
+
+static u8 versal_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+
+	reg = readl(&crp_base->boot_mode_usr);
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+int board_late_init(void)
+{
+	u8 bootmode;
+	struct udevice *dev;
+	int bootseq = -1;
+	int bootseq_len = 0;
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	bootmode = versal_get_bootmode();
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "usb_dfu0 usb_dfu1";
+		break;
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "jtag pxe dhcp";
+		break;
+	case QSPI_MODE_24BIT:
+		puts("QSPI_MODE_24\n");
+		mode = "xspi0";
+		break;
+	case QSPI_MODE_32BIT:
+		puts("QSPI_MODE_32\n");
+		mode = "xspi0";
+		break;
+	case OSPI_MODE:
+		puts("OSPI_MODE\n");
+		mode = "xspi0";
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1050000", &dev)) {
+			puts("Boot from EMMC but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1040000", &dev)) {
+			puts("Boot from SD0 but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@f1050000", &dev)) {
+			puts("Boot from SD1 but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	if (bootseq >= 0) {
+		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+		debug("Bootseq len: %x\n", bootseq_len);
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+			     bootseq_len);
+	if (!new_targets)
+		return -ENOMEM;
+
+	if (bootseq >= 0)
+		sprintf(new_targets, "%s%x %s", mode, bootseq,
+			env_targets ? env_targets : "");
+	else
+		sprintf(new_targets, "%s %s", mode,
+			env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	return board_late_init_xilinx();
+}
+
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base_lowest() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = versal_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case OSPI_MODE:
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/roms/u-boot/board/xilinx/versal/cmds.c b/roms/u-boot/board/xilinx/versal/cmds.c
new file mode 100644
index 000000000..f5735d0c6
--- /dev/null
+++ b/roms/u-boot/board/xilinx/versal/cmds.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <cpu_func.h>
+#include <command.h>
+#include <common.h>
+#include <log.h>
+#include <memalign.h>
+#include <versalpl.h>
+#include <zynqmp_firmware.h>
+
+static int do_versal_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	u32 buf_lo, buf_hi;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	ulong addr, *pdi_buf;
+	size_t len;
+	int ret;
+
+	if (argc != cmdtp->maxargs) {
+		debug("pdi_load: incorrect parameters passed\n");
+		return CMD_RET_USAGE;
+	}
+
+	addr = simple_strtol(argv[2], NULL, 16);
+	if (!addr) {
+		debug("pdi_load: zero pdi_data address\n");
+		return CMD_RET_USAGE;
+	}
+
+	len = simple_strtoul(argv[3], NULL, 16);
+	if (!len) {
+		debug("pdi_load: zero size\n");
+		return CMD_RET_USAGE;
+	}
+
+	pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
+	if ((ulong)addr != (ulong)pdi_buf) {
+		memcpy((void *)pdi_buf, (void *)addr, len);
+		debug("Pdi addr:0x%lx aligned to 0x%lx\n",
+		      addr, (ulong)pdi_buf);
+	}
+
+	flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
+
+	buf_lo = lower_32_bits((ulong)pdi_buf);
+	buf_hi = upper_32_bits((ulong)pdi_buf);
+
+	ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+				buf_hi, 0, ret_payload);
+	if (ret)
+		printf("PDI load failed with err: 0x%08x\n", ret);
+
+	return ret;
+}
+
+static struct cmd_tbl cmd_versal_sub[] = {
+	U_BOOT_CMD_MKENT(loadpdi, 4, 1, do_versal_load_pdi, "", ""),
+};
+
+/**
+ * do_versal - Handle the "versal" command-line command
+ * @cmdtp:      Command data struct pointer
+ * @flag:       Command flag
+ * @argc:       Command-line argument count
+ * @argv:       Array of command-line arguments
+ *
+ * Processes the versal specific commands
+ *
+ * Return: return 0 on success, Error value if command fails.
+ * CMD_RET_USAGE incase of incorrect/missing parameters.
+ */
+static int do_versal(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	struct cmd_tbl *c;
+	int ret = CMD_RET_USAGE;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	c = find_cmd_tbl(argv[1], &cmd_versal_sub[0],
+			 ARRAY_SIZE(cmd_versal_sub));
+	if (c)
+		ret = c->cmd(c, flag, argc, argv);
+
+	return cmd_process_error(c, ret);
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char versal_help_text[] =
+	"loadpdi addr len - Load pdi image\n"
+	"load pdi image at ddr address 'addr' with pdi image size 'len'\n"
+;
+#endif
+
+U_BOOT_CMD(versal, 4, 1, do_versal,
+	   "versal sub-system",
+	   versal_help_text
+)
+
diff --git a/roms/u-boot/board/xilinx/zynq/.gitignore b/roms/u-boot/board/xilinx/zynq/.gitignore
new file mode 100644
index 000000000..ab66a7f2a
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/.gitignore
@@ -0,0 +1 @@
+/ps7_init_gpl.[ch]
diff --git a/roms/u-boot/board/xilinx/zynq/Kconfig b/roms/u-boot/board/xilinx/zynq/Kconfig
new file mode 100644
index 000000000..d6f40631c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/Kconfig
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2018, Xilinx, Inc.
+
+if ARCH_ZYNQ
+
+config CMD_ZYNQ
+	bool "Enable Zynq specific commands"
+	default y
+	help
+	  Enables Zynq specific commands.
+
+config CMD_ZYNQ_AES
+	bool "Enable zynq aes command for decryption of encrypted images"
+	depends on CMD_ZYNQ
+	depends on FPGA_ZYNQPL
+	help
+	  Decrypts the encrypted image present in source address
+	  and places the decrypted image at destination address.
+
+config CMD_ZYNQ_RSA
+	bool "Enable zynq rsa command for loading secure images"
+	default y
+	depends on CMD_ZYNQ
+	depends on CMD_ZYNQ_AES
+	help
+	  Enabling this will support zynq secure image verification.
+	  The secure image is a xilinx specific BOOT.BIN with
+	  either authentication or encryption or both encryption
+	  and authentication feature enabled while generating
+	  BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/roms/u-boot/board/xilinx/zynq/MAINTAINERS b/roms/u-boot/board/xilinx/zynq/MAINTAINERS
new file mode 100644
index 000000000..b5b9e2fe4
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/MAINTAINERS
@@ -0,0 +1,9 @@
+ZYNQ BOARD
+M:	Michal Simek <monstr@monstr.eu>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/zynq-*
+F:	board/xilinx/zynq/
+F:	include/configs/zynq*.h
+F:	configs/zynq_*_defconfig
+F:	configs/xilinx_zynq_*
diff --git a/roms/u-boot/board/xilinx/zynq/Makefile b/roms/u-boot/board/xilinx/zynq/Makefile
new file mode 100644
index 000000000..856617158
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/Makefile
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= board.o
+
+ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"")
+PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE))
+init-objs := ps_init_gpl.o
+spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_FILE)
+	$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
+endif
+
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
+ifeq ($(init-objs),)
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
+	$(hw-platform-y)/ps7_init_gpl.o)
+endif
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),)
+init-objs := ps7_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/))
+endif
+endif
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQ) += cmds.o
+obj-$(CONFIG_CMD_ZYNQ_RSA) += bootimg.o
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_ps7_init_gpl.o := -I$(srctree)/$(src)
diff --git a/roms/u-boot/board/xilinx/zynq/board.c b/roms/u-boot/board/xilinx/zynq/board.c
new file mode 100644
index 000000000..e2e9b3f0f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/board.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <log.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <watchdog.h>
+#include <wdt.h>
+#include <zynqpl.h>
+#include <asm/global_data.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		printf("Silicon version:\t%d\n", zynq_get_silicon_version());
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_QSPI:
+		mode = "qspi";
+		env_set("modeboot", "qspiboot");
+		break;
+	case ZYNQ_BM_NAND:
+		mode = "nand";
+		env_set("modeboot", "nandboot");
+		break;
+	case ZYNQ_BM_NOR:
+		mode = "nor";
+		env_set("modeboot", "norboot");
+		break;
+	case ZYNQ_BM_SD:
+		mode = "mmc0";
+		env_set("modeboot", "sdboot");
+		break;
+	case ZYNQ_BM_JTAG:
+		mode = "jtag pxe dhcp";
+		env_set("modeboot", "jtagboot");
+		break;
+	default:
+		mode = "";
+		env_set("modeboot", "");
+		break;
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
+	if (!new_targets)
+		return -ENOMEM;
+
+	sprintf(new_targets, "%s %s", mode,
+		env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	return board_late_init_xilinx();
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#else
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	zynq_ddrc_init();
+
+	return 0;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case ZYNQ_BM_SD:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case ZYNQ_BM_NAND:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case ZYNQ_BM_NOR:
+	case ZYNQ_BM_QSPI:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case ZYNQ_BM_JTAG:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/roms/u-boot/board/xilinx/zynq/bootimg.c b/roms/u-boot/board/xilinx/zynq/bootimg.c
new file mode 100644
index 000000000..2f55078dd
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/bootimg.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <log.h>
+#include <part.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <u-boot/md5.h>
+#include <zynq_bootimg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQ_IMAGE_PHDR_OFFSET		0x09C
+#define ZYNQ_IMAGE_FSBL_LEN_OFFSET	0x040
+#define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT	0x0F
+#define ZYNQ_PART_HDR_WORD_COUNT	0x10
+#define ZYNQ_MAXIMUM_IMAGE_WORD_LEN	0x40000000
+#define MD5_CHECKSUM_SIZE	16
+
+struct headerarray {
+	u32 fields[16];
+};
+
+/*
+ * Check whether the given partition is last partition or not
+ */
+static int zynq_islastpartition(struct headerarray *head)
+{
+	int index;
+
+	debug("%s\n", __func__);
+	if (head->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT] != 0xFFFFFFFF)
+		return -1;
+
+	for (index = 0; index < ZYNQ_PART_HDR_WORD_COUNT - 1; index++) {
+		if (head->fields[index] != 0x0)
+			return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * Get the partition count from the partition header
+ */
+int zynq_get_part_count(struct partition_hdr *part_hdr_info)
+{
+	u32 count;
+	struct headerarray *hap;
+
+	debug("%s\n", __func__);
+
+	for (count = 0; count < ZYNQ_MAX_PARTITION_NUMBER; count++) {
+		hap = (struct headerarray *)&part_hdr_info[count];
+		if (zynq_islastpartition(hap) != -1)
+			break;
+	}
+
+	return count;
+}
+
+/*
+ * Get the partition info of all the partitions available.
+ */
+int zynq_get_partition_info(u32 image_base_addr, u32 *fsbl_len,
+			    struct partition_hdr *part_hdr)
+{
+	u32 parthdroffset;
+
+	*fsbl_len = *((u32 *)(image_base_addr + ZYNQ_IMAGE_FSBL_LEN_OFFSET));
+
+	parthdroffset = *((u32 *)(image_base_addr + ZYNQ_IMAGE_PHDR_OFFSET));
+
+	parthdroffset += image_base_addr;
+
+	memcpy(part_hdr, (u32 *)parthdroffset,
+	       (sizeof(struct partition_hdr) * ZYNQ_MAX_PARTITION_NUMBER));
+
+	return 0;
+}
+
+/*
+ * Check whether the partition header is valid or not
+ */
+int zynq_validate_hdr(struct partition_hdr *header)
+{
+	struct headerarray *hap;
+	u32 index;
+	u32 checksum;
+
+	debug("%s\n", __func__);
+
+	hap = (struct headerarray *)header;
+
+	for (index = 0; index < ZYNQ_PART_HDR_WORD_COUNT; index++) {
+		if (hap->fields[index])
+			break;
+	}
+	if (index == ZYNQ_PART_HDR_WORD_COUNT)
+		return -1;
+
+	checksum = 0;
+	for (index = 0; index < ZYNQ_PART_HDR_CHKSUM_WORD_COUNT; index++)
+		checksum += hap->fields[index];
+
+	checksum ^= 0xFFFFFFFF;
+
+	if (hap->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT] != checksum) {
+		printf("Error: Checksum 0x%8.8x != 0x%8.8x\n",
+		       checksum, hap->fields[ZYNQ_PART_HDR_CHKSUM_WORD_COUNT]);
+		return -1;
+	}
+
+	if (header->imagewordlen > ZYNQ_MAXIMUM_IMAGE_WORD_LEN) {
+		printf("INVALID_PARTITION_LENGTH\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * Validate the partition by calculationg the md5 checksum for the
+ * partition and compare with checksum present in checksum offset of
+ * partition
+ */
+int zynq_validate_partition(u32 start_addr, u32 len, u32 chksum_off)
+{
+	u8 checksum[MD5_CHECKSUM_SIZE];
+	u8 calchecksum[MD5_CHECKSUM_SIZE];
+
+	memcpy(&checksum[0], (u32 *)chksum_off, MD5_CHECKSUM_SIZE);
+
+	md5_wd((u8 *)start_addr, len, &calchecksum[0], 0x10000);
+
+	if (!memcmp(checksum, calchecksum, MD5_CHECKSUM_SIZE))
+		return 0;
+
+	printf("Error: Partition DataChecksum\n");
+	return -1;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/cmds.c b/roms/u-boot/board/xilinx/zynq/cmds.c
new file mode 100644
index 000000000..6c697caa6
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/cmds.c
@@ -0,0 +1,553 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <linux/bitops.h>
+#include <u-boot/md5.h>
+#include <u-boot/rsa.h>
+#include <u-boot/rsa-mod-exp.h>
+#include <u-boot/sha256.h>
+#include <zynqpl.h>
+#include <fpga.h>
+#include <zynq_bootimg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_ZYNQ_RSA
+
+#define ZYNQ_EFUSE_RSA_ENABLE_MASK	0x400
+#define ZYNQ_ATTRIBUTE_PL_IMAGE_MASK		0x20
+#define ZYNQ_ATTRIBUTE_CHECKSUM_TYPE_MASK	0x7000
+#define ZYNQ_ATTRIBUTE_RSA_PRESENT_MASK		0x8000
+#define ZYNQ_ATTRIBUTE_RSA_PART_OWNER_MASK	0x30000
+
+#define ZYNQ_RSA_MODULAR_SIZE			256
+#define ZYNQ_RSA_MODULAR_EXT_SIZE		256
+#define ZYNQ_RSA_EXPO_SIZE			64
+#define ZYNQ_RSA_SPK_SIGNATURE_SIZE		256
+#define ZYNQ_RSA_PARTITION_SIGNATURE_SIZE	256
+#define ZYNQ_RSA_SIGNATURE_SIZE			0x6C0
+#define ZYNQ_RSA_HEADER_SIZE			4
+#define ZYNQ_RSA_MAGIC_WORD_SIZE		60
+#define ZYNQ_RSA_PART_OWNER_UBOOT		1
+#define ZYNQ_RSA_ALIGN_PPK_START		64
+
+#define WORD_LENGTH_SHIFT	2
+
+static u8 *ppkmodular;
+static u8 *ppkmodularex;
+
+struct zynq_rsa_public_key {
+	uint len;		/* Length of modulus[] in number of u32 */
+	u32 n0inv;		/* -1 / modulus[0] mod 2^32 */
+	u32 *modulus;	/* modulus as little endian array */
+	u32 *rr;		/* R^2 as little endian array */
+};
+
+static struct zynq_rsa_public_key public_key;
+
+static struct partition_hdr part_hdr[ZYNQ_MAX_PARTITION_NUMBER];
+
+/*
+ * Extract the primary public key components from already autheticated FSBL
+ */
+static void zynq_extract_ppk(u32 fsbl_len)
+{
+	u32 padsize;
+	u8 *ppkptr;
+
+	debug("%s\n", __func__);
+
+	/*
+	 * Extract the authenticated PPK from OCM i.e at end of the FSBL
+	 */
+	ppkptr = (u8 *)(fsbl_len + ZYNQ_OCM_BASEADDR);
+	padsize = ((u32)ppkptr % ZYNQ_RSA_ALIGN_PPK_START);
+	if (padsize)
+		ppkptr += (ZYNQ_RSA_ALIGN_PPK_START - padsize);
+
+	ppkptr += ZYNQ_RSA_HEADER_SIZE;
+
+	ppkptr += ZYNQ_RSA_MAGIC_WORD_SIZE;
+
+	ppkmodular = (u8 *)ppkptr;
+	ppkptr += ZYNQ_RSA_MODULAR_SIZE;
+	ppkmodularex = (u8 *)ppkptr;
+	ppkptr += ZYNQ_RSA_MODULAR_EXT_SIZE;
+}
+
+/*
+ * Calculate the inverse(-1 / modulus[0] mod 2^32 ) for the PPK
+ */
+static u32 zynq_calc_inv(void)
+{
+	u32 modulus = public_key.modulus[0];
+	u32 tmp = BIT(1);
+	u32 inverse;
+
+	inverse = modulus & BIT(0);
+
+	while (tmp) {
+		inverse *= 2 - modulus * inverse;
+		tmp *= tmp;
+	}
+
+	return ~(inverse - 1);
+}
+
+/*
+ * Recreate the signature by padding the bytes and verify with hash value
+ */
+static int zynq_pad_and_check(u8 *signature, u8 *hash)
+{
+	u8 padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
+			0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04,
+			0x20};
+	u8 *pad_ptr = signature + 256;
+	u32 pad = 202;
+	u32 ii;
+
+	/*
+	 * Re-Create PKCS#1v1.5 Padding
+	 * MSB  ----------------------------------------------------LSB
+	 * 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
+	 */
+	if (*--pad_ptr != 0 || *--pad_ptr != 1)
+		return -1;
+
+	for (ii = 0; ii < pad; ii++) {
+		if (*--pad_ptr != 0xFF)
+			return -1;
+	}
+
+	if (*--pad_ptr != 0)
+		return -1;
+
+	for (ii = 0; ii < sizeof(padding); ii++) {
+		if (*--pad_ptr != padding[ii])
+			return -1;
+	}
+
+	for (ii = 0; ii < 32; ii++) {
+		if (*--pad_ptr != hash[ii])
+			return -1;
+	}
+	return 0;
+}
+
+/*
+ * Verify and extract the hash value from signature using the public key
+ * and compare it with calculated hash value.
+ */
+static int zynq_rsa_verify_key(const struct zynq_rsa_public_key *key,
+			       const u8 *sig, const u32 sig_len, const u8 *hash)
+{
+	int status;
+	void *buf;
+
+	if (!key || !sig || !hash)
+		return -1;
+
+	if (sig_len != (key->len * sizeof(u32))) {
+		printf("Signature is of incorrect length %d\n", sig_len);
+		return -1;
+	}
+
+	/* Sanity check for stack size */
+	if (sig_len > ZYNQ_RSA_SPK_SIGNATURE_SIZE) {
+		printf("Signature length %u exceeds maximum %d\n", sig_len,
+		       ZYNQ_RSA_SPK_SIGNATURE_SIZE);
+		return -1;
+	}
+
+	buf = malloc(sig_len);
+	if (!buf)
+		return -1;
+
+	memcpy(buf, sig, sig_len);
+
+	status = zynq_pow_mod((u32 *)key, (u32 *)buf);
+	if (status == -1) {
+		free(buf);
+		return status;
+	}
+
+	status = zynq_pad_and_check((u8 *)buf, (u8 *)hash);
+
+	free(buf);
+	return status;
+}
+
+/*
+ * Authenticate the partition
+ */
+static int zynq_authenticate_part(u8 *buffer, u32 size)
+{
+	u8 hash_signature[32];
+	u8 *spk_modular;
+	u8 *spk_modular_ex;
+	u8 *signature_ptr;
+	u32 status;
+
+	debug("%s\n", __func__);
+
+	signature_ptr = (u8 *)(buffer + size - ZYNQ_RSA_SIGNATURE_SIZE);
+
+	signature_ptr += ZYNQ_RSA_HEADER_SIZE;
+
+	signature_ptr += ZYNQ_RSA_MAGIC_WORD_SIZE;
+
+	ppkmodular = (u8 *)signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_SIZE;
+	ppkmodularex = signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_EXT_SIZE;
+	signature_ptr += ZYNQ_RSA_EXPO_SIZE;
+
+	sha256_csum_wd((const unsigned char *)signature_ptr,
+		       (ZYNQ_RSA_MODULAR_EXT_SIZE + ZYNQ_RSA_EXPO_SIZE +
+		       ZYNQ_RSA_MODULAR_SIZE),
+		       (unsigned char *)hash_signature, 0x1000);
+
+	spk_modular = (u8 *)signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_SIZE;
+	spk_modular_ex = (u8 *)signature_ptr;
+	signature_ptr += ZYNQ_RSA_MODULAR_EXT_SIZE;
+	signature_ptr += ZYNQ_RSA_EXPO_SIZE;
+
+	public_key.len = ZYNQ_RSA_MODULAR_SIZE / sizeof(u32);
+	public_key.modulus = (u32 *)ppkmodular;
+	public_key.rr = (u32 *)ppkmodularex;
+	public_key.n0inv = zynq_calc_inv();
+
+	status = zynq_rsa_verify_key(&public_key, signature_ptr,
+				     ZYNQ_RSA_SPK_SIGNATURE_SIZE,
+				     hash_signature);
+	if (status)
+		return status;
+
+	signature_ptr += ZYNQ_RSA_SPK_SIGNATURE_SIZE;
+
+	sha256_csum_wd((const unsigned char *)buffer,
+		       (size - ZYNQ_RSA_PARTITION_SIGNATURE_SIZE),
+		       (unsigned char *)hash_signature, 0x1000);
+
+	public_key.len = ZYNQ_RSA_MODULAR_SIZE / sizeof(u32);
+	public_key.modulus = (u32 *)spk_modular;
+	public_key.rr = (u32 *)spk_modular_ex;
+	public_key.n0inv = zynq_calc_inv();
+
+	return zynq_rsa_verify_key(&public_key, (u8 *)signature_ptr,
+				   ZYNQ_RSA_PARTITION_SIGNATURE_SIZE,
+				   (u8 *)hash_signature);
+}
+
+/*
+ * Parses the partition header and verfies the authenticated and
+ * encrypted image.
+ */
+static int zynq_verify_image(u32 src_ptr)
+{
+	u32 silicon_ver, image_base_addr, status;
+	u32 partition_num = 0;
+	u32 efuseval, srcaddr, size, fsbl_len;
+	struct partition_hdr *hdr_ptr;
+	u32 part_data_len, part_img_len, part_attr;
+	u32 part_load_addr, part_dst_addr, part_chksum_offset;
+	u32 part_start_addr, part_total_size, partitioncount;
+	bool encrypt_part_flag = false;
+	bool part_chksum_flag = false;
+	bool signed_part_flag = false;
+
+	image_base_addr = src_ptr;
+
+	silicon_ver = zynq_get_silicon_version();
+
+	/* RSA not supported in silicon versions 1.0 and 2.0 */
+	if (silicon_ver == 0 || silicon_ver == 1)
+		return -1;
+
+	zynq_get_partition_info(image_base_addr, &fsbl_len,
+				&part_hdr[0]);
+
+	/* Extract ppk if efuse was blown Otherwise return error */
+	efuseval = readl(&efuse_base->status);
+	if (!(efuseval & ZYNQ_EFUSE_RSA_ENABLE_MASK))
+		return -1;
+
+	zynq_extract_ppk(fsbl_len);
+
+	partitioncount = zynq_get_part_count(&part_hdr[0]);
+
+	/*
+	 * As the first two partitions are related to fsbl,
+	 * we can ignore those two in bootimage and the below
+	 * code doesn't need to validate it as fsbl is already
+	 * done by now
+	 */
+	if (partitioncount <= 2 ||
+	    partitioncount > ZYNQ_MAX_PARTITION_NUMBER)
+		return -1;
+
+	while (partition_num < partitioncount) {
+		if (((part_hdr[partition_num].partitionattr &
+		   ZYNQ_ATTRIBUTE_RSA_PART_OWNER_MASK) >> 16) !=
+		   ZYNQ_RSA_PART_OWNER_UBOOT) {
+			printf("UBOOT is not Owner for partition %d\n",
+			       partition_num);
+			partition_num++;
+			continue;
+		}
+		hdr_ptr = &part_hdr[partition_num];
+		status = zynq_validate_hdr(hdr_ptr);
+		if (status)
+			return status;
+
+		part_data_len = hdr_ptr->datawordlen;
+		part_img_len = hdr_ptr->imagewordlen;
+		part_attr = hdr_ptr->partitionattr;
+		part_load_addr = hdr_ptr->loadaddr;
+		part_chksum_offset = hdr_ptr->checksumoffset;
+		part_start_addr = hdr_ptr->partitionstart;
+		part_total_size = hdr_ptr->partitionwordlen;
+
+		if (part_data_len != part_img_len) {
+			debug("Encrypted\n");
+			encrypt_part_flag = true;
+		}
+
+		if (part_attr & ZYNQ_ATTRIBUTE_CHECKSUM_TYPE_MASK)
+			part_chksum_flag = true;
+
+		if (part_attr & ZYNQ_ATTRIBUTE_RSA_PRESENT_MASK) {
+			debug("RSA Signed\n");
+			signed_part_flag = true;
+			size = part_total_size << WORD_LENGTH_SHIFT;
+		} else {
+			size = part_img_len;
+		}
+
+		if (!signed_part_flag && !part_chksum_flag) {
+			printf("Partition not signed & no chksum\n");
+			partition_num++;
+			continue;
+		}
+
+		srcaddr = image_base_addr +
+			  (part_start_addr << WORD_LENGTH_SHIFT);
+
+		/*
+		 * This validation is just for PS DDR.
+		 * TODO: Update this for PL DDR check as well.
+		 */
+		if (part_load_addr < gd->bd->bi_dram[0].start &&
+		    ((part_load_addr + part_data_len) >
+		    (gd->bd->bi_dram[0].start +
+		     gd->bd->bi_dram[0].size))) {
+			printf("INVALID_LOAD_ADDRESS_FAIL\n");
+			return -1;
+		}
+
+		if (part_attr & ZYNQ_ATTRIBUTE_PL_IMAGE_MASK)
+			part_load_addr = srcaddr;
+		else
+			memcpy((u32 *)part_load_addr, (u32 *)srcaddr,
+			       size);
+
+		if (part_chksum_flag) {
+			part_chksum_offset = image_base_addr +
+					     (part_chksum_offset <<
+					     WORD_LENGTH_SHIFT);
+			status = zynq_validate_partition(part_load_addr,
+							 (part_total_size <<
+							  WORD_LENGTH_SHIFT),
+							 part_chksum_offset);
+			if (status != 0) {
+				printf("PART_CHKSUM_FAIL\n");
+				return -1;
+			}
+			debug("Partition Validation Done\n");
+		}
+
+		if (signed_part_flag) {
+			status = zynq_authenticate_part((u8 *)part_load_addr,
+							size);
+			if (status != 0) {
+				printf("AUTHENTICATION_FAIL\n");
+				return -1;
+			}
+			debug("Authentication Done\n");
+		}
+
+		if (encrypt_part_flag) {
+			debug("DECRYPTION\n");
+
+			part_dst_addr = part_load_addr;
+
+			if (part_attr & ZYNQ_ATTRIBUTE_PL_IMAGE_MASK) {
+				partition_num++;
+				continue;
+			}
+
+			status = zynq_decrypt_load(part_load_addr,
+						   part_img_len,
+						   part_dst_addr,
+						   part_data_len,
+						   BIT_NONE);
+			if (status != 0) {
+				printf("DECRYPTION_FAIL\n");
+				return -1;
+			}
+		}
+		partition_num++;
+	}
+
+	return 0;
+}
+
+static int do_zynq_rsa(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char *const argv[])
+{
+	u32 src_ptr;
+	char *endp;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_FAILURE;
+
+	src_ptr = simple_strtoul(argv[2], &endp, 16);
+	if (*argv[2] == 0 || *endp != 0)
+		return CMD_RET_USAGE;
+
+	if (zynq_verify_image(src_ptr))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+#ifdef CONFIG_CMD_ZYNQ_AES
+static int zynq_decrypt_image(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	char *endp;
+	u32 srcaddr, srclen, dstaddr, dstlen;
+	int status;
+	u8 imgtype = BIT_NONE;
+
+	if (argc < 5 && argc > cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	if (argc == 5) {
+		if (!strcmp("load", argv[2]))
+			imgtype = BIT_FULL;
+		else if (!strcmp("loadp", argv[2]))
+			imgtype = BIT_PARTIAL;
+		else
+			return CMD_RET_USAGE;
+
+		srcaddr = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+
+		dstaddr = 0xFFFFFFFF;
+		dstlen = srclen;
+	} else {
+		srcaddr = simple_strtoul(argv[2], &endp, 16);
+		if (*argv[2] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		srclen = simple_strtoul(argv[3], &endp, 16);
+		if (*argv[3] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstaddr = simple_strtoul(argv[4], &endp, 16);
+		if (*argv[4] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+		dstlen = simple_strtoul(argv[5], &endp, 16);
+		if (*argv[5] == 0 || *endp != 0)
+			return CMD_RET_USAGE;
+	}
+
+	/*
+	 * Roundup source and destination lengths to
+	 * word size
+	 */
+	if (srclen % 4)
+		srclen = roundup(srclen, 4);
+	if (dstlen % 4)
+		dstlen = roundup(dstlen, 4);
+
+	status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr,
+				   dstlen >> 2, imgtype);
+	if (status != 0)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+static struct cmd_tbl zynq_commands[] = {
+#ifdef CONFIG_CMD_ZYNQ_RSA
+	U_BOOT_CMD_MKENT(rsa, 3, 1, do_zynq_rsa, "", ""),
+#endif
+#ifdef CONFIG_CMD_ZYNQ_AES
+	U_BOOT_CMD_MKENT(aes, 6, 1, zynq_decrypt_image, "", ""),
+#endif
+};
+
+static int do_zynq(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	struct cmd_tbl *zynq_cmd;
+	int ret;
+
+	if (!ARRAY_SIZE(zynq_commands)) {
+		puts("No zynq specific command enabled\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	zynq_cmd = find_cmd_tbl(argv[1], zynq_commands,
+				ARRAY_SIZE(zynq_commands));
+	if (!zynq_cmd)
+		return CMD_RET_USAGE;
+
+	ret = zynq_cmd->cmd(zynq_cmd, flag, argc, argv);
+
+	return cmd_process_error(zynq_cmd, ret);
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char zynq_help_text[] =
+	""
+#ifdef CONFIG_CMD_ZYNQ_RSA
+	"rsa <baseaddr>  - Verifies the authenticated and encrypted\n"
+	"                  zynq images and loads them back to load\n"
+	"                  addresses as specified in BOOT image(BOOT.BIN)\n"
+#endif
+#ifdef CONFIG_CMD_ZYNQ_AES
+	"aes <srcaddr> <srclen> <dstaddr> <dstlen>\n"
+	"                - Decrypts the encrypted image present in source\n"
+	"                  address and places the decrypted image at\n"
+	"                  destination address\n"
+	"aes load <srcaddr> <srclen>\n"
+	"aes loadp <srcaddr> <srclen>\n"
+	"       if operation type is load or loadp, it loads the encrypted\n"
+	"       full or partial bitstream on to PL respectively.\n"
+#endif
+	;
+#endif
+
+U_BOOT_CMD(zynq,	6,	0,	do_zynq,
+	   "Zynq specific commands", zynq_help_text
+);
diff --git a/roms/u-boot/board/xilinx/zynq/xil_io.h b/roms/u-boot/board/xilinx/zynq/xil_io.h
new file mode 100644
index 000000000..e933f7b5f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/xil_io.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H
+
+/*
+ * This empty file is here because ps7_init_gpl.c exported by hw project
+ * has #include "xil_io.h" line.
+ */
+
+#endif /* XIL_IO_H */
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
new file mode 100644
index 000000000..82f270c2e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C,  0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC084DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x452460D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0002880BU),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0002840CU),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00025804U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00026004U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000008BU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000008CU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000084U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000EBU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000CBU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000CCU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74,  0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054,  0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001680U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0XF8000834, 0x003F003FU, 0x003A0039U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	unsigned long *ps7_mio_init_data;
+	unsigned long *ps7_pll_init_data;
+	unsigned long *ps7_clock_init_data;
+	unsigned long *ps7_ddr_init_data;
+	unsigned long *ps7_peripherals_init_data;
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cse-nand b/roms/u-boot/board/xilinx/zynq/zynq-cse-nand
new file mode 120000
index 000000000..9d89a9957
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cse-nand
@@ -0,0 +1 @@
+zynq-zc770-xm011
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cse-nor b/roms/u-boot/board/xilinx/zynq/zynq-cse-nor
new file mode 120000
index 000000000..bb80693ea
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cse-nor
@@ -0,0 +1 @@
+zynq-zc770-xm012
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-cse-qspi-single b/roms/u-boot/board/xilinx/zynq/zynq-cse-qspi-single
new file mode 120000
index 000000000..764d14117
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-cse-qspi-single
@@ -0,0 +1 @@
+zynq-zc706
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
new file mode 100644
index 000000000..75095ee3d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00029000U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F9U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001240U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001240U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001218U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	int ret = -1;
+
+	ret = ps7_config(ps7_post_config_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
new file mode 100644
index 000000000..337af2d96
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -0,0 +1,12491 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000180[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x1e
+    // .. ==> 0XF8000190[13:8] = 0x0000001EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001E00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101E00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb0
+    // .. .. ==> 0XF800612C[19:10] = 0x000000B0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0002C000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xb1
+    // .. .. ==> 0XF8006130[19:10] = 0x000000B1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002C400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x0002C400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006134[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbc
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006138[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbb
+    // .. .. ==> 0XF8006138[19:10] = 0x000000BBU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002EC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002EC03U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006154[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x77
+    // .. .. ==> 0XF8006158[9:0] = 0x00000077U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000077U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF800615C[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006160[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x105
+    // .. .. ==> 0XF8006168[10:0] = 0x00000105U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000105U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000105U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x106
+    // .. .. ==> 0XF800616C[10:0] = 0x00000106U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000106U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000106U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x111
+    // .. .. ==> 0XF8006170[10:0] = 0x00000111U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000111U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000111U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x110
+    // .. .. ==> 0XF8006174[10:0] = 0x00000110U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000110U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000110U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF800617C[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb7
+    // .. .. ==> 0XF8006180[9:0] = 0x000000B7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000B7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 50
+    // .. ==> 0XF8000830[5:0] = 0x00000032U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000032U
+    // .. SDIO0_CD_SEL = 46
+    // .. ==> 0XF8000830[21:16] = 0x0000002EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002E0032U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
new file mode 100644
index 000000000..248c72861
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -0,0 +1,12820 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x800
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x800
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000800U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. DIRECTION_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_0 = 0x2000
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
new file mode 100644
index 000000000..c84ee6b1f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -0,0 +1,12731 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x25
+    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
+    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
+    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x19
+    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
+    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
+    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
+    // .. .. reg_phy_gatelvl_init_ratio = 0x109
+    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
+    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
+    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
+    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
+    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
+    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
+    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xde
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
+    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
+    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xea
+    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000700[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000724[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000728[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800072C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000730[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000734[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000738[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 14
+    // .. ==> 0XF8000830[21:16] = 0x0000000EU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. DIRECTION_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. OP_ENABLE_1 = 0x8000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00008000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0x7fff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x8000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. DIRECTION_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. OP_ENABLE_1 = 0x4000
+    // .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x00004000U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. MASK_1_LSW = 0xbfff
+    // .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
+    // .. .. .. .. DATA_1_LSW = 0x4000
+    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
+    // .. .. .. ..
+    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
new file mode 100644
index 000000000..b4663818d
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B00, 0x00000071U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B00, 0x00000303U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B00, 0x00000303U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
new file mode 100644
index 000000000..254a512cc
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
new file mode 100644
index 000000000..f4362b943
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
@@ -0,0 +1,763 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+	EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
new file mode 100644
index 000000000..621de09cc
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+	EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+	EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+	EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+	EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+	EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+	EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
new file mode 100644
index 000000000..eefd46d93
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
@@ -0,0 +1,754 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+	EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+	}
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
new file mode 100644
index 000000000..7a15ea572
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -0,0 +1,12389 @@
+// SPDX-License-Identifier: GPL-2.0+
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. ..
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. ..
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // ..
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // ..
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // ..
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xa
+    // .. ==> 0XF8000170[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00100A00U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x7
+    // .. ==> 0XF8000180[13:8] = 0x00000007U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100700U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // ..
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // ..
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // ..
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x18
+    // .. .. ==> 0XF8006018[15:10] = 0x00000018U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452460D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0xf
+    // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF66666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. ..
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. ..
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. ..
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF800612C[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xcf
+    // .. .. ==> 0XF800612C[19:10] = 0x000000CFU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00033C00U
+    // .. ..
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00033C03U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x3
+    // .. .. ==> 0XF8006130[9:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000003U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00034000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00034003U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006134[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xbd
+    // .. .. ==> 0XF8006134[19:10] = 0x000000BDU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002F400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002F400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006138[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xc1
+    // .. .. ==> 0XF8006138[19:10] = 0x000000C1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00030400U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00030400U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006154[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x83
+    // .. .. ==> 0XF8006158[9:0] = 0x00000083U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000083U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000083U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7f
+    // .. .. ==> 0XF800615C[9:0] = 0x0000007FU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007FU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000007FU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x78
+    // .. .. ==> 0XF8006160[9:0] = 0x00000078U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000078U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000078U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x124
+    // .. .. ==> 0XF8006168[10:0] = 0x00000124U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000124U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000124U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x125
+    // .. .. ==> 0XF800616C[10:0] = 0x00000125U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000125U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000125U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x112
+    // .. .. ==> 0XF8006170[10:0] = 0x00000112U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000112U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000112U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x116
+    // .. .. ==> 0XF8006174[10:0] = 0x00000116U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000116U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000116U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF800617C[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc3
+    // .. .. ==> 0XF8006180[9:0] = 0x000000C3U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C3U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C3U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbf
+    // .. .. ==> 0XF8006184[9:0] = 0x000000BFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BFU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000BFU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xb8
+    // .. .. ==> 0XF8006188[9:0] = 0x000000B8U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B8U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000B8U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. ..
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. ..
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. ..
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. ..
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000704[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000708[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800070C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000710[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000714[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000718[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000702U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000720[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000720[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000700U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800073C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000740[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000744[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000748[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800074C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000750[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000754[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000302U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000758[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800075C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000760[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000764[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000768[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800076C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000303U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000770[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000774[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000778[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800077C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000780[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000784[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000788[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800078C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000790[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000305U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000794[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF8000798[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 1
+    // .. ==> 0XF800079C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000304U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007A8[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007AC[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B0[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 1
+    // .. ==> 0XF80007B4[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000380U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007B8, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007BC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007BC, 0x00003F01U ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007CC[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 46
+    // .. ==> 0XF8000830[5:0] = 0x0000002EU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000002EU
+    // .. SDIO0_CD_SEL = 47
+    // .. ==> 0XF8000830[21:16] = 0x0000002FU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U
+    // ..
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x002F002EU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // ..
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // ..
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. ..
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // ..
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // ..
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // ..
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // ..
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init()
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
new file mode 100644
index 000000000..5d573868c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
new file mode 100644
index 000000000..5d573868c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
+	EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
+	EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
new file mode 100644
index 000000000..a376ba574
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * Procedure to generate this file (using Vivado Webpack 2018.2):
+ * + Install board files from digilent/vivado-boards repository
+ *   (commit 6a45981 from 2018-06-05)
+ * + Start Vivado and create a new RTL project with the Zybo-z7-20 board
+ * + Create a block design
+ *   - Add "ZYNQ7 Processing System" IP
+ *   - Run "Block Automation" (Check "Apply Board Preset")
+ *   - Connect ports FCLK_CLK0 and M_AXI_GP0_ACLK
+ *   - Save diagram changes
+ *   - Go to sources view, select the block diagram,
+ *     and select "Generate Output Products"
+ * + Copy the generated "ps7_init_gpl.c" file
+ * + Perform manual editions based on existing Zynq boards
+ *   and the checkpatch.pl script
+ *
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00027000U),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00027000U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C00U),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00028800U),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000073U),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F1U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F1U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F7U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000BCU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000B3U),
+	EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+	EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+	EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001600U),
+	EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001302U),
+	EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001303U),
+	EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001305U),
+	EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001304U),
+	EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001200U),
+	EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
+	EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
+	EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
+	EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
+	EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
+	EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKWRITE(0xE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0xF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0xF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	int ret = -1;
+
+	ret = ps7_config(ps7_post_config_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/roms/u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/roms/u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
new file mode 100644
index 000000000..fda6d18dd
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -0,0 +1,12568 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_t_cksre = 0x6 */
+	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_t_cksrx = 0x6 */
+	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_t_ckesr = 0x4 */
+	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	/* .. .. reg_ddrc_t_ckpde = 0x2 */
+	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
+	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
+	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
+	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
+	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B00[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCI_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. reserved_INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE_B = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCI_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. reserved_SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. reserved_DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. reserved_DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. reserved_SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. reserved_SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. reserved_GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. reserved_RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. reserved_VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. reserved_REFIO_TEST = 0x0 */
+	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
+	/* .. reserved_REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. reserved_DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. reserved_CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reserved_VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reserved_VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reserved_VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reserved_INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. reserved_TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reserved_INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_LVL_INP_EN_0 = 1 */
+	/* .. ==> 0XF8000900[3:3] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. USER_LVL_OUT_EN_0 = 1 */
+	/* .. ==> 0XF8000900[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. USER_LVL_INP_EN_1 = 1 */
+	/* .. ==> 0XF8000900[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. USER_LVL_OUT_EN_1 = 1 */
+	/* .. ==> 0XF8000900[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. reserved_FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. reserved_FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. reserved_FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. .. START: AFI2 SECURE REGISTER */
+	/* .. .. FINISH: AFI2 SECURE REGISTER */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+
+unsigned long ps7_pll_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
+	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_sdram = 0x1 */
+	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_loopback = 0x0 */
+	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_max_rank_rd = 0xf */
+	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_debug_mode = 0x0 */
+	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq0_wait_t = 0x0 */
+	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
+	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
+	/* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
+	/* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
+	/* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_t_cksre = 0x6 */
+	/* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_t_cksrx = 0x6 */
+	/* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_t_ckesr = 0x4 */
+	/* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	/* .. .. reg_ddrc_t_ckpde = 0x2 */
+	/* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_ckpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U */
+	/* .. .. reg_ddrc_t_ckdpde = 0x2 */
+	/* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_ckdpdx = 0x2 */
+	/* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U */
+	/* .. .. reg_ddrc_t_ckcsx = 0x3 */
+	/* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
+	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
+	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
+	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_2t_delay = 0x0 */
+	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_loopback = 0x0 */
+	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_rank0_delays = 0x1 */
+	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_int_lpbk = 0x0 */
+	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. CLK_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. SRSTN_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. REFIO_TEST = 0x0 */
+	/* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U */
+	/* .. REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_2_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_INP_ICT_EN_0 = 3 */
+	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
+	/* .. USER_INP_ICT_EN_1 = 3 */
+	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
+	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+
+unsigned long ps7_pll_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: PLL SLCR REGISTERS */
+	/* .. .. START: ARM PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x177 */
+	/* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00177000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x1a */
+	/* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001A000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. ARM_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. SRCSEL = 0x0 */
+	/* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. .. DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U */
+	/* .. .. .. CPU_6OR4XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. .. CPU_3OR2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U */
+	/* .. .. .. CPU_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. .. CPU_1XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. .. CPU_PERI_CLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	/* .. .. FINISH: ARM PLL INIT */
+	/* .. .. START: DDR PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1db */
+	/* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001DB000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x15 */
+	/* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00015000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. DDR_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. .. DDR_3XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. DDR_2XCLKACT = 0x1 */
+	/* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
+	/* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
+	/* .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
+	/* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
+	/* .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	/* .. .. FINISH: DDR PLL INIT */
+	/* .. .. START: IO PLL INIT */
+	/* .. .. PLL_RES = 0xc */
+	/* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U */
+	/* .. .. PLL_CP = 0x2 */
+	/* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. LOCK_CNT = 0x1f4 */
+	/* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x001F4000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
+	/* .. .. .. START: UPDATE FB_DIV */
+	/* .. .. .. PLL_FDIV = 0x14 */
+	/* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
+	/* .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00014000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
+	/* .. .. .. FINISH: UPDATE FB_DIV */
+	/* .. .. .. START: BY PASS PLL */
+	/* .. .. .. PLL_BYPASS_FORCE = 1 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	/* .. .. .. FINISH: BY PASS PLL */
+	/* .. .. .. START: ASSERT RESET */
+	/* .. .. .. PLL_RESET = 1 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	/* .. .. .. FINISH: ASSERT RESET */
+	/* .. .. .. START: DEASSERT RESET */
+	/* .. .. .. PLL_RESET = 0 */
+	/* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	/* .. .. .. FINISH: DEASSERT RESET */
+	/* .. .. .. START: CHECK PLL STATUS */
+	/* .. .. .. IO_PLL_LOCK = 1 */
+	/* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
+	/* .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. .. */
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	/* .. .. .. FINISH: CHECK PLL STATUS */
+	/* .. .. .. START: REMOVE PLL BY PASS */
+	/* .. .. .. PLL_BYPASS_FORCE = 0 */
+	/* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
+	/* .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. .. */
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	/* .. .. .. FINISH: REMOVE PLL BY PASS */
+	/* .. .. FINISH: IO PLL INIT */
+	/* .. FINISH: PLL SLCR REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: CLOCK CONTROL SLCR REGISTERS */
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000128[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. DIVISOR0 = 0x34 */
+	/* .. ==> 0XF8000128[13:8] = 0x00000034U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00003400U */
+	/* .. DIVISOR1 = 0x2 */
+	/* .. ==> 0XF8000128[25:20] = 0x00000002U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000138[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000138[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF8000140[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000140[6:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x8 */
+	/* .. ==> 0XF8000140[13:8] = 0x00000008U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U */
+	/* .. DIVISOR1 = 0x1 */
+	/* .. ==> 0XF8000140[25:20] = 0x00000001U */
+	/* ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
+	/* .. CLKACT = 0x1 */
+	/* .. ==> 0XF800014C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF800014C[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x5 */
+	/* .. ==> 0XF800014C[13:8] = 0x00000005U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	/* .. CLKACT0 = 0x1 */
+	/* .. ==> 0XF8000150[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. CLKACT1 = 0x0 */
+	/* .. ==> 0XF8000150[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000150[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0x14 */
+	/* .. ==> 0XF8000150[13:8] = 0x00000014U */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
+	/* .. CLKACT0 = 0x0 */
+	/* .. ==> 0XF8000154[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. CLKACT1 = 0x1 */
+	/* .. ==> 0XF8000154[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. SRCSEL = 0x0 */
+	/* .. ==> 0XF8000154[5:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. DIVISOR = 0xa */
+	/* .. ==> 0XF8000154[13:8] = 0x0000000AU */
+	/* ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
+	/* .. .. START: TRACE CLOCK */
+	/* .. .. FINISH: TRACE CLOCK */
+	/* .. .. CLKACT = 0x1 */
+	/* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR = 0x5 */
+	/* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0xa */
+	/* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x7 */
+	/* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000700U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x5 */
+	/* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
+	/* .. .. SRCSEL = 0x0 */
+	/* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U */
+	/* .. .. DIVISOR0 = 0x14 */
+	/* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
+	/* .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U */
+	/* .. .. DIVISOR1 = 0x1 */
+	/* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
+	/* .. .. CLK_621_TRUE = 0x1 */
+	/* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	/* .. .. DMA_CPU_2XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. USB0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. .. USB1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. GEM0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U */
+	/* .. .. GEM1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. SDI0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000400U */
+	/* .. .. SDI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. SPI0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. SPI1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. CAN0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. CAN1_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. I2C0_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U */
+	/* .. .. I2C1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. UART0_CPU_1XCLKACT = 0x0 */
+	/* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. UART1_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. GPIO_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U */
+	/* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U */
+	/* .. .. SMC_CPU_1XCLKACT = 0x1 */
+	/* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
+	/* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
+	/* .. START: THIS SHOULD BE BLANK */
+	/* .. FINISH: THIS SHOULD BE BLANK */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: DDR INITIALIZATION */
+	/* .. .. START: LOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	/* .. .. FINISH: LOCK DDR */
+	/* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
+	/* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x0000007FU */
+	/* .. .. reg_ddrc_active_ranks = 0x1 */
+	/* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
+	/* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_block = 0x1 */
+	/* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
+	/* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
+	/* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
+	/* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
+	/* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
+	/* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU */
+	/* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
+	/* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U */
+	/* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
+	/* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	/* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U */
+	/* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	/* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
+	/* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_w_xact_run_length = 0x8 */
+	/* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U */
+	/* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
+	/* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	/* .. .. reg_ddrc_t_rc = 0x1a */
+	/* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
+	/* .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU */
+	/* .. .. reg_ddrc_t_rfc_min = 0x54 */
+	/* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
+	/* .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001500U */
+	/* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
+	/* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
+	/* .. .. reg_ddrc_wr2pre = 0x12 */
+	/* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U */
+	/* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
+	/* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_t_faw = 0x15 */
+	/* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
+	/* .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005400U */
+	/* .. .. reg_ddrc_t_ras_max = 0x23 */
+	/* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
+	/* .. ..     ==> MASK : 0x003F0000U    VAL : 0x00230000U */
+	/* .. .. reg_ddrc_t_ras_min = 0x13 */
+	/* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
+	/* .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U */
+	/* .. .. reg_ddrc_t_cke = 0x4 */
+	/* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
+	/* .. .. reg_ddrc_write_latency = 0x5 */
+	/* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_rd2wr = 0x7 */
+	/* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U */
+	/* .. .. reg_ddrc_wr2rd = 0xe */
+	/* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
+	/* .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U */
+	/* .. .. reg_ddrc_t_xp = 0x4 */
+	/* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U */
+	/* .. .. reg_ddrc_pad_pd = 0x0 */
+	/* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd2pre = 0x4 */
+	/* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U */
+	/* .. .. reg_ddrc_t_rcd = 0x7 */
+	/* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	/* .. .. reg_ddrc_t_ccd = 0x4 */
+	/* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U */
+	/* .. .. reg_ddrc_t_rrd = 0x6 */
+	/* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U */
+	/* .. .. reg_ddrc_refresh_margin = 0x2 */
+	/* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_t_rp = 0x7 */
+	/* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U */
+	/* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
+	/* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U */
+	/* .. .. reg_ddrc_sdram = 0x1 */
+	/* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_mobile = 0x0 */
+	/* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_clock_stop_en = 0x0 */
+	/* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_read_latency = 0x7 */
+	/* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
+	/* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U */
+	/* .. .. reg_ddrc_dis_pad_pd = 0x0 */
+	/* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_loopback = 0x0 */
+	/* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
+	/* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
+	/* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_prefer_write = 0x0 */
+	/* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_max_rank_rd = 0xf */
+	/* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU */
+	/* .. .. reg_ddrc_mr_wr = 0x0 */
+	/* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_addr = 0x0 */
+	/* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_data = 0x0 */
+	/* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_mr_wr_busy = 0x0 */
+	/* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_type = 0x0 */
+	/* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
+	/* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
+	/* .. .. reg_ddrc_final_wait_x32 = 0x7 */
+	/* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
+	/* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_t_mrd = 0x4 */
+	/* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	/* .. .. reg_ddrc_emr2 = 0x8 */
+	/* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_emr3 = 0x0 */
+	/* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	/* .. .. reg_ddrc_mr = 0x930 */
+	/* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
+	/* .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U */
+	/* .. .. reg_ddrc_emr = 0x4 */
+	/* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
+	/* .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	/* .. .. reg_ddrc_burst_rdwr = 0x4 */
+	/* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U */
+	/* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
+	/* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
+	/* .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001670U */
+	/* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U */
+	/* .. .. reg_ddrc_burstchop = 0x0 */
+	/* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
+	/* .. .. reg_ddrc_force_low_pri_n = 0x0 */
+	/* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_dq = 0x0 */
+	/* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_debug_mode = 0x0 */
+	/* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_level_start = 0x0 */
+	/* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq0_wait_t = 0x0 */
+	/* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
+	/* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
+	/* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U */
+	/* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
+	/* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U */
+	/* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
+	/* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U */
+	/* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
+	/* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
+	/* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	/* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
+	/* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
+	/* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
+	/* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
+	/* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
+	/* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
+	/* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
+	/* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
+	/* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	/* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
+	/* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
+	/* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
+	/* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U */
+	/* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
+	/* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U */
+	/* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
+	/* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U */
+	/* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
+	/* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U */
+	/* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
+	/* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	/* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U */
+	/* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U */
+	/* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
+	/* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. .. reg_phy_rd_local_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U */
+	/* .. .. reg_phy_idle_local_odt = 0x3 */
+	/* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U */
+	/* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
+	/* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
+	/* .. .. reg_phy_rd_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_cmd_to_data = 0x0 */
+	/* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
+	/* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U */
+	/* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
+	/* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_fixed_re = 0x1 */
+	/* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
+	/* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
+	/* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_clk_stall_level = 0x0 */
+	/* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
+	/* .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U */
+	/* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
+	/* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
+	/* .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	/* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
+	/* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U */
+	/* .. .. reg_ddrc_dis_dll_calib = 0x0 */
+	/* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
+	/* .. .. reg_ddrc_rd_odt_delay = 0x3 */
+	/* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U */
+	/* .. .. reg_ddrc_wr_odt_delay = 0x0 */
+	/* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rd_odt_hold = 0x0 */
+	/* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_wr_odt_hold = 0x5 */
+	/* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	/* .. .. reg_ddrc_pageclose = 0x0 */
+	/* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_lpr_num_entries = 0x1f */
+	/* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
+	/* .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU */
+	/* .. .. reg_ddrc_auto_pre_en = 0x0 */
+	/* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_refresh_update_level = 0x0 */
+	/* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_wc = 0x0 */
+	/* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
+	/* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_selfref_en = 0x0 */
+	/* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	/* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
+	/* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U */
+	/* .. .. reg_arb_go2critical_en = 0x1 */
+	/* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	/* .. .. reg_ddrc_wrlvl_ww = 0x41 */
+	/* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U */
+	/* .. .. reg_ddrc_rdlvl_rr = 0x41 */
+	/* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U */
+	/* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
+	/* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
+	/* .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	/* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
+	/* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U */
+	/* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
+	/* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	/* .. .. refresh_timer0_start_value_x32 = 0x0 */
+	/* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U */
+	/* .. .. refresh_timer1_start_value_x32 = 0x8 */
+	/* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
+	/* .. .. reg_ddrc_dis_auto_zq = 0x0 */
+	/* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_ddr3 = 0x1 */
+	/* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. reg_ddrc_t_mod = 0x200 */
+	/* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U */
+	/* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
+	/* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U */
+	/* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
+	/* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
+	/* .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	/* .. .. t_zq_short_interval_x1024 = 0xc845 */
+	/* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
+	/* .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000C845U */
+	/* .. .. dram_rstn_x1024 = 0x67 */
+	/* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
+	/* .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06700000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
+	/* .. .. deeppowerdown_en = 0x0 */
+	/* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. deeppowerdown_to_x1024 = 0xff */
+	/* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
+	/* .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	/* .. .. dfi_wrlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU */
+	/* .. .. dfi_rdlvl_max_x1024 = 0xfff */
+	/* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
+	/* .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U */
+	/* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
+	/* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
+	/* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U */
+	/* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U */
+	/* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
+	/* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	/* .. .. reg_ddrc_2t_delay = 0x0 */
+	/* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_skip_ocd = 0x1 */
+	/* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
+	/* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
+	/* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
+	/* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
+	/* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
+	/* .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U */
+	/* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
+	/* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	/* .. .. START: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	/* .. .. FINISH: RESET ECC ERROR */
+	/* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
+	/* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	/* .. .. CORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
+	/* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	/* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
+	/* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	/* .. .. STAT_NUM_CORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U */
+	/* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
+	/* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_ecc_mode = 0x0 */
+	/* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_scrub = 0x1 */
+	/* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	/* .. .. reg_phy_dif_on = 0x0 */
+	/* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U */
+	/* .. .. reg_phy_dif_off = 0x0 */
+	/* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_data_slice_in_use = 0x1 */
+	/* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
+	/* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_tx = 0x0 */
+	/* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_board_lpbk_rx = 0x0 */
+	/* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_shift_dq = 0x0 */
+	/* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_err_clr = 0x0 */
+	/* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_dq_offset = 0x40 */
+	/* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
+	/* .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
+	/* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00023C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
+	/* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
+	/* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00022C00U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
+	/* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
+	/* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U */
+	/* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
+	/* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00024800U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
+	/* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U */
+	/* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
+	/* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000077U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
+	/* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
+	/* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
+	/* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000075U */
+	/* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
+	/* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E4U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
+	/* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000DFU */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
+	/* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E0U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
+	/* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
+	/* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
+	/* .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000E7U */
+	/* .. .. reg_phy_fifo_we_in_force = 0x0 */
+	/* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. .. reg_phy_fifo_we_in_delay = 0x0 */
+	/* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
+	/* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B7U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
+	/* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
+	/* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
+	/* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000B5U */
+	/* .. .. reg_phy_wr_data_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. .. reg_phy_wr_data_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
+	/* .. .. reg_phy_loopback = 0x0 */
+	/* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bl2 = 0x0 */
+	/* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_phy_at_spd_atpg = 0x0 */
+	/* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_enable = 0x0 */
+	/* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_force_err = 0x0 */
+	/* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. reg_phy_bist_mode = 0x0 */
+	/* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. .. reg_phy_invert_clkout = 0x1 */
+	/* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
+	/* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. .. reg_phy_sel_logic = 0x0 */
+	/* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
+	/* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
+	/* .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U */
+	/* .. .. reg_phy_ctrl_slave_force = 0x0 */
+	/* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_use_rank0_delays = 0x1 */
+	/* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U */
+	/* .. .. reg_phy_lpddr = 0x0 */
+	/* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_cmd_latency = 0x0 */
+	/* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_int_lpbk = 0x0 */
+	/* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
+	/* .. .. reg_phy_wr_rl_delay = 0x2 */
+	/* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
+	/* .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U */
+	/* .. .. reg_phy_rd_rl_delay = 0x4 */
+	/* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
+	/* .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U */
+	/* .. .. reg_phy_dll_lock_diff = 0xf */
+	/* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
+	/* .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U */
+	/* .. .. reg_phy_use_wr_level = 0x1 */
+	/* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U */
+	/* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
+	/* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U */
+	/* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
+	/* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U */
+	/* .. .. reg_phy_dis_calib_rst = 0x0 */
+	/* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_phy_ctrl_slave_delay = 0x0 */
+	/* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	/* .. .. reg_arb_page_addr_mask = 0x0 */
+	/* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_wr_portn = 0x3ff */
+	/* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
+	/* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_rmw_portn = 0x1 */
+	/* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_arb_pri_rd_portn = 0x3ff */
+	/* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
+	/* .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU */
+	/* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U */
+	/* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
+	/* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	/* .. .. reg_ddrc_lpddr2 = 0x0 */
+	/* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_per_bank_refresh = 0x0 */
+	/* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_derate_enable = 0x0 */
+	/* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_mr4_margin = 0x0 */
+	/* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
+	/* .. .. reg_ddrc_mr4_read_interval = 0x0 */
+	/* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	/* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
+	/* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U */
+	/* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U */
+	/* .. .. reg_ddrc_t_mrw = 0x5 */
+	/* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
+	/* .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	/* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
+	/* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
+	/* .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A6U */
+	/* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
+	/* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
+	/* .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
+	/* .. .. START: POLL ON DCI STATUS */
+	/* .. .. DONE = 1 */
+	/* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	/* .. .. FINISH: POLL ON DCI STATUS */
+	/* .. .. START: UNLOCK DDR */
+	/* .. .. reg_ddrc_soft_rstb = 0x1 */
+	/* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. reg_ddrc_powerdown_en = 0x0 */
+	/* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_data_bus_width = 0x0 */
+	/* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_burst8_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_rdwr_idle_gap = 1 */
+	/* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U */
+	/* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_act_bypass = 0x0 */
+	/* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U */
+	/* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
+	/* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	/* .. .. FINISH: UNLOCK DDR */
+	/* .. .. START: CHECK DDR STATUS */
+	/* .. .. ddrc_reg_operating_mode = 1 */
+	/* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U */
+	/* .. .. */
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	/* .. .. FINISH: CHECK DDR STATUS */
+	/* .. FINISH: DDR INITIALIZATION */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: OCM REMAPPING */
+	/* .. VREF_EN = 0x1 */
+	/* .. ==> 0XF8000B00[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. CLK_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. SRSTN_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B00[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
+	/* .. FINISH: OCM REMAPPING */
+	/* .. START: DDRIOB SETTINGS */
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B40[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B40[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B40[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B40[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B40[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B40[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B40[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B44[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B44[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B44[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B44[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B44[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B44[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B44[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B48[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B48[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B48[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B48[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B48[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B48[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B48[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x1 */
+	/* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000002U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B50[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B50[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B50[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B50[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B50[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B50[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B50[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B54[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x2 */
+	/* .. ==> 0XF8000B54[2:1] = 0x00000002U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000004U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B54[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x1 */
+	/* .. ==> 0XF8000B54[4:4] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000010U */
+	/* .. DCR_TYPE = 0x3 */
+	/* .. ==> 0XF8000B54[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. IBUF_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B54[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B54[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	/* .. INP_POWER = 0x0 */
+	/* .. ==> 0XF8000B58[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. INP_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[2:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000006U    VAL : 0x00000000U */
+	/* .. DCI_UPDATE = 0x0 */
+	/* .. ==> 0XF8000B58[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. TERM_EN = 0x0 */
+	/* .. ==> 0XF8000B58[4:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. DCR_TYPE = 0x0 */
+	/* .. ==> 0XF8000B58[6:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000000U */
+	/* .. IBUF_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[7:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000000U */
+	/* .. TERM_DISABLE_MODE = 0x0 */
+	/* .. ==> 0XF8000B58[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. OUTPUT_EN = 0x3 */
+	/* .. ==> 0XF8000B58[10:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000600U    VAL : 0x00000600U */
+	/* .. PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B58[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x3 */
+	/* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U */
+	/* .. SLEW_N = 0x3 */
+	/* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B60[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B60[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B60[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B64[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B64[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B64[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. DRIVE_P = 0x1c */
+	/* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
+	/* ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU */
+	/* .. DRIVE_N = 0xc */
+	/* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
+	/* ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U */
+	/* .. SLEW_P = 0x6 */
+	/* .. ==> 0XF8000B68[18:14] = 0x00000006U */
+	/* ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U */
+	/* .. SLEW_N = 0x1f */
+	/* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
+	/* ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U */
+	/* .. GTL = 0x0 */
+	/* .. ==> 0XF8000B68[26:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x07000000U    VAL : 0x00000000U */
+	/* .. RTERM = 0x0 */
+	/* .. ==> 0XF8000B68[31:27] = 0x00000000U */
+	/* ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	/* .. VREF_INT_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. VREF_SEL = 0x0 */
+	/* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000001EU    VAL : 0x00000000U */
+	/* .. VREF_EXT_EN = 0x3 */
+	/* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000060U    VAL : 0x00000060U */
+	/* .. VREF_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000180U    VAL : 0x00000000U */
+	/* .. REFIO_EN = 0x1 */
+	/* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000200U */
+	/* .. REFIO_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DRST_B_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. CKE_PULLUP_EN = 0x0 */
+	/* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x00004000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
+	/* .. .. START: ASSERT RESET */
+	/* .. .. RESET = 1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
+	/* .. .. FINISH: ASSERT RESET */
+	/* .. .. START: DEASSERT RESET */
+	/* .. .. RESET = 0 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	/* .. .. FINISH: DEASSERT RESET */
+	/* .. .. RESET = 0x1 */
+	/* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. .. ENABLE = 0x1 */
+	/* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. .. VRP_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. .. VRN_TRI = 0x0 */
+	/* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. .. VRP_OUT = 0x0 */
+	/* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U */
+	/* .. .. VRN_OUT = 0x1 */
+	/* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U */
+	/* .. .. NREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U */
+	/* .. .. NREF_OPT4 = 0x1 */
+	/* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
+	/* .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U */
+	/* .. .. PREF_OPT1 = 0x0 */
+	/* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U */
+	/* .. .. PREF_OPT2 = 0x0 */
+	/* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U */
+	/* .. .. UPDATE_CONTROL = 0x0 */
+	/* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. .. INIT_COMPLETE = 0x0 */
+	/* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. .. TST_CLK = 0x0 */
+	/* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. .. TST_HLN = 0x0 */
+	/* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. .. TST_HLP = 0x0 */
+	/* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. .. TST_RST = 0x0 */
+	/* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U */
+	/* .. .. INT_DCI_EN = 0x0 */
+	/* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
+	/* .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U */
+	/* .. .. */
+	EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
+	/* .. FINISH: DDRIOB SETTINGS */
+	/* .. START: MIO PROGRAMMING */
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000700[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000700[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000700[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000700[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000700[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000700[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000700[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000700[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000700[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000704[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000704[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000704[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000704[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000704[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000704[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000704[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000704[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000704[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000708[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000708[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000708[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000708[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000708[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000708[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000708[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000708[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000708[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800070C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800070C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800070C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800070C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800070C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800070C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800070C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800070C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800070C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000710[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000710[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000710[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000710[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000710[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000710[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000710[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000710[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000710[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000714[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000714[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000714[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000714[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000714[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000714[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000714[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000714[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000714[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000718[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000718[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000718[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000718[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000718[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000718[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000718[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000718[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000718[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800071C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800071C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800071C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800071C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800071C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800071C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800071C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800071C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800071C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000720[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000720[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000720[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000720[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000720[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000720[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000720[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000720[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000720[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000724[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000724[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000724[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000724[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000724[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000724[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000724[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000724[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000724[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000728[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000728[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000728[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000728[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000728[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000728[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000728[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000728[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000728[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800072C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800072C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800072C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800072C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800072C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800072C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800072C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800072C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800072C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000730[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000730[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000730[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000730[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000730[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000730[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000730[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000730[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000730[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000734[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000734[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000734[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000734[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000734[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000734[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000734[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000734[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000734[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000738[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000738[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000738[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000738[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000738[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF8000738[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF8000738[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF8000738[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000738[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800073C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800073C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800073C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800073C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800073C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF800073C[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 3 */
+	/* .. ==> 0XF800073C[11:9] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF800073C[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800073C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000740[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000740[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000740[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000740[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000740[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000740[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000740[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000740[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000740[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000744[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000744[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000744[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000744[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000744[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000744[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000744[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000744[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000744[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000748[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000748[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000748[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000748[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000748[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000748[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000748[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000748[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000748[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800074C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800074C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800074C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800074C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800074C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800074C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800074C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800074C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF800074C[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000750[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000750[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000750[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000750[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000750[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000750[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000750[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000750[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000750[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000754[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000754[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000754[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000754[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000754[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000754[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000754[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000754[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 1 */
+	/* .. ==> 0XF8000754[13:13] = 0x00000001U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00002000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000758[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000758[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000758[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000758[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000758[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000758[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000758[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000758[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000758[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800075C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800075C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800075C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800075C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800075C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800075C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800075C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800075C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800075C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000760[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000760[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000760[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000760[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000760[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000760[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000760[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000760[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000760[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000764[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000764[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000764[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000764[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000764[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000764[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000764[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000764[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000764[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000768[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF8000768[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF8000768[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000768[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000768[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000768[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF8000768[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000768[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000768[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800076C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 1 */
+	/* .. ==> 0XF800076C[1:1] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000002U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF800076C[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800076C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800076C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800076C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 4 */
+	/* .. ==> 0XF800076C[11:9] = 0x00000004U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800076C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800076C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000770[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000770[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000770[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000770[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000770[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000770[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000770[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000770[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000770[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000774[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000774[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000774[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000774[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000774[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000774[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000774[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000774[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000774[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000778[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000778[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000778[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000778[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000778[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000778[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000778[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000778[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000778[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF800077C[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800077C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800077C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800077C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800077C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800077C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800077C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800077C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800077C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000780[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000780[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000780[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000780[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000780[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000780[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000780[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000780[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000780[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000784[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000784[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000784[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000784[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000784[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000784[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000784[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000784[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000784[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000788[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000788[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000788[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000788[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000788[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000788[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000788[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000788[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000788[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800078C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800078C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800078C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800078C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800078C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800078C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800078C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800078C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800078C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF8000790[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000790[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000790[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000790[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000790[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000790[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000790[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000790[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000790[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000794[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000794[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000794[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000794[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000794[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000794[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000794[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000794[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000794[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF8000798[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF8000798[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF8000798[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF8000798[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF8000798[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF8000798[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF8000798[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF8000798[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF8000798[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF800079C[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF800079C[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 1 */
+	/* .. ==> 0XF800079C[2:2] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000004U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF800079C[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF800079C[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF800079C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF800079C[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF800079C[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF800079C[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007A8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007A8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007A8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007A8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007A8[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007A8[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007A8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007A8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007A8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007AC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007AC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007AC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007AC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007AC[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007AC[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007AC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007AC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007AC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B0[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007B4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 1 */
+	/* .. ==> 0XF80007B4[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007B4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007B8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007B8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007B8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007B8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007B8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007B8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007B8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 1 */
+	/* .. ==> 0XF80007B8[12:12] = 0x00000001U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00001000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007B8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007BC[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007BC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007BC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007BC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007BC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C0[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
+	/* .. TRI_ENABLE = 1 */
+	/* .. ==> 0XF80007C4[0:0] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000001U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 7 */
+	/* .. ==> 0XF80007C4[7:5] = 0x00000007U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007C8[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007C8[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007C8[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007C8[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007C8[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007C8[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007C8[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007C8[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007C8[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007CC[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007CC[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007CC[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007CC[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 0 */
+	/* .. ==> 0XF80007CC[7:5] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007CC[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007CC[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007CC[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007CC[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D0[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D0[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D0[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D0[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D0[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D0[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D0[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D0[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D0[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	/* .. TRI_ENABLE = 0 */
+	/* .. ==> 0XF80007D4[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. L0_SEL = 0 */
+	/* .. ==> 0XF80007D4[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. L1_SEL = 0 */
+	/* .. ==> 0XF80007D4[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. L2_SEL = 0 */
+	/* .. ==> 0XF80007D4[4:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000018U    VAL : 0x00000000U */
+	/* .. L3_SEL = 4 */
+	/* .. ==> 0XF80007D4[7:5] = 0x00000004U */
+	/* ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U */
+	/* .. Speed = 0 */
+	/* .. ==> 0XF80007D4[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. IO_Type = 1 */
+	/* .. ==> 0XF80007D4[11:9] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U */
+	/* .. PULLUP = 0 */
+	/* .. ==> 0XF80007D4[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. DisableRcvr = 0 */
+	/* .. ==> 0XF80007D4[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	/* .. SDIO0_WP_SEL = 55 */
+	/* .. ==> 0XF8000830[5:0] = 0x00000037U */
+	/* ..     ==> MASK : 0x0000003FU    VAL : 0x00000037U */
+	/* .. SDIO0_CD_SEL = 47 */
+	/* .. ==> 0XF8000830[21:16] = 0x0000002FU */
+	/* ..     ==> MASK : 0x003F0000U    VAL : 0x002F0000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
+	/* .. FINISH: MIO PROGRAMMING */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B48[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B50[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	/* .. IBUF_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[7:7] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000080U    VAL : 0x00000080U */
+	/* .. TERM_DISABLE_MODE = 0x1 */
+	/* .. ==> 0XF8000B54[8:8] = 0x00000001U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000100U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	/* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* .. START: SRAM/NOR SET OPMODE */
+	/* .. FINISH: SRAM/NOR SET OPMODE */
+	/* .. START: QSPI REGISTERS */
+	/* .. Holdb_dr = 1 */
+	/* .. ==> 0XE000D000[19:19] = 0x00000001U */
+	/* ..     ==> MASK : 0x00080000U    VAL : 0x00080000U */
+	/* .. */
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	/* .. FINISH: QSPI REGISTERS */
+	/* .. START: PL POWER ON RESET REGISTERS */
+	/* .. PCFG_POR_CNT_4K = 0 */
+	/* .. ==> 0XF8007000[29:29] = 0x00000000U */
+	/* ..     ==> MASK : 0x20000000U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	/* .. FINISH: PL POWER ON RESET REGISTERS */
+	/* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* .. .. START: NAND SET CYCLE */
+	/* .. .. FINISH: NAND SET CYCLE */
+	/* .. .. START: OPMODE */
+	/* .. .. FINISH: OPMODE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS0 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS0 BASE ADDRESS */
+	/* .. .. START: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
+	/* .. .. START: DIRECT COMMAND */
+	/* .. .. FINISH: DIRECT COMMAND */
+	/* .. .. START: NOR CS1 BASE ADDRESS */
+	/* .. .. FINISH: NOR CS1 BASE ADDRESS */
+	/* .. .. START: USB RESET */
+	/* .. .. .. START: USB0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. DIRECTION_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. OP_ENABLE_1 = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x0 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. MASK_1_LSW = 0xbfff */
+	/* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
+	/* .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U */
+	/* .. .. .. .. DATA_1_LSW = 0x4000 */
+	/* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
+	/* .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U */
+	/* .. .. .. .. */
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB0 RESET */
+	/* .. .. .. START: USB1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: USB1 RESET */
+	/* .. .. FINISH: USB RESET */
+	/* .. .. START: ENET RESET */
+	/* .. .. .. START: ENET0 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET0 RESET */
+	/* .. .. .. START: ENET1 RESET */
+	/* .. .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. .. START: DIR MODE BANK 1 */
+	/* .. .. .. .. FINISH: DIR MODE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: ENET1 RESET */
+	/* .. .. FINISH: ENET RESET */
+	/* .. .. START: I2C RESET */
+	/* .. .. .. START: I2C0 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C0 RESET */
+	/* .. .. .. START: I2C1 RESET */
+	/* .. .. .. .. START: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
+	/* .. .. .. .. START: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: OUTPUT ENABLE */
+	/* .. .. .. .. FINISH: OUTPUT ENABLE */
+	/* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
+	/* .. .. .. .. START: ADD 1 MS DELAY */
+	/* .. .. .. .. */
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	/* .. .. .. .. FINISH: ADD 1 MS DELAY */
+	/* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
+	/* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
+	/* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
+	/* .. .. .. FINISH: I2C1 RESET */
+	/* .. .. FINISH: I2C RESET */
+	/* .. .. START: NOR CHIP SELECT */
+	/* .. .. .. START: DIR MODE BANK 0 */
+	/* .. .. .. FINISH: DIR MODE BANK 0 */
+	/* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
+	/* .. .. .. START: OUTPUT ENABLE BANK 0 */
+	/* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
+	/* .. .. FINISH: NOR CHIP SELECT */
+	/* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+unsigned long ps7_post_config_1_0[] = {
+	/* START: top */
+	/* .. START: SLCR SETTINGS */
+	/* .. UNLOCK_KEY = 0XDF0D */
+	/* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	/* .. FINISH: SLCR SETTINGS */
+	/* .. START: ENABLING LEVEL SHIFTER */
+	/* .. USER_INP_ICT_EN_0 = 3 */
+	/* .. ==> 0XF8000900[1:0] = 0x00000003U */
+	/* ..     ==> MASK : 0x00000003U    VAL : 0x00000003U */
+	/* .. USER_INP_ICT_EN_1 = 3 */
+	/* .. ==> 0XF8000900[3:2] = 0x00000003U */
+	/* ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	/* .. FINISH: ENABLING LEVEL SHIFTER */
+	/* .. START: FPGA RESETS TO 0 */
+	/* .. reserved_3 = 0 */
+	/* .. ==> 0XF8000240[31:25] = 0x00000000U */
+	/* ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U */
+	/* .. FPGA_ACP_RST = 0 */
+	/* .. ==> 0XF8000240[24:24] = 0x00000000U */
+	/* ..     ==> MASK : 0x01000000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS3_RST = 0 */
+	/* .. ==> 0XF8000240[23:23] = 0x00000000U */
+	/* ..     ==> MASK : 0x00800000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS2_RST = 0 */
+	/* .. ==> 0XF8000240[22:22] = 0x00000000U */
+	/* ..     ==> MASK : 0x00400000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS1_RST = 0 */
+	/* .. ==> 0XF8000240[21:21] = 0x00000000U */
+	/* ..     ==> MASK : 0x00200000U    VAL : 0x00000000U */
+	/* .. FPGA_AXDS0_RST = 0 */
+	/* .. ==> 0XF8000240[20:20] = 0x00000000U */
+	/* ..     ==> MASK : 0x00100000U    VAL : 0x00000000U */
+	/* .. reserved_2 = 0 */
+	/* .. ==> 0XF8000240[19:18] = 0x00000000U */
+	/* ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U */
+	/* .. FSSW1_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[17:17] = 0x00000000U */
+	/* ..     ==> MASK : 0x00020000U    VAL : 0x00000000U */
+	/* .. FSSW0_FPGA_RST = 0 */
+	/* .. ==> 0XF8000240[16:16] = 0x00000000U */
+	/* ..     ==> MASK : 0x00010000U    VAL : 0x00000000U */
+	/* .. reserved_1 = 0 */
+	/* .. ==> 0XF8000240[15:14] = 0x00000000U */
+	/* ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW1_RST = 0 */
+	/* .. ==> 0XF8000240[13:13] = 0x00000000U */
+	/* ..     ==> MASK : 0x00002000U    VAL : 0x00000000U */
+	/* .. FPGA_FMSW0_RST = 0 */
+	/* .. ==> 0XF8000240[12:12] = 0x00000000U */
+	/* ..     ==> MASK : 0x00001000U    VAL : 0x00000000U */
+	/* .. FPGA_DMA3_RST = 0 */
+	/* .. ==> 0XF8000240[11:11] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000800U    VAL : 0x00000000U */
+	/* .. FPGA_DMA2_RST = 0 */
+	/* .. ==> 0XF8000240[10:10] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000400U    VAL : 0x00000000U */
+	/* .. FPGA_DMA1_RST = 0 */
+	/* .. ==> 0XF8000240[9:9] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000200U    VAL : 0x00000000U */
+	/* .. FPGA_DMA0_RST = 0 */
+	/* .. ==> 0XF8000240[8:8] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000100U    VAL : 0x00000000U */
+	/* .. reserved = 0 */
+	/* .. ==> 0XF8000240[7:4] = 0x00000000U */
+	/* ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U */
+	/* .. FPGA3_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[3:3] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000008U    VAL : 0x00000000U */
+	/* .. FPGA2_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[2:2] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000004U    VAL : 0x00000000U */
+	/* .. FPGA1_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[1:1] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000002U    VAL : 0x00000000U */
+	/* .. FPGA0_OUT_RST = 0 */
+	/* .. ==> 0XF8000240[0:0] = 0x00000000U */
+	/* ..     ==> MASK : 0x00000001U    VAL : 0x00000000U */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	/* .. FINISH: FPGA RESETS TO 0 */
+	/* .. START: AFI REGISTERS */
+	/* .. .. START: AFI0 REGISTERS */
+	/* .. .. FINISH: AFI0 REGISTERS */
+	/* .. .. START: AFI1 REGISTERS */
+	/* .. .. FINISH: AFI1 REGISTERS */
+	/* .. .. START: AFI2 REGISTERS */
+	/* .. .. FINISH: AFI2 REGISTERS */
+	/* .. .. START: AFI3 REGISTERS */
+	/* .. .. FINISH: AFI3 REGISTERS */
+	/* .. FINISH: AFI REGISTERS */
+	/* .. START: LOCK IT BACK */
+	/* .. LOCK_KEY = 0X767B */
+	/* .. ==> 0XF8000004[15:0] = 0x0000767BU */
+	/* ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU */
+	/* .. */
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	/* .. FINISH: LOCK IT BACK */
+	/* FINISH: top */
+	/* */
+	EMIT_EXIT(),
+
+	/* */
+};
+
+
+#include "xil_io.h"
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret = -1;
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ret = ps7_config(ps7_post_config_1_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ret = ps7_config(ps7_post_config_2_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	} else {
+		ret = ps7_config(ps7_post_config_3_0);
+		if (ret != PS7_INIT_SUCCESS)
+			return ret;
+	}
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+	/* Get the PS_VERSION on run time */
+	unsigned long si_ver = ps7GetSiliconVersion();
+	int ret;
+	/*int pcw_ver = 0; */
+
+	if (si_ver == PCW_SILICON_VERSION_1) {
+		ps7_mio_init_data = ps7_mio_init_data_1_0;
+		ps7_pll_init_data = ps7_pll_init_data_1_0;
+		ps7_clock_init_data = ps7_clock_init_data_1_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+		/*pcw_ver = 1; */
+
+	} else if (si_ver == PCW_SILICON_VERSION_2) {
+		ps7_mio_init_data = ps7_mio_init_data_2_0;
+		ps7_pll_init_data = ps7_pll_init_data_2_0;
+		ps7_clock_init_data = ps7_clock_init_data_2_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+		/*pcw_ver = 2; */
+
+	} else {
+		ps7_mio_init_data = ps7_mio_init_data_3_0;
+		ps7_pll_init_data = ps7_pll_init_data_3_0;
+		ps7_clock_init_data = ps7_clock_init_data_3_0;
+		ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+		ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+		/*pcw_ver = 3; */
+	}
+
+	/* MIO init */
+	ret = ps7_config(ps7_mio_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* PLL init */
+	ret = ps7_config(ps7_pll_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* Clock init */
+	ret = ps7_config(ps7_clock_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* DDR init */
+	ret = ps7_config(ps7_ddr_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	/* Peripherals init */
+	ret = ps7_config(ps7_peripherals_init_data);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	return PS7_INIT_SUCCESS;
+}
+
diff --git a/roms/u-boot/board/xilinx/zynqmp/Kconfig b/roms/u-boot/board/xilinx/zynqmp/Kconfig
new file mode 100644
index 000000000..7d1f7398c
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2018, Xilinx, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if ARCH_ZYNQMP
+
+config CMD_ZYNQMP
+	bool "Enable ZynqMP specific commands"
+	default y
+	help
+	  Enable ZynqMP specific commands like "zynqmp secure"
+	  which is used for zynqmp secure image verification.
+	  The secure image is a xilinx specific BOOT.BIN with
+	  either authentication or encryption or both encryption
+	  and authentication feature enabled while generating
+	  BOOT.BIN using Xilinx bootgen tool.
+
+endif
diff --git a/roms/u-boot/board/xilinx/zynqmp/MAINTAINERS b/roms/u-boot/board/xilinx/zynqmp/MAINTAINERS
new file mode 100644
index 000000000..56c637943
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/MAINTAINERS
@@ -0,0 +1,17 @@
+XILINX_ZYNQMP BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+F:	arch/arm/dts/zynqmp-*
+F:	arch/arm/dts/avnet-ultra96*
+F:	board/xilinx/common/
+F:	board/xilinx/zynqmp/
+F:	include/configs/xilinx_zynqmp*
+F:	configs/xilinx_zynqmp*
+F:	configs/avnet_ultra96_rev1_defconfig
+
+ARM ZYNQMP AVNET ULTRAZED EV BOARD
+M:	Luca Ceresoli <luca@lucaceresoli.net>
+S:	Maintained
+F:	arch/arm/dts/avnet-ultrazedev-*
+F:	configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
diff --git a/roms/u-boot/board/xilinx/zynqmp/Makefile b/roms/u-boot/board/xilinx/zynqmp/Makefile
new file mode 100644
index 000000000..7d8277ca4
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/Makefile
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+
+obj-y	:= zynqmp.o
+
+ifneq ($(CONFIG_XILINX_PS_INIT_FILE),"")
+PS_INIT_FILE := $(shell cd $(srctree); readlink -f $(CONFIG_XILINX_PS_INIT_FILE))
+init-objs := ps_init_gpl.o
+spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_INIT_FILE)
+	$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
+endif
+
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
+ifeq ($(init-objs),)
+hw-platform-y :=$(shell echo $(DEVICE_TREE))
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+	$(hw-platform-y)/psu_init_gpl.o)
+endif
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+ifdef_any_of = $(filter-out undefined,$(foreach v,$(1),$(origin $(v))))
+
+ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),)
+obj-y += $(init-objs)
+endif
+
+ifdef CONFIG_SPL_BUILD
+ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
+obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o
+$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE
+endif
+endif
+
+obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_ZYNQMP) += cmds.o
+endif
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
+
+# To suppress "warning: cast to pointer from integer of different size"
+CFLAGS_psu_init_gpl.o += -Wno-int-to-pointer-cast
diff --git a/roms/u-boot/board/xilinx/zynqmp/avnet-ultra96-rev1 b/roms/u-boot/board/xilinx/zynqmp/avnet-ultra96-rev1
new file mode 120000
index 000000000..f2beed309
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/avnet-ultra96-rev1
@@ -0,0 +1 @@
+zynqmp-zcu100-revC
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
new file mode 100644
index 000000000..d030e7977
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c
@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/cmds.c b/roms/u-boot/board/xilinx/zynqmp/cmds.c
new file mode 100644
index 000000000..cf63ad97f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/cmds.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <zynqmp_firmware.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+struct aes {
+	u64 srcaddr;
+	u64 ivaddr;
+	u64 keyaddr;
+	u64 dstaddr;
+	u64 len;
+	u64 op;
+	u64 keysrc;
+};
+
+static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc,
+				   char *const argv[])
+{
+	u64 src_addr, addr;
+	u32 len, src_lo, src_hi;
+	u8 *key_ptr = NULL;
+	int ret;
+	u32 key_lo = 0;
+	u32 key_hi = 0;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	src_addr = simple_strtoull(argv[2], NULL, 16);
+	len = simple_strtoul(argv[3], NULL, 16);
+
+	if (argc == 5)
+		key_ptr = (uint8_t *)(uintptr_t)simple_strtoull(argv[4],
+								NULL, 16);
+
+	if ((ulong)src_addr != ALIGN((ulong)src_addr,
+				     CONFIG_SYS_CACHELINE_SIZE)) {
+		printf("Failed: source address not aligned:%lx\n",
+		       (ulong)src_addr);
+		return -EINVAL;
+	}
+
+	src_lo = lower_32_bits((ulong)src_addr);
+	src_hi = upper_32_bits((ulong)src_addr);
+	flush_dcache_range((ulong)src_addr, (ulong)(src_addr + len));
+
+	if (key_ptr) {
+		key_lo = lower_32_bits((ulong)key_ptr);
+		key_hi = upper_32_bits((ulong)key_ptr);
+		flush_dcache_range((ulong)key_ptr,
+				   (ulong)(key_ptr + KEY_PTR_LEN));
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi,
+				key_lo, key_hi, ret_payload);
+	if (ret) {
+		printf("Failed: secure op status:0x%x\n", ret);
+	} else {
+		addr = (u64)ret_payload[1] << 32 | ret_payload[2];
+		printf("Verified image at 0x%llx\n", addr);
+		env_set_hex("zynqmp_verified_img_addr", addr);
+	}
+
+	return ret;
+}
+
+static int do_zynqmp_mmio_read(struct cmd_tbl *cmdtp, int flag, int argc,
+			       char *const argv[])
+{
+	u32 read_val, addr;
+	int ret;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+
+	ret = zynqmp_mmio_read(addr, &read_val);
+	if (!ret)
+		printf("mmio read value at 0x%x = 0x%x\n",
+		       addr, read_val);
+	else
+		printf("Failed: mmio read\n");
+
+	return ret;
+}
+
+static int do_zynqmp_mmio_write(struct cmd_tbl *cmdtp, int flag, int argc,
+				char *const argv[])
+{
+	u32 addr, mask, val;
+	int ret;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	mask = simple_strtoul(argv[3], NULL, 16);
+	val = simple_strtoul(argv[4], NULL, 16);
+
+	ret = zynqmp_mmio_write(addr, mask, val);
+	if (ret != 0)
+		printf("Failed: mmio write\n");
+
+	return ret;
+}
+
+static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct aes, aes, 1);
+	int ret;
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+
+	if (zynqmp_firmware_version() <= PMUFW_V1_0) {
+		puts("ERR: PMUFW v1.0 or less is detected\n");
+		puts("ERR: Encrypt/Decrypt feature is not supported\n");
+		puts("ERR: Please upgrade PMUFW\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (argc < cmdtp->maxargs - 1)
+		return CMD_RET_USAGE;
+
+	aes->srcaddr = simple_strtoul(argv[2], NULL, 16);
+	aes->ivaddr = simple_strtoul(argv[3], NULL, 16);
+	aes->len = simple_strtoul(argv[4], NULL, 16);
+	aes->op = simple_strtoul(argv[5], NULL, 16);
+	aes->keysrc = simple_strtoul(argv[6], NULL, 16);
+	aes->dstaddr = simple_strtoul(argv[7], NULL, 16);
+
+	flush_dcache_range((ulong)aes, (ulong)(aes) +
+			   roundup(sizeof(struct aes), ARCH_DMA_MINALIGN));
+
+	if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+		flush_dcache_range(aes->srcaddr,
+				   (aes->srcaddr +
+				    roundup(aes->len, ARCH_DMA_MINALIGN)));
+		flush_dcache_range(aes->ivaddr,
+				   (aes->ivaddr +
+				    roundup(IV_SIZE, ARCH_DMA_MINALIGN)));
+		flush_dcache_range(aes->dstaddr,
+				   (aes->dstaddr +
+				    roundup(aes->len, ARCH_DMA_MINALIGN)));
+	}
+
+	if (aes->keysrc == 0) {
+		if (argc < cmdtp->maxargs)
+			return CMD_RET_USAGE;
+
+		aes->keyaddr = simple_strtoul(argv[8], NULL, 16);
+		if (aes->keyaddr)
+			flush_dcache_range(aes->keyaddr,
+					   (aes->keyaddr +
+					    roundup(KEY_PTR_LEN,
+						    ARCH_DMA_MINALIGN)));
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+				lower_32_bits((ulong)aes), 0, 0, ret_payload);
+	if (ret || ret_payload[1])
+		printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+
+	return ret;
+}
+
+#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
+static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	u8 mode;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	mode = simple_strtoul(argv[2], NULL, 16);
+	if (mode != TCM_LOCK && mode != TCM_SPLIT) {
+		printf("Mode should be either 0(lock)/1(split)\n");
+		return CMD_RET_FAILURE;
+	}
+
+	dcache_disable();
+	tcm_init(mode);
+	dcache_enable();
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char * const argv[])
+{
+	u32 addr, size;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	size = simple_strtoul(argv[3], NULL, 16);
+	flush_dcache_range((ulong)addr, (ulong)(addr + size));
+
+	zynqmp_pmufw_load_config_object((const void *)(uintptr_t)addr,
+					(size_t)size);
+
+	return 0;
+}
+
+static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char * const argv[])
+{
+	u64 srcaddr, mod, exp;
+	u32 srclen, rsaop, size, ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (argc != cmdtp->maxargs)
+		return CMD_RET_USAGE;
+
+	if (zynqmp_firmware_version() <= PMUFW_V1_0) {
+		puts("ERR: PMUFW v1.0 or less is detected\n");
+		puts("ERR: Encrypt/Decrypt feature is not supported\n");
+		puts("ERR: Please upgrade PMUFW\n");
+		return CMD_RET_FAILURE;
+	}
+
+	srcaddr = simple_strtoul(argv[2], NULL, 16);
+	srclen = simple_strtoul(argv[3], NULL, 16);
+	if (srclen != RSA_KEY_SIZE) {
+		puts("ERR: srclen should be equal to 0x200(512 bytes)\n");
+		return CMD_RET_USAGE;
+	}
+
+	mod = simple_strtoul(argv[4], NULL, 16);
+	exp = simple_strtoul(argv[5], NULL, 16);
+	rsaop = simple_strtoul(argv[6], NULL, 16);
+	if (!(rsaop == 0 || rsaop == 1)) {
+		puts("ERR: rsaop should be either 0 or 1\n");
+		return CMD_RET_USAGE;
+	}
+
+	memcpy((void *)srcaddr + srclen, (void *)mod, MODULUS_LEN);
+
+	/*
+	 * For encryption we load public exponent (key size 4096-bits),
+	 * for decryption we load private exponent (32-bits)
+	 */
+	if (rsaop) {
+		memcpy((void *)srcaddr + srclen + MODULUS_LEN,
+		       (void *)exp, PUB_EXPO_LEN);
+		size = srclen + MODULUS_LEN + PUB_EXPO_LEN;
+	} else {
+		memcpy((void *)srcaddr + srclen + MODULUS_LEN,
+		       (void *)exp, PRIV_EXPO_LEN);
+		size = srclen + MODULUS_LEN + PRIV_EXPO_LEN;
+	}
+
+	flush_dcache_range((ulong)srcaddr,
+			   (ulong)(srcaddr) + roundup(size, ARCH_DMA_MINALIGN));
+
+	ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr),
+				lower_32_bits((ulong)srcaddr), srclen, rsaop,
+				ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: RSA status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag,
+			  int argc, char * const argv[])
+{
+	u64 srcaddr, hashaddr;
+	u32 srclen, ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (argc > cmdtp->maxargs || argc < (cmdtp->maxargs - 1))
+		return CMD_RET_USAGE;
+
+	if (zynqmp_firmware_version() <= PMUFW_V1_0) {
+		puts("ERR: PMUFW v1.0 or less is detected\n");
+		puts("ERR: Encrypt/Decrypt feature is not supported\n");
+		puts("ERR: Please upgrade PMUFW\n");
+		return CMD_RET_FAILURE;
+	}
+
+	srcaddr = simple_strtoul(argv[2], NULL, 16);
+	srclen = simple_strtoul(argv[3], NULL, 16);
+
+	if (argc == 5) {
+		hashaddr = simple_strtoul(argv[4], NULL, 16);
+		flush_dcache_range(hashaddr,
+				   hashaddr + roundup(ZYNQMP_SHA3_SIZE,
+						      ARCH_DMA_MINALIGN));
+	} else {
+		hashaddr = srcaddr;
+	}
+
+	/* Check srcaddr or srclen != 0 */
+	if (!srcaddr || !srclen) {
+		puts("ERR: srcaddr & srclen should not be 0\n");
+		return CMD_RET_USAGE;
+	}
+
+	flush_dcache_range(srcaddr,
+			   srcaddr + roundup(srclen, ARCH_DMA_MINALIGN));
+
+	ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0,
+				ZYNQMP_SHA3_INIT, ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr),
+				lower_32_bits((ulong)srcaddr),
+				srclen, ZYNQMP_SHA3_UPDATE, ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr),
+				lower_32_bits((ulong)hashaddr),
+				ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL,
+				ret_payload);
+	if (ret || ret_payload[1]) {
+		printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n",
+		       ret, ret_payload[1]);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static struct cmd_tbl cmd_zynqmp_sub[] = {
+	U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
+	U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""),
+	U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""),
+	U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""),
+	U_BOOT_CMD_MKENT(aes, 9, 0, do_zynqmp_aes, "", ""),
+	U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""),
+	U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""),
+#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
+	U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""),
+#endif
+};
+
+/**
+ * do_zynqmp - Handle the "zynqmp" command-line command
+ * @cmdtp:	Command data struct pointer
+ * @flag:	Command flag
+ * @argc:	Command-line argument count
+ * @argv:	Array of command-line arguments
+ *
+ * Processes the zynqmp specific commands
+ *
+ * Return: return 0 on success and CMD_RET_USAGE incase of misuse and error
+ */
+static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	struct cmd_tbl *c;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0],
+			 ARRAY_SIZE(cmd_zynqmp_sub));
+
+	if (c)
+		return c->cmd(c, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+}
+
+/***************************************************/
+#ifdef CONFIG_SYS_LONGHELP
+static char zynqmp_help_text[] =
+	"secure src len [key_addr] - verifies secure images of $len bytes\n"
+	"                            long at address $src. Optional key_addr\n"
+	"                            can be specified if user key needs to\n"
+	"                            be used for decryption\n"
+	"zynqmp mmio_read address - read from address\n"
+	"zynqmp mmio_write address mask value - write value after masking to\n"
+	"					address\n"
+	"zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr] -\n"
+	"	Encrypts or decrypts blob of data at src address and puts it\n"
+	"	back to dstaddr using key and iv at keyaddr and ivaddr\n"
+	"	respectively. keysrc value specifies from which source key\n"
+	"	has to be used, it can be User/Device/PUF key. A value of 0\n"
+	"	for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
+	"	aesop value specifies the operation which can be 0 for\n"
+	"	decrypt and 1 for encrypt operation\n"
+#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
+	"zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n"
+	"		       initialized before accessing to avoid ECC\n"
+	"		       errors. mode specifies in which mode TCM has\n"
+	"		       to be initialized. Supported modes will be\n"
+	"		       lock(0)/split(1)\n"
+#endif
+	"zynqmp pmufw address size - load PMU FW configuration object\n"
+	"zynqmp rsa srcaddr srclen mod exp rsaop -\n"
+	"	Performs RSA encryption and RSA decryption on blob of data\n"
+	"	at srcaddr and puts it back in srcaddr using modulus and\n"
+	"	public or private exponent\n"
+	"	srclen : must be key size(4096 bits)\n"
+	"	exp :	private key exponent for RSA decryption(4096 bits)\n"
+	"		public key exponent for RSA encryption(32 bits)\n"
+	"	rsaop :	0 for RSA Decryption, 1 for RSA Encryption\n"
+	"zynqmp sha3 srcaddr srclen [key_addr] -\n"
+	"	Generates sha3 hash value for data blob at srcaddr and puts\n"
+	"	48 bytes hash value into srcaddr\n"
+	"	Optional key_addr can be specified for saving sha3 hash value\n"
+	"	Note: srcaddr/srclen should not be 0\n"
+	;
+#endif
+
+U_BOOT_CMD(
+	zynqmp, 9, 1, do_zynqmp,
+	"ZynqMP sub-system",
+	zynqmp_help_text
+)
diff --git a/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.S b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.S
new file mode 100644
index 000000000..c4ca77e39
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.S
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+.section .rodata
+
+.global zynqmp_pm_cfg_obj
+.type   zynqmp_pm_cfg_obj, @object
+.global zynqmp_pm_cfg_obj_size
+.type   zynqmp_pm_cfg_obj_size, @object
+
+zynqmp_pm_cfg_obj:
+.align 4
+.incbin CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE
+
+zynqmp_pm_cfg_obj_end:
+
+zynqmp_pm_cfg_obj_size:
+.int zynqmp_pm_cfg_obj_end - zynqmp_pm_cfg_obj
diff --git a/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.h b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.h
new file mode 100644
index 000000000..86e785490
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/pm_cfg_obj.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Luca Ceresoli <luca@lucaceresoli.net>
+ *
+ * Declaration of PMU config object binary blob linked in at build time.
+ */
+
+extern const u32 zynqmp_pm_cfg_obj[];
+extern const int zynqmp_pm_cfg_obj_size;
diff --git a/roms/u-boot/board/xilinx/zynqmp/sleep.h b/roms/u-boot/board/xilinx/zynqmp/sleep.h
new file mode 100644
index 000000000..a962319ff
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/sleep.h
@@ -0,0 +1 @@
+/* Intentionally empty file for psu_init* */
diff --git a/roms/u-boot/board/xilinx/zynqmp/tap_delays.c b/roms/u-boot/board/xilinx/zynqmp/tap_delays.c
new file mode 100644
index 000000000..1cab25f00
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/tap_delays.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZynqMP SoC Tap Delay Programming
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <zynqmp_tap_delay.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+#include <mmc.h>
+
+#define SD_DLL_CTRL			0xFF180358
+#define SD_ITAP_DLY			0xFF180314
+#define SD_OTAP_DLY			0xFF180318
+#define SD0_DLL_RST_MASK		0x00000004
+#define SD0_DLL_RST			0x00000004
+#define SD1_DLL_RST_MASK		0x00040000
+#define SD1_DLL_RST			0x00040000
+#define SD0_ITAPCHGWIN_MASK		0x00000200
+#define SD0_ITAPCHGWIN			0x00000200
+#define SD1_ITAPCHGWIN_MASK		0x02000000
+#define SD1_ITAPCHGWIN			0x02000000
+#define SD0_ITAPDLYENA_MASK		0x00000100
+#define SD0_ITAPDLYENA			0x00000100
+#define SD1_ITAPDLYENA_MASK		0x01000000
+#define SD1_ITAPDLYENA			0x01000000
+#define SD0_ITAPDLYSEL_MASK		0x000000FF
+#define SD1_ITAPDLYSEL_MASK		0x00FF0000
+#define SD0_OTAPDLYSEL_MASK		0x0000003F
+#define SD1_OTAPDLYSEL_MASK		0x003F0000
+
+void zynqmp_dll_reset(u8 deviceid)
+{
+	/* Issue DLL Reset */
+	if (deviceid == 0)
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+				  SD0_DLL_RST);
+	else
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+				  SD1_DLL_RST);
+
+	mdelay(1);
+
+	/* Release DLL Reset */
+	if (deviceid == 0)
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+	else
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+}
+
+void arasan_zynqmp_set_tapdelay(u8 deviceid, u32 itap_delay, u32 otap_delay)
+{
+	if (deviceid == 0) {
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK,
+				  SD0_DLL_RST);
+		/* Program ITAP */
+		if (itap_delay) {
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+					  SD0_ITAPCHGWIN);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA_MASK,
+					  SD0_ITAPDLYENA);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
+					  itap_delay);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN_MASK,
+					  0x0);
+		}
+
+		/* Program OTAP */
+		if (otap_delay)
+			zynqmp_mmio_write(SD_OTAP_DLY, SD0_OTAPDLYSEL_MASK,
+					  otap_delay);
+
+		zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST_MASK, 0x0);
+	} else {
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK,
+				  SD1_DLL_RST);
+		/* Program ITAP */
+		if (itap_delay) {
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+					  SD1_ITAPCHGWIN);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA_MASK,
+					  SD1_ITAPDLYENA);
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
+					  (itap_delay << 16));
+			zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN_MASK,
+					  0x0);
+		}
+
+		/* Program OTAP */
+		if (otap_delay)
+			zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
+					  (otap_delay << 16));
+
+		zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST_MASK, 0x0);
+	}
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/xil_io.h b/roms/u-boot/board/xilinx/zynqmp/xil_io.h
new file mode 100644
index 000000000..e6caa7c85
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/xil_io.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+#include <common.h>
+#include <linux/delay.h>
+
+#define xil_printf(...)
+
+static void Xil_Out32(unsigned long addr, unsigned long val)
+{
+	writel(val, addr);
+}
+
+static int Xil_In32(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static void __maybe_unused usleep(u32 sleep)
+{
+	udelay(sleep);
+}
+
+#endif /* XIL_IO_H */
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
new file mode 100644
index 000000000..be9992c90
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
@@ -0,0 +1,1163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+	psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010B02U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1310U);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0510U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0129A4A4U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180204, 0x00FFE000U, 0x00000000U);
+	psu_mask_write(0xFF180208, 0xFFFFE3FCU, 0x00B02240U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
+	psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
+		      int d_lfhf, int d_cp, int d_res)
+{
+	unsigned int pll_ctrl_regval;
+	unsigned int pll_status_regval;
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 16);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
+	pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
+	pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
+	pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+	pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+	pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+	pll_status_regval = 0x00000000;
+	while ((pll_status_regval & 0x00000002U) != 0x00000002U)
+		pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
+
+	pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+	pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+	pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
+	Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	int cur_PLLCR0;
+
+	cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL0PLLCR0;
+
+	cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL1PLLCR0;
+
+	cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL2PLLCR0;
+
+	cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL3PLLCR0;
+
+	cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SL4PLLCR0;
+
+	cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+	int cur_DX8SLBPLLCR0;
+
+	cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+	Xil_Out32(0xFD080068, 0x02120000);
+	Xil_Out32(0xFD081404, 0x02120000);
+	Xil_Out32(0xFD081444, 0x02120000);
+	Xil_Out32(0xFD081484, 0x02120000);
+	Xil_Out32(0xFD0814C4, 0x02120000);
+	Xil_Out32(0xFD081504, 0x02120000);
+	Xil_Out32(0xFD0817C4, 0x02120000);
+	int cur_fbdiv;
+
+	cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+	dpll_prog(48, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return (0);
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000331U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000B36U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000C21U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000E19U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00001616U);
+	Xil_Out32(0xFD070010U, 0x80000018U);
+	Xil_Out32(0xFD070010U, 0x80000010U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	Xil_Out32(0xFD080068, cur_PLLCR0);
+	Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+	Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+	Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+	Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+	Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+	Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+	for (int tp = 0; tp < 20; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	dpll_prog(cur_fbdiv, 63, 625, 3, 3, 2);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+	prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+	prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+	prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+	for (int tp = 0; tp < 2000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0014FE01);
+
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x8000007E)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x000091C7U);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80008FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return (0);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+	prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+	Xil_Out32(0xFD070180U, 0x02160010U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+	for (int tp = 0; tp < 4000; tp++)
+		regval = Xil_In32(0xFD070018);
+
+	prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+	prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+	prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+	prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+	prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+	prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+	prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+	prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0, count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini
new file mode 120000
index 000000000..5a70cd2f5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini
@@ -0,0 +1 @@
+zynqmp-zcu102-rev1.0
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc0 b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc0
new file mode 120000
index 000000000..f2beed309
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc0
@@ -0,0 +1 @@
+zynqmp-zcu100-revC
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc1 b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc1
new file mode 120000
index 000000000..5a70cd2f5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-emmc1
@@ -0,0 +1 @@
+zynqmp-zcu102-rev1.0
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-qspi b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-qspi
new file mode 120000
index 000000000..5a70cd2f5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-mini-qspi
@@ -0,0 +1 @@
+zynqmp-zcu102-rev1.0
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
new file mode 120000
index 000000000..a64c140b8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
new file mode 100644
index 000000000..dbed7b789
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-topic-miamimp-xilinx-xdp-v1r1/psu_init_gpl.c
@@ -0,0 +1,1038 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010602U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02013C00U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF18030C, 0x00070007U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000C02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000103U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011802U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000C00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07340301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A09U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07241008U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00331008U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E10U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000634U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x1A000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x023FEF1EU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02A00F1EU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x01001FFFU);
+	psu_mask_write(0xFF180144, 0x02A00F1EU, 0x02A00F1EU);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180160, 0x01FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF7FFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0007FFF9U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x03FEDFBFU);
+	psu_mask_write(0xFF18017C, 0x01FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x01FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FFFFF4U);
+	psu_mask_write(0xFF180404, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0010, 0xFFFFFFFFU, 0xDFFF2000U);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x00012000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0000U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+	psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U);
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000082U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000106U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x03FE0001U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD380000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3B0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD380014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3B0014, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+	int count = 0;
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+static void psu_init_sdio_pinmux(void)
+{
+	if (Xil_In32(0xFF0A0064U) & (1U << 19)) {
+		psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+		psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+
+		psu_mask_write(0xFF18030C, 0x00040000U, 0x00040000U);
+
+		psu_mask_write(0xFF180320, 0x33843384U, 0x02801284U);
+	} else {
+		psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	}
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	psu_init_sdio_pinmux();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
new file mode 100644
index 000000000..b8ea291f8
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
@@ -0,0 +1,740 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F0E2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D0419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000802U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x281C0404U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320E08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0x0000003FU, 0x00000000U);
+	psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40237C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40637C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD402360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD406360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40506C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4040F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000022U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401C14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD401C40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40194C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD405C14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD405C40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40594C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD405950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000001U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF9B0000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF9B0014, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	Xil_Out32(0xFD070180U, 0x00AB002BU);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 =
+		L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) | 0x20 | 0x4 |
+		((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 =
+		L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) | 0x40 | 0x8 |
+		((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int tmp_regval;
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
new file mode 100644
index 000000000..520fff28f
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
@@ -0,0 +1,462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E60EC6CU);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013000U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010802U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020204U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x003800D4U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x0000003DU);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x64032010U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x38801C20U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0604U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00040200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	Xil_Out32(0xFD070180U, 0x00800020U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
new file mode 100644
index 000000000..6b0705df3
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c
@@ -0,0 +1,907 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFC7FE07FU, 0x54000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03004U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+	psu_mask_write(0xFF180320, 0x33803380U, 0x02801280U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000011U);
+	psu_mask_write(0xFD402860, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD402868, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000018U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000D3U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000DAU);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184D1BU);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081906U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
new file mode 100644
index 000000000..59de4373b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+	psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+	psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
new file mode 100644
index 000000000..59de4373b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+	psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+	psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
new file mode 100644
index 000000000..59de4373b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U);
+	psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U);
+	psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
new file mode 100644
index 000000000..e0b71abd5
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c
@@ -0,0 +1,917 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x000000E0U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xAF000000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x0003F000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000240U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x00003380U, 0x00000080U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000800U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000800U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0000U);
+	mask_delay(5);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000011U);
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
new file mode 100644
index 000000000..e01915f7e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
@@ -0,0 +1,989 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000400U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC3081020U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000102U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x0028B090U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00404310U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00208030U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x0002020AU);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00360000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00001205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00240012U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0E0B010CU);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00030412U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x04070F0DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00A05000U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x05040306U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01020404U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000201U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030303U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x810B0008U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x00E32DCBU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8206U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00A00070U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000901U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x00000015U);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F060606U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F03D28U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x85642AD0U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xA0AA0580U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A040A1U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06180C08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x2816050AU);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080064U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00602B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00231008U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x0000080EU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000024U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000012U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x810091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00030236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x00894C58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00BD0CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x71000000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x05102000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD090000, 0x0000FFFFU, 0x00000845U);
+	psu_mask_write(0xFD090004, 0x002DB5ADU, 0x002DB5ADU);
+	psu_mask_write(0xFD090800, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD09000C, 0x0000007FU, 0x00000010U);
+	psu_mask_write(0xFD090010, 0x0000007FU, 0x00000010U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000003U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000003U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x51000006U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B00000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x039E1FFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000FC0U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008001U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33803380U, 0x00800080U);
+	psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+	psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40E094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40E37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40D06C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40C0F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000033U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+	Xil_Out32(0xFD090000U, 0x00000845U);
+	Xil_Out32(0xFD090004U, 0x003FFFFFU);
+	Xil_Out32(0xFD09000CU, 0x00000010U);
+	Xil_Out32(0xFD090010U, 0x00000010U);
+	Xil_Out32(0xFD090800U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000331U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000B36U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000C21U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00000E19U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	regval = Xil_In32(0xFD070018);
+	while ((regval & 0x1) != 0x0)
+		regval = Xil_In32(0xFD070018);
+
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	regval = Xil_In32(0xFD070018);
+	Xil_Out32(0xFD070014U, 0x00001616U);
+	Xil_Out32(0xFD070010U, 0x80000038U);
+	Xil_Out32(0xFD070010U, 0x80000030U);
+	Xil_Out32(0xFD0701B0U, 0x00000005U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0014FE01);
+
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x8000007E)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x010091C7U);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80008FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x810091C7U);
+	Xil_Out32(0xFD070180U, 0x010B0008U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD070020U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x0000001FU, 0x0000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
+
+unsigned long psu_post_config_data(void)
+{
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
new file mode 100644
index 000000000..6adbf5e23
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
@@ -0,0 +1,966 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015900U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x80008E69U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85610U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x5DB80000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	prog_reg(0xFD070010U, 0x00000008U, 0x00000003U, 0x00000001U);
+	prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+	prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000819U);
+	prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+	while ((Xil_In32(0xFD070018) & 0x1) == 1)
+		;
+	prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+	prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000899U);
+	prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+	while ((Xil_In32(0xFD070018) & 0x1) == 1)
+		;
+	prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+	prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+	prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+	prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000819U);
+	prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+	while ((Xil_In32(0xFD070018) & 0x1) == 1)
+		;
+	prog_reg(0xFD070010U, 0x00000008U, 0x00000003U, 0x00000000U);
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 8)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 8) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 8) | 0x40
+			    | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 8) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int tmp_regval;
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c
new file mode 100644
index 000000000..1f3f2e66b
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.1/psu_init_gpl.c
@@ -0,0 +1,1042 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014400U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015B00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010D00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010700U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010700U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02022600U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010D00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000702U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01001002U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000702U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000402U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01011000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011F02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01001000U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010E03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000300U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0080808AU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020103U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1107010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020192D5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000801U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FD78U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42021010U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCE401290U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01132B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x0000000CU);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000003EU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x0000000CU);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000003EU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x0597F128U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_delay(1);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+	mask_delay(5);
+	psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+	psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+	psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+	psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+	psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+	psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+	psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+	psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+	psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+	psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+	psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+	psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+	psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+	psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+	psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+	psu_mask_write(0xFD480094, 0x00007E00U, 0x00004A00U);
+	psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+	psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+	psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+	psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+	psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+	psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+	psu_mask_write(0xFD48013C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+	psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+	psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD48008C, 0x0000B000U, 0x00008000U);
+	psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
new file mode 100644
index 000000000..8ecd9ee90
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c
@@ -0,0 +1,817 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000820CU);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000600FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x008005F0U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04121U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28220708U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B08U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00340F09U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A2A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080788, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0807C0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080888, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0808C0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080988, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0809C0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080AC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080BC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080CC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080DC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E88, 0xFFFFFFFFU, 0x0000000AU);
+	psu_mask_write(0xFD080EC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F88, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080FC0, 0xFFFFFFFFU, 0x00020000U);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U);
+	psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U);
+	psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00003FBFU, 0x00002417U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	int dpll_divisor;
+
+	dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U;
+	prog_reg(0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U);
+	prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+	Xil_Out32(0xFD080004U, 0x00040003U);
+	while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+		;
+	prog_reg(0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U);
+	prog_reg(0xFD1A0080, 0x3F00, 0x8, dpll_divisor);
+	Xil_Out32(0xFD080004U, 0x40040071U);
+	while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+		;
+	Xil_Out32(0xFD080004U, 0x40040001U);
+	while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U)
+		;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	Xil_Out32(0xFD08001CU, 0x55AA5498U);
+	Xil_Out32(0xFD08142CU, 0x00041830U);
+	Xil_Out32(0xFD08146CU, 0x00041830U);
+	Xil_Out32(0xFD0814ACU, 0x00041830U);
+	Xil_Out32(0xFD0814ECU, 0x00041830U);
+	Xil_Out32(0xFD08152CU, 0x00041830U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+	Xil_Out32(0xFD08001CU, 0x55AA5480U);
+	Xil_Out32(0xFD08142CU, 0x00041800U);
+	Xil_Out32(0xFD08146CU, 0x00041800U);
+	Xil_Out32(0xFD0814ACU, 0x00041800U);
+	Xil_Out32(0xFD0814ECU, 0x00041800U);
+	Xil_Out32(0xFD08152CU, 0x00041800U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod;
+
+	Xil_Out32(0xFD40EC4C, 0x00000020);
+
+	Xil_Out32(0xFD410010, 0x00000001);
+
+	maskstatus = mask_poll(0xFD40EF14, 0x2);
+
+	if (maskstatus == 0) {
+		/* xil_printf("SERDES initialization timed out\n\r"); */
+		return maskstatus;
+	}
+
+	tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+
+	tmp_0_2 = tmp_0_1 & (0x7);
+	tmp_0_3 = tmp_0_1 & (0x38);
+
+	Xil_Out32(0xFD410010, 0x00000000);
+	Xil_Out32(0xFD410014, 0x00000000);
+
+	tmp_0_2_mod = (tmp_0_2 << 1) | (0x1);
+	tmp_0_2_mod = (tmp_0_2_mod << 4);
+
+	tmp_0_3 = tmp_0_3 >> 3;
+	Xil_Out32(0xFD40EC4C, tmp_0_3);
+
+	Xil_Out32(0xFD40EC48, tmp_0_2_mod);
+	return maskstatus;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int regvalue;
+	unsigned int tmp_regval;
+
+	Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000);
+
+	regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU));
+	regvalue &= 0x7;
+	Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue);
+
+	Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000);
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+
+	status &= init_serdes();
+	init_peripheral();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
new file mode 100644
index 000000000..383e3d0c7
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0x7B3F007FU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EEFU);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F122E7U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			/* xil_printf("#SERDES initialization timed out\n\r");*/
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if ((p_code >= 0x26) && (p_code <= 0x3C))
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if ((n_code >= 0x26) && (n_code <= 0x3C))
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if ((i_code >= 0xC) && (i_code <= 0x12))
+			match_ical_code[i_code - 0xC] += 1;
+
+		if ((r_code >= 0x6) && (r_code <= 0xC))
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+			    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+			    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+
+	status &= psu_afi_config();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revC b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revC
new file mode 120000
index 000000000..529e18f52
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revC
@@ -0,0 +1 @@
+zynqmp-zcu104-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
new file mode 100644
index 000000000..15f0be1a4
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
@@ -0,0 +1,793 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010A02U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010A02U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+	psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
+	psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD405978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD409978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D978, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00003FFFU, 0x00002457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod;
+
+	Xil_Out32(0xFD40EC4C, 0x00000020);
+
+	Xil_Out32(0xFD410010, 0x00000001);
+
+	maskstatus = mask_poll(0xFD40EF14, 0x2);
+
+	if (maskstatus == 0) {
+		xil_printf("SERDES initialization timed out\n\r");
+		return maskstatus;
+	}
+
+	tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+
+	tmp_0_2 = tmp_0_1 & (0x7);
+	tmp_0_3 = tmp_0_1 & (0x38);
+
+	Xil_Out32(0xFD410010, 0x00000000);
+	Xil_Out32(0xFD410014, 0x00000000);
+
+	tmp_0_2_mod = (tmp_0_2 << 1) | (0x1);
+	tmp_0_2_mod = (tmp_0_2_mod << 4);
+
+	tmp_0_3 = tmp_0_3 >> 3;
+	Xil_Out32(0xFD40EC4C, tmp_0_3);
+
+	Xil_Out32(0xFD40EC48, tmp_0_2_mod);
+	return maskstatus;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	unsigned int regvalue;
+	unsigned int tmp_regval;
+
+	Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000);
+	Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000);
+
+	regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU));
+	regvalue &= 0x7;
+	Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue);
+
+	Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000);
+
+	tmp_regval = Xil_In32(0xFD690040);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690040, tmp_regval);
+
+	tmp_regval = Xil_In32(0xFD690030);
+	tmp_regval &= ~0x00000001;
+	Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+
+	status &= init_serdes();
+	init_peripheral();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c
new file mode 100644
index 000000000..7c6664dc9
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu111-revA/psu_init_gpl.c
@@ -0,0 +1,978 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00012D00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010E03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x008180BBU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000909U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01762B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00018046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revA b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revA
new file mode 120000
index 000000000..7abf1dc46
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revA
@@ -0,0 +1 @@
+zynqmp-zc1254-revA
\ No newline at end of file
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
new file mode 100644
index 000000000..2d93b2005
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
@@ -0,0 +1,584 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF180308, 0x00000060U, 0x00000060U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102412U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D041AU);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E6U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000805U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05612C0U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200404U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0200U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330E08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180204, 0x00000073U, 0x00000002U);
+	psu_mask_write(0xFF180208, 0xFFFFFF8CU, 0x00B03004U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008044U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000140U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+	Xil_Out32(0xFD070180U, 0x00AB002BU);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
new file mode 100644
index 000000000..f07e60abb
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c
@@ -0,0 +1,1880 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate);
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_R006_tREFPRD;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
+			  u32 lane2_protocol, u32 lane2_rate,
+			  u32 lane1_protocol, u32 lane1_rate,
+			  u32 lane0_protocol, u32 lane0_rate)
+{
+	Xil_Out32(0xFD410098, 0x00000000);
+	Xil_Out32(0xFD401010, 0x00000040);
+	Xil_Out32(0xFD405010, 0x00000040);
+	Xil_Out32(0xFD409010, 0x00000040);
+	Xil_Out32(0xFD40D010, 0x00000040);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	Xil_Out32(0xFD410098, 0x00000004);
+	mask_delay(50);
+	if (lane0_rate == 1)
+		Xil_Out32(0xFD410098, 0x0000000E);
+	Xil_Out32(0xFD410098, 0x00000006);
+	if (lane0_rate == 1) {
+		Xil_Out32(0xFD40000C, 0x00000004);
+		Xil_Out32(0xFD40400C, 0x00000004);
+		Xil_Out32(0xFD40800C, 0x00000004);
+		Xil_Out32(0xFD40C00C, 0x00000004);
+		Xil_Out32(0xFD410098, 0x00000007);
+		mask_delay(400);
+		Xil_Out32(0xFD40000C, 0x0000000C);
+		Xil_Out32(0xFD40400C, 0x0000000C);
+		Xil_Out32(0xFD40800C, 0x0000000C);
+		Xil_Out32(0xFD40C00C, 0x0000000C);
+		mask_delay(15);
+		Xil_Out32(0xFD410098, 0x0000000F);
+		mask_delay(100);
+	}
+	if (lane0_protocol != 0)
+		mask_poll(0xFD4023E4, 0x00000010U);
+	if (lane1_protocol != 0)
+		mask_poll(0xFD4063E4, 0x00000010U);
+	if (lane2_protocol != 0)
+		mask_poll(0xFD40A3E4, 0x00000010U);
+	if (lane3_protocol != 0)
+		mask_poll(0xFD40E3E4, 0x00000010U);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x000000C0);
+	Xil_Out32(0xFD405010, 0x000000C0);
+	Xil_Out32(0xFD409010, 0x000000C0);
+	Xil_Out32(0xFD40D010, 0x000000C0);
+	Xil_Out32(0xFD401010, 0x00000080);
+	Xil_Out32(0xFD405010, 0x00000080);
+	Xil_Out32(0xFD409010, 0x00000080);
+	Xil_Out32(0xFD40D010, 0x00000080);
+
+	Xil_Out32(0xFD402084, 0x000000C0);
+	Xil_Out32(0xFD406084, 0x000000C0);
+	Xil_Out32(0xFD40A084, 0x000000C0);
+	Xil_Out32(0xFD40E084, 0x000000C0);
+	mask_delay(50);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x00000000);
+	Xil_Out32(0xFD405010, 0x00000000);
+	Xil_Out32(0xFD409010, 0x00000000);
+	Xil_Out32(0xFD40D010, 0x00000000);
+	Xil_Out32(0xFD402084, 0x00000000);
+	Xil_Out32(0xFD406084, 0x00000000);
+	Xil_Out32(0xFD40A084, 0x00000000);
+	Xil_Out32(0xFD40E084, 0x00000000);
+	mask_delay(500);
+	return 1;
+}
+
+static int serdes_bist_static_settings(u32 lane_active)
+{
+	if (lane_active == 0) {
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD403068, 0x1);
+		Xil_Out32(0xFD40306C, 0x1);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403008, 0x0);
+		Xil_Out32(0xFD40300C, 0xF4);
+		Xil_Out32(0xFD403010, 0x0);
+		Xil_Out32(0xFD403014, 0x0);
+		Xil_Out32(0xFD403018, 0x00);
+		Xil_Out32(0xFD40301C, 0xFB);
+		Xil_Out32(0xFD403020, 0xFF);
+		Xil_Out32(0xFD403024, 0x0);
+		Xil_Out32(0xFD403028, 0x00);
+		Xil_Out32(0xFD40302C, 0x00);
+		Xil_Out32(0xFD403030, 0x4A);
+		Xil_Out32(0xFD403034, 0x4A);
+		Xil_Out32(0xFD403038, 0x4A);
+		Xil_Out32(0xFD40303C, 0x4A);
+		Xil_Out32(0xFD403040, 0x0);
+		Xil_Out32(0xFD403044, 0x14);
+		Xil_Out32(0xFD403048, 0x02);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+	}
+	if (lane_active == 1) {
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD407068, 0x1);
+		Xil_Out32(0xFD40706C, 0x1);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407008, 0x0);
+		Xil_Out32(0xFD40700C, 0xF4);
+		Xil_Out32(0xFD407010, 0x0);
+		Xil_Out32(0xFD407014, 0x0);
+		Xil_Out32(0xFD407018, 0x00);
+		Xil_Out32(0xFD40701C, 0xFB);
+		Xil_Out32(0xFD407020, 0xFF);
+		Xil_Out32(0xFD407024, 0x0);
+		Xil_Out32(0xFD407028, 0x00);
+		Xil_Out32(0xFD40702C, 0x00);
+		Xil_Out32(0xFD407030, 0x4A);
+		Xil_Out32(0xFD407034, 0x4A);
+		Xil_Out32(0xFD407038, 0x4A);
+		Xil_Out32(0xFD40703C, 0x4A);
+		Xil_Out32(0xFD407040, 0x0);
+		Xil_Out32(0xFD407044, 0x14);
+		Xil_Out32(0xFD407048, 0x02);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 2) {
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40B068, 0x1);
+		Xil_Out32(0xFD40B06C, 0x1);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B008, 0x0);
+		Xil_Out32(0xFD40B00C, 0xF4);
+		Xil_Out32(0xFD40B010, 0x0);
+		Xil_Out32(0xFD40B014, 0x0);
+		Xil_Out32(0xFD40B018, 0x00);
+		Xil_Out32(0xFD40B01C, 0xFB);
+		Xil_Out32(0xFD40B020, 0xFF);
+		Xil_Out32(0xFD40B024, 0x0);
+		Xil_Out32(0xFD40B028, 0x00);
+		Xil_Out32(0xFD40B02C, 0x00);
+		Xil_Out32(0xFD40B030, 0x4A);
+		Xil_Out32(0xFD40B034, 0x4A);
+		Xil_Out32(0xFD40B038, 0x4A);
+		Xil_Out32(0xFD40B03C, 0x4A);
+		Xil_Out32(0xFD40B040, 0x0);
+		Xil_Out32(0xFD40B044, 0x14);
+		Xil_Out32(0xFD40B048, 0x02);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 3) {
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40F068, 0x1);
+		Xil_Out32(0xFD40F06C, 0x1);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F008, 0x0);
+		Xil_Out32(0xFD40F00C, 0xF4);
+		Xil_Out32(0xFD40F010, 0x0);
+		Xil_Out32(0xFD40F014, 0x0);
+		Xil_Out32(0xFD40F018, 0x00);
+		Xil_Out32(0xFD40F01C, 0xFB);
+		Xil_Out32(0xFD40F020, 0xFF);
+		Xil_Out32(0xFD40F024, 0x0);
+		Xil_Out32(0xFD40F028, 0x00);
+		Xil_Out32(0xFD40F02C, 0x00);
+		Xil_Out32(0xFD40F030, 0x4A);
+		Xil_Out32(0xFD40F034, 0x4A);
+		Xil_Out32(0xFD40F038, 0x4A);
+		Xil_Out32(0xFD40F03C, 0x4A);
+		Xil_Out32(0xFD40F040, 0x0);
+		Xil_Out32(0xFD40F044, 0x14);
+		Xil_Out32(0xFD40F048, 0x02);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+	}
+	return 1;
+}
+
+static int serdes_bist_run(u32 lane_active)
+{
+	if (lane_active == 0) {
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
+	}
+	if (lane_active == 1) {
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
+	}
+	if (lane_active == 2) {
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
+	}
+	if (lane_active == 3) {
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
+	}
+	mask_delay(100);
+	return 1;
+}
+
+static int serdes_bist_result(u32 lane_active)
+{
+	u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+
+	if (lane_active == 0) {
+		pkt_cnt_l0 = Xil_In32(0xFD40304C);
+		pkt_cnt_h0 = Xil_In32(0xFD403050);
+		err_cnt_l0 = Xil_In32(0xFD403054);
+		err_cnt_h0 = Xil_In32(0xFD403058);
+	}
+	if (lane_active == 1) {
+		pkt_cnt_l0 = Xil_In32(0xFD40704C);
+		pkt_cnt_h0 = Xil_In32(0xFD407050);
+		err_cnt_l0 = Xil_In32(0xFD407054);
+		err_cnt_h0 = Xil_In32(0xFD407058);
+	}
+	if (lane_active == 2) {
+		pkt_cnt_l0 = Xil_In32(0xFD40B04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40B050);
+		err_cnt_l0 = Xil_In32(0xFD40B054);
+		err_cnt_h0 = Xil_In32(0xFD40B058);
+	}
+	if (lane_active == 3) {
+		pkt_cnt_l0 = Xil_In32(0xFD40F04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40F050);
+		err_cnt_l0 = Xil_In32(0xFD40F054);
+		err_cnt_h0 = Xil_In32(0xFD40F058);
+	}
+	if (lane_active == 0)
+		Xil_Out32(0xFD403004, 0x0);
+	if (lane_active == 1)
+		Xil_Out32(0xFD407004, 0x0);
+	if (lane_active == 2)
+		Xil_Out32(0xFD40B004, 0x0);
+	if (lane_active == 3)
+		Xil_Out32(0xFD40F004, 0x0);
+	if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
+	    (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
+		return 0;
+	return 1;
+}
+
+static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate,
+				     u32 lane2_protocol, u32 lane2_rate,
+				     u32 lane1_protocol, u32 lane1_rate,
+				     u32 lane0_protocol, u32 lane0_rate,
+				     u32 gen2_calib)
+{
+	u64 tempbistresult;
+	u32 currbistresult[4];
+	u32 prevbistresult[4];
+	u32 itercount = 0;
+	u32 ill12_val[4], ill1_val[4];
+	u32 loop = 0;
+	u32 iterresult[8];
+	u32 meancount[4];
+	u32 bistpasscount[4];
+	u32 meancountalt[4];
+	u32 meancountalt_bistpasscount[4];
+	u32 lane0_active;
+	u32 lane1_active;
+	u32 lane2_active;
+	u32 lane3_active;
+
+	lane0_active = (lane0_protocol == 1);
+	lane1_active = (lane1_protocol == 1);
+	lane2_active = (lane2_protocol == 1);
+	lane3_active = (lane3_protocol == 1);
+	for (loop = 0; loop <= 3; loop++) {
+		iterresult[loop] = 0;
+		iterresult[loop + 4] = 0;
+		meancountalt[loop] = 0;
+		meancountalt_bistpasscount[loop] = 0;
+		meancount[loop] = 0;
+		prevbistresult[loop] = 0;
+		bistpasscount[loop] = 0;
+	}
+	itercount = 0;
+	if (lane0_active)
+		serdes_bist_static_settings(0);
+	if (lane1_active)
+		serdes_bist_static_settings(1);
+	if (lane2_active)
+		serdes_bist_static_settings(2);
+	if (lane3_active)
+		serdes_bist_static_settings(3);
+	do {
+		if (gen2_calib != 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401924, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x000000F0U,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405924, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x000000F0U,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409924, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x000000F0U,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D924, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x000000F0U,
+					       ill12_val[3]);
+		}
+		if (gen2_calib == 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401928, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x0000000FU,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405928, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x0000000FU,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409928, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x0000000FU,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D928, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x0000000FU,
+					       ill12_val[3]);
+		}
+
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
+		if (lane0_active == 1)
+			currbistresult[0] = 0;
+		if (lane1_active == 1)
+			currbistresult[1] = 0;
+		if (lane2_active == 1)
+			currbistresult[2] = 0;
+		if (lane3_active == 1)
+			currbistresult[3] = 0;
+		serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol,
+			       lane2_rate, lane1_protocol, lane1_rate,
+			       lane0_protocol, lane0_rate);
+		if (lane3_active == 1)
+			serdes_bist_run(3);
+		if (lane2_active == 1)
+			serdes_bist_run(2);
+		if (lane1_active == 1)
+			serdes_bist_run(1);
+		if (lane0_active == 1)
+			serdes_bist_run(0);
+		tempbistresult = 0;
+		if (lane3_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(3);
+		tempbistresult = tempbistresult << 1;
+		if (lane2_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(2);
+		tempbistresult = tempbistresult << 1;
+		if (lane1_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(1);
+		tempbistresult = tempbistresult << 1;
+		if (lane0_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(0);
+		Xil_Out32(0xFD410098, 0x0);
+		Xil_Out32(0xFD410098, 0x2);
+
+		if (itercount < 32) {
+			iterresult[0] =
+			    ((iterresult[0] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[1] =
+			    ((iterresult[1] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[2] =
+			    ((iterresult[2] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[3] =
+			    ((iterresult[3] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		} else {
+			iterresult[4] =
+			    ((iterresult[4] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[5] =
+			    ((iterresult[5] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[6] =
+			    ((iterresult[6] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[7] =
+			    ((iterresult[7] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		}
+		currbistresult[0] =
+		    currbistresult[0] | ((tempbistresult & 0x1) == 1);
+		currbistresult[1] =
+		    currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
+		currbistresult[2] =
+		    currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
+		currbistresult[3] =
+		    currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
+
+		for (loop = 0; loop <= 3; loop++) {
+			if (currbistresult[loop] == 1 && prevbistresult[loop] == 1)
+				bistpasscount[loop] = bistpasscount[loop] + 1;
+			if (bistpasscount[loop] < 4 &&
+			    currbistresult[loop] == 0 && itercount > 2) {
+				if (meancountalt_bistpasscount[loop] <
+				    bistpasscount[loop]) {
+					meancountalt_bistpasscount[loop] =
+					    bistpasscount[loop];
+					meancountalt[loop] =
+					    ((itercount - 1) -
+					     ((bistpasscount[loop] + 1) / 2));
+				}
+				bistpasscount[loop] = 0;
+			}
+			if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
+			    (currbistresult[loop] == 0 || itercount == 63) &&
+			    prevbistresult[loop] == 1)
+				meancount[loop] =
+				    (itercount - 1) -
+				    ((bistpasscount[loop] + 1) / 2);
+			prevbistresult[loop] = currbistresult[loop];
+		}
+	} while (++itercount < 64);
+
+	for (loop = 0; loop <= 3; loop++) {
+		if (lane0_active == 0 && loop == 0)
+			continue;
+		if (lane1_active == 0 && loop == 1)
+			continue;
+		if (lane2_active == 0 && loop == 2)
+			continue;
+		if (lane3_active == 0 && loop == 3)
+			continue;
+
+		if (meancount[loop] == 0)
+			meancount[loop] = meancountalt[loop];
+
+		if (gen2_calib != 1) {
+			ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x04 + meancount[loop] * 8) >=
+			     0x100) ? 0x10 : 0x00;
+			Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]);
+		}
+		if (gen2_calib == 1) {
+			ill1_val[loop] =
+			    ((0x104 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x104 + meancount[loop] * 8) >=
+			     0x200) ? 0x02 : 0x01;
+			Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]);
+		}
+	}
+	if (gen2_calib != 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401924, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405924, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409924, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D924, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
+	}
+	if (gen2_calib == 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401928, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405928, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409928, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D928, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
+	}
+
+	if (lane0_active == 1)
+		psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
+	if (lane1_active == 1)
+		psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
+	if (lane2_active == 1)
+		psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
+	if (lane3_active == 1)
+		psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
+
+	Xil_Out32(0xFD410098, 0);
+	if (lane0_active == 1) {
+		Xil_Out32(0xFD403004, 0);
+		Xil_Out32(0xFD403008, 0);
+		Xil_Out32(0xFD40300C, 0);
+		Xil_Out32(0xFD403010, 0);
+		Xil_Out32(0xFD403014, 0);
+		Xil_Out32(0xFD403018, 0);
+		Xil_Out32(0xFD40301C, 0);
+		Xil_Out32(0xFD403020, 0);
+		Xil_Out32(0xFD403024, 0);
+		Xil_Out32(0xFD403028, 0);
+		Xil_Out32(0xFD40302C, 0);
+		Xil_Out32(0xFD403030, 0);
+		Xil_Out32(0xFD403034, 0);
+		Xil_Out32(0xFD403038, 0);
+		Xil_Out32(0xFD40303C, 0);
+		Xil_Out32(0xFD403040, 0);
+		Xil_Out32(0xFD403044, 0);
+		Xil_Out32(0xFD403048, 0);
+		Xil_Out32(0xFD40304C, 0);
+		Xil_Out32(0xFD403050, 0);
+		Xil_Out32(0xFD403054, 0);
+		Xil_Out32(0xFD403058, 0);
+		Xil_Out32(0xFD403068, 1);
+		Xil_Out32(0xFD40306C, 0);
+		Xil_Out32(0xFD4010AC, 0);
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
+	}
+	if (lane1_active == 1) {
+		Xil_Out32(0xFD407004, 0);
+		Xil_Out32(0xFD407008, 0);
+		Xil_Out32(0xFD40700C, 0);
+		Xil_Out32(0xFD407010, 0);
+		Xil_Out32(0xFD407014, 0);
+		Xil_Out32(0xFD407018, 0);
+		Xil_Out32(0xFD40701C, 0);
+		Xil_Out32(0xFD407020, 0);
+		Xil_Out32(0xFD407024, 0);
+		Xil_Out32(0xFD407028, 0);
+		Xil_Out32(0xFD40702C, 0);
+		Xil_Out32(0xFD407030, 0);
+		Xil_Out32(0xFD407034, 0);
+		Xil_Out32(0xFD407038, 0);
+		Xil_Out32(0xFD40703C, 0);
+		Xil_Out32(0xFD407040, 0);
+		Xil_Out32(0xFD407044, 0);
+		Xil_Out32(0xFD407048, 0);
+		Xil_Out32(0xFD40704C, 0);
+		Xil_Out32(0xFD407050, 0);
+		Xil_Out32(0xFD407054, 0);
+		Xil_Out32(0xFD407058, 0);
+		Xil_Out32(0xFD407068, 1);
+		Xil_Out32(0xFD40706C, 0);
+		Xil_Out32(0xFD4050AC, 0);
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
+	}
+	if (lane2_active == 1) {
+		Xil_Out32(0xFD40B004, 0);
+		Xil_Out32(0xFD40B008, 0);
+		Xil_Out32(0xFD40B00C, 0);
+		Xil_Out32(0xFD40B010, 0);
+		Xil_Out32(0xFD40B014, 0);
+		Xil_Out32(0xFD40B018, 0);
+		Xil_Out32(0xFD40B01C, 0);
+		Xil_Out32(0xFD40B020, 0);
+		Xil_Out32(0xFD40B024, 0);
+		Xil_Out32(0xFD40B028, 0);
+		Xil_Out32(0xFD40B02C, 0);
+		Xil_Out32(0xFD40B030, 0);
+		Xil_Out32(0xFD40B034, 0);
+		Xil_Out32(0xFD40B038, 0);
+		Xil_Out32(0xFD40B03C, 0);
+		Xil_Out32(0xFD40B040, 0);
+		Xil_Out32(0xFD40B044, 0);
+		Xil_Out32(0xFD40B048, 0);
+		Xil_Out32(0xFD40B04C, 0);
+		Xil_Out32(0xFD40B050, 0);
+		Xil_Out32(0xFD40B054, 0);
+		Xil_Out32(0xFD40B058, 0);
+		Xil_Out32(0xFD40B068, 1);
+		Xil_Out32(0xFD40B06C, 0);
+		Xil_Out32(0xFD4090AC, 0);
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
+	}
+	if (lane3_active == 1) {
+		Xil_Out32(0xFD40F004, 0);
+		Xil_Out32(0xFD40F008, 0);
+		Xil_Out32(0xFD40F00C, 0);
+		Xil_Out32(0xFD40F010, 0);
+		Xil_Out32(0xFD40F014, 0);
+		Xil_Out32(0xFD40F018, 0);
+		Xil_Out32(0xFD40F01C, 0);
+		Xil_Out32(0xFD40F020, 0);
+		Xil_Out32(0xFD40F024, 0);
+		Xil_Out32(0xFD40F028, 0);
+		Xil_Out32(0xFD40F02C, 0);
+		Xil_Out32(0xFD40F030, 0);
+		Xil_Out32(0xFD40F034, 0);
+		Xil_Out32(0xFD40F038, 0);
+		Xil_Out32(0xFD40F03C, 0);
+		Xil_Out32(0xFD40F040, 0);
+		Xil_Out32(0xFD40F044, 0);
+		Xil_Out32(0xFD40F048, 0);
+		Xil_Out32(0xFD40F04C, 0);
+		Xil_Out32(0xFD40F050, 0);
+		Xil_Out32(0xFD40F054, 0);
+		Xil_Out32(0xFD40F058, 0);
+		Xil_Out32(0xFD40F068, 1);
+		Xil_Out32(0xFD40F06C, 0);
+		Xil_Out32(0xFD40D0AC, 0);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
+	}
+	return 1;
+}
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate)
+{
+	unsigned int rdata = 0;
+	unsigned int sata_gen2 = 1;
+	unsigned int temp_ill12 = 0;
+	unsigned int temp_PLL_REF_SEL_OFFSET;
+	unsigned int temp_TM_IQ_ILL1;
+	unsigned int temp_TM_E_ILL1;
+	unsigned int temp_tx_dig_tm_61;
+	unsigned int temp_tm_dig_6;
+	unsigned int temp_pll_fbdiv_frac_3_msb_offset;
+
+	if (lane0_protocol == 2 || lane0_protocol == 1) {
+		Xil_Out32(0xFD401910, 0xF3);
+		Xil_Out32(0xFD40193C, 0xF3);
+		Xil_Out32(0xFD401914, 0xF3);
+		Xil_Out32(0xFD401940, 0xF3);
+	}
+	if (lane1_protocol == 2 || lane1_protocol == 1) {
+		Xil_Out32(0xFD405910, 0xF3);
+		Xil_Out32(0xFD40593C, 0xF3);
+		Xil_Out32(0xFD405914, 0xF3);
+		Xil_Out32(0xFD405940, 0xF3);
+	}
+	if (lane2_protocol == 2 || lane2_protocol == 1) {
+		Xil_Out32(0xFD409910, 0xF3);
+		Xil_Out32(0xFD40993C, 0xF3);
+		Xil_Out32(0xFD409914, 0xF3);
+		Xil_Out32(0xFD409940, 0xF3);
+	}
+	if (lane3_protocol == 2 || lane3_protocol == 1) {
+		Xil_Out32(0xFD40D910, 0xF3);
+		Xil_Out32(0xFD40D93C, 0xF3);
+		Xil_Out32(0xFD40D914, 0xF3);
+		Xil_Out32(0xFD40D940, 0xF3);
+	}
+
+	if (sata_gen2 == 1) {
+		if (lane0_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
+			Xil_Out32(0xFD402360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
+			psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD401924);
+			Xil_Out32(0xFD4018F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40106C);
+			psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
+
+			Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40106C, temp_tm_dig_6);
+			Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
+			Xil_Out32(0xFD401990, temp_ill12);
+			Xil_Out32(0xFD401924, temp_TM_E_ILL1);
+		}
+		if (lane1_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
+			Xil_Out32(0xFD406360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
+			psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD405924);
+			Xil_Out32(0xFD4058F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40506C);
+			psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40506C, temp_tm_dig_6);
+			Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
+			Xil_Out32(0xFD405990, temp_ill12);
+			Xil_Out32(0xFD405924, temp_TM_E_ILL1);
+		}
+		if (lane2_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
+			Xil_Out32(0xFD40A360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
+			psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD409924);
+			Xil_Out32(0xFD4098F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40906C);
+			psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40906C, temp_tm_dig_6);
+			Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
+			Xil_Out32(0xFD409990, temp_ill12);
+			Xil_Out32(0xFD409924, temp_TM_E_ILL1);
+		}
+		if (lane3_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
+			Xil_Out32(0xFD40E360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
+			psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
+			Xil_Out32(0xFD40D8F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40D06C);
+			psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40D06C, temp_tm_dig_6);
+			Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
+			Xil_Out32(0xFD40D990, temp_ill12);
+			Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
+		}
+		rdata = Xil_In32(0xFD410098);
+		rdata = (rdata & 0xDF);
+		Xil_Out32(0xFD410098, rdata);
+	}
+
+	if (lane0_protocol == 2 && lane0_rate == 3) {
+		psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane1_protocol == 2 && lane1_rate == 3) {
+		psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane2_protocol == 2 && lane2_rate == 3) {
+		psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane3_protocol == 2 && lane3_rate == 3) {
+		psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
+	}
+
+	if (lane0_protocol == 1) {
+		if (lane0_rate == 0) {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+		} else {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, lane0_rate,
+						  1);
+		}
+	}
+
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401914, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401940, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401990, 0x20);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401924, 0x37);
+
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405914, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405940, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405990, 0x20);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405924, 0x37);
+
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409914, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409940, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409990, 0x20);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409924, 0x37);
+
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D914, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D940, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D990, 0x20);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D924, 0x37);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
new file mode 100644
index 000000000..fc3605d60
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c
@@ -0,0 +1,1882 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate);
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	mask_delay(1);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+	mask_delay(5);
+	psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+	psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+	psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+
+	serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD40A3E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
+	psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+	int cur_R006_tREFPRD;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
+			  u32 lane2_protocol, u32 lane2_rate,
+			  u32 lane1_protocol, u32 lane1_rate,
+			  u32 lane0_protocol, u32 lane0_rate)
+{
+	Xil_Out32(0xFD410098, 0x00000000);
+	Xil_Out32(0xFD401010, 0x00000040);
+	Xil_Out32(0xFD405010, 0x00000040);
+	Xil_Out32(0xFD409010, 0x00000040);
+	Xil_Out32(0xFD40D010, 0x00000040);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	Xil_Out32(0xFD410098, 0x00000004);
+	mask_delay(50);
+	if (lane0_rate == 1)
+		Xil_Out32(0xFD410098, 0x0000000E);
+	Xil_Out32(0xFD410098, 0x00000006);
+	if (lane0_rate == 1) {
+		Xil_Out32(0xFD40000C, 0x00000004);
+		Xil_Out32(0xFD40400C, 0x00000004);
+		Xil_Out32(0xFD40800C, 0x00000004);
+		Xil_Out32(0xFD40C00C, 0x00000004);
+		Xil_Out32(0xFD410098, 0x00000007);
+		mask_delay(400);
+		Xil_Out32(0xFD40000C, 0x0000000C);
+		Xil_Out32(0xFD40400C, 0x0000000C);
+		Xil_Out32(0xFD40800C, 0x0000000C);
+		Xil_Out32(0xFD40C00C, 0x0000000C);
+		mask_delay(15);
+		Xil_Out32(0xFD410098, 0x0000000F);
+		mask_delay(100);
+	}
+	if (lane0_protocol != 0)
+		mask_poll(0xFD4023E4, 0x00000010U);
+	if (lane1_protocol != 0)
+		mask_poll(0xFD4063E4, 0x00000010U);
+	if (lane2_protocol != 0)
+		mask_poll(0xFD40A3E4, 0x00000010U);
+	if (lane3_protocol != 0)
+		mask_poll(0xFD40E3E4, 0x00000010U);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x000000C0);
+	Xil_Out32(0xFD405010, 0x000000C0);
+	Xil_Out32(0xFD409010, 0x000000C0);
+	Xil_Out32(0xFD40D010, 0x000000C0);
+	Xil_Out32(0xFD401010, 0x00000080);
+	Xil_Out32(0xFD405010, 0x00000080);
+	Xil_Out32(0xFD409010, 0x00000080);
+	Xil_Out32(0xFD40D010, 0x00000080);
+
+	Xil_Out32(0xFD402084, 0x000000C0);
+	Xil_Out32(0xFD406084, 0x000000C0);
+	Xil_Out32(0xFD40A084, 0x000000C0);
+	Xil_Out32(0xFD40E084, 0x000000C0);
+	mask_delay(50);
+	Xil_Out32(0xFD402084, 0x00000080);
+	Xil_Out32(0xFD406084, 0x00000080);
+	Xil_Out32(0xFD40A084, 0x00000080);
+	Xil_Out32(0xFD40E084, 0x00000080);
+	mask_delay(50);
+	Xil_Out32(0xFD401010, 0x00000000);
+	Xil_Out32(0xFD405010, 0x00000000);
+	Xil_Out32(0xFD409010, 0x00000000);
+	Xil_Out32(0xFD40D010, 0x00000000);
+	Xil_Out32(0xFD402084, 0x00000000);
+	Xil_Out32(0xFD406084, 0x00000000);
+	Xil_Out32(0xFD40A084, 0x00000000);
+	Xil_Out32(0xFD40E084, 0x00000000);
+	mask_delay(500);
+	return 1;
+}
+
+static int serdes_bist_static_settings(u32 lane_active)
+{
+	if (lane_active == 0) {
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD403068, 0x1);
+		Xil_Out32(0xFD40306C, 0x1);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403008, 0x0);
+		Xil_Out32(0xFD40300C, 0xF4);
+		Xil_Out32(0xFD403010, 0x0);
+		Xil_Out32(0xFD403014, 0x0);
+		Xil_Out32(0xFD403018, 0x00);
+		Xil_Out32(0xFD40301C, 0xFB);
+		Xil_Out32(0xFD403020, 0xFF);
+		Xil_Out32(0xFD403024, 0x0);
+		Xil_Out32(0xFD403028, 0x00);
+		Xil_Out32(0xFD40302C, 0x00);
+		Xil_Out32(0xFD403030, 0x4A);
+		Xil_Out32(0xFD403034, 0x4A);
+		Xil_Out32(0xFD403038, 0x4A);
+		Xil_Out32(0xFD40303C, 0x4A);
+		Xil_Out32(0xFD403040, 0x0);
+		Xil_Out32(0xFD403044, 0x14);
+		Xil_Out32(0xFD403048, 0x02);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
+	}
+	if (lane_active == 1) {
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD407068, 0x1);
+		Xil_Out32(0xFD40706C, 0x1);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407008, 0x0);
+		Xil_Out32(0xFD40700C, 0xF4);
+		Xil_Out32(0xFD407010, 0x0);
+		Xil_Out32(0xFD407014, 0x0);
+		Xil_Out32(0xFD407018, 0x00);
+		Xil_Out32(0xFD40701C, 0xFB);
+		Xil_Out32(0xFD407020, 0xFF);
+		Xil_Out32(0xFD407024, 0x0);
+		Xil_Out32(0xFD407028, 0x00);
+		Xil_Out32(0xFD40702C, 0x00);
+		Xil_Out32(0xFD407030, 0x4A);
+		Xil_Out32(0xFD407034, 0x4A);
+		Xil_Out32(0xFD407038, 0x4A);
+		Xil_Out32(0xFD40703C, 0x4A);
+		Xil_Out32(0xFD407040, 0x0);
+		Xil_Out32(0xFD407044, 0x14);
+		Xil_Out32(0xFD407048, 0x02);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 2) {
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40B068, 0x1);
+		Xil_Out32(0xFD40B06C, 0x1);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B008, 0x0);
+		Xil_Out32(0xFD40B00C, 0xF4);
+		Xil_Out32(0xFD40B010, 0x0);
+		Xil_Out32(0xFD40B014, 0x0);
+		Xil_Out32(0xFD40B018, 0x00);
+		Xil_Out32(0xFD40B01C, 0xFB);
+		Xil_Out32(0xFD40B020, 0xFF);
+		Xil_Out32(0xFD40B024, 0x0);
+		Xil_Out32(0xFD40B028, 0x00);
+		Xil_Out32(0xFD40B02C, 0x00);
+		Xil_Out32(0xFD40B030, 0x4A);
+		Xil_Out32(0xFD40B034, 0x4A);
+		Xil_Out32(0xFD40B038, 0x4A);
+		Xil_Out32(0xFD40B03C, 0x4A);
+		Xil_Out32(0xFD40B040, 0x0);
+		Xil_Out32(0xFD40B044, 0x14);
+		Xil_Out32(0xFD40B048, 0x02);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
+	}
+
+	if (lane_active == 3) {
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+		Xil_Out32(0xFD40F068, 0x1);
+		Xil_Out32(0xFD40F06C, 0x1);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F008, 0x0);
+		Xil_Out32(0xFD40F00C, 0xF4);
+		Xil_Out32(0xFD40F010, 0x0);
+		Xil_Out32(0xFD40F014, 0x0);
+		Xil_Out32(0xFD40F018, 0x00);
+		Xil_Out32(0xFD40F01C, 0xFB);
+		Xil_Out32(0xFD40F020, 0xFF);
+		Xil_Out32(0xFD40F024, 0x0);
+		Xil_Out32(0xFD40F028, 0x00);
+		Xil_Out32(0xFD40F02C, 0x00);
+		Xil_Out32(0xFD40F030, 0x4A);
+		Xil_Out32(0xFD40F034, 0x4A);
+		Xil_Out32(0xFD40F038, 0x4A);
+		Xil_Out32(0xFD40F03C, 0x4A);
+		Xil_Out32(0xFD40F040, 0x0);
+		Xil_Out32(0xFD40F044, 0x14);
+		Xil_Out32(0xFD40F048, 0x02);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
+	}
+	return 1;
+}
+
+static int serdes_bist_run(u32 lane_active)
+{
+	if (lane_active == 0) {
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4010AC, 0x0020);
+		Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
+	}
+	if (lane_active == 1) {
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD4050AC, 0x0020);
+		Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
+	}
+	if (lane_active == 2) {
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
+		Xil_Out32(0xFD4090AC, 0x0020);
+		Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
+	}
+	if (lane_active == 3) {
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
+		Xil_Out32(0xFD40D0AC, 0x0020);
+		Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
+	}
+	mask_delay(100);
+	return 1;
+}
+
+static int serdes_bist_result(u32 lane_active)
+{
+	u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
+
+	if (lane_active == 0) {
+		pkt_cnt_l0 = Xil_In32(0xFD40304C);
+		pkt_cnt_h0 = Xil_In32(0xFD403050);
+		err_cnt_l0 = Xil_In32(0xFD403054);
+		err_cnt_h0 = Xil_In32(0xFD403058);
+	}
+	if (lane_active == 1) {
+		pkt_cnt_l0 = Xil_In32(0xFD40704C);
+		pkt_cnt_h0 = Xil_In32(0xFD407050);
+		err_cnt_l0 = Xil_In32(0xFD407054);
+		err_cnt_h0 = Xil_In32(0xFD407058);
+	}
+	if (lane_active == 2) {
+		pkt_cnt_l0 = Xil_In32(0xFD40B04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40B050);
+		err_cnt_l0 = Xil_In32(0xFD40B054);
+		err_cnt_h0 = Xil_In32(0xFD40B058);
+	}
+	if (lane_active == 3) {
+		pkt_cnt_l0 = Xil_In32(0xFD40F04C);
+		pkt_cnt_h0 = Xil_In32(0xFD40F050);
+		err_cnt_l0 = Xil_In32(0xFD40F054);
+		err_cnt_h0 = Xil_In32(0xFD40F058);
+	}
+	if (lane_active == 0)
+		Xil_Out32(0xFD403004, 0x0);
+	if (lane_active == 1)
+		Xil_Out32(0xFD407004, 0x0);
+	if (lane_active == 2)
+		Xil_Out32(0xFD40B004, 0x0);
+	if (lane_active == 3)
+		Xil_Out32(0xFD40F004, 0x0);
+	if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
+	    (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
+		return 0;
+	return 1;
+}
+
+static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate,
+				     u32 lane2_protocol, u32 lane2_rate,
+				     u32 lane1_protocol, u32 lane1_rate,
+				     u32 lane0_protocol, u32 lane0_rate,
+				     u32 gen2_calib)
+{
+	u64 tempbistresult;
+	u32 currbistresult[4];
+	u32 prevbistresult[4];
+	u32 itercount = 0;
+	u32 ill12_val[4], ill1_val[4];
+	u32 loop = 0;
+	u32 iterresult[8];
+	u32 meancount[4];
+	u32 bistpasscount[4];
+	u32 meancountalt[4];
+	u32 meancountalt_bistpasscount[4];
+	u32 lane0_active;
+	u32 lane1_active;
+	u32 lane2_active;
+	u32 lane3_active;
+
+	lane0_active = (lane0_protocol == 1);
+	lane1_active = (lane1_protocol == 1);
+	lane2_active = (lane2_protocol == 1);
+	lane3_active = (lane3_protocol == 1);
+	for (loop = 0; loop <= 3; loop++) {
+		iterresult[loop] = 0;
+		iterresult[loop + 4] = 0;
+		meancountalt[loop] = 0;
+		meancountalt_bistpasscount[loop] = 0;
+		meancount[loop] = 0;
+		prevbistresult[loop] = 0;
+		bistpasscount[loop] = 0;
+	}
+	itercount = 0;
+	if (lane0_active)
+		serdes_bist_static_settings(0);
+	if (lane1_active)
+		serdes_bist_static_settings(1);
+	if (lane2_active)
+		serdes_bist_static_settings(2);
+	if (lane3_active)
+		serdes_bist_static_settings(3);
+	do {
+		if (gen2_calib != 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x04 + itercount * 8) >=
+				     0x100) ? 0x10 : 0x00;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401924, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x000000F0U,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405924, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x000000F0U,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409924, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x000000F0U,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D924, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x000000F0U,
+					       ill12_val[3]);
+		}
+		if (gen2_calib == 1) {
+			if (lane0_active == 1)
+				ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
+			if (lane0_active == 1)
+				ill12_val[0] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane1_active == 1)
+				ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
+			if (lane1_active == 1)
+				ill12_val[1] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane2_active == 1)
+				ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
+			if (lane2_active == 1)
+				ill12_val[2] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+			if (lane3_active == 1)
+				ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
+			if (lane3_active == 1)
+				ill12_val[3] =
+				    ((0x104 + itercount * 8) >=
+				     0x200) ? 0x02 : 0x01;
+
+			if (lane0_active == 1)
+				Xil_Out32(0xFD401928, ill1_val[0]);
+			if (lane0_active == 1)
+				psu_mask_write(0xFD401990, 0x0000000FU,
+					       ill12_val[0]);
+			if (lane1_active == 1)
+				Xil_Out32(0xFD405928, ill1_val[1]);
+			if (lane1_active == 1)
+				psu_mask_write(0xFD405990, 0x0000000FU,
+					       ill12_val[1]);
+			if (lane2_active == 1)
+				Xil_Out32(0xFD409928, ill1_val[2]);
+			if (lane2_active == 1)
+				psu_mask_write(0xFD409990, 0x0000000FU,
+					       ill12_val[2]);
+			if (lane3_active == 1)
+				Xil_Out32(0xFD40D928, ill1_val[3]);
+			if (lane3_active == 1)
+				psu_mask_write(0xFD40D990, 0x0000000FU,
+					       ill12_val[3]);
+		}
+
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
+		if (lane0_active == 1)
+			currbistresult[0] = 0;
+		if (lane1_active == 1)
+			currbistresult[1] = 0;
+		if (lane2_active == 1)
+			currbistresult[2] = 0;
+		if (lane3_active == 1)
+			currbistresult[3] = 0;
+		serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol,
+			       lane2_rate, lane1_protocol, lane1_rate,
+			       lane0_protocol, lane0_rate);
+		if (lane3_active == 1)
+			serdes_bist_run(3);
+		if (lane2_active == 1)
+			serdes_bist_run(2);
+		if (lane1_active == 1)
+			serdes_bist_run(1);
+		if (lane0_active == 1)
+			serdes_bist_run(0);
+		tempbistresult = 0;
+		if (lane3_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(3);
+		tempbistresult = tempbistresult << 1;
+		if (lane2_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(2);
+		tempbistresult = tempbistresult << 1;
+		if (lane1_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(1);
+		tempbistresult = tempbistresult << 1;
+		if (lane0_active == 1)
+			tempbistresult = tempbistresult | serdes_bist_result(0);
+		Xil_Out32(0xFD410098, 0x0);
+		Xil_Out32(0xFD410098, 0x2);
+
+		if (itercount < 32) {
+			iterresult[0] =
+			    ((iterresult[0] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[1] =
+			    ((iterresult[1] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[2] =
+			    ((iterresult[2] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[3] =
+			    ((iterresult[3] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		} else {
+			iterresult[4] =
+			    ((iterresult[4] << 1) |
+			     ((tempbistresult & 0x1) == 0x1));
+			iterresult[5] =
+			    ((iterresult[5] << 1) |
+			     ((tempbistresult & 0x2) == 0x2));
+			iterresult[6] =
+			    ((iterresult[6] << 1) |
+			     ((tempbistresult & 0x4) == 0x4));
+			iterresult[7] =
+			    ((iterresult[7] << 1) |
+			     ((tempbistresult & 0x8) == 0x8));
+		}
+		currbistresult[0] =
+		    currbistresult[0] | ((tempbistresult & 0x1) == 1);
+		currbistresult[1] =
+		    currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
+		currbistresult[2] =
+		    currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
+		currbistresult[3] =
+		    currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
+
+		for (loop = 0; loop <= 3; loop++) {
+			if (currbistresult[loop] == 1 && prevbistresult[loop] == 1)
+				bistpasscount[loop] = bistpasscount[loop] + 1;
+			if (bistpasscount[loop] < 4 && currbistresult[loop] == 0 &&
+			    itercount > 2) {
+				if (meancountalt_bistpasscount[loop] <
+				    bistpasscount[loop]) {
+					meancountalt_bistpasscount[loop] =
+					    bistpasscount[loop];
+					meancountalt[loop] =
+					    ((itercount - 1) -
+					     ((bistpasscount[loop] + 1) / 2));
+				}
+				bistpasscount[loop] = 0;
+			}
+			if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
+			    (currbistresult[loop] == 0 || itercount == 63) &&
+			    prevbistresult[loop] == 1)
+				meancount[loop] =
+				    (itercount - 1) -
+				    ((bistpasscount[loop] + 1) / 2);
+			prevbistresult[loop] = currbistresult[loop];
+		}
+	} while (++itercount < 64);
+
+	for (loop = 0; loop <= 3; loop++) {
+		if (lane0_active == 0 && loop == 0)
+			continue;
+		if (lane1_active == 0 && loop == 1)
+			continue;
+		if (lane2_active == 0 && loop == 2)
+			continue;
+		if (lane3_active == 0 && loop == 3)
+			continue;
+
+		if (meancount[loop] == 0)
+			meancount[loop] = meancountalt[loop];
+
+		if (gen2_calib != 1) {
+			ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x04 + meancount[loop] * 8) >=
+			     0x100) ? 0x10 : 0x00;
+			Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]);
+		}
+		if (gen2_calib == 1) {
+			ill1_val[loop] =
+			    ((0x104 + meancount[loop] * 8) % 0x100);
+			ill12_val[loop] =
+			    ((0x104 + meancount[loop] * 8) >=
+			     0x200) ? 0x02 : 0x01;
+			Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]);
+			Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]);
+			Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]);
+			Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]);
+		}
+	}
+	if (gen2_calib != 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401924, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405924, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409924, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D924, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
+	}
+	if (gen2_calib == 1) {
+		if (lane0_active == 1)
+			Xil_Out32(0xFD401928, ill1_val[0]);
+		if (lane0_active == 1)
+			psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
+		if (lane1_active == 1)
+			Xil_Out32(0xFD405928, ill1_val[1]);
+		if (lane1_active == 1)
+			psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
+		if (lane2_active == 1)
+			Xil_Out32(0xFD409928, ill1_val[2]);
+		if (lane2_active == 1)
+			psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
+		if (lane3_active == 1)
+			Xil_Out32(0xFD40D928, ill1_val[3]);
+		if (lane3_active == 1)
+			psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
+	}
+
+	if (lane0_active == 1)
+		psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
+	if (lane1_active == 1)
+		psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
+	if (lane2_active == 1)
+		psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
+	if (lane3_active == 1)
+		psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
+
+	Xil_Out32(0xFD410098, 0);
+	if (lane0_active == 1) {
+		Xil_Out32(0xFD403004, 0);
+		Xil_Out32(0xFD403008, 0);
+		Xil_Out32(0xFD40300C, 0);
+		Xil_Out32(0xFD403010, 0);
+		Xil_Out32(0xFD403014, 0);
+		Xil_Out32(0xFD403018, 0);
+		Xil_Out32(0xFD40301C, 0);
+		Xil_Out32(0xFD403020, 0);
+		Xil_Out32(0xFD403024, 0);
+		Xil_Out32(0xFD403028, 0);
+		Xil_Out32(0xFD40302C, 0);
+		Xil_Out32(0xFD403030, 0);
+		Xil_Out32(0xFD403034, 0);
+		Xil_Out32(0xFD403038, 0);
+		Xil_Out32(0xFD40303C, 0);
+		Xil_Out32(0xFD403040, 0);
+		Xil_Out32(0xFD403044, 0);
+		Xil_Out32(0xFD403048, 0);
+		Xil_Out32(0xFD40304C, 0);
+		Xil_Out32(0xFD403050, 0);
+		Xil_Out32(0xFD403054, 0);
+		Xil_Out32(0xFD403058, 0);
+		Xil_Out32(0xFD403068, 1);
+		Xil_Out32(0xFD40306C, 0);
+		Xil_Out32(0xFD4010AC, 0);
+		psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
+		psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
+	}
+	if (lane1_active == 1) {
+		Xil_Out32(0xFD407004, 0);
+		Xil_Out32(0xFD407008, 0);
+		Xil_Out32(0xFD40700C, 0);
+		Xil_Out32(0xFD407010, 0);
+		Xil_Out32(0xFD407014, 0);
+		Xil_Out32(0xFD407018, 0);
+		Xil_Out32(0xFD40701C, 0);
+		Xil_Out32(0xFD407020, 0);
+		Xil_Out32(0xFD407024, 0);
+		Xil_Out32(0xFD407028, 0);
+		Xil_Out32(0xFD40702C, 0);
+		Xil_Out32(0xFD407030, 0);
+		Xil_Out32(0xFD407034, 0);
+		Xil_Out32(0xFD407038, 0);
+		Xil_Out32(0xFD40703C, 0);
+		Xil_Out32(0xFD407040, 0);
+		Xil_Out32(0xFD407044, 0);
+		Xil_Out32(0xFD407048, 0);
+		Xil_Out32(0xFD40704C, 0);
+		Xil_Out32(0xFD407050, 0);
+		Xil_Out32(0xFD407054, 0);
+		Xil_Out32(0xFD407058, 0);
+		Xil_Out32(0xFD407068, 1);
+		Xil_Out32(0xFD40706C, 0);
+		Xil_Out32(0xFD4050AC, 0);
+		psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
+		psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
+	}
+	if (lane2_active == 1) {
+		Xil_Out32(0xFD40B004, 0);
+		Xil_Out32(0xFD40B008, 0);
+		Xil_Out32(0xFD40B00C, 0);
+		Xil_Out32(0xFD40B010, 0);
+		Xil_Out32(0xFD40B014, 0);
+		Xil_Out32(0xFD40B018, 0);
+		Xil_Out32(0xFD40B01C, 0);
+		Xil_Out32(0xFD40B020, 0);
+		Xil_Out32(0xFD40B024, 0);
+		Xil_Out32(0xFD40B028, 0);
+		Xil_Out32(0xFD40B02C, 0);
+		Xil_Out32(0xFD40B030, 0);
+		Xil_Out32(0xFD40B034, 0);
+		Xil_Out32(0xFD40B038, 0);
+		Xil_Out32(0xFD40B03C, 0);
+		Xil_Out32(0xFD40B040, 0);
+		Xil_Out32(0xFD40B044, 0);
+		Xil_Out32(0xFD40B048, 0);
+		Xil_Out32(0xFD40B04C, 0);
+		Xil_Out32(0xFD40B050, 0);
+		Xil_Out32(0xFD40B054, 0);
+		Xil_Out32(0xFD40B058, 0);
+		Xil_Out32(0xFD40B068, 1);
+		Xil_Out32(0xFD40B06C, 0);
+		Xil_Out32(0xFD4090AC, 0);
+		psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
+		psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
+	}
+	if (lane3_active == 1) {
+		Xil_Out32(0xFD40F004, 0);
+		Xil_Out32(0xFD40F008, 0);
+		Xil_Out32(0xFD40F00C, 0);
+		Xil_Out32(0xFD40F010, 0);
+		Xil_Out32(0xFD40F014, 0);
+		Xil_Out32(0xFD40F018, 0);
+		Xil_Out32(0xFD40F01C, 0);
+		Xil_Out32(0xFD40F020, 0);
+		Xil_Out32(0xFD40F024, 0);
+		Xil_Out32(0xFD40F028, 0);
+		Xil_Out32(0xFD40F02C, 0);
+		Xil_Out32(0xFD40F030, 0);
+		Xil_Out32(0xFD40F034, 0);
+		Xil_Out32(0xFD40F038, 0);
+		Xil_Out32(0xFD40F03C, 0);
+		Xil_Out32(0xFD40F040, 0);
+		Xil_Out32(0xFD40F044, 0);
+		Xil_Out32(0xFD40F048, 0);
+		Xil_Out32(0xFD40F04C, 0);
+		Xil_Out32(0xFD40F050, 0);
+		Xil_Out32(0xFD40F054, 0);
+		Xil_Out32(0xFD40F058, 0);
+		Xil_Out32(0xFD40F068, 1);
+		Xil_Out32(0xFD40F06C, 0);
+		Xil_Out32(0xFD40D0AC, 0);
+		psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
+		psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
+	}
+	return 1;
+}
+
+static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
+			   u32 lane2_protocol, u32 lane2_rate,
+			   u32 lane1_protocol, u32 lane1_rate,
+			   u32 lane0_protocol, u32 lane0_rate)
+{
+	unsigned int rdata = 0;
+	unsigned int sata_gen2 = 1;
+	unsigned int temp_ill12 = 0;
+	unsigned int temp_PLL_REF_SEL_OFFSET;
+	unsigned int temp_TM_IQ_ILL1;
+	unsigned int temp_TM_E_ILL1;
+	unsigned int temp_tx_dig_tm_61;
+	unsigned int temp_tm_dig_6;
+	unsigned int temp_pll_fbdiv_frac_3_msb_offset;
+
+	if (lane0_protocol == 2 || lane0_protocol == 1) {
+		Xil_Out32(0xFD401910, 0xF3);
+		Xil_Out32(0xFD40193C, 0xF3);
+		Xil_Out32(0xFD401914, 0xF3);
+		Xil_Out32(0xFD401940, 0xF3);
+	}
+	if (lane1_protocol == 2 || lane1_protocol == 1) {
+		Xil_Out32(0xFD405910, 0xF3);
+		Xil_Out32(0xFD40593C, 0xF3);
+		Xil_Out32(0xFD405914, 0xF3);
+		Xil_Out32(0xFD405940, 0xF3);
+	}
+	if (lane2_protocol == 2 || lane2_protocol == 1) {
+		Xil_Out32(0xFD409910, 0xF3);
+		Xil_Out32(0xFD40993C, 0xF3);
+		Xil_Out32(0xFD409914, 0xF3);
+		Xil_Out32(0xFD409940, 0xF3);
+	}
+	if (lane3_protocol == 2 || lane3_protocol == 1) {
+		Xil_Out32(0xFD40D910, 0xF3);
+		Xil_Out32(0xFD40D93C, 0xF3);
+		Xil_Out32(0xFD40D914, 0xF3);
+		Xil_Out32(0xFD40D940, 0xF3);
+	}
+
+	if (sata_gen2 == 1) {
+		if (lane0_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
+			Xil_Out32(0xFD402360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
+			psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD401924);
+			Xil_Out32(0xFD4018F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40106C);
+			psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
+
+			Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40106C, temp_tm_dig_6);
+			Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
+			Xil_Out32(0xFD401990, temp_ill12);
+			Xil_Out32(0xFD401924, temp_TM_E_ILL1);
+		}
+		if (lane1_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
+			Xil_Out32(0xFD406360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
+			psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD405924);
+			Xil_Out32(0xFD4058F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40506C);
+			psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40506C, temp_tm_dig_6);
+			Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
+			Xil_Out32(0xFD405990, temp_ill12);
+			Xil_Out32(0xFD405924, temp_TM_E_ILL1);
+		}
+		if (lane2_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
+			Xil_Out32(0xFD40A360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
+			psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD409924);
+			Xil_Out32(0xFD4098F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40906C);
+			psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40906C, temp_tm_dig_6);
+			Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
+			Xil_Out32(0xFD409990, temp_ill12);
+			Xil_Out32(0xFD409924, temp_TM_E_ILL1);
+		}
+		if (lane3_protocol == 2) {
+			temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
+			Xil_Out32(0xFD40E360, 0x0);
+			temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
+			psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
+			temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
+			temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
+			Xil_Out32(0xFD40D8F8, 0x78);
+			temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
+			temp_tm_dig_6 = Xil_In32(0xFD40D06C);
+			psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
+			psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
+			temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
+
+			serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0);
+
+			Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
+			Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
+			Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
+			Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
+			Xil_Out32(0xFD40D06C, temp_tm_dig_6);
+			Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
+			temp_ill12 =
+			    temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
+			Xil_Out32(0xFD40D990, temp_ill12);
+			Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
+		}
+		rdata = Xil_In32(0xFD410098);
+		rdata = (rdata & 0xDF);
+		Xil_Out32(0xFD410098, rdata);
+	}
+
+	if (lane0_protocol == 2 && lane0_rate == 3) {
+		psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane1_protocol == 2 && lane1_rate == 3) {
+		psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane2_protocol == 2 && lane2_rate == 3) {
+		psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
+	}
+	if (lane3_protocol == 2 && lane3_rate == 3) {
+		psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+		psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
+	}
+
+	if (lane0_protocol == 1) {
+		if (lane0_rate == 0) {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+		} else {
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, 0, 0);
+			serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
+						  lane2_protocol, lane2_rate,
+						  lane1_protocol, lane1_rate,
+						  lane0_protocol, lane0_rate,
+						  1);
+		}
+	}
+
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401914, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401940, 0xF3);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401990, 0x20);
+	if (lane0_protocol == 3)
+		Xil_Out32(0xFD401924, 0x37);
+
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405914, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405940, 0xF3);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405990, 0x20);
+	if (lane1_protocol == 3)
+		Xil_Out32(0xFD405924, 0x37);
+
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409914, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409940, 0xF3);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409990, 0x20);
+	if (lane2_protocol == 3)
+		Xil_Out32(0xFD409924, 0x37);
+
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D914, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D940, 0xF3);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D990, 0x20);
+	if (lane3_protocol == 3)
+		Xil_Out32(0xFD40D924, 0x37);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+	int count = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xc] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp/zynqmp.c b/roms/u-boot/board/xilinx/zynqmp/zynqmp.c
new file mode 100644
index 000000000..ee4d0c85e
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp/zynqmp.c
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <debug_uart.h>
+#include <env.h>
+#include <env_internal.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <sata.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <malloc.h>
+#include <wdt.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/psu_init_gpl.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/ptrace.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <zynqmppl.h>
+#include <zynqmp_firmware.h>
+#include <g_dnl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include "../common/board.h"
+
+#include "pm_cfg_obj.h"
+
+#define ZYNQMP_VERSION_SIZE	7
+#define EFUSE_VCU_DIS_MASK	0x100
+#define EFUSE_VCU_DIS_SHIFT	8
+#define EFUSE_GPU_DIS_MASK	0x20
+#define EFUSE_GPU_DIS_SHIFT	5
+#define IDCODE2_PL_INIT_MASK	0x200
+#define IDCODE2_PL_INIT_SHIFT	9
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
+static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+
+enum {
+	ZYNQMP_VARIANT_EG = BIT(0U),
+	ZYNQMP_VARIANT_EV = BIT(1U),
+	ZYNQMP_VARIANT_CG = BIT(2U),
+	ZYNQMP_VARIANT_DR = BIT(3U),
+};
+
+static const struct {
+	u32 id;
+	u8 device;
+	u8 variants;
+} zynqmp_devices[] = {
+	{
+		.id = 0x04711093,
+		.device = 2,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04710093,
+		.device = 3,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04721093,
+		.device = 4,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04720093,
+		.device = 5,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04739093,
+		.device = 6,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04730093,
+		.device = 7,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04738093,
+		.device = 9,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04740093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04750093,
+		.device = 15,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04759093,
+		.device = 17,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04758093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x047E1093,
+		.device = 21,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E3093,
+		.device = 23,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E5093,
+		.device = 25,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E4093,
+		.device = 27,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E0093,
+		.device = 28,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E2093,
+		.device = 29,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E6093,
+		.device = 39,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FD093,
+		.device = 43,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047F8093,
+		.device = 46,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FF093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FB093,
+		.device = 48,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FE093,
+		.device = 49,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+};
+
+static char *zynqmp_get_silicon_idcode_name(void)
+{
+	u32 i;
+	u32 idcode, idcode2;
+	char name[ZYNQMP_VERSION_SIZE];
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+	if (ret) {
+		debug("%s: Getting chipid failed\n", __func__);
+		return "unknown";
+	}
+
+	/*
+	 * Firmware returns:
+	 * payload[0][31:0]  = status of the operation
+	 * payload[1]] = IDCODE
+	 * payload[2][19:0]  = Version
+	 * payload[2][28:20] = EXTENDED_IDCODE
+	 * payload[2][29] = PL_INIT
+	 */
+
+	idcode  = ret_payload[1];
+	idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+	debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
+	      idcode2);
+
+	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
+		if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
+			break;
+	}
+
+	if (i >= ARRAY_SIZE(zynqmp_devices))
+		return "unknown";
+
+	/* Add device prefix to the name */
+	ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
+		       zynqmp_devices[i].device);
+	if (ret < 0)
+		return "unknown";
+
+	if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
+		/* Devices with EV variant might be EG/CG/EV family */
+		if (idcode2 & IDCODE2_PL_INIT_MASK) {
+			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
+				      EFUSE_VCU_DIS_SHIFT) << 1 |
+				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
+				      EFUSE_GPU_DIS_SHIFT);
+
+			/*
+			 * Get family name based on extended idcode values as
+			 * determined on UG1087, EXTENDED_IDCODE register
+			 * description
+			 */
+			switch (family) {
+			case 0x00:
+				strncat(name, "ev", 2);
+				break;
+			case 0x10:
+				strncat(name, "eg", 2);
+				break;
+			case 0x11:
+				strncat(name, "cg", 2);
+				break;
+			default:
+				/* Do not append family name*/
+				break;
+			}
+		} else {
+			/*
+			 * When PL powered down the VCU Disable efuse cannot be
+			 * read. So, ignore the bit and just findout if it is CG
+			 * or EG/EV variant.
+			 */
+			strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
+				"e", 2);
+		}
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
+		/* Devices with CG variant might be EG or CG family */
+		strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
+		strncat(name, "eg", 2);
+	} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
+		strncat(name, "dr", 2);
+	} else {
+		debug("Variant not identified\n");
+	}
+
+	return strdup(name);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
+	int ret;
+
+	ret = psu_init();
+	if (ret)
+		return ret;
+
+	/*
+	 * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
+	 * supply sense channel to SysMon supply registers inside the IP.
+	 * This register must be programmed to complete SysMon IP
+	 * configuration. The default register configuration after
+	 * power-up is incorrect. Hence, fix this by writing the
+	 * correct value - 0x3210.
+	 */
+	writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
+	       ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
+
+	/* Delay is required for clocks to be propagated */
+	udelay(1000000);
+#endif
+
+#ifdef CONFIG_DEBUG_UART
+	/* Uart debug for sure */
+	debug_uart_init();
+	puts("Debug uart enabled\n"); /* or printch() */
+#endif
+
+	return 0;
+}
+
+static int multi_boot(void)
+{
+	u32 multiboot;
+
+	multiboot = readl(&csu_base->multi_boot);
+
+	printf("Multiboot:\t%d\n", multiboot);
+
+	return 0;
+}
+
+#define PS_SYSMON_ANALOG_BUS_VAL	0x3210
+#define PS_SYSMON_ANALOG_BUS_REG	0xFFA50914
+
+int board_init(void)
+{
+#if defined(CONFIG_ZYNQMP_FIRMWARE)
+	struct udevice *dev;
+
+	uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
+	if (!dev)
+		panic("PMU Firmware device not found - Enable it");
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+	/* Check *at build time* if the filename is an non-empty string */
+	if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
+		zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
+						zynqmp_pm_cfg_obj_size);
+	printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
+#else
+	if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
+		xilinx_read_eeprom();
+#endif
+
+	printf("EL Level:\tEL%d\n", current_el());
+
+	/* Bug in ROM sets wrong value in this register */
+	writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
+
+#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
+	zynqmppl.name = zynqmp_get_silicon_idcode_name();
+	printf("Chip ID:\t%s\n", zynqmppl.name);
+	fpga_init();
+	fpga_add(fpga_xilinx, &zynqmppl);
+#endif
+
+	if (current_el() == 3)
+		multi_boot();
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	u32 val;
+
+	if (current_el() != 3)
+		return 0;
+
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+
+	if (!val) {
+		val = readl(&crlapb_base->timestamp_ref_ctrl);
+		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+		writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+		/* Program freq register in System counter */
+		writel(zynqmp_get_system_timer_freq(),
+		       &iou_scntr_secure->base_frequency_id_register);
+		/* And enable system counter */
+		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+		       &iou_scntr_secure->counter_control_register);
+	}
+	return 0;
+}
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+			 char *const argv[])
+{
+	int ret = 0;
+
+	if (current_el() > 1) {
+		smp_kick_all_cpus();
+		dcache_disable();
+		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
+				    ES_TO_AARCH64);
+	} else {
+		printf("FAIL: current EL is not above EL1\n");
+		ret = EINVAL;
+	}
+	return ret;
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
+{
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+#else
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = get_effective_memsize();
+
+	mem_map_fill();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
+#endif
+
+void reset_cpu(void)
+{
+}
+
+static u8 __maybe_unused zynqmp_get_bootmode(void)
+{
+	u8 bootmode;
+	u32 reg = 0;
+	int ret;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
+	if (ret)
+		return -EINVAL;
+
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
+	bootmode = reg & BOOT_MODES_MASK;
+
+	return bootmode;
+}
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+static const struct {
+	u32 bit;
+	const char *name;
+} reset_reasons[] = {
+	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
+	{ RESET_REASON_SOFT, "SOFT" },
+	{ RESET_REASON_SRST, "SRST" },
+	{ RESET_REASON_PSONLY, "PS-ONLY" },
+	{ RESET_REASON_PMU, "PMU" },
+	{ RESET_REASON_INTERNAL, "INTERNAL" },
+	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
+	{}
+};
+
+static int reset_reason(void)
+{
+	u32 reg;
+	int i, ret;
+	const char *reason = NULL;
+
+	ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
+	if (ret)
+		return -EINVAL;
+
+	puts("Reset reason:\t");
+
+	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
+		if (reg & reset_reasons[i].bit) {
+			reason = reset_reasons[i].name;
+			printf("%s ", reset_reasons[i].name);
+			break;
+		}
+	}
+
+	puts("\n");
+
+	env_set("reset_reason", reason);
+
+	return 0;
+}
+
+static int set_fdtfile(void)
+{
+	char *compatible, *fdtfile;
+	const char *suffix = ".dtb";
+	const char *vendor = "xilinx/";
+	int fdt_compat_len;
+
+	if (env_get("fdtfile"))
+		return 0;
+
+	compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
+					 &fdt_compat_len);
+	if (compatible && fdt_compat_len) {
+		char *name;
+
+		debug("Compatible: %s\n", compatible);
+
+		name = strchr(compatible, ',');
+		if (!name)
+			return -EINVAL;
+
+		name++;
+
+		fdtfile = calloc(1, strlen(vendor) + strlen(name) +
+				 strlen(suffix) + 1);
+		if (!fdtfile)
+			return -ENOMEM;
+
+		sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
+
+		env_set("fdtfile", fdtfile);
+		free(fdtfile);
+	}
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u8 bootmode;
+	struct udevice *dev;
+	int bootseq = -1;
+	int bootseq_len = 0;
+	int env_targets_len = 0;
+	const char *mode;
+	char *new_targets;
+	char *env_targets;
+	int ret;
+
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
+	usb_ether_init();
+#endif
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
+
+	if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		return 0;
+
+	ret = set_fdtfile();
+	if (ret)
+		return ret;
+
+	bootmode = zynqmp_get_bootmode();
+
+	puts("Bootmode: ");
+	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "usb_dfu0 usb_dfu1";
+		env_set("modeboot", "usb_dfu_spl");
+		break;
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		mode = "jtag pxe dhcp";
+		env_set("modeboot", "jtagboot");
+		break;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		mode = "qspi0";
+		puts("QSPI_MODE\n");
+		env_set("modeboot", "qspiboot");
+		break;
+	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff160000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff160000", &dev)) {
+			puts("Boot from EMMC but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff160000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff160000", &dev)) {
+			puts("Boot from SD0 but without SD0 enabled!\n");
+			return -1;
+		}
+		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		env_set("modeboot", "sdboot");
+		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+		if (uclass_get_device_by_name(UCLASS_MMC,
+					      "mmc@ff170000", &dev) &&
+		    uclass_get_device_by_name(UCLASS_MMC,
+					      "sdhci@ff170000", &dev)) {
+			puts("Boot from SD1 but without SD1 enabled!\n");
+			return -1;
+		}
+		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+
+		mode = "mmc";
+		bootseq = dev_seq(dev);
+		env_set("modeboot", "sdboot");
+		break;
+	case NAND_MODE:
+		puts("NAND_MODE\n");
+		mode = "nand0";
+		env_set("modeboot", "nandboot");
+		break;
+	default:
+		mode = "";
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	if (bootseq >= 0) {
+		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+		debug("Bootseq len: %x\n", bootseq_len);
+		env_set_hex("bootseq", bootseq);
+	}
+
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	env_targets = env_get("boot_targets");
+	if (env_targets)
+		env_targets_len = strlen(env_targets);
+
+	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+			     bootseq_len);
+	if (!new_targets)
+		return -ENOMEM;
+
+	if (bootseq >= 0)
+		sprintf(new_targets, "%s%x %s", mode, bootseq,
+			env_targets ? env_targets : "");
+	else
+		sprintf(new_targets, "%s %s", mode,
+			env_targets ? env_targets : "");
+
+	env_set("boot_targets", new_targets);
+
+	reset_reason();
+
+	return board_late_init_xilinx();
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: Xilinx ZynqMP\n");
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	u32 bootmode = zynqmp_get_bootmode();
+
+	if (prio)
+		return ENVL_UNKNOWN;
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+			return ENVL_FAT;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+			return ENVL_EXT4;
+		return ENVL_UNKNOWN;
+	case NAND_MODE:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+			return ENVL_NAND;
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+			return ENVL_UBI;
+		return ENVL_UNKNOWN;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+			return ENVL_SPI_FLASH;
+		return ENVL_UNKNOWN;
+	case JTAG_MODE:
+	default:
+		return ENVL_NOWHERE;
+	}
+}
diff --git a/roms/u-boot/board/xilinx/zynqmp_r5/MAINTAINERS b/roms/u-boot/board/xilinx/zynqmp_r5/MAINTAINERS
new file mode 100644
index 000000000..ac2676497
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp_r5/MAINTAINERS
@@ -0,0 +1,7 @@
+XILINX_ZYNQMP_R5 BOARDS
+M:	Michal Simek <michal.simek@xilinx.com>
+S:	Maintained
+F:	arch/arm/dts/zynqmp-r5*
+F:	board/xilinx/zynqmp_r5/
+F:	include/configs/xilinx_zynqmp_r5_*
+F:	configs/xilinx_zynqmp_r5_*
diff --git a/roms/u-boot/board/xilinx/zynqmp_r5/Makefile b/roms/u-boot/board/xilinx/zynqmp_r5/Makefile
new file mode 100644
index 000000000..c5a3e3d32
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp_r5/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+#
+
+obj-y	:= board.o
diff --git a/roms/u-boot/board/xilinx/zynqmp_r5/board.c b/roms/u-boot/board/xilinx/zynqmp_r5/board.c
new file mode 100644
index 000000000..5c5a2e938
--- /dev/null
+++ b/roms/u-boot/board/xilinx/zynqmp_r5/board.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}