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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/doc/SPI/README.altera_spi | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/doc/SPI/README.altera_spi')
-rw-r--r-- | roms/u-boot/doc/SPI/README.altera_spi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/roms/u-boot/doc/SPI/README.altera_spi b/roms/u-boot/doc/SPI/README.altera_spi new file mode 100644 index 000000000..b07449f80 --- /dev/null +++ b/roms/u-boot/doc/SPI/README.altera_spi @@ -0,0 +1,6 @@ +SoCFPGA EPCS/EPCQx1 mini howto: +- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild +- The controller base address is the "Base" in QSys + 0x400 +- Set MSEL[4:0]=10010 (AS Standard) +- Load the bitstream into FPGA, enable bridges +- Only then will the driver work |