Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

5 files changed, 318 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/bus/Kconfig b/roms/u-boot/drivers/bus/Kconfig
new file mode 100644
index 000000000..d742ed333
--- /dev/null
+++ b/roms/u-boot/drivers/bus/Kconfig
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Bus Devices
+#
+
+menu "Bus devices"
+
+config TI_PWMSS
+	bool
+	default y if ARCH_OMAP2PLUS && PWM_TI_EHRPWM
+	help
+	  PWM Subsystem driver support for AM33xx SOC.
+
+config TI_SYSC
+	bool "TI sysc interconnect target module driver"
+	depends on ARCH_OMAP2PLUS
+	help
+	  Generic driver for Texas Instruments interconnect target module
+	  found on many TI SoCs.
+
+config UNIPHIER_SYSTEM_BUS
+	bool "UniPhier System Bus driver"
+	depends on ARCH_UNIPHIER
+	default y
+	help
+	  Support for UniPhier System Bus, a simple external bus.  This is
+	  needed to use on-board devices connected to UniPhier SoCs.
+
+endmenu
diff --git a/roms/u-boot/drivers/bus/Makefile b/roms/u-boot/drivers/bus/Makefile
new file mode 100644
index 000000000..a2e71c7b3
--- /dev/null
+++ b/roms/u-boot/drivers/bus/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the bus drivers.
+#
+
+obj-$(CONFIG_TI_PWMSS)	+= ti-pwmss.o
+obj-$(CONFIG_TI_SYSC)	+= ti-sysc.o
+obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
diff --git a/roms/u-boot/drivers/bus/ti-pwmss.c b/roms/u-boot/drivers/bus/ti-pwmss.c
new file mode 100644
index 000000000..265b4cf83
--- /dev/null
+++ b/roms/u-boot/drivers/bus/ti-pwmss.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Pulse-Width Modulation Subsystem (pwmss)
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+static const struct udevice_id ti_pwmss_ids[] = {
+	{.compatible = "ti,am33xx-pwmss"},
+	{}
+};
+
+U_BOOT_DRIVER(ti_pwmss) = {
+	.name = "ti_pwmss",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = ti_pwmss_ids,
+	.bind = dm_scan_fdt_dev,
+};
diff --git a/roms/u-boot/drivers/bus/ti-sysc.c b/roms/u-boot/drivers/bus/ti-sysc.c
new file mode 100644
index 000000000..778c0654f
--- /dev/null
+++ b/roms/u-boot/drivers/bus/ti-sysc.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments sysc interconnect target driver
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+
+enum ti_sysc_clocks {
+	TI_SYSC_FCK,
+	TI_SYSC_ICK,
+	TI_SYSC_MAX_CLOCKS,
+};
+
+static const char *const clock_names[] = {"fck", "ick"};
+
+struct ti_sysc_priv {
+	int clocks_count;
+	struct clk clocks[TI_SYSC_MAX_CLOCKS];
+};
+
+static const struct udevice_id ti_sysc_ids[] = {
+	{.compatible = "ti,sysc-omap2"},
+	{.compatible = "ti,sysc-omap4"},
+	{.compatible = "ti,sysc-omap4-simple"},
+	{.compatible = "ti,sysc-omap3430-sr"},
+	{.compatible = "ti,sysc-omap3630-sr"},
+	{.compatible = "ti,sysc-omap4-sr"},
+	{.compatible = "ti,sysc-omap3-sham"},
+	{.compatible = "ti,sysc-omap-aes"},
+	{.compatible = "ti,sysc-mcasp"},
+	{.compatible = "ti,sysc-usb-host-fs"},
+	{}
+};
+
+static int ti_sysc_get_one_clock(struct udevice *dev, enum ti_sysc_clocks index)
+{
+	struct ti_sysc_priv *priv = dev_get_priv(dev);
+	const char *name;
+	int err;
+
+	switch (index) {
+	case TI_SYSC_FCK:
+		break;
+	case TI_SYSC_ICK:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	name = clock_names[index];
+
+	err = clk_get_by_name(dev, name, &priv->clocks[index]);
+	if (err) {
+		if (err == -ENODATA)
+			return 0;
+
+		dev_err(dev, "failed to get %s clock\n", name);
+		return err;
+	}
+
+	return 0;
+}
+
+static int ti_sysc_put_clocks(struct udevice *dev)
+{
+	struct ti_sysc_priv *priv = dev_get_priv(dev);
+	int err;
+
+	err = clk_release_all(priv->clocks, priv->clocks_count);
+	if (err)
+		dev_err(dev, "failed to release all clocks\n");
+
+	return err;
+}
+
+static int ti_sysc_get_clocks(struct udevice *dev)
+{
+	struct ti_sysc_priv *priv = dev_get_priv(dev);
+	int i, err;
+
+	for (i = 0; i < TI_SYSC_MAX_CLOCKS; i++) {
+		err = ti_sysc_get_one_clock(dev, i);
+		if (!err)
+			priv->clocks_count++;
+		else if (err != -ENOENT)
+			return err;
+	}
+
+	return 0;
+}
+
+static int ti_sysc_child_post_remove(struct udevice *dev)
+{
+	struct ti_sysc_priv *priv = dev_get_priv(dev->parent);
+	int i, err;
+
+	for (i = 0; i < priv->clocks_count; i++) {
+		err = clk_disable(&priv->clocks[i]);
+		if (err) {
+			dev_err(dev->parent, "failed to disable %s clock\n",
+				clock_names[i]);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static int ti_sysc_child_pre_probe(struct udevice *dev)
+{
+	struct ti_sysc_priv *priv = dev_get_priv(dev->parent);
+	int i, err;
+
+	for (i = 0; i < priv->clocks_count; i++) {
+		err = clk_enable(&priv->clocks[i]);
+		if (err) {
+			dev_err(dev->parent, "failed to enable %s clock\n",
+				clock_names[i]);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static int ti_sysc_remove(struct udevice *dev)
+{
+	return ti_sysc_put_clocks(dev);
+}
+
+static int ti_sysc_probe(struct udevice *dev)
+{
+	int err;
+
+	err = ti_sysc_get_clocks(dev);
+	if (err)
+		goto clocks_err;
+
+	return 0;
+
+clocks_err:
+	ti_sysc_put_clocks(dev);
+	return err;
+}
+
+U_BOOT_DRIVER(ti_sysc) = {
+	.name = "ti_sysc",
+	.id = UCLASS_SIMPLE_BUS,
+	.of_match = ti_sysc_ids,
+	.probe = ti_sysc_probe,
+	.remove = ti_sysc_remove,
+	.child_pre_probe = ti_sysc_child_pre_probe,
+	.child_post_remove = ti_sysc_child_post_remove,
+	.priv_auto = sizeof(struct ti_sysc_priv)
+};
diff --git a/roms/u-boot/drivers/bus/uniphier-system-bus.c b/roms/u-boot/drivers/bus/uniphier-system-bus.c
new file mode 100644
index 000000000..ea08d66a0
--- /dev/null
+++ b/roms/u-boot/drivers/bus/uniphier-system-bus.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+#include <dm.h>
+
+/* System Bus Controller registers */
+#define UNIPHIER_SBC_BASE	0x100	/* base address of bank0 space */
+#define    UNIPHIER_SBC_BASE_BE		BIT(0)	/* bank_enable */
+#define UNIPHIER_SBC_CTRL0	0x200	/* timing parameter 0 of bank0 */
+#define UNIPHIER_SBC_CTRL1	0x204	/* timing parameter 1 of bank0 */
+#define UNIPHIER_SBC_CTRL2	0x208	/* timing parameter 2 of bank0 */
+#define UNIPHIER_SBC_CTRL3	0x20c	/* timing parameter 3 of bank0 */
+#define UNIPHIER_SBC_CTRL4	0x300	/* timing parameter 4 of bank0 */
+
+#define UNIPHIER_SBC_STRIDE	0x10	/* register stride to next bank */
+
+#if 1
+/* slower but LED works */
+#define SBCTRL0_VALUE	0x55450000
+#define SBCTRL1_VALUE	0x07168d00
+#define SBCTRL2_VALUE	0x34000009
+#define SBCTRL4_VALUE	0x02110110
+
+#else
+/* faster but LED does not work */
+#define SBCTRL0_VALUE	0x55450000
+#define SBCTRL1_VALUE	0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_VALUE	0x34000009
+#define SBCTRL4_VALUE	0x02110210
+#endif
+
+void uniphier_system_bus_set_reg(void __iomem *membase)
+{
+	void __iomem *bank0_base = membase;
+	void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE;
+
+	/*
+	 * Only CS1 is connected to support card.
+	 * BKSZ[1:0] should be set to "01".
+	 */
+	writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0);
+	writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1);
+	writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2);
+	writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4);
+
+	if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) {
+		/*
+		 * Boot Swap On: boot from external NOR/SRAM
+		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+		 *
+		 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+		 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+		 */
+		writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE);
+	} else {
+		/*
+		 * Boot Swap Off: boot from mask ROM
+		 * 0x40000000-0x41ffffff: mask ROM
+		 * 0x42000000-0x43efffff: memory bank (31MB)
+		 * 0x43f00000-0x43ffffff: peripherals (1MB)
+		 */
+		writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */
+		writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE);
+	}
+}
+
+static int uniphier_system_bus_probe(struct udevice *dev)
+{
+	fdt_addr_t base;
+	void __iomem *membase;
+
+	base = dev_read_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	membase = devm_ioremap(dev, base, SZ_1K);
+	if (!membase)
+		return -ENOMEM;
+
+	uniphier_system_bus_set_reg(membase);
+
+	return 0;
+}
+
+static const struct udevice_id uniphier_system_bus_match[] = {
+	{ .compatible = "socionext,uniphier-system-bus" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_system_bus_driver) = {
+	.name	= "uniphier-system-bus",
+	.id	= UCLASS_SIMPLE_BUS,
+	.of_match = uniphier_system_bus_match,
+	.probe = uniphier_system_bus_probe,
+};