Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

7 files changed, 573 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/cache/Kconfig b/roms/u-boot/drivers/cache/Kconfig
new file mode 100644
index 000000000..1e452ad6d
--- /dev/null
+++ b/roms/u-boot/drivers/cache/Kconfig
@@ -0,0 +1,42 @@
+#
+# Cache controllers
+#
+
+menu "Cache Controller drivers"
+
+config CACHE
+	bool "Enable Driver Model for Cache controllers"
+	depends on DM
+	help
+	  Enable driver model for cache controllers that are found on
+	  most CPU's. Cache is memory that the CPU can access directly and
+	  is usually located on the same chip. This uclass can be used for
+	  configuring settings that be found from a device tree file.
+
+config L2X0_CACHE
+	tristate "PL310 cache driver"
+	select CACHE
+	depends on ARM
+	help
+	  This driver is for the PL310 cache controller commonly found on
+	  ARMv7(32-bit) devices. The driver configures the cache settings
+	  found in the device tree.
+
+config V5L2_CACHE
+	bool "Andes V5L2 cache driver"
+	select CACHE
+	depends on RISCV_NDS_CACHE
+	help
+	  Support Andes V5L2 cache controller in AE350 platform.
+	  It will configure tag and data ram timing control from the
+	  device tree and enable L2 cache.
+
+config NCORE_CACHE
+	bool "Arteris Ncore cache coherent unit driver"
+	select CACHE
+	help
+	  This driver is for the Arteris Ncore cache coherent unit (CCU)
+	  controller. The driver initializes cache directories and coherent
+	  agent interfaces.
+
+endmenu
diff --git a/roms/u-boot/drivers/cache/Makefile b/roms/u-boot/drivers/cache/Makefile
new file mode 100644
index 000000000..fed50be3f
--- /dev/null
+++ b/roms/u-boot/drivers/cache/Makefile
@@ -0,0 +1,6 @@
+
+obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_cache.o
+obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/roms/u-boot/drivers/cache/cache-l2x0.c b/roms/u-boot/drivers/cache/cache-l2x0.c
new file mode 100644
index 000000000..a1556fbf1
--- /dev/null
+++ b/roms/u-boot/drivers/cache/cache-l2x0.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/pl310.h>
+
+static void l2c310_of_parse_and_init(struct udevice *dev)
+{
+	u32 tag[3] = { 0, 0, 0 };
+	u32 saved_reg, prefetch;
+	struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+
+	/* Disable the L2 Cache */
+	clrbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);
+
+	saved_reg = readl(&regs->pl310_aux_ctrl);
+	if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
+		if (prefetch)
+			saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
+		else
+			saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
+	}
+
+	if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
+		if (prefetch)
+			saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
+		else
+			saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
+	}
+
+	if (dev_read_bool(dev, "arm,shared-override"))
+		saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE;
+
+	writel(saved_reg, &regs->pl310_aux_ctrl);
+
+	saved_reg = readl(&regs->pl310_tag_latency_ctrl);
+	if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
+		saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+			     L310_LATENCY_CTRL_WR(tag[1] - 1) |
+			     L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+	writel(saved_reg, &regs->pl310_tag_latency_ctrl);
+
+	saved_reg = readl(&regs->pl310_data_latency_ctrl);
+	if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
+		saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
+			     L310_LATENCY_CTRL_WR(tag[1] - 1) |
+			     L310_LATENCY_CTRL_SETUP(tag[2] - 1);
+	writel(saved_reg, &regs->pl310_data_latency_ctrl);
+
+	/* Enable the L2 cache */
+	setbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+static int l2x0_probe(struct udevice *dev)
+{
+	l2c310_of_parse_and_init(dev);
+
+	return 0;
+}
+
+
+static const struct udevice_id l2x0_ids[] = {
+	{ .compatible = "arm,pl310-cache" },
+	{}
+};
+
+U_BOOT_DRIVER(pl310_cache) = {
+	.name   = "pl310_cache",
+	.id     = UCLASS_CACHE,
+	.of_match = l2x0_ids,
+	.probe	= l2x0_probe,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/cache/cache-ncore.c b/roms/u-boot/drivers/cache/cache-ncore.c
new file mode 100644
index 000000000..3beff780d
--- /dev/null
+++ b/roms/u-boot/drivers/cache/cache-ncore.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+#include <dm.h>
+#include <hang.h>
+#include <wait_bit.h>
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+/* Directory */
+#define DIRUSFER		0x80010
+#define DIRUCASER0		0x80040
+#define DIRUSFMCR		0x80080
+#define DIRUSFMAR		0x80084
+
+#define DIRUSFMCR_SFID_SHIFT	16
+
+/* Coherent cache agent interface */
+#define CAIUIDR			0x00ffc
+
+#define CAIUIDR_CA_GET(v)	(((v) & 0x00008000) >> 15)
+#define CAIUIDR_TYPE_GET(v)	(((v) & 0x000f0000) >> 16)
+#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT	0
+#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT	1
+
+/* Coherent subsystem */
+#define CSADSER0		0xff040
+#define CSUIDR			0xffff8
+#define CSIDR			0xffffc
+
+#define CSUIDR_NUMCAIUS_GET(v)	(((v) & 0x0000007f) >> 0)
+#define CSUIDR_NUMDIRUS_GET(v)	(((v) & 0x003f0000) >> 16)
+#define CSUIDR_NUMCMIUS_GET(v)	(((v) & 0x3f000000) >> 24)
+
+#define CSIDR_NUMSFS_GET(v)	(((v) & 0x007c0000) >> 18)
+
+#define DIR_REG_SZ		0x1000
+#define CAIU_REG_SZ		0x1000
+
+#define CCU_DIR_REG_ADDR(base, reg, dir)	\
+		((base) + (reg) + ((dir) * DIR_REG_SZ))
+
+/* OCRAM firewall register */
+#define OCRAM_FW_01			0x100204
+#define OCRAM_SECURE_REGIONS		4
+
+#define OCRAM_PRIVILEGED_MASK		BIT(29)
+#define OCRAM_SECURE_MASK		BIT(30)
+
+static void ncore_ccu_init_dirs(void __iomem *base)
+{
+	ulong i, f;
+	int ret;
+	u32 num_of_dirs;
+	u32 num_of_snoop_filters;
+	u32 reg;
+
+	num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+	num_of_snoop_filters =
+		CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
+
+	/* Initialize each snoop filter in each directory */
+	for (f = 0; f < num_of_snoop_filters; f++) {
+		reg = f << DIRUSFMCR_SFID_SHIFT;
+		for (i = 0; i < num_of_dirs; i++) {
+			/* Initialize all entries */
+			writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
+
+			/* Poll snoop filter maintenance operation active
+			 * bit become 0.
+			 */
+			ret = wait_for_bit_le32((const void *)
+						CCU_DIR_REG_ADDR(base,
+								 DIRUSFMAR, i),
+						BIT(0), false, 1000, false);
+			if (ret) {
+				puts("CCU: Directory initialization failed!\n");
+				hang();
+			}
+
+			/* Enable snoop filter, a bit per snoop filter */
+			setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+				     BIT(f));
+		}
+	}
+}
+
+static void ncore_ccu_init_coh_agent(void __iomem *base)
+{
+	u32 num_of_coh_agent_intf;
+	u32 num_of_dirs;
+	u32 reg;
+	u32 type;
+	u32 i, dir;
+
+	num_of_coh_agent_intf =
+		CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
+	num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+
+	for (i = 0; i < num_of_coh_agent_intf; i++) {
+		reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
+		if (CAIUIDR_CA_GET(reg)) {
+			/* Caching agent bit is enabled, enable caching agent
+			 * snoop in each directory
+			 */
+			for (dir = 0; dir < num_of_dirs; dir++) {
+				setbits_le32((ulong)
+					     CCU_DIR_REG_ADDR(base, DIRUCASER0,
+							      dir),
+					     BIT(i));
+			}
+		}
+
+		type = CAIUIDR_TYPE_GET(reg);
+		if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
+		    type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
+			/* DVM support is enabled, enable ACE DVM snoop*/
+			setbits_le32((ulong)(base + CSADSER0),
+				     BIT(i));
+		}
+	}
+}
+
+static void ocram_bypass_firewall(void __iomem *base)
+{
+	int i;
+
+	for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
+		clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
+			     OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	}
+}
+
+static int ncore_ccu_probe(struct udevice *dev)
+{
+	void __iomem *base;
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	base = (void __iomem *)addr;
+
+	ncore_ccu_init_dirs(base);
+	ncore_ccu_init_coh_agent(base);
+	ocram_bypass_firewall(base);
+
+	return 0;
+}
+
+static const struct udevice_id ncore_ccu_ids[] = {
+	{ .compatible = "arteris,ncore-ccu" },
+	{}
+};
+
+U_BOOT_DRIVER(ncore_ccu) = {
+	.name   = "ncore_ccu",
+	.id     = UCLASS_CACHE,
+	.of_match = ncore_ccu_ids,
+	.probe	= ncore_ccu_probe,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/cache/cache-uclass.c b/roms/u-boot/drivers/cache/cache-uclass.c
new file mode 100644
index 000000000..3b20a10f0
--- /dev/null
+++ b/roms/u-boot/drivers/cache/cache-uclass.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+
+int cache_get_info(struct udevice *dev, struct cache_info *info)
+{
+	struct cache_ops *ops = cache_get_ops(dev);
+
+	if (!ops->get_info)
+		return -ENOSYS;
+
+	return ops->get_info(dev, info);
+}
+
+int cache_enable(struct udevice *dev)
+{
+	struct cache_ops *ops = cache_get_ops(dev);
+
+	if (!ops->enable)
+		return -ENOSYS;
+
+	return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+	struct cache_ops *ops = cache_get_ops(dev);
+
+	if (!ops->disable)
+		return -ENOSYS;
+
+	return ops->disable(dev);
+}
+
+UCLASS_DRIVER(cache) = {
+	.id		= UCLASS_CACHE,
+	.name		= "cache",
+	.post_bind	= dm_scan_fdt_dev,
+};
diff --git a/roms/u-boot/drivers/cache/cache-v5l2.c b/roms/u-boot/drivers/cache/cache-v5l2.c
new file mode 100644
index 000000000..2c7983d0c
--- /dev/null
+++ b/roms/u-boot/drivers/cache/cache-v5l2.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cache.h>
+#include <dm.h>
+#include <hang.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/ofnode.h>
+#include <linux/bitops.h>
+
+struct l2cache {
+	volatile u64	configure;
+	volatile u64	control;
+	volatile u64	hpm0;
+	volatile u64	hpm1;
+	volatile u64	hpm2;
+	volatile u64	hpm3;
+	volatile u64	error_status;
+	volatile u64	ecc_error;
+	volatile u64	cctl_command0;
+	volatile u64	cctl_access_line0;
+	volatile u64	cctl_command1;
+	volatile u64	cctl_access_line1;
+	volatile u64	cctl_command2;
+	volatile u64	cctl_access_line2;
+	volatile u64	cctl_command3;
+	volatile u64	cctl_access_line4;
+	volatile u64	cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE	0x1
+/* prefetch */
+#define IPREPETCH_OFF	3
+#define DPREPETCH_OFF	5
+#define IPREPETCH_MSK	(3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK	(3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF	8
+#define TRAMICTL_OFF	10
+#define TRAMOCTL_MSK	(3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK	BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF	11
+#define DRAMICTL_OFF	13
+#define DRAMOCTL_MSK	(3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK	BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart)	((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL	0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart)		(0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart)		(0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart)	(1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart)	(2 << ((hart) * 4))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+	struct l2cache	*regs;
+	u32		iprefetch;
+	u32		dprefetch;
+	u32 		tram_ctl[2];
+	u32 		dram_ctl[2];
+};
+
+static int v5l2_enable(struct udevice *dev)
+{
+	struct v5l2_plat *plat = dev_get_plat(dev);
+	volatile struct l2cache *regs = plat->regs;
+
+	if (regs)
+		setbits_le32(&regs->control, L2_ENABLE);
+
+	return 0;
+}
+
+static int v5l2_disable(struct udevice *dev)
+{
+	struct v5l2_plat *plat = dev_get_plat(dev);
+	volatile struct l2cache *regs = plat->regs;
+	u8 hart = gd->arch.boot_hart;
+	void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+	if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
+		writel(L2_WBINVAL_ALL, cctlcmd);
+
+		while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
+			if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+				printf("L2 flush illegal! hanging...");
+				hang();
+			}
+		}
+		clrbits_le32(&regs->control, L2_ENABLE);
+	}
+
+	return 0;
+}
+
+static int v5l2_of_to_plat(struct udevice *dev)
+{
+	struct v5l2_plat *plat = dev_get_plat(dev);
+	struct l2cache *regs;
+
+	regs = (struct l2cache *)dev_read_addr(dev);
+	plat->regs = regs;
+
+	plat->iprefetch = -EINVAL;
+	plat->dprefetch = -EINVAL;
+	plat->tram_ctl[0] = -EINVAL;
+	plat->dram_ctl[0] = -EINVAL;
+
+	/* Instruction and data fetch prefetch depth */
+	dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
+	dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
+
+	/* Set tag RAM and data RAM setup and output cycle */
+	dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
+	dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
+
+	return 0;
+}
+
+static int v5l2_probe(struct udevice *dev)
+{
+	struct v5l2_plat *plat = dev_get_plat(dev);
+	struct l2cache *regs = plat->regs;
+	u32 ctl_val;
+
+	ctl_val = readl(&regs->control);
+
+	if (!(ctl_val & L2_ENABLE))
+		ctl_val |= L2_ENABLE;
+
+	if (plat->iprefetch != -EINVAL) {
+		ctl_val &= ~(IPREPETCH_MSK);
+		ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
+	}
+
+	if (plat->dprefetch != -EINVAL) {
+		ctl_val &= ~(DPREPETCH_MSK);
+		ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
+	}
+
+	if (plat->tram_ctl[0] != -EINVAL) {
+		ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
+		ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
+		ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
+	}
+
+	if (plat->dram_ctl[0] != -EINVAL) {
+		ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
+		ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
+		ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
+	}
+
+	writel(ctl_val, &regs->control);
+
+	return 0;
+}
+
+static const struct udevice_id v5l2_cache_ids[] = {
+	{ .compatible = "v5l2cache" },
+	{}
+};
+
+static const struct cache_ops v5l2_cache_ops = {
+	.enable		= v5l2_enable,
+	.disable	= v5l2_disable,
+};
+
+U_BOOT_DRIVER(v5l2_cache) = {
+	.name   = "v5l2_cache",
+	.id     = UCLASS_CACHE,
+	.of_match = v5l2_cache_ids,
+	.of_to_plat = v5l2_of_to_plat,
+	.probe	= v5l2_probe,
+	.plat_auto	= sizeof(struct v5l2_plat),
+	.ops = &v5l2_cache_ops,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/cache/sandbox_cache.c b/roms/u-boot/drivers/cache/sandbox_cache.c
new file mode 100644
index 000000000..0fb767e43
--- /dev/null
+++ b/roms/u-boot/drivers/cache/sandbox_cache.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
+{
+	info->base = 0x11223344;
+
+	return 0;
+}
+
+static int sandbox_enable(struct udevice *dev)
+{
+	return 0;
+}
+
+static int snadbox_disable(struct udevice *dev)
+{
+	return 0;
+}
+
+
+static const struct cache_ops sandbox_cache_ops = {
+	.get_info	= sandbox_get_info,
+	.enable 	= sandbox_enable,
+	.disable	= snadbox_disable,
+};
+
+static const struct udevice_id sandbox_cache_ids[] = {
+	{ .compatible = "sandbox,cache" },
+	{ }
+};
+
+U_BOOT_DRIVER(cache_sandbox) = {
+	.name		= "cache_sandbox",
+	.id		= UCLASS_CACHE,
+	.of_match	= sandbox_cache_ids,
+	.ops		= &sandbox_cache_ops,
+};