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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/drivers/clk/exynos/clk-pll.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/drivers/clk/exynos/clk-pll.h')
-rw-r--r-- | roms/u-boot/drivers/clk/exynos/clk-pll.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/roms/u-boot/drivers/clk/exynos/clk-pll.h b/roms/u-boot/drivers/clk/exynos/clk-pll.h new file mode 100644 index 000000000..c79aac442 --- /dev/null +++ b/roms/u-boot/drivers/clk/exynos/clk-pll.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Exynos PLL helper functions for clock drivers. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham <thomas.ab@samsung.com> + */ + +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq); |