Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

10 files changed, 7304 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/clk/mediatek/Makefile b/roms/u-boot/drivers/clk/mediatek/Makefile
new file mode 100644
index 000000000..522e72422
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
+
+# SoC Drivers
+obj-$(CONFIG_MT8512) += clk-mt8512.o
+obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
+obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
+obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
+obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt7622.c b/roms/u-boot/drivers/clk/mediatek/clk-mt7622.c
new file mode 100644
index 000000000..259ea3359
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt7622.c
@@ -0,0 +1,790 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7622 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT7622_CLKSQ_STB_CON0		0x20
+#define MT7622_PLL_ISO_CON0		0x2c
+#define MT7622_PLL_FMAX			(2500UL * MHZ)
+#define MT7622_CON0_RST_BAR		BIT(24)
+
+#define MCU_AXI_DIV			0x640
+#define AXI_DIV_MSK			GENMASK(4, 0)
+#define AXI_DIV_SEL(x)			(x)
+
+#define MCU_BUS_MUX			0x7c0
+#define MCU_BUS_MSK			GENMASK(10, 9)
+#define MCU_BUS_SEL(x)			((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT7622_CON0_RST_BAR,			\
+		.fmax = MT7622_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+	    21, 0x204, 24, 0x204, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+	    21, 0x214, 24, 0x214, 0),
+	PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+	    7, 0x224, 24, 0x224, 14),
+	PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+	    21, 0x300, 1, 0x304, 0),
+	PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+	    21, 0x314, 1, 0x318, 0),
+	PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
+	    31, 0x324, 1, 0x328, 0),
+	PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
+	    31, 0x334, 1, 0x338, 0),
+	PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
+	    21, 0x344, 1, 0x348, 0),
+	PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+	    21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
+	FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
+	FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
+	FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
+	FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
+	FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
+	FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
+	FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
+	FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
+	FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
+	FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+	FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
+	FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+	FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
+	FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
+	FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
+	FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+	FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+	FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+	FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
+	FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
+	FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
+	FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
+	FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+	FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+	FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+	FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
+	FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+	FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+	FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+	FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
+	FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+	FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+	FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+	FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
+	FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
+	FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
+	FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
+	FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
+	FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
+	FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
+	FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
+	FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
+	FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
+	FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+	FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+	FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
+};
+
+static const int axi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_UNIVPLL_D7
+};
+
+static const int mem_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_DMPLL
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8
+};
+
+static const int eth_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	-1,
+	CLK_TOP_UNIVPLL_D7
+};
+
+static const int pwm_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int f10m_ref_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL4_D16
+};
+
+static const int nfi_infra_parents[] = {
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D8,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_SYSPLL1_D4
+};
+
+static const int flash_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL_D80_D4,
+	CLK_TOP_SYSPLL2_D8,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int uart_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi0_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_XTAL
+};
+
+static const int spi1_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL4_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_XTAL
+};
+
+static const int msdc30_0_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D16,
+	CLK_TOP_UNIV48M
+};
+
+static const int a1sys_hp_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_AUD1PLL,
+	CLK_TOP_AUD2PLL,
+	CLK_XTAL
+};
+
+static const int intdir_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL_D2,
+	CLK_TOP_SGMIIPLL
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_SYSPLL3_D2
+};
+
+static const int pmicspi_parents[] = {
+	CLK_XTAL,
+	-1,
+	-1,
+	-1,
+	-1,
+	CLK_TOP_UNIVPLL2_D16
+};
+
+static const int atb_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5
+};
+
+static const int audio_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_SYSPLL4_D4,
+	CLK_TOP_UNIVPLL1_D16
+};
+
+static const int usb20_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_XTAL
+};
+
+static const int aud1_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_AUD1PLL
+};
+
+static const int asm_l_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int apll1_ck_parents[] = {
+	CLK_TOP_AUD1_SEL,
+	CLK_TOP_AUD2_SEL
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
+	MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
+	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
+	MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
+
+	/* CLK_CFG_1 */
+	MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
+	MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
+	MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
+
+	/* CLK_CFG_2 */
+	MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
+	MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
+	MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
+	MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
+
+	/* CLK_CFG_3 */
+	MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
+	MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
+	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
+	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
+
+	/* CLK_CFG_4 */
+	MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
+	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
+	MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
+	MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
+
+	/* CLK_CFG_5 */
+	MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
+	MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
+		       CLK_DOMAIN_SCPSYS),
+	MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
+	MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
+
+	/* CLK_CFG_6 */
+	MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
+	MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
+	MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
+	MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
+
+	/* CLK_CFG_7 */
+	MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
+	MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
+	MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
+
+	/* CLK_AUDDIV_0 */
+	MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
+	MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
+	MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
+	MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
+	MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
+	MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
+};
+
+/* infracfg */
+static const struct mtk_gate_regs infra_cg_regs = {
+	.set_ofs = 0x40,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x48,
+};
+
+#define GATE_INFRA(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate infra_cgs[] = {
+	GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
+	GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
+	GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
+	GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
+	GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
+	GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
+};
+
+/* pericfg */
+static const struct mtk_gate_regs peri0_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0x10,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+	.set_ofs = 0xC,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x1C,
+};
+
+#define GATE_PERI0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &peri0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_PERI1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &peri1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate peri_cgs[] = {
+	/* PERI0 */
+	GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
+	GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
+	GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
+	GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
+	GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
+	GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
+	GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
+	GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
+	GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+	GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
+	GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
+	GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
+	GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
+	GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
+	GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
+	GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
+	GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
+	GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
+	GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
+	GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
+	GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
+	GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+	GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
+	GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
+	GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
+	GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
+
+	/* PERI1 */
+	GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
+	GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
+};
+
+/* pciesys */
+static const struct mtk_gate_regs pcie_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x30,
+	.sta_ofs = 0x30,
+};
+
+#define GATE_PCIE(_id, _parent, _shift) {		\
+		.id = _id,				\
+		.parent = _parent,			\
+		.regs = &pcie_cg_regs,			\
+		.shift = _shift,			\
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate pcie_cgs[] = {
+	GATE_PCIE(CLK_PCIE_P1_AUX_EN, CLK_TOP_P1_1MHZ, 12),
+	GATE_PCIE(CLK_PCIE_P1_OBFF_EN, CLK_TOP_4MHZ, 13),
+	GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
+	GATE_PCIE(CLK_PCIE_P1_AXI_EN, CLK_TOP_HIF_SEL, 15),
+	GATE_PCIE(CLK_PCIE_P1_MAC_EN, CLK_TOP_PCIE1_MAC_EN, 16),
+	GATE_PCIE(CLK_PCIE_P1_PIPE_EN, CLK_TOP_PCIE1_PIPE_EN, 17),
+	GATE_PCIE(CLK_PCIE_P0_AUX_EN, CLK_TOP_P0_1MHZ, 18),
+	GATE_PCIE(CLK_PCIE_P0_OBFF_EN, CLK_TOP_4MHZ, 19),
+	GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
+	GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),
+	GATE_PCIE(CLK_PCIE_P0_MAC_EN, CLK_TOP_PCIE0_MAC_EN, 22),
+	GATE_PCIE(CLK_PCIE_P0_PIPE_EN, CLK_TOP_PCIE0_PIPE_EN, 23),
+	GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
+	GATE_PCIE(CLK_SATA_AXI_EN, CLK_TOP_HIF_SEL, 27),
+	GATE_PCIE(CLK_SATA_ASIC_EN, CLK_TOP_SATA_ASIC, 28),
+	GATE_PCIE(CLK_SATA_RBC_EN, CLK_TOP_SATA_RBC, 29),
+	GATE_PCIE(CLK_SATA_PM_EN, CLK_TOP_UNIVPLL2_D4, 30),
+};
+
+/* ethsys */
+static const struct mtk_gate_regs eth_cg_regs = {
+	.sta_ofs = 0x30,
+};
+
+#define GATE_ETH(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &eth_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate eth_cgs[] = {
+	GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
+	GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
+	GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
+	GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
+	GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
+};
+
+static const struct mtk_gate_regs sgmii_cg_regs = {
+	.sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII(_id, _parent, _shift) {			\
+	.id = _id,						\
+	.parent = _parent,					\
+	.regs = &sgmii_cg_regs,					\
+	.shift = _shift,					\
+	.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+}
+
+static const struct mtk_gate_regs ssusb_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x30,
+	.sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) {                      \
+	.id = _id,                                              \
+	.parent = _parent,                                      \
+	.regs = &ssusb_cg_regs,                                 \
+	.shift = _shift,                                        \
+	.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,  \
+}
+
+static const struct mtk_gate sgmii_cgs[] = {
+	GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
+	GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
+	GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
+	GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
+};
+
+static const struct mtk_gate ssusb_cgs[] = {
+	GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+	GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+	GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+	GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+	GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
+	GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
+};
+
+static const struct mtk_clk_tree mt7622_clk_tree = {
+	.xtal_rate = 25 * MHZ,
+	.xtal2_rate = 25 * MHZ,
+	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt7622_mcucfg_probe(struct udevice *dev)
+{
+	void __iomem *base;
+
+	base = dev_read_addr_ptr(dev);
+	if (!base)
+		return -ENOENT;
+
+	clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
+			AXI_DIV_SEL(0x12));
+	clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
+			MCU_BUS_SEL(0x1));
+
+	return 0;
+}
+
+static int mt7622_apmixedsys_probe(struct udevice *dev)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
+	if (ret)
+		return ret;
+
+	/* reduce clock square disable time */
+	// writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
+	writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
+
+	/* extend pwr/iso control timing to 1us */
+	writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
+
+	return 0;
+}
+
+static int mt7622_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt7622_clk_tree);
+}
+
+static int mt7622_infracfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
+}
+
+static int mt7622_pericfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
+}
+
+static int mt7622_pciesys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
+}
+
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+	if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+	if (ret)
+		debug("Warning: failed to bind reset controller\n");
+	}
+
+	return ret;
+}
+
+static int mt7622_ethsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
+}
+
+static int mt7622_ethsys_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+	if (ret)
+		debug("Warning: failed to bind reset controller\n");
+#endif
+
+	return ret;
+}
+
+static int mt7622_sgmiisys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
+}
+
+static int mt7622_ssusbsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs);
+}
+
+static const struct udevice_id mt7622_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt7622-apmixedsys" },
+	{ }
+};
+
+static const struct udevice_id mt7622_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt7622-topckgen" },
+	{ }
+};
+
+static const struct udevice_id mt7622_infracfg_compat[] = {
+	{ .compatible = "mediatek,mt7622-infracfg", },
+	{ }
+};
+
+static const struct udevice_id mt7622_pericfg_compat[] = {
+	{ .compatible = "mediatek,mt7622-pericfg", },
+	{ }
+};
+
+static const struct udevice_id mt7622_pciesys_compat[] = {
+	{ .compatible = "mediatek,mt7622-pciesys", },
+	{ }
+};
+
+static const struct udevice_id mt7622_ethsys_compat[] = {
+	{ .compatible = "mediatek,mt7622-ethsys", },
+	{ }
+};
+
+static const struct udevice_id mt7622_sgmiisys_compat[] = {
+	{ .compatible = "mediatek,mt7622-sgmiisys", },
+	{ }
+};
+
+static const struct udevice_id mt7622_mcucfg_compat[] = {
+	{ .compatible = "mediatek,mt7622-mcucfg" },
+	{ }
+};
+
+static const struct udevice_id mt7622_ssusbsys_compat[] = {
+	{ .compatible = "mediatek,mt7622-ssusbsys" },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_mcucfg) = {
+	.name = "mt7622-mcucfg",
+	.id = UCLASS_SYSCON,
+	.of_match = mt7622_mcucfg_compat,
+	.probe = mt7622_mcucfg_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt7622-clock-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_apmixed_compat,
+	.probe = mt7622_apmixedsys_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt7622-clock-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_topckgen_compat,
+	.probe = mt7622_topckgen_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+	.name = "mt7622-clock-infracfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_infracfg_compat,
+	.probe = mt7622_infracfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_pericfg) = {
+	.name = "mt7622-clock-pericfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_pericfg_compat,
+	.probe = mt7622_pericfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_pciesys) = {
+	.name = "mt7622-clock-pciesys",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_pciesys_compat,
+	.probe = mt7622_pciesys_probe,
+	.bind = mt7622_pciesys_bind,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_ethsys) = {
+	.name = "mt7622-clock-ethsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_ethsys_compat,
+	.probe = mt7622_ethsys_probe,
+	.bind = mt7622_ethsys_bind,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
+	.name = "mt7622-clock-sgmiisys",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_sgmiisys_compat,
+	.probe = mt7622_sgmiisys_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+	.name = "mt7622-clock-ssusbsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7622_ssusbsys_compat,
+	.probe = mt7622_ssusbsys_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt7623.c b/roms/u-boot/drivers/clk/mediatek/clk-mt7623.c
new file mode 100644
index 000000000..0c7411ee8
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt7623.c
@@ -0,0 +1,915 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7623 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7623-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT7623_CLKSQ_STB_CON0		0x18
+#define MT7623_PLL_ISO_CON0		0x24
+#define MT7623_PLL_FMAX			(2000UL * MHZ)
+#define MT7623_CON0_RST_BAR		BIT(27)
+
+#define MCU_AXI_DIV			0x60
+#define AXI_DIV_MSK			GENMASK(4, 0)
+#define AXI_DIV_SEL(x)			(x)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT7623_CON0_RST_BAR,			\
+		.fmax = MT7623_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
+	    21, 0x204, 24, 0x204, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
+	    21, 0x210, 4, 0x214, 0),
+	PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
+	    7, 0x220, 4, 0x224, 14),
+	PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
+	    21, 0x230, 4, 0x234, 0),
+	PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
+	    21, 0x240, 4, 0x244, 0),
+	PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
+	    21, 0x250, 4, 0x254, 0),
+	PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
+	    31, 0x270, 4, 0x274, 0),
+	PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
+	    31, 0x280, 4, 0x284, 0),
+	PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
+	    31, 0x290, 4, 0x294, 0),
+	PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
+	    31, 0x2a0, 4, 0x2a4, 0),
+	PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
+	    31, 0x2b0, 4, 0x2b4, 0),
+	PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
+	    31, 0x2c0, 4, 0x2c4, 0),
+	PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
+	    21, 0x2d0, 4, 0x2d4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
+	FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
+	FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
+	FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
+	FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
+	FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
+	FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
+	FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
+	FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
+	FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
+	FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
+	FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
+	FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
+	FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
+	FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
+	FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+	FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+	FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
+	FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
+	FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
+	FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
+	FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
+	FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
+	FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
+	FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
+	FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
+	FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
+	FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
+
+	FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
+	FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+	FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+	FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+	FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
+	FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
+	FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
+	FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
+	FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+	FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
+	FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
+	FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
+	FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
+	FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
+	FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
+	FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
+	FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
+
+	FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
+	FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
+	FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
+	FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
+
+	FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
+	FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+
+	FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
+	FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
+	FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
+
+	FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
+	FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
+	FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
+
+	FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
+	FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
+	FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
+
+	FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
+	FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
+	FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
+
+	FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
+	FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
+	FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
+
+	FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
+
+	FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
+	FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
+	FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
+	FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
+	FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
+
+	FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
+	FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
+	FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
+	FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
+	FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
+	FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
+	FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
+	FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
+	FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
+};
+
+static const int axi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_MMPLL_D2,
+	CLK_TOP_DMPLL_D2
+};
+
+static const int mem_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_DMPLL
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8
+};
+
+static const int mm_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_VENCPLL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_DMPLL
+};
+
+static const int pwm_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_UNIVPLL1_D4
+};
+
+static const int vdec_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_VDECPLL,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_VENCPLL,
+	CLK_TOP_MSDCPLL_D2,
+	CLK_TOP_MMPLL_D2
+};
+
+static const int mfg_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_MMPLL,
+	CLK_TOP_DMPLL_X2,
+	CLK_TOP_MSDCPLL,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL1_D2
+};
+
+static const int camtg_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL_D26,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_MSDCPLL_D2,
+	CLK_TOP_MMPLL_D2
+};
+
+static const int uart_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL1_D8
+};
+
+static const int usb20_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_TOP_UNIVPLL3_D4
+};
+
+static const int msdc30_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_MSDCPLL_D2,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL1_D4,
+	CLK_TOP_UNIVPLL2_D4,
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int pmicspi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_SYSPLL2_D8,
+	CLK_TOP_SYSPLL1_D16,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_UNIVPLL_D26,
+	CLK_TOP_DMPLL_D2,
+	CLK_TOP_DMPLL_D4
+};
+
+static const int scp_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_DMPLL_D2,
+	CLK_TOP_DMPLL_D4
+};
+
+static const int dpi0_tve_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_MIPIPLL,
+	CLK_TOP_MIPIPLL_D2,
+	CLK_TOP_MIPIPLL_D4,
+	CLK_XTAL,
+	CLK_TOP_TVDPLL,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_TVDPLL_D4
+};
+
+static const int dpi1_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_TVDPLL,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_TVDPLL_D4
+};
+
+static const int hdmi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_HDMIPLL,
+	CLK_TOP_HDMIPLL_D2,
+	CLK_TOP_HDMIPLL_D3
+};
+
+static const int apll_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_AUDPLL,
+	CLK_TOP_AUDPLL_D4,
+	CLK_TOP_AUDPLL_D8,
+	CLK_TOP_AUDPLL_D16,
+	CLK_TOP_AUDPLL_D24,
+	CLK_XTAL,
+	CLK_XTAL
+};
+
+static const int rtc_parents[] = {
+	CLK_TOP_32K_INTERNAL,
+	CLK_TOP_32K_EXTERNAL,
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL3_D8
+};
+
+static const int nfi2x_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL4_D4,
+	CLK_XTAL
+};
+
+static const int emmc_hclk_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL2_D2
+};
+
+static const int flash_parents[] = {
+	CLK_TOP_CLK26M_D8,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL2_D8,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int di_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_TVD2PLL,
+	CLK_TOP_TVD2PLL_D2,
+	CLK_XTAL
+};
+
+static const int nr_osd_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_VENCPLL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_DMPLL
+};
+
+static const int hdmirx_bist_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL_D3,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D16,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_VENCPLL,
+	CLK_XTAL
+};
+
+static const int intdir_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_MMPLL,
+	CLK_TOP_SYSPLL_D2,
+	CLK_TOP_UNIVPLL_D2
+};
+
+static const int asm_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL_D5
+};
+
+static const int ms_card_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL3_D8,
+	CLK_TOP_SYSPLL4_D4
+};
+
+static const int ethif_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_DMPLL,
+	CLK_TOP_DMPLL_D2
+};
+
+static const int hdmirx_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL_D52
+};
+
+static const int cmsys_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL
+};
+
+static const int clk_8bdac_parents[] = {
+	CLK_TOP_32K_INTERNAL,
+	CLK_TOP_8BDAC,
+	CLK_XTAL,
+	CLK_XTAL
+};
+
+static const int aud2dvd_parents[] = {
+	CLK_TOP_AUD_48K_TIMING,
+	CLK_TOP_AUD_44K_TIMING
+};
+
+static const int padmclk_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL_D26,
+	CLK_TOP_UNIVPLL_D52,
+	CLK_TOP_UNIVPLL_D108,
+	CLK_TOP_UNIVPLL2_D8,
+	CLK_TOP_UNIVPLL2_D16,
+	CLK_TOP_UNIVPLL2_D32
+};
+
+static const int aud_mux_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_AUD1PLL_98M,
+	CLK_TOP_AUD2PLL_90M,
+	CLK_TOP_HADDS2PLL_98M,
+	CLK_TOP_AUD_EXTCK1_DIV,
+	CLK_TOP_AUD_EXTCK2_DIV
+};
+
+static const int aud_src_parents[] = {
+	CLK_TOP_AUD_MUX1_SEL,
+	CLK_TOP_AUD_MUX2_SEL
+};
+
+static const struct mtk_composite top_muxes[] = {
+	MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
+	MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
+	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
+	MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
+		       CLK_DOMAIN_SCPSYS),
+
+	MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
+	MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
+	MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
+		       CLK_DOMAIN_SCPSYS),
+	MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
+
+	MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
+	MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
+	MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
+	MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
+
+	MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
+	MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
+	MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
+	MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
+
+	MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
+	MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
+	MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
+	MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
+
+	MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
+	MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
+	MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
+
+	MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
+	MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
+	MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
+
+	MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
+	MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
+	MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
+	MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
+
+	MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
+	MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
+	MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
+	MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
+
+	MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
+	MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
+	MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
+		       CLK_DOMAIN_SCPSYS),
+
+	MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
+	MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
+	MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
+
+	MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
+	MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
+	MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
+	MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
+
+	MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
+
+	MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
+	MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
+	MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
+
+	MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
+	MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
+	MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
+	MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
+	MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
+	MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
+};
+
+/* infracfg */
+static const struct mtk_gate_regs infra_cg_regs = {
+	.set_ofs = 0x40,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x48,
+};
+
+#define GATE_INFRA(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate infra_cgs[] = {
+	GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
+	GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
+	GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
+	GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
+	GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
+	GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
+	GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
+	GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
+	GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
+	GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
+	GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
+	GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
+	GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
+	GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
+	GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
+	GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
+	GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
+	GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
+};
+
+/* pericfg */
+static const struct mtk_gate_regs peri0_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0x10,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+	.set_ofs = 0xC,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x1C,
+};
+
+#define GATE_PERI0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &peri0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_PERI1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &peri1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate peri_cgs[] = {
+	GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
+	GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
+	GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
+	GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
+	GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
+	GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
+	GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
+	GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
+	GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
+	GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
+	GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
+	GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
+	GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
+	GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
+	GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
+	GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
+	GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
+	GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
+	GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
+	GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
+	GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
+	GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
+	GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
+	GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
+	GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
+	GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
+	GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
+	GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
+	GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
+	GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
+	GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
+	GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
+
+	GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
+	GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
+	GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
+	GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
+	GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
+	GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
+	GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
+	GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
+	GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
+	GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
+	GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
+	GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
+};
+
+/* ethsys and hifsys */
+static const struct mtk_gate_regs eth_hif_cg_regs = {
+	.sta_ofs = 0x30,
+};
+
+#define GATE_ETH_HIF(_id, _parent, _shift, _flag) {		\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &eth_hif_cg_regs,			\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR_INV | (_flag),	\
+	}
+
+#define GATE_ETH_HIF0(_id, _parent, _shift)				\
+	GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
+
+#define GATE_ETH_HIF1(_id, _parent, _shift)				\
+	GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
+
+static const struct mtk_gate eth_cgs[] = {
+	GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
+	GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
+	GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
+	GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
+	GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
+	GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
+	GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
+	GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
+};
+
+static const struct mtk_gate hif_cgs[] = {
+	GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
+	GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
+	GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
+	GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
+	GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
+};
+
+static const struct mtk_clk_tree mt7623_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_SYSPLL,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt7623_mcucfg_probe(struct udevice *dev)
+{
+	void __iomem *base;
+
+	base = dev_read_addr_ptr(dev);
+	if (!base)
+		return -ENOENT;
+
+	clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
+			AXI_DIV_SEL(0x12));
+
+	return 0;
+}
+
+static int mt7623_apmixedsys_probe(struct udevice *dev)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
+	if (ret)
+		return ret;
+
+	/* reduce clock square disable time */
+	writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
+	/* extend control timing to 1us */
+	writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
+
+	return 0;
+}
+
+static int mt7623_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt7623_clk_tree);
+}
+
+static int mt7623_infracfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
+}
+
+static int mt7623_pericfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
+}
+
+static int mt7623_hifsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
+}
+
+static int mt7623_ethsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
+}
+
+static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+	if (ret)
+		debug("Warning: failed to bind reset controller\n");
+#endif
+
+	return ret;
+}
+
+static const struct udevice_id mt7623_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt7623-apmixedsys" },
+	{ }
+};
+
+static const struct udevice_id mt7623_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt7623-topckgen" },
+	{ }
+};
+
+static const struct udevice_id mt7623_infracfg_compat[] = {
+	{ .compatible = "mediatek,mt7623-infracfg", },
+	{ }
+};
+
+static const struct udevice_id mt7623_pericfg_compat[] = {
+	{ .compatible = "mediatek,mt7623-pericfg", },
+	{ }
+};
+
+static const struct udevice_id mt7623_ethsys_compat[] = {
+	{ .compatible = "mediatek,mt7623-ethsys" },
+	{ }
+};
+
+static const struct udevice_id mt7623_hifsys_compat[] = {
+	{ .compatible = "mediatek,mt7623-hifsys" },
+	{ }
+};
+
+static const struct udevice_id mt7623_mcucfg_compat[] = {
+	{ .compatible = "mediatek,mt7623-mcucfg" },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_mcucfg) = {
+	.name = "mt7623-mcucfg",
+	.id = UCLASS_SYSCON,
+	.of_match = mt7623_mcucfg_compat,
+	.probe = mt7623_mcucfg_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt7623-clock-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7623_apmixed_compat,
+	.probe = mt7623_apmixedsys_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt7623-clock-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt7623_topckgen_compat,
+	.probe = mt7623_topckgen_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+	.name = "mt7623-infracfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7623_infracfg_compat,
+	.probe = mt7623_infracfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_pericfg) = {
+	.name = "mt7623-pericfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7623_pericfg_compat,
+	.probe = mt7623_pericfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_hifsys) = {
+	.name = "mt7623-clock-hifsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7623_hifsys_compat,
+	.probe = mt7623_hifsys_probe,
+	.bind = mt7623_ethsys_hifsys_bind,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_ethsys) = {
+	.name = "mt7623-clock-ethsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7623_ethsys_compat,
+	.probe = mt7623_ethsys_probe,
+	.bind = mt7623_ethsys_hifsys_bind,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt7629.c b/roms/u-boot/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 000000000..31b6fa022
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,768 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7629-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT7629_CLKSQ_STB_CON0		0x20
+#define MT7629_PLL_ISO_CON0		0x2c
+#define MT7629_PLL_FMAX			(2500UL * MHZ)
+#define MT7629_CON0_RST_BAR		BIT(24)
+
+#define MCU_AXI_DIV			0x640
+#define AXI_DIV_MSK			GENMASK(4, 0)
+#define AXI_DIV_SEL(x)			(x)
+
+#define MCU_BUS_MUX			0x7c0
+#define MCU_BUS_MSK			GENMASK(10, 9)
+#define MCU_BUS_SEL(x)			((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT7629_CON0_RST_BAR,			\
+		.fmax = MT7629_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+	    21, 0x204, 24, 0x204, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+	    21, 0x214, 24, 0x214, 0),
+	PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+	    7, 0x224, 24, 0x224, 14),
+	PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+	    21, 0x300, 1, 0x304, 0),
+	PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+	    21, 0x314, 1, 0x318, 0),
+	PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+	    21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)			\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
+	FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
+	FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
+	FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
+	FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
+	FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
+	FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
+	FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
+	FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
+	FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
+	FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+	FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
+	FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+	FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
+	FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
+	FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
+	FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
+	FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+	FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4),
+	FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8),
+	FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+	FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
+	FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
+	FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+	FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
+	FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
+	FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
+	FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+	FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+	FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+	FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
+	FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+	FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+	FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+	FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
+	FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+	FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+	FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+	FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
+	FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
+	FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
+	FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
+	FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
+	FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4),
+	FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
+	FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
+	FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1),
+	FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1),
+	FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1),
+	FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1),
+	FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
+	FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1),
+	FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1),
+	FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4),
+	FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
+	FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1),
+	FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
+	FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1),
+	FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+	FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+};
+
+static const int axi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_UNIVPLL_D7,
+	CLK_TOP_DMPLL
+};
+
+static const int mem_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_DMPLL
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8
+};
+
+static const int eth_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_SGMIIPLL_D2,
+	CLK_TOP_UNIVPLL_D7,
+	CLK_TOP_DMPLL
+};
+
+static const int pwm_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int f10m_ref_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SGMIIPLL_D2
+};
+
+static const int nfi_infra_parents[] = {
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D8,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL_D7
+};
+
+static const int flash_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL_D80_D4,
+	CLK_TOP_SYSPLL2_D8,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int uart_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi0_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_XTAL
+};
+
+static const int spi1_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D2,
+	CLK_XTAL,
+	CLK_TOP_SYSPLL4_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_XTAL
+};
+
+static const int msdc30_0_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D16,
+	CLK_TOP_UNIV48M
+};
+
+static const int msdc30_1_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D16,
+	CLK_TOP_UNIV48M,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL2_D2
+};
+
+static const int ap2wbmcu_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIV48M,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL2_D2
+};
+
+static const int audio_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_SYSPLL4_D4,
+	CLK_TOP_SYSPLL1_D16
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_DMPLL_D4
+};
+
+static const int pmicspi_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_SYSPLL1_D16,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_DMPLL_D8
+};
+
+static const int scp_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int atb_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5
+};
+
+static const int hif_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	-1,
+	CLK_TOP_UNIVPLL_D7
+};
+
+static const int sata_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int usb20_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL1_D8
+};
+
+static const int aud1_parents[] = {
+	CLK_XTAL
+};
+
+static const int irrx_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_SYSPLL4_D16
+};
+
+static const int crypto_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL_D2
+};
+
+static const int gpt10m_parents[] = {
+	CLK_XTAL,
+	CLK_TOP_CLKXTAL_D4
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
+	MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
+	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
+	MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
+
+	/* CLK_CFG_1 */
+	MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
+	MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
+	MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
+
+	/* CLK_CFG_2 */
+	MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
+	MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
+	MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
+	MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
+
+	/* CLK_CFG_3 */
+	MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
+	MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
+	MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23),
+	MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31),
+
+	/* CLK_CFG_4 */
+	MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7),
+	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
+	MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
+	MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
+
+	/* CLK_CFG_5 */
+	MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
+	MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
+		       CLK_DOMAIN_SCPSYS),
+	MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23),
+	MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
+
+	/* CLK_CFG_6 */
+	MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
+	MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
+	MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23),
+	MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31),
+
+	/* CLK_CFG_7 */
+	MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7),
+	MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),
+	MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23),
+	MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31),
+
+	/* CLK_CFG_8 */
+	MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
+	MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
+	MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
+};
+
+/* infracfg */
+static const struct mtk_gate_regs infra_cg_regs = {
+	.set_ofs = 0x40,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x48,
+};
+
+#define GATE_INFRA(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate infra_cgs[] = {
+	GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0),
+	GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2),
+	GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4),
+	GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18),
+	GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19),
+};
+
+/* pericfg */
+static const struct mtk_gate_regs peri0_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0x10,
+	.sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+	.set_ofs = 0xC,
+	.clr_ofs = 0x14,
+	.sta_ofs = 0x1C,
+};
+
+#define GATE_PERI0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &peri0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_PERI1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &peri1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate peri_cgs[] = {
+	GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
+	GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
+	GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
+	GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
+	GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
+	GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
+	GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
+	GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
+	GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
+	GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14),
+	GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),
+	GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18),
+	GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19),
+	GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20),
+	GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22),
+	GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23),
+	GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28),
+	GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29),
+	GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30),
+	GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31),
+	GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1),
+};
+
+/* ethsys */
+static const struct mtk_gate_regs eth_cg_regs = {
+	.sta_ofs = 0x30,
+};
+
+#define GATE_ETH(_id, _parent, _shift, _flag) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &eth_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR_INV | (_flag),	\
+	}
+
+#define GATE_ETH0(_id, _parent, _shift)				\
+	GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
+
+#define GATE_ETH1(_id, _parent, _shift)				\
+	GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
+
+static const struct mtk_gate eth_cgs[] = {
+	GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6),
+	GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
+	GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
+	GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
+	GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16),
+};
+
+static const struct mtk_gate_regs sgmii_cg_regs = {
+	.set_ofs = 0xE4,
+	.clr_ofs = 0xE4,
+	.sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII(_id, _parent, _shift) {			\
+	.id = _id,						\
+	.parent = _parent,					\
+	.regs = &sgmii_cg_regs,					\
+	.shift = _shift,					\
+	.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+}
+
+static const struct mtk_gate sgmii_cgs[] = {
+	GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2),
+	GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
+	GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
+	GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
+};
+
+static const struct mtk_gate_regs ssusb_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x30,
+	.sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) {			\
+	.id = _id,						\
+	.parent = _parent,					\
+	.regs = &ssusb_cg_regs,					\
+	.shift = _shift,					\
+	.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+}
+
+static const struct mtk_gate ssusb_cgs[] = {
+	GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+	GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+	GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+	GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+	GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7),
+	GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
+};
+
+static const struct mtk_clk_tree mt7629_clk_tree = {
+	.xtal_rate = 40 * MHZ,
+	.xtal2_rate = 20 * MHZ,
+	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt7629_mcucfg_probe(struct udevice *dev)
+{
+	void __iomem *base;
+
+	base = dev_read_addr_ptr(dev);
+	if (!base)
+		return -ENOENT;
+
+	clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
+			AXI_DIV_SEL(0x12));
+	clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
+			MCU_BUS_SEL(0x1));
+
+	return 0;
+}
+
+static int mt7629_apmixedsys_probe(struct udevice *dev)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = mtk_common_clk_init(dev, &mt7629_clk_tree);
+	if (ret)
+		return ret;
+
+	/* reduce clock square disable time */
+	writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0);
+	/* extend pwr/iso control timing to 1us */
+	writel(0x80008, priv->base + MT7629_PLL_ISO_CON0);
+
+	return 0;
+}
+
+static int mt7629_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt7629_clk_tree);
+}
+
+static int mt7629_infracfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs);
+}
+
+static int mt7629_pericfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
+}
+
+static int mt7629_ethsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
+}
+
+static int mt7629_ethsys_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+	if (ret)
+		debug("Warning: failed to bind reset controller\n");
+#endif
+
+	return ret;
+}
+
+static int mt7629_sgmiisys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
+}
+
+static int mt7629_ssusbsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs);
+}
+
+static const struct udevice_id mt7629_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt7629-apmixedsys" },
+	{ }
+};
+
+static const struct udevice_id mt7629_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt7629-topckgen" },
+	{ }
+};
+
+static const struct udevice_id mt7629_infracfg_compat[] = {
+	{ .compatible = "mediatek,mt7629-infracfg", },
+	{ }
+};
+
+static const struct udevice_id mt7629_pericfg_compat[] = {
+	{ .compatible = "mediatek,mt7629-pericfg", },
+	{ }
+};
+
+static const struct udevice_id mt7629_ethsys_compat[] = {
+	{ .compatible = "mediatek,mt7629-ethsys", },
+	{ }
+};
+
+static const struct udevice_id mt7629_sgmiisys_compat[] = {
+	{ .compatible = "mediatek,mt7629-sgmiisys", },
+	{ }
+};
+
+static const struct udevice_id mt7629_ssusbsys_compat[] = {
+	{ .compatible = "mediatek,mt7629-ssusbsys" },
+	{ }
+};
+
+static const struct udevice_id mt7629_mcucfg_compat[] = {
+	{ .compatible = "mediatek,mt7629-mcucfg" },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_mcucfg) = {
+	.name = "mt7629-mcucfg",
+	.id = UCLASS_SYSCON,
+	.of_match = mt7629_mcucfg_compat,
+	.probe = mt7629_mcucfg_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt7629-clock-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_apmixed_compat,
+	.probe = mt7629_apmixedsys_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt7629-clock-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_topckgen_compat,
+	.probe = mt7629_topckgen_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+	.name = "mt7629-clock-infracfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_infracfg_compat,
+	.probe = mt7629_infracfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_pericfg) = {
+	.name = "mt7629-clock-pericfg",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_pericfg_compat,
+	.probe = mt7629_pericfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_ethsys) = {
+	.name = "mt7629-clock-ethsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_ethsys_compat,
+	.probe = mt7629_ethsys_probe,
+	.bind = mt7629_ethsys_bind,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
+	.name = "mt7629-clock-sgmiisys",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_sgmiisys_compat,
+	.probe = mt7629_sgmiisys_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+	.name = "mt7629-clock-ssusbsys",
+	.id = UCLASS_CLK,
+	.of_match = mt7629_ssusbsys_compat,
+	.probe = mt7629_ssusbsys_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt8183.c b/roms/u-boot/drivers/clk/mediatek/clk-mt8183.c
new file mode 100644
index 000000000..17e653a1f
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt8183.c
@@ -0,0 +1,823 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8183 SoC
+ *
+ * Copyright (C) 2020 BayLibre, SAS
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8183-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8183_PLL_FMAX		(3800UL * MHZ)
+#define MT8183_PLL_FMIN		(1500UL * MHZ)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \
+	    _pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) {	\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = _rst_bar_mask,				\
+		.fmax = MT8183_PLL_FMAX,				\
+		.fmin = MT8183_PLL_FMIN,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pcwibits = _pcwibits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001,
+	    HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
+	    0x0204, 0),
+	PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001,
+	    HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
+	    0x0214, 0),
+	PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001,
+	    HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
+	    0x0294, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001,
+	    HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
+	    0x0224, 0),
+	PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
+	    HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
+	    0x0234, 0),
+	PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001,
+	    0, 0, 22, 8, 0x0254, 24, 0x0254, 0),
+	PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001,
+	    HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
+	    0x0274, 0),
+	PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001,
+	    0, 0, 22, 8, 0x0244, 24, 0x0244, 0),
+	PLL(CLK_APMIXED_TVDPLL, 0x0260, 0x026C, 0x00000001,
+	    0, 0, 22, 8, 0x0264, 24, 0x0264, 0),
+	PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001,
+	    0, 0, 32, 8, 0x02A0, 1, 0x02A4, 0),
+	PLL(CLK_APMIXED_APLL2, 0x02b4, 0x02c4, 0x00000001,
+	    0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0),
+};
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
+	FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000),
+	FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR(CLK_TOP_CLK13M, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_F26M_CK_D2, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_CK, CLK_APMIXED_MAINPLL, 1,
+	       1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_SYSPLL_D2, CLK_TOP_SYSPLL_CK, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1,
+	       3, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1,
+	       5, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1,
+	       7, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_SYSPLL_D2_D2, CLK_TOP_SYSPLL_D2, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D2_D4, CLK_TOP_SYSPLL_D2, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D2_D8, CLK_TOP_SYSPLL_D2, 1,
+	       8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D2_D16, CLK_TOP_SYSPLL_D2, 1,
+	       16, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D3_D2, CLK_TOP_SYSPLL_D3, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D3_D4, CLK_TOP_SYSPLL_D3, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D3_D8, CLK_TOP_SYSPLL_D3, 1,
+	       8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D5_D2, CLK_TOP_SYSPLL_D5, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D5_D4, CLK_TOP_SYSPLL_D5, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D7_D2, CLK_TOP_SYSPLL_D7, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_SYSPLL_D7_D4, CLK_TOP_SYSPLL_D7, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_CK, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL_CK, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D2_D2, CLK_TOP_UNIVPLL_D2, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D2_D4, CLK_TOP_UNIVPLL_D2, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D2_D8, CLK_TOP_UNIVPLL_D2, 1,
+	       8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D3_D2, CLK_TOP_UNIVPLL_D3, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D3_D4, CLK_TOP_UNIVPLL_D3, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D3_D8, CLK_TOP_UNIVPLL_D3, 1,
+	       8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1,
+	       8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVP_192M_CK, CLK_TOP_UNIVP_192M, 1, 1,
+	       CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVP_192M_D2, CLK_TOP_UNIVP_192M_CK, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVP_192M_D4, CLK_TOP_UNIVP_192M_CK, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVP_192M_D8, CLK_TOP_UNIVP_192M_CK, 1,
+	       8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVP_192M_D16, CLK_TOP_UNIVP_192M_CK, 1,
+	       16, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVP_192M_D32, CLK_TOP_UNIVP_192M_CK, 1,
+	       32, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_APLL1_CK, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL2_CK, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL_CK, CLK_APMIXED_TVDPLL, 1, 1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL_CK, 1, 2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL_D8, CLK_APMIXED_TVDPLL, 1, 8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_TVDPLL_D16, CLK_APMIXED_TVDPLL, 1,
+	       16, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_CK, CLK_APMIXED_MMPLL, 1, 1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1,
+	       2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1,
+	       4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MFGPLL_CK, CLK_APMIXED_MFGPLL, 1, 1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MSDCPLL_CK, CLK_APMIXED_MSDCPLL, 1,
+	       1, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1,
+	       2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1,
+	       4, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1,
+	       8, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1,
+	       16, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_AD_OSC_CK, CLK_TOP_ULPOSC, 1, 1, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_OSC_D2, CLK_TOP_ULPOSC, 1, 2, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_OSC_D4, CLK_TOP_ULPOSC, 1, 4, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_OSC_D8, CLK_TOP_ULPOSC, 1, 8, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_OSC_D16, CLK_TOP_ULPOSC, 1, 16, CLK_PARENT_TOPCKGEN),
+	FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2, CLK_PARENT_APMIXED),
+	FACTOR(CLK_TOP_UNIVPLL_D3_D16, CLK_TOP_UNIVPLL_D3, 1,
+	       16, CLK_PARENT_TOPCKGEN),
+};
+
+static const int axi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D4,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_OSC_D4
+};
+
+static const int mm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MMPLL_D7,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int img_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MMPLL_D6,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int cam_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2,
+	CLK_TOP_MMPLL_D6,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_MMPLL_D7,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_SYSPLL_D3_D2,
+	CLK_TOP_UNIVPLL_D3_D2
+};
+
+static const int dsp_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MMPLL_D6,
+	CLK_TOP_MMPLL_D7,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int dsp1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MMPLL_D6,
+	CLK_TOP_MMPLL_D7,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int dsp2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MMPLL_D6,
+	CLK_TOP_MMPLL_D7,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int ipu_if_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MMPLL_D6,
+	CLK_TOP_MMPLL_D7,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int mfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MFGPLL_CK,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3
+};
+
+static const int f52m_mfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_UNIVPLL_D3_D4,
+	CLK_TOP_UNIVPLL_D3_D8
+};
+
+static const int camtg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVP_192M_D8,
+	CLK_TOP_UNIVPLL_D3_D8,
+	CLK_TOP_UNIVP_192M_D4,
+	CLK_TOP_UNIVPLL_D3_D16,
+	CLK_TOP_F26M_CK_D2,
+	CLK_TOP_UNIVP_192M_D16,
+	CLK_TOP_UNIVP_192M_D32
+};
+
+static const int camtg2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVP_192M_D8,
+	CLK_TOP_UNIVPLL_D3_D8,
+	CLK_TOP_UNIVP_192M_D4,
+	CLK_TOP_UNIVPLL_D3_D16,
+	CLK_TOP_F26M_CK_D2,
+	CLK_TOP_UNIVP_192M_D16,
+	CLK_TOP_UNIVP_192M_D32
+};
+
+static const int camtg3_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVP_192M_D8,
+	CLK_TOP_UNIVPLL_D3_D8,
+	CLK_TOP_UNIVP_192M_D4,
+	CLK_TOP_UNIVPLL_D3_D16,
+	CLK_TOP_F26M_CK_D2,
+	CLK_TOP_UNIVP_192M_D16,
+	CLK_TOP_UNIVP_192M_D32
+};
+
+static const int camtg4_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVP_192M_D8,
+	CLK_TOP_UNIVPLL_D3_D8,
+	CLK_TOP_UNIVP_192M_D4,
+	CLK_TOP_UNIVPLL_D3_D16,
+	CLK_TOP_F26M_CK_D2,
+	CLK_TOP_UNIVP_192M_D16,
+	CLK_TOP_UNIVP_192M_D32
+};
+
+static const int uart_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3_D8
+};
+
+static const int spi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D5_D2,
+	CLK_TOP_SYSPLL_D3_D4,
+	CLK_TOP_MSDCPLL_D4
+};
+
+static const int msdc50_hclk_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_SYSPLL_D3_D2
+};
+
+static const int msdc50_0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MSDCPLL_CK,
+	CLK_TOP_MSDCPLL_D2,
+	CLK_TOP_UNIVPLL_D2_D4,
+	CLK_TOP_SYSPLL_D3_D2,
+	CLK_TOP_UNIVPLL_D2_D2
+};
+
+static const int msdc30_1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_MSDCPLL_D2
+};
+
+static const int msdc30_2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_SYSPLL_D3_D2,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_MSDCPLL_D2
+};
+
+static const int audio_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D5_D4,
+	CLK_TOP_SYSPLL_D7_D4,
+	CLK_TOP_SYSPLL_D2_D16
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D4,
+	CLK_TOP_SYSPLL_D7_D2
+};
+
+static const int pmicspi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D8,
+	CLK_TOP_OSC_D8
+};
+
+static const int fpwrap_ulposc_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_OSC_D16,
+	CLK_TOP_OSC_D4,
+	CLK_TOP_OSC_D8
+};
+
+static const int atb_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_SYSPLL_D5
+};
+
+static const int sspm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2_D4,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D3
+};
+
+static const int dpi0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_TVDPLL_D4,
+	CLK_TOP_TVDPLL_D8,
+	CLK_TOP_TVDPLL_D16,
+	CLK_TOP_UNIVPLL_D5_D2,
+	CLK_TOP_UNIVPLL_D3_D4,
+	CLK_TOP_SYSPLL_D3_D4,
+	CLK_TOP_UNIVPLL_D3_D8
+};
+
+static const int scam_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D5_D2
+};
+
+static const int disppwm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3_D4,
+	CLK_TOP_OSC_D2,
+	CLK_TOP_OSC_D4,
+	CLK_TOP_OSC_D16
+};
+
+static const int usb_top_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D5_D4,
+	CLK_TOP_UNIVPLL_D3_D4,
+	CLK_TOP_UNIVPLL_D5_D2
+};
+
+static const int ssusb_top_xhci_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D5_D4,
+	CLK_TOP_UNIVPLL_D3_D4,
+	CLK_TOP_UNIVPLL_D5_D2
+};
+
+static const int spm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D8
+};
+
+static const int i2c_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D8,
+	CLK_TOP_UNIVPLL_D5_D2
+};
+
+static const int scp_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2_D8,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int seninf_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2_D2,
+	CLK_TOP_UNIVPLL_D3_D2,
+	CLK_TOP_UNIVPLL_D2_D4
+};
+
+static const int dxcc_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_SYSPLL_D2_D4,
+	CLK_TOP_SYSPLL_D2_D8
+};
+
+static const int aud_engen1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_D2,
+	CLK_TOP_APLL1_D4,
+	CLK_TOP_APLL1_D8
+};
+
+static const int aud_engen2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_D2,
+	CLK_TOP_APLL2_D4,
+	CLK_TOP_APLL2_D8
+};
+
+static const int faes_ufsfde_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2,
+	CLK_TOP_SYSPLL_D2_D2,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_SYSPLL_D2_D4,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int fufs_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D2_D4,
+	CLK_TOP_SYSPLL_D2_D8,
+	CLK_TOP_SYSPLL_D2_D16
+};
+
+static const int aud_1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_CK
+};
+
+static const int aud_2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_CK
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2),
+	MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3),
+	MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3),
+	MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4),
+	/* CLK_CFG_1 */
+	MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4),
+	MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4),
+	MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4),
+	MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4),
+	/* CLK_CFG_2 */
+	MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2),
+	MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2),
+	MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3),
+	MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3),
+	/* CLK_CFG_3 */
+	MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3),
+	MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3),
+	MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1),
+	MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2),
+	/* CLK_CFG_4 */
+	MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2),
+	MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3),
+	MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3),
+	MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3),
+	/* CLK_CFG_5 */
+	MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2),
+	MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2),
+	MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2),
+	MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2),
+	/* CLK_CFG_6 */
+	MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2),
+	MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3),
+	MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4),
+	MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1),
+	/* CLK_CFG_7 */
+	MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3),
+	MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2),
+	MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2),
+	MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1),
+	/* CLK_CFG_8 */
+	MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2),
+	MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3),
+	MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2),
+	MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2),
+	/* CLK_CFG_9 */
+	MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2),
+	MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2),
+	MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3),
+	MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2),
+	/* CLK_CFG_10 */
+	MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1),
+	MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1),
+};
+
+static const struct mtk_clk_tree mt8183_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_CLK13M,
+	.muxes_offs = CLK_TOP_MUX_AXI,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+	.set_ofs = 0x80,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+	.set_ofs = 0x88,
+	.clr_ofs = 0x8c,
+	.sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xa8,
+	.sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+	.set_ofs = 0xc0,
+	.clr_ofs = 0xc4,
+	.sta_ofs = 0xc8,
+};
+
+#define GATE_INFRA0(_id, _parent, _shift) {		\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &infra0_cg_regs,				\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,		\
+	}
+
+#define GATE_INFRA1(_id, _parent, _shift) {		\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &infra1_cg_regs,				\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,		\
+	}
+
+#define GATE_INFRA2(_id, _parent, _shift) {		\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &infra2_cg_regs,				\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,		\
+	}
+
+#define GATE_INFRA3(_id, _parent, _shift) {		\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &infra3_cg_regs,				\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,		\
+	}
+
+static const struct mtk_gate infra_clks[] = {
+	/* INFRA0 */
+	GATE_INFRA0(CLK_INFRA_PMIC_TMR, CLK_TOP_MUX_AXI, 0),
+	GATE_INFRA0(CLK_INFRA_PMIC_AP, CLK_TOP_MUX_AXI, 1),
+	GATE_INFRA0(CLK_INFRA_PMIC_MD, CLK_TOP_MUX_AXI, 2),
+	GATE_INFRA0(CLK_INFRA_PMIC_CONN, CLK_TOP_MUX_AXI, 3),
+	GATE_INFRA0(CLK_INFRA_SCPSYS, CLK_TOP_MUX_SCP, 4),
+	GATE_INFRA0(CLK_INFRA_SEJ, CLK_TOP_CLK26M, 5),
+	GATE_INFRA0(CLK_INFRA_APXGPT, CLK_TOP_MUX_AXI, 6),
+	GATE_INFRA0(CLK_INFRA_ICUSB, CLK_TOP_MUX_AXI, 8),
+	GATE_INFRA0(CLK_INFRA_GCE, CLK_TOP_MUX_AXI, 9),
+	GATE_INFRA0(CLK_INFRA_THERM, CLK_TOP_MUX_AXI, 10),
+	GATE_INFRA0(CLK_INFRA_I2C0, CLK_TOP_MUX_I2C, 11),
+	GATE_INFRA0(CLK_INFRA_I2C1, CLK_TOP_MUX_I2C, 12),
+	GATE_INFRA0(CLK_INFRA_I2C2, CLK_TOP_MUX_I2C, 13),
+	GATE_INFRA0(CLK_INFRA_I2C3, CLK_TOP_MUX_I2C, 14),
+	GATE_INFRA0(CLK_INFRA_PWM_HCLK, CLK_TOP_MUX_AXI, 15),
+	GATE_INFRA0(CLK_INFRA_PWM1, CLK_TOP_MUX_I2C, 16),
+	GATE_INFRA0(CLK_INFRA_PWM2, CLK_TOP_MUX_I2C, 17),
+	GATE_INFRA0(CLK_INFRA_PWM3, CLK_TOP_MUX_I2C, 18),
+	GATE_INFRA0(CLK_INFRA_PWM4, CLK_TOP_MUX_I2C, 19),
+	GATE_INFRA0(CLK_INFRA_PWM, CLK_TOP_MUX_I2C, 21),
+	GATE_INFRA0(CLK_INFRA_UART0, CLK_TOP_MUX_UART, 22),
+	GATE_INFRA0(CLK_INFRA_UART1, CLK_TOP_MUX_UART, 23),
+	GATE_INFRA0(CLK_INFRA_UART2, CLK_TOP_MUX_UART, 24),
+	GATE_INFRA0(CLK_INFRA_UART3, CLK_TOP_MUX_UART, 25),
+	GATE_INFRA0(CLK_INFRA_GCE_26M, CLK_TOP_MUX_AXI, 27),
+	GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, CLK_TOP_MUX_AXI, 28),
+	GATE_INFRA0(CLK_INFRA_BTIF, CLK_TOP_MUX_AXI, 31),
+	/* INFRA1 */
+	GATE_INFRA1(CLK_INFRA_SPI0, CLK_TOP_MUX_SPI, 1),
+	GATE_INFRA1(CLK_INFRA_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 2),
+	GATE_INFRA1(CLK_INFRA_MSDC1, CLK_TOP_MUX_AXI, 4),
+	GATE_INFRA1(CLK_INFRA_MSDC2, CLK_TOP_MUX_AXI, 5),
+	GATE_INFRA1(CLK_INFRA_MSDC0_SCK, CLK_TOP_MUX_MSDC50_0, 6),
+	GATE_INFRA1(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
+	GATE_INFRA1(CLK_INFRA_GCPU, CLK_TOP_MUX_AXI, 8),
+	GATE_INFRA1(CLK_INFRA_TRNG, CLK_TOP_MUX_AXI, 9),
+	GATE_INFRA1(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
+	GATE_INFRA1(CLK_INFRA_CPUM, CLK_TOP_MUX_AXI, 11),
+	GATE_INFRA1(CLK_INFRA_CCIF1_AP, CLK_TOP_MUX_AXI, 12),
+	GATE_INFRA1(CLK_INFRA_CCIF1_MD, CLK_TOP_MUX_AXI, 13),
+	GATE_INFRA1(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
+	GATE_INFRA1(CLK_INFRA_MSDC1_SCK, CLK_TOP_MUX_MSDC30_1, 16),
+	GATE_INFRA1(CLK_INFRA_MSDC2_SCK, CLK_TOP_MUX_MSDC30_2, 17),
+	GATE_INFRA1(CLK_INFRA_AP_DMA, CLK_TOP_MUX_AXI, 18),
+	GATE_INFRA1(CLK_INFRA_XIU, CLK_TOP_MUX_AXI, 19),
+	GATE_INFRA1(CLK_INFRA_DEVICE_APC, CLK_TOP_MUX_AXI, 20),
+	GATE_INFRA1(CLK_INFRA_CCIF_AP, CLK_TOP_MUX_AXI, 23),
+	GATE_INFRA1(CLK_INFRA_DEBUGSYS, CLK_TOP_MUX_AXI, 24),
+	GATE_INFRA1(CLK_INFRA_AUDIO, CLK_TOP_MUX_AXI, 25),
+	GATE_INFRA1(CLK_INFRA_CCIF_MD, CLK_TOP_MUX_AXI, 26),
+	GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, CLK_TOP_MUX_DXCC, 27),
+	GATE_INFRA1(CLK_INFRA_DXCC_AO, CLK_TOP_MUX_DXCC, 28),
+	GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30),
+	GATE_INFRA1(CLK_INFRA_DRAMC_F26M, CLK_TOP_CLK26M, 31),
+	/* INFRA2 */
+	GATE_INFRA2(CLK_INFRA_IRTX, CLK_TOP_CLK26M, 0),
+	GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1),
+	GATE_INFRA2(CLK_INFRA_DISP_PWM, CLK_TOP_MUX_AXI, 2),
+	GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, CLK_TOP_MUX_AXI, 3),
+	GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4),
+	GATE_INFRA2(CLK_INFRA_SPI1, CLK_TOP_MUX_SPI, 6),
+	GATE_INFRA2(CLK_INFRA_I2C4, CLK_TOP_MUX_I2C, 7),
+	GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, CLK_TOP_CLK26M, 8),
+	GATE_INFRA2(CLK_INFRA_SPI2, CLK_TOP_MUX_SPI, 9),
+	GATE_INFRA2(CLK_INFRA_SPI3, CLK_TOP_MUX_SPI, 10),
+	GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, CLK_TOP_MUX_SSUSB_TOP_XHCI, 11),
+	GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, CLK_TOP_MUX_FUFS, 12),
+	GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, CLK_TOP_MUX_FUFS, 13),
+	GATE_INFRA2(CLK_INFRA_MD32_BCLK, CLK_TOP_MUX_AXI, 14),
+	GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, CLK_TOP_MUX_AXI, 16),
+	GATE_INFRA2(CLK_INFRA_I2C5, CLK_TOP_MUX_I2C, 18),
+	GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, CLK_TOP_MUX_I2C, 19),
+	GATE_INFRA2(CLK_INFRA_I2C5_IMM, CLK_TOP_MUX_I2C, 20),
+	GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, CLK_TOP_MUX_I2C, 21),
+	GATE_INFRA2(CLK_INFRA_I2C1_IMM, CLK_TOP_MUX_I2C, 22),
+	GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, CLK_TOP_MUX_I2C, 23),
+	GATE_INFRA2(CLK_INFRA_I2C2_IMM, CLK_TOP_MUX_I2C, 24),
+	GATE_INFRA2(CLK_INFRA_SPI4, CLK_TOP_MUX_SPI, 25),
+	GATE_INFRA2(CLK_INFRA_SPI5, CLK_TOP_MUX_SPI, 26),
+	GATE_INFRA2(CLK_INFRA_CQ_DMA, CLK_TOP_MUX_AXI, 27),
+	GATE_INFRA2(CLK_INFRA_UFS, CLK_TOP_MUX_FUFS, 28),
+	GATE_INFRA2(CLK_INFRA_AES_UFSFDE, CLK_TOP_MUX_FAES_UFSFDE, 29),
+	GATE_INFRA2(CLK_INFRA_UFS_TICK, CLK_TOP_MUX_FUFS, 30),
+	/* INFRA3 */
+	GATE_INFRA3(CLK_INFRA_MSDC0_SELF, CLK_TOP_MUX_MSDC50_0, 0),
+	GATE_INFRA3(CLK_INFRA_MSDC1_SELF, CLK_TOP_MUX_MSDC50_0, 1),
+	GATE_INFRA3(CLK_INFRA_MSDC2_SELF, CLK_TOP_MUX_MSDC50_0, 2),
+	GATE_INFRA3(CLK_INFRA_UFS_AXI, CLK_TOP_MUX_AXI, 5),
+	GATE_INFRA3(CLK_INFRA_I2C6, CLK_TOP_MUX_I2C, 6),
+	GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7),
+	GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8),
+	GATE_INFRA3(CLK_INFRA_CCIF2_AP, CLK_TOP_MUX_AXI, 16),
+	GATE_INFRA3(CLK_INFRA_CCIF2_MD, CLK_TOP_MUX_AXI, 17),
+	GATE_INFRA3(CLK_INFRA_CCIF3_AP, CLK_TOP_MUX_AXI, 18),
+	GATE_INFRA3(CLK_INFRA_CCIF3_MD, CLK_TOP_MUX_AXI, 19),
+	GATE_INFRA3(CLK_INFRA_SEJ_F13M, CLK_TOP_CLK26M, 20),
+	GATE_INFRA3(CLK_INFRA_AES_BCLK, CLK_TOP_MUX_AXI, 21),
+	GATE_INFRA3(CLK_INFRA_I2C7, CLK_TOP_MUX_I2C, 22),
+	GATE_INFRA3(CLK_INFRA_I2C8, CLK_TOP_MUX_I2C, 23),
+	GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24),
+};
+
+static int mt8183_apmixedsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8183_clk_tree);
+}
+
+static int mt8183_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8183_clk_tree);
+}
+
+static int mt8183_infracfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks);
+}
+
+static const struct udevice_id mt8183_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt8183-apmixedsys", },
+	{ }
+};
+
+static const struct udevice_id mt8183_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt8183-topckgen", },
+	{ }
+};
+
+static const struct udevice_id mt8183_infracfg_compat[] = {
+	{ .compatible = "mediatek,mt8183-infracfg", },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt8183-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8183_apmixed_compat,
+	.probe = mt8183_apmixedsys_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt8183-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt8183_topckgen_compat,
+	.probe = mt8183_topckgen_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+	.name = "mt8183-infracfg",
+	.id = UCLASS_CLK,
+	.of_match = mt8183_infracfg_compat,
+	.probe = mt8183_infracfg_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt8512.c b/roms/u-boot/drivers/clk/mediatek/clk-mt8512.c
new file mode 100644
index 000000000..193e069cb
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt8512.c
@@ -0,0 +1,874 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8512 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8512-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT8512_PLL_FMAX		(3800UL * MHZ)
+#define MT8512_PLL_FMIN		(1500UL * MHZ)
+#define MT8512_CON0_RST_BAR	BIT(23)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) {		\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT8512_CON0_RST_BAR,			\
+		.fmax = MT8512_PLL_FMAX,				\
+		.fmin = MT8512_PLL_FMIN,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pcwibits = 8,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+		.pcw_chg_reg = _pcw_chg_reg,			\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
+	    0, 22, 0x0310, 24, 0x0310, 0, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
+	    HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+	PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
+	    HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+	PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
+	    0, 22, 0x0354, 24, 0x0354, 0, 0),
+	PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
+	    0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
+	PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
+	    0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
+	PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
+	    0, 22, 0x0378, 24, 0x0378, 0, 0),
+	PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
+	    0, 22, 0x0394, 24, 0x0394, 0, 0),
+	PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
+	    0, 22, 0x03A4, 24, 0x03A4, 0, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+	FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
+	FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+	FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
+	FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+	FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
+	FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+	FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+	FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+	FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
+	FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+	FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+	FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+	FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+	FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+	FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+	FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2),
+	FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4),
+	FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8),
+	FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16),
+	FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32),
+	FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64),
+	FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13),
+	FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2),
+	FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4),
+	FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+	FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
+	FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
+	FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
+	FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
+	FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
+	FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+	FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
+	FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
+	FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
+	FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
+	FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
+	FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
+	FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
+	FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
+	FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
+	FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
+	FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4),
+	FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
+	FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1),
+	FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2),
+	FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2),
+};
+
+static const int axi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_CLK32K
+};
+
+static const int mem_parents[] = {
+	CLK_TOP_DSPPLL,
+	CLK_TOP_IPPLL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int uart_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL1_D4,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_SYSPLL4_D2
+};
+
+static const int spis_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_UNIVPLL1_D4,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_SYSPLL4_D2
+};
+
+static const int msdc50_0_hc_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL1_D4,
+	CLK_TOP_SYSPLL2_D2
+};
+
+static const int msdc50_0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MSDCPLL_D2,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL1_D4,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int msdc50_2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MSDCPLL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL1_D4
+};
+
+static const int audio_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL2_D8,
+	CLK_TOP_APLL1_D4,
+	CLK_TOP_APLL2_D4
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_APLL2_D8,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_APLL1_D8,
+	CLK_TOP_UNIVPLL3_D4
+};
+
+static const int hapll1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1,
+	CLK_TOP_APLL1_D2,
+	CLK_TOP_APLL1_D3,
+	CLK_TOP_APLL1_D4,
+	CLK_TOP_APLL1_D8,
+	CLK_TOP_APLL1_D16,
+	CLK_TOP_SYS_26M_D2
+};
+
+static const int hapll2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2,
+	CLK_TOP_APLL2_D2,
+	CLK_TOP_APLL2_D3,
+	CLK_TOP_APLL2_D4,
+	CLK_TOP_APLL2_D8,
+	CLK_TOP_APLL2_D16,
+	CLK_TOP_SYS_26M_D2
+};
+
+static const int asm_l_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL_D5
+};
+
+static const int aud_spdif_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2,
+	CLK_TOP_DSPPLL
+};
+
+static const int aud_1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1
+};
+
+static const int aud_2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2
+};
+
+static const int ssusb_sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL3_D2
+};
+
+static const int spm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL1_D8
+};
+
+static const int i2c_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_UNIVPLL3_D2,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_SYSPLL2_D8,
+	CLK_TOP_CLK32K
+};
+
+static const int pwm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_CLK32K
+};
+
+static const int dsp_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DSPPLL,
+	CLK_TOP_DSPPLL_D2,
+	CLK_TOP_DSPPLL_D4,
+	CLK_TOP_DSPPLL_D8,
+	CLK_TOP_APLL2_D4,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_CLK32K
+};
+
+static const int nfi2x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_SYSPLL_D7,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_MSDCPLL_D2,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL_D5
+};
+
+static const int spinfi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL2_D8,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_SYSPLL4_D2,
+	CLK_TOP_SYSPLL2_D4,
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL3_D2
+};
+
+static const int ecc_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int gcpu_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_UNIVPLL2_D2
+};
+
+static const int gcpu_cpm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL1_D4
+};
+
+static const int mbist_diag_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYS_26M_D2
+};
+
+static const int ip0_nna_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DSPPLL,
+	CLK_TOP_DSPPLL_D2,
+	CLK_TOP_DSPPLL_D4,
+	CLK_TOP_IPPLL,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_IPPLL_D2,
+	CLK_TOP_MSDCPLL_D2
+};
+
+static const int ip2_wfst_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL2_D2,
+	CLK_TOP_IPPLL,
+	CLK_TOP_IPPLL_D2,
+	CLK_TOP_SYS_26M_D2,
+	CLK_TOP_MSDCPLL
+};
+
+static const int sflash_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL1_D16,
+	CLK_TOP_SYSPLL2_D8,
+	CLK_TOP_SYSPLL3_D4,
+	CLK_TOP_UNIVPLL3_D4,
+	CLK_TOP_UNIVPLL1_D8,
+	CLK_TOP_USB20_192M_D2,
+	CLK_TOP_UNIVPLL2_D4
+};
+
+static const int sram_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DSPPLL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_APLL1,
+	CLK_TOP_APLL2,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_SYS_26M_D2
+};
+
+static const int mm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_SYSPLL_D3,
+	CLK_TOP_SYSPLL1_D2,
+	CLK_TOP_SYSPLL_D5,
+	CLK_TOP_SYSPLL1_D4,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int dpi0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_TCONPLL_D2,
+	CLK_TOP_TCONPLL_D4,
+	CLK_TOP_TCONPLL_D8,
+	CLK_TOP_TCONPLL_D16,
+	CLK_TOP_TCONPLL_D32,
+	CLK_TOP_TCONPLL_D64
+};
+
+static const int dbg_atclk_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL1_D2,
+	CLK_TOP_UNIVPLL_D5
+};
+
+static const int occ_104m_parents[] = {
+	CLK_TOP_UNIVPLL2_D4,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int occ_68m_parents[] = {
+	CLK_TOP_SYSPLL1_D8,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const int occ_182m_parents[] = {
+	CLK_TOP_SYSPLL2_D2,
+	CLK_TOP_UNIVPLL1_D4,
+	CLK_TOP_UNIVPLL2_D8
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_CFG_0 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
+			      0x040, 0x044, 0x048, 0, 3, 7,
+			      0x4, 0, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
+			      0x040, 0x044, 0x048, 8, 2, 15,
+			      0x4, 1, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
+			      0x040, 0x044, 0x048, 16, 1, 23,
+			      0x4, 2, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents,
+			      0x040, 0x044, 0x048, 24, 3, 31,
+			      0x4, 3, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_1 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents,
+			      0x050, 0x054, 0x058, 0, 3, 7,
+			      0x4, 4, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents,
+			      0x050, 0x054, 0x058, 8, 2, 15,
+			      0x4, 5, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
+			      0x050, 0x054, 0x058, 16, 2, 23,
+			      0x4, 6, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
+			      0x050, 0x054, 0x058, 24, 3, 31,
+			      0x4, 7, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_2 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents,
+			      0x060, 0x064, 0x068, 0, 3, 7,
+			      0x4, 8, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
+			      0x060, 0x064, 0x068, 8, 3, 15,
+			      0x4, 9, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents,
+			      0x060, 0x064, 0x068, 16, 2, 23,
+			      0x4, 10, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
+			      0x060, 0x064, 0x068, 24, 3, 31,
+			      0x4, 11, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_3 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
+			      0x070, 0x074, 0x078, 0, 3, 7,
+			      0x4, 12, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents,
+			      0x070, 0x074, 0x078, 8, 3, 15,
+			      0x4, 13, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents,
+			      0x070, 0x074, 0x078, 16, 3, 23,
+			      0x4, 14, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents,
+			      0x070, 0x074, 0x078, 24, 3, 31,
+			      0x4, 15, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_4 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents,
+			      0x080, 0x084, 0x088, 0, 2, 7,
+			      0x4, 16, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
+			      0x080, 0x084, 0x088, 8, 2, 15,
+			      0x4, 17, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
+			      0x080, 0x084, 0x088, 16, 2, 23,
+			      0x4, 18, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents,
+			      0x080, 0x084, 0x088, 24, 2, 31,
+			      0x4, 19, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_5 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
+			      0x090, 0x094, 0x098, 0, 1, 7,
+			      0x4, 20, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
+			      0x090, 0x094, 0x098, 8, 1, 15,
+			      0x4, 21, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents,
+			      0x090, 0x094, 0x098, 16, 2, 23,
+			      0x4, 22, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
+			      0x090, 0x094, 0x098, 24, 2, 31,
+			      0x4, 23, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_6 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents,
+			      0x0a0, 0x0a4, 0x0a8, 0, 1, 7,
+			      0x4, 24, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents,
+			      0x0a0, 0x0a4, 0x0a8, 8, 3, 15,
+			      0x4, 25, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents,
+			      0x0a0, 0x0a4, 0x0a8, 16, 3, 23,
+			      0x4, 26, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
+			      0x0a0, 0x0a4, 0x0a8, 24, 3, 31,
+			      0x4, 27, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_7 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents,
+			      0x0b0, 0x0b4, 0x0b8, 0, 3, 7,
+			      0x4, 28, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents,
+			      0x0b0, 0x0b4, 0x0b8, 8, 3, 15,
+			      0x4, 29, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents,
+			      0x0b0, 0x0b4, 0x0b8, 16, 2, 23,
+			      0x4, 30, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
+			      0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
+			      0x4, 31, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_8 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents,
+			      0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
+			      0x8, 0, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents,
+			      0x0c0, 0x0c4, 0x0c8, 8, 1, 15,
+			      0x8, 1, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,
+			      0x0c0, 0x0c4, 0x0c8, 16, 3, 23,
+			      0x8, 2, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents,
+			      0x0c0, 0x0c4, 0x0c8, 24, 3, 31,
+			      0x8, 3, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_9 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents,
+			      0x0d0, 0x0d4, 0x0d8, 0, 3, 7,
+			      0x8, 4, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents,
+			      0x0d0, 0x0d4, 0x0d8, 8, 3, 15,
+			      0x8, 5, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents,
+			      0x0d0, 0x0d4, 0x0d8, 16, 3, 23,
+			      0x8, 6, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents,
+			      0x0d0, 0x0d4, 0x0d8, 24, 3, 31,
+			      0x8, 7, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_10 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents,
+			      0x0e0, 0x0e4, 0x0e8, 0, 3, 7,
+			      0x8, 8, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents,
+			      0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
+			      0x8, 9, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents,
+			      0x0e0, 0x0e4, 0x0e8, 16, 1, 23,
+			      0x8, 10, CLK_MUX_SETCLR_UPD),
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents,
+			      0x0e0, 0x0e4, 0x0e8, 24, 1, 31,
+			      0x8, 11, CLK_MUX_SETCLR_UPD),
+	/* CLK_CFG_11 */
+	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents,
+			      0x0ec, 0x0f0, 0x0f4, 0, 2, 7,
+			      0x8, 12, CLK_MUX_SETCLR_UPD),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x0,
+	.sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x104,
+	.sta_ofs = 0x104,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate top_clks[] = {
+	/* TOP0 */
+	GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
+	GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
+	GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
+	GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8),
+	GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9),
+	GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
+	GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+	.set_ofs = 0x294,
+	.clr_ofs = 0x294,
+	.sta_ofs = 0x294,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+	.set_ofs = 0x80,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+	.set_ofs = 0x88,
+	.clr_ofs = 0x8c,
+	.sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xa8,
+	.sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra4_cg_regs = {
+	.set_ofs = 0xc0,
+	.clr_ofs = 0xc4,
+	.sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra5_cg_regs = {
+	.set_ofs = 0xd0,
+	.clr_ofs = 0xd4,
+	.sta_ofs = 0xd8,
+};
+
+#define GATE_INFRA0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_INFRA1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_INFRA2(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra2_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_INFRA3(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra3_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_INFRA4(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra4_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_INFRA5(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &infra5_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate infra_clks[] = {
+	/* INFRA0 */
+	GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
+	/* INFRA1 */
+	GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
+	GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
+	GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
+	GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
+	GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
+	GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16),
+	GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17),
+	GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18),
+	GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19),
+	GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20),
+	GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21),
+	GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
+	GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
+	GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
+	GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
+	GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27),
+	GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
+	GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
+	/* INFRA2 */
+	GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1),
+	GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2),
+	GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
+	GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
+	GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
+	GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
+	GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
+	GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
+	GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
+	GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+	GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
+	GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29),
+	/* INFRA3 */
+	GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0),
+	GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1),
+	GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
+	GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4),
+	GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
+	GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+	/* INFRA4 */
+	GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
+	GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
+	GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
+	GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
+	GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
+	GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23),
+	GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
+	GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
+	GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
+	/* INFRA5 */
+	GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1),
+	GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2),
+	GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
+	GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
+	GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
+	GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
+};
+
+static const struct mtk_clk_tree mt8512_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_SYSPLL1_D2,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt8512_apmixedsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8512_clk_tree);
+}
+
+static int mt8512_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8512_clk_tree);
+}
+
+static int mt8512_topckgen_cg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks);
+}
+
+static int mt8512_infracfg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks);
+}
+
+static const struct udevice_id mt8512_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt8512-apmixedsys", },
+	{ }
+};
+
+static const struct udevice_id mt8512_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt8512-topckgen", },
+	{ }
+};
+
+static const struct udevice_id mt8512_topckgen_cg_compat[] = {
+	{ .compatible = "mediatek,mt8512-topckgen-cg", },
+	{ }
+};
+
+static const struct udevice_id mt8512_infracfg_compat[] = {
+	{ .compatible = "mediatek,mt8512-infracfg", },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt8512-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8512_apmixed_compat,
+	.probe = mt8512_apmixedsys_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt8512-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt8512_topckgen_compat,
+	.probe = mt8512_topckgen_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+	.name = "mt8512-topckgen-cg",
+	.id = UCLASS_CLK,
+	.of_match = mt8512_topckgen_cg_compat,
+	.probe = mt8512_topckgen_cg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+	.name = "mt8512-infracfg",
+	.id = UCLASS_CLK,
+	.of_match = mt8512_infracfg_compat,
+	.probe = mt8512_infracfg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt8516.c b/roms/u-boot/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 000000000..29f70620e
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8516 SoC
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT8516_PLL_FMAX		(1502UL * MHZ)
+#define MT8516_CON0_RST_BAR	BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT8516_CON0_RST_BAR,			\
+		.fmax = MT8516_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
+		21, 0x0104, 24, 0x0104, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+		HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+	PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+		HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+	PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
+		21, 0x0164, 24, 0x0164, 0),
+	PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
+		31, 0x0180, 1, 0x0184, 0),
+	PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
+		31, 0x01A0, 1, 0x01A4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+	FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+	FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+	FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+	FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+	FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+	FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+	FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+	FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+	FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+	FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+	FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+	FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+	FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+	FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+	FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+	FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+	FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+	FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+	FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+	FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
+	FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+	FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
+	FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+	FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+	FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
+	FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
+	FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
+	FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+	FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+	FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
+	FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
+	FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+	FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
+	FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
+	FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+};
+
+static const int gfmux_emi1x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DMPLL,
+};
+
+static const int emi_ddrphy_parents[] = {
+	CLK_TOP_GFMUX_EMI1X_SEL,
+	CLK_TOP_GFMUX_EMI1X_SEL,
+};
+
+static const int ahb_infra_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D10,
+};
+
+static const int csw_mux_mfg_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_UNIVPLL_D2,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_MMPLL380M,
+};
+
+static const int msdc0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_MMPLL_200M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MMPLL_D2,
+};
+
+static const int pwm_mm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+};
+
+static const int uart1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+};
+
+static const int msdc1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_MMPLL_200M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MMPLL_D2,
+};
+
+static const int spm_52m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+};
+
+static const int pmicspi_parents[] = {
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_USB_PHY48M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK26M,
+};
+
+static const int qaxi_aud26m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_AHB_INFRA_SEL,
+};
+
+static const int aud_intbus_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D22,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D11,
+};
+
+static const int nfi2x_pad_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D10,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D5
+};
+
+static const int nfi1x_pad_parents[] = {
+	CLK_TOP_AHB_INFRA_SEL,
+	CLK_TOP_NFI1X,
+};
+
+static const int mfg_mm_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CSW_MUX_MFG_SEL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D3,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D14
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D16
+};
+
+static const int usb_78m_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D20,
+};
+
+static const int spinor_parents[] = {
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int msdc2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_MMPLL_200M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MMPLL_D2
+};
+
+static const int eth_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int axi_mfg_in_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_MMPLL380M,
+};
+
+static const int slow_mfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D24
+};
+
+static const int aud1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1
+};
+
+static const int aud2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_RG_APLL1_D2_EN,
+	CLK_TOP_RG_APLL1_D4_EN,
+	CLK_TOP_RG_APLL1_D8_EN
+};
+
+static const int aud_engen2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_RG_APLL2_D2_EN,
+	CLK_TOP_RG_APLL2_D4_EN,
+	CLK_TOP_RG_APLL2_D8_EN
+};
+
+static const int i2c_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int aud_i2s0_m_parents[] = {
+	CLK_TOP_RG_AUD1,
+	CLK_TOP_RG_AUD2
+};
+
+static const int pwm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int spi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_UNIVPLL_D6
+};
+
+static const int aud_spdifin_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2
+};
+
+static const int uart2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24
+};
+
+static const int bsi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D10,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int dbg_atclk_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D5
+};
+
+static const int csw_nfiecc_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_NFI2X_PAD_SEL,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CSW_NFIECC_SEL,
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_MUX_SEL0 */
+	MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+	MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+	MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+	MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+	MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
+	MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+	MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+	MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+	MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+	MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
+	MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+	MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+	MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+	/* CLK_MUX_SEL1 */
+	MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+	MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+	MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
+	MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+	MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+	/* CLK_MUX_SEL8 */
+	MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+	MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+	MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+	MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
+	MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
+	MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+	MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+	MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+	MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+	MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+	/* CLK_MUX_SEL9 */
+	MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+	MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+	MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+	MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+	MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+	MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+	MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+	/* CLK_MUX_SEL13 */
+	MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+	MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+	MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+	MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+	MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+	MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+	MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+	MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+	.set_ofs = 0x50,
+	.clr_ofs = 0x80,
+	.sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x54,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+	.set_ofs = 0x6c,
+	.clr_ofs = 0x9c,
+	.sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+	.set_ofs = 0xa0,
+	.clr_ofs = 0xb0,
+	.sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xb4,
+	.sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+	.set_ofs = 0x44,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x44,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top2_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2_I(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top2_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP3(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top3_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP4_I(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top4_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP5(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate top_clks[] = {
+	/* TOP0 */
+	GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+	GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
+	GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
+	GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
+	GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
+	GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
+	GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
+	GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
+	GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
+	GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
+	GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
+	GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+	GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+	GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
+	GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
+	GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+	GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
+	GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
+	GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+	GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+	GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
+	GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
+	GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
+	GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+	GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
+	GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+	GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
+	GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+	GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
+	GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
+	GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+	GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+	/* TOP2 */
+	GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
+	GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+	GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
+	GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
+	GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
+	GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
+	GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
+	GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
+	GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
+	GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
+	GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
+	GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
+	GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
+	GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
+	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
+	GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
+	GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
+	GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
+	GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
+	GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
+	GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
+	GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+	GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
+	GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
+	GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
+	GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
+	GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
+	/* TOP3 */
+	GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+	GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+	GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
+	GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
+	GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
+	GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
+	GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
+	GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
+	GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
+	GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
+	GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+	GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+	GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+	GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
+	GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
+	GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
+	/* TOP4 */
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
+	/* TOP5 */
+	GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+	GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
+	GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
+	GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+	GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+	GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
+	GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
+	GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
+	GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_DMPLL,
+	.muxes_offs = CLK_TOP_UART0_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt8516_apmixedsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_cg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8516_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt8516-apmixedsys", },
+	{ }
+};
+
+static const struct udevice_id mt8516_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt8516-topckgen", },
+	{ }
+};
+
+static const struct udevice_id mt8516_topckgen_cg_compat[] = {
+	{ .compatible = "mediatek,mt8516-topckgen-cg", },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt8516-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8516_apmixed_compat,
+	.probe = mt8516_apmixedsys_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt8516-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt8516_topckgen_compat,
+	.probe = mt8516_topckgen_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+	.name = "mt8516-topckgen-cg",
+	.id = UCLASS_CLK,
+	.of_match = mt8516_topckgen_cg_compat,
+	.probe = mt8516_topckgen_cg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mt8518.c b/roms/u-boot/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 000000000..238651483
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1559 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX		(3000UL * MHZ)
+#define MT8518_CON0_RST_BAR	BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,	\
+	    _pd_shift, _pcw_reg, _pcw_shift) {				\
+		.id = _id,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.rst_bar_mask = MT8518_CON0_RST_BAR,			\
+		.fmax = MT8518_PLL_FMAX,				\
+		.flags = _flags,					\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+	}
+
+static const struct mtk_pll_data apmixed_plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
+	    0, 21, 0x0104, 24, 0x0104, 0),
+	PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+	    HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+	PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+	    HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+	PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
+	    0, 21, 0x0164, 24, 0x0164, 0),
+	PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
+	    0, 31, 0x0180, 1, 0x0184, 0),
+	PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
+	    0, 31, 0x01A0, 1, 0x01A4, 0),
+	PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
+	    0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div)	\
+	FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+	FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
+	FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
+	FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+	FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+	FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+	FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+	FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+	FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+	FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+	FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+	FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+	FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+	FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+	FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+	FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+	FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+	FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+	FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+	FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+	FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+	FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+	FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+	FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+	FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+	FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+	FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+	FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+	FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+	FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
+	FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+	FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
+	FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+	FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
+	FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+	FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+	FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
+	FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
+	FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
+	FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+	FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+	FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
+	FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
+	FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
+	FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
+	FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
+	FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
+	FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
+	FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
+	FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
+	FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
+	FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
+	FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
+	FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
+	FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
+	FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
+	FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
+	FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
+	FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
+	FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
+	FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
+	FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24
+};
+
+static const int emi1x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_DMPLL
+};
+
+static const int emi_ddrphy_parents[] = {
+	CLK_TOP_EMI1X_SEL,
+	CLK_TOP_EMI1X_SEL
+};
+
+static const int msdc1_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MMPLL_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12
+};
+
+static const int pwm_mm_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int pmicspi_parents[] = {
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_USB20_48M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK26M_D2
+};
+
+static const int nfi2x_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_MAINPLL_D10,
+	CLK_TOP_MAINPLL_D12
+};
+
+static const int ddrphycfg_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D16
+};
+
+static const int smi_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D14
+};
+
+static const int usb_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int spinor_parents[] = {
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12
+};
+
+static const int eth_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D40,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D20
+};
+
+static const int aud1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_SRC_SEL
+};
+
+static const int aud2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_SRC_SEL
+};
+
+static const int i2c_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_USB20_48M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D8
+};
+
+static const int aud_i2s0_m_parents[] = {
+	CLK_TOP_AUD1,
+	CLK_TOP_AUD2
+};
+
+static const int aud_spdifin_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D2,
+	CLK_TOP_TVDPLL
+};
+
+static const int dbg_atclk_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D5
+};
+
+static const int png_sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int sej_13m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK26M_D2
+};
+
+static const int imgrz_sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL_D6
+};
+
+static const int graph_eclk_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_MAINPLL_D8
+};
+
+static const int fdbi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_MAINPLL_D14,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_TVDPLL_D4,
+	CLK_TOP_TVDPLL_D8,
+	CLK_TOP_TVDPLL_D16
+};
+
+static const int faudio_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_APLL1_D4,
+	CLK_TOP_APLL2_D4
+};
+
+static const int fa2sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_SRC_SEL,
+	CLK_TOP_RG_APLL1_D2,
+	CLK_TOP_RG_APLL1_D4,
+	CLK_TOP_RG_APLL1_D8,
+	CLK_TOP_RG_APLL1_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_RG_APLL1_D3
+};
+
+static const int fa1sys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_SRC_SEL,
+	CLK_TOP_RG_APLL2_D2,
+	CLK_TOP_RG_APLL2_D4,
+	CLK_TOP_RG_APLL2_D8,
+	CLK_TOP_RG_APLL2_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_RG_APLL2_D3
+};
+
+static const int fasm_m_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D7
+};
+
+static const int fecc_ck_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D3,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D3
+};
+
+static const int pe2_mac_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D10
+};
+
+static const int cmsys_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_APLL2,
+	CLK_TOP_APLL2_D2,
+	CLK_TOP_APLL2_D4,
+	CLK_TOP_APLL2_D3
+};
+
+static const int gcpu_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_MAINPLL_D5,
+	CLK_TOP_MAINPLL_D6,
+	CLK_TOP_MAINPLL_D7,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int spis_ck_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D5,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D3
+};
+
+static const int apll1_ref_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL
+};
+
+static const int int_32k_parents[] = {
+	CLK_TOP_CLK32K,
+	CLK_TOP_CLK26M_D793
+};
+
+static const int apll1_src_parents[] = {
+	CLK_TOP_APLL1,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL
+};
+
+static const int apll2_src_parents[] = {
+	CLK_TOP_APLL2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL
+};
+
+static const int faud_intbus_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_RG_APLL2_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_RG_APLL1_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D20
+};
+
+static const int axibus_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_MAINPLL_D11,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_APLL2_D8
+};
+
+static const int hapll1_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL1_SRC_SEL,
+	CLK_TOP_RG_APLL1_D2,
+	CLK_TOP_RG_APLL1_D4,
+	CLK_TOP_RG_APLL1_D8,
+	CLK_TOP_RG_APLL1_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M_D8,
+	CLK_TOP_RG_APLL1_D3
+};
+
+static const int hapll2_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_APLL2_SRC_SEL,
+	CLK_TOP_RG_APLL2_D2,
+	CLK_TOP_RG_APLL2_D4,
+	CLK_TOP_RG_APLL2_D8,
+	CLK_TOP_RG_APLL2_D16,
+	CLK_TOP_CLK26M_D2,
+	CLK_TOP_CLK26M_D4,
+	CLK_TOP_RG_APLL2_D3
+};
+
+static const int spinfi_parents[] = {
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D24,
+	CLK_TOP_UNIVPLL_D20,
+	CLK_TOP_MAINPLL_D22,
+	CLK_TOP_UNIVPLL_D16,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_UNIVPLL_D12,
+	CLK_TOP_UNIVPLL_D10,
+	CLK_TOP_MAINPLL_D11
+};
+
+static const int msdc0_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_APMIXED_MMPLL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MMPLL_D2
+};
+
+static const int msdc0_clk50_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D6
+};
+
+static const int msdc2_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_UNIVPLL_D6,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_UNIVPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D16,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MMPLL_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_MAINPLL_D12,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_APMIXED_MMPLL
+};
+
+static const int disp_dpi_ck_parents[] = {
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK26M,
+	CLK_TOP_TVDPLL_D2,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_TVDPLL_D4,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_TVDPLL_D8,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_CLK_NULL,
+	CLK_TOP_TVDPLL_D16
+};
+
+static const struct mtk_composite top_muxes[] = {
+	/* CLK_MUX_SEL0 */
+	MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+	MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
+	MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+	MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
+	MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+	MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
+	MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
+	MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
+	/* CLK_MUX_SEL1 */
+	MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
+	MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+	MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
+	MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
+	/* CLK_MUX_SEL8 */
+	MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+	MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+	MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+	MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+	MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
+	/* CLK_SEL_9 */
+	MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+	MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+	MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+	MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+	/* CLK_MUX_SEL13 */
+	MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
+	MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
+	MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
+	MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+	MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
+	MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
+	/* CLK_MUX_SEL14 */
+	MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
+	MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
+	MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
+	MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
+	MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
+	MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
+	MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
+	/* CLK_MUX_SEL15 */
+	MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
+	MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
+	MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
+	MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
+	MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
+	/* CLK_MUX_SEL16 */
+	MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
+	MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
+	/* CLK_MUX_SEL17 */
+	MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
+	MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
+	MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
+	MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
+	MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
+	/* CLK_MUX_SEL19 */
+	MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
+	MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
+	/* CLK_MUX_SEL21 */
+	MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
+	MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
+	MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
+	/* CLK_MUX_SEL22 */
+	MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
+	MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
+	MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
+	MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
+	/* CLK_MUX_SEL23 */
+	MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
+	MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
+	MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
+	MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+	.set_ofs = 0x50,
+	.clr_ofs = 0x80,
+	.sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x54,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+	.set_ofs = 0x6c,
+	.clr_ofs = 0x9c,
+	.sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+	.set_ofs = 0x44,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x44,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+	.set_ofs = 0xa0,
+	.clr_ofs = 0xb0,
+	.sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+	.set_ofs = 0x120,
+	.clr_ofs = 0x140,
+	.sta_ofs = 0xe0,
+};
+
+static const struct mtk_gate_regs top6_cg_regs = {
+	.set_ofs = 0x128,
+	.clr_ofs = 0x148,
+	.sta_ofs = 0xe8,
+};
+
+static const struct mtk_gate_regs top7_cg_regs = {
+	.set_ofs = 0x12c,
+	.clr_ofs = 0x14c,
+	.sta_ofs = 0xec,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top0_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP1(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top1_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top2_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP2_I(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top2_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP3(_id, _parent, _shift) {			\
+		.id = _id,					\
+		.parent = _parent,				\
+		.regs = &top3_cg_regs,				\
+		.shift = _shift,				\
+		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP4(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top4_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP5(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP5_I(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top5_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP6(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top6_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN,	\
+	}
+
+#define GATE_TOP7(_id, _parent, _shift) {				\
+		.id = _id,						\
+		.parent = _parent,					\
+		.regs = &top7_cg_regs,					\
+		.shift = _shift,					\
+		.flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN,	\
+	}
+
+static const struct mtk_gate top_clks[] = {
+	/* TOP0 */
+	GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+	GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
+	GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
+	GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
+	GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
+	GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
+	GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
+	GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
+	GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
+	GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
+	GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
+	GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
+	GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
+	GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
+	GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
+	GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
+	GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
+	GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+	GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+	GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
+	GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+	GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
+	GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
+	GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+	GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+	GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
+	GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+	GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
+	GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+	GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+	GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
+	GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
+	GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+	GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+	/* TOP2 */
+	GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+	GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
+	GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
+	GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
+	GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
+	GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
+	GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
+	GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
+	GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
+	GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
+	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
+	GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
+	GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
+	GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
+	GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
+	GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
+	GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+	GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
+	GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
+	GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
+	GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
+	GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
+	/* TOP3 */
+	GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+	GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+	GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+	GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+	/* TOP4 */
+	GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+	GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+	GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
+	GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
+	GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
+	GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
+	GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+	GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+	GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+	GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
+	/* TOP5 */
+	GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
+	GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
+	GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
+	GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
+	GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
+	GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
+	GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
+	GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
+	GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
+	GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
+	GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
+	GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
+	GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
+	GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
+	GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
+	GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
+	GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
+	GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
+	/* TOP6 */
+	GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
+	GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
+	GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
+	GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
+	GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
+	GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
+	GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
+	GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
+	/* TOP7 */
+	GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
+};
+
+static const struct mtk_clk_tree mt8518_clk_tree = {
+	.xtal_rate = 26 * MHZ,
+	.xtal2_rate = 26 * MHZ,
+	.fdivs_offs = CLK_TOP_DMPLL,
+	.muxes_offs = CLK_TOP_UART0_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
+static int mt8518_apmixedsys_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_probe(struct udevice *dev)
+{
+	return mtk_common_clk_init(dev, &mt8518_clk_tree);
+}
+
+static int mt8518_topckgen_cg_probe(struct udevice *dev)
+{
+	return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8518_apmixed_compat[] = {
+	{ .compatible = "mediatek,mt8518-apmixedsys", },
+	{ }
+};
+
+static const struct udevice_id mt8518_topckgen_compat[] = {
+	{ .compatible = "mediatek,mt8518-topckgen", },
+	{ }
+};
+
+static const struct udevice_id mt8518_topckgen_cg_compat[] = {
+	{ .compatible = "mediatek,mt8518-topckgen-cg", },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+	.name = "mt8518-apmixedsys",
+	.id = UCLASS_CLK,
+	.of_match = mt8518_apmixed_compat,
+	.probe = mt8518_apmixedsys_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_apmixedsys_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+	.name = "mt8518-topckgen",
+	.id = UCLASS_CLK,
+	.of_match = mt8518_topckgen_compat,
+	.probe = mt8518_topckgen_probe,
+	.priv_auto	= sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+	.name = "mt8518-topckgen-cg",
+	.id = UCLASS_CLK,
+	.of_match = mt8518_topckgen_cg_compat,
+	.probe = mt8518_topckgen_cg_probe,
+	.priv_auto	= sizeof(struct mtk_cg_priv),
+	.ops = &mtk_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mtk.c b/roms/u-boot/drivers/clk/mediatek/clk-mtk.c
new file mode 100644
index 000000000..d43b8a064
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mtk.c
@@ -0,0 +1,537 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek common clock driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include "clk-mtk.h"
+
+#define REG_CON0			0
+#define REG_CON1			4
+
+#define CON0_BASE_EN			BIT(0)
+#define CON0_PWR_ON			BIT(0)
+#define CON0_ISO_EN			BIT(1)
+#define CON1_PCW_CHG			BIT(31)
+
+#define POSTDIV_MASK			0x7
+#define INTEGER_BITS			7
+
+/* scpsys clock off control */
+#define CLK_SCP_CFG0			0x200
+#define CLK_SCP_CFG1			0x204
+#define SCP_ARMCK_OFF_EN		GENMASK(9, 0)
+#define SCP_AXICK_DCM_DIS_EN		BIT(0)
+#define SCP_AXICK_26M_SEL_EN		BIT(4)
+
+/* shared functions */
+
+/*
+ * In case the rate change propagation to parent clocks is undesirable,
+ * this function is recursively called to find the parent to calculate
+ * the accurate frequency.
+ */
+static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
+				      const struct driver *drv)
+{
+	struct clk parent = { .id = id, };
+
+	if (drv) {
+		struct udevice *dev;
+
+		if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
+			return -ENODEV;
+
+		parent.dev = dev;
+	} else {
+		parent.dev = clk->dev;
+	}
+
+	return clk_get_rate(&parent);
+}
+
+static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
+				  const struct mtk_composite *mux)
+{
+	u32 val, index = 0;
+
+	while (mux->parent[index] != parent)
+		if (++index == mux->num_parents)
+			return -EINVAL;
+
+	if (mux->flags & CLK_MUX_SETCLR_UPD) {
+		val = (mux->mux_mask << mux->mux_shift);
+		writel(val, base + mux->mux_clr_reg);
+
+		val = (index << mux->mux_shift);
+		writel(val, base + mux->mux_set_reg);
+
+		if (mux->upd_shift >= 0)
+			writel(BIT(mux->upd_shift), base + mux->upd_reg);
+	} else {
+		/* switch mux to a select parent */
+		val = readl(base + mux->mux_reg);
+		val &= ~(mux->mux_mask << mux->mux_shift);
+
+		val |= index << mux->mux_shift;
+		writel(val, base + mux->mux_reg);
+	}
+
+	return 0;
+}
+
+/* apmixedsys functions */
+
+static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
+					   u32 fin, u32 pcw, int postdiv)
+{
+	int pcwbits = pll->pcwbits;
+	int pcwfbits;
+	int ibits;
+	u64 vco;
+	u8 c = 0;
+
+	/* The fractional part of the PLL divider. */
+	ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+	pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
+
+	vco = (u64)fin * pcw;
+
+	if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
+		c = 1;
+
+	vco >>= pcwfbits;
+
+	if (c)
+		vco++;
+
+	return ((unsigned long)vco + postdiv - 1) / postdiv;
+}
+
+/**
+ * MediaTek PLLs are configured through their pcw value. The pcw value
+ * describes a divider in the PLL feedback loop which consists of 7 bits
+ * for the integer part and the remaining bits (if present) for the
+ * fractional part. Also they have a 3 bit power-of-two post divider.
+ */
+static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
+	u32 val, chg;
+
+	/* set postdiv */
+	val = readl(priv->base + pll->pd_reg);
+	val &= ~(POSTDIV_MASK << pll->pd_shift);
+	val |= (ffs(postdiv) - 1) << pll->pd_shift;
+
+	/* postdiv and pcw need to set at the same time if on same register */
+	if (pll->pd_reg != pll->pcw_reg) {
+		writel(val, priv->base + pll->pd_reg);
+		val = readl(priv->base + pll->pcw_reg);
+	}
+
+	/* set pcw */
+	val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
+	val |= pcw << pll->pcw_shift;
+
+	if (pll->pcw_chg_reg) {
+		chg = readl(priv->base + pll->pcw_chg_reg);
+		chg |= CON1_PCW_CHG;
+		writel(val, priv->base + pll->pcw_reg);
+		writel(chg, priv->base + pll->pcw_chg_reg);
+	} else {
+		val |= CON1_PCW_CHG;
+		writel(val, priv->base + pll->pcw_reg);
+	}
+
+	udelay(20);
+}
+
+/**
+ * mtk_pll_calc_values - calculate good values for a given input frequency.
+ * @clk:	The clk
+ * @pcw:	The pcw value (output)
+ * @postdiv:	The post divider (output)
+ * @freq:	The desired target frequency
+ */
+static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
+				u32 freq)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
+	unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
+	u64 _pcw;
+	int ibits;
+	u32 val;
+
+	if (freq > pll->fmax)
+		freq = pll->fmax;
+
+	for (val = 0; val < 5; val++) {
+		*postdiv = 1 << val;
+		if ((u64)freq * *postdiv >= fmin)
+			break;
+	}
+
+	/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
+	ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+	_pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
+	do_div(_pcw, priv->tree->xtal2_rate);
+
+	*pcw = (u32)_pcw;
+}
+
+static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
+{
+	u32 pcw = 0;
+	u32 postdiv;
+
+	mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
+	mtk_pll_set_rate_regs(clk, pcw, postdiv);
+
+	return 0;
+}
+
+static ulong mtk_apmixedsys_get_rate(struct clk *clk)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
+	u32 postdiv;
+	u32 pcw;
+
+	postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
+		   POSTDIV_MASK;
+	postdiv = 1 << postdiv;
+
+	pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
+	pcw &= GENMASK(pll->pcwbits - 1, 0);
+
+	return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
+				     pcw, postdiv);
+}
+
+static int mtk_apmixedsys_enable(struct clk *clk)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
+	u32 r;
+
+	r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
+	writel(r, priv->base + pll->pwr_reg);
+	udelay(1);
+
+	r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
+	writel(r, priv->base + pll->pwr_reg);
+	udelay(1);
+
+	r = readl(priv->base + pll->reg + REG_CON0);
+	r |= pll->en_mask;
+	writel(r, priv->base + pll->reg + REG_CON0);
+
+	udelay(20);
+
+	if (pll->flags & HAVE_RST_BAR) {
+		r = readl(priv->base + pll->reg + REG_CON0);
+		r |= pll->rst_bar_mask;
+		writel(r, priv->base + pll->reg + REG_CON0);
+	}
+
+	return 0;
+}
+
+static int mtk_apmixedsys_disable(struct clk *clk)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
+	u32 r;
+
+	if (pll->flags & HAVE_RST_BAR) {
+		r = readl(priv->base + pll->reg + REG_CON0);
+		r &= ~pll->rst_bar_mask;
+		writel(r, priv->base + pll->reg + REG_CON0);
+	}
+
+	r = readl(priv->base + pll->reg + REG_CON0);
+	r &= ~CON0_BASE_EN;
+	writel(r, priv->base + pll->reg + REG_CON0);
+
+	r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
+	writel(r, priv->base + pll->pwr_reg);
+
+	r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
+	writel(r, priv->base + pll->pwr_reg);
+
+	return 0;
+}
+
+/* topckgen functions */
+
+static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
+				    ulong parent_rate)
+{
+	u64 rate = parent_rate * fdiv->mult;
+
+	do_div(rate, fdiv->div);
+
+	return rate;
+}
+
+static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
+	ulong rate;
+
+	switch (fdiv->flags & CLK_PARENT_MASK) {
+	case CLK_PARENT_APMIXED:
+		rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
+				DM_DRIVER_GET(mtk_clk_apmixedsys));
+		break;
+	case CLK_PARENT_TOPCKGEN:
+		rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
+		break;
+
+	default:
+		rate = priv->tree->xtal_rate;
+	}
+
+	return mtk_factor_recalc_rate(fdiv, rate);
+}
+
+static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_composite *mux = &priv->tree->muxes[off];
+	u32 index;
+
+	index = readl(priv->base + mux->mux_reg);
+	index &= mux->mux_mask << mux->mux_shift;
+	index = index >> mux->mux_shift;
+
+	if (mux->parent[index])
+		return mtk_clk_find_parent_rate(clk, mux->parent[index],
+						NULL);
+
+	return priv->tree->xtal_rate;
+}
+
+static ulong mtk_topckgen_get_rate(struct clk *clk)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (clk->id < priv->tree->fdivs_offs)
+		return priv->tree->fclks[clk->id].rate;
+	else if (clk->id < priv->tree->muxes_offs)
+		return mtk_topckgen_get_factor_rate(clk, clk->id -
+						    priv->tree->fdivs_offs);
+	else
+		return mtk_topckgen_get_mux_rate(clk, clk->id -
+						 priv->tree->muxes_offs);
+}
+
+static int mtk_topckgen_enable(struct clk *clk)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_composite *mux;
+	u32 val;
+
+	if (clk->id < priv->tree->muxes_offs)
+		return 0;
+
+	mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
+	if (mux->gate_shift < 0)
+		return 0;
+
+	/* enable clock gate */
+	if (mux->flags & CLK_MUX_SETCLR_UPD) {
+		val = BIT(mux->gate_shift);
+		writel(val, priv->base + mux->mux_clr_reg);
+	} else {
+		val = readl(priv->base + mux->gate_reg);
+		val &= ~BIT(mux->gate_shift);
+		writel(val, priv->base + mux->gate_reg);
+	}
+
+	if (mux->flags & CLK_DOMAIN_SCPSYS) {
+		/* enable scpsys clock off control */
+		writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
+		writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
+		       priv->base + CLK_SCP_CFG1);
+	}
+
+	return 0;
+}
+
+static int mtk_topckgen_disable(struct clk *clk)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_composite *mux;
+	u32 val;
+
+	if (clk->id < priv->tree->muxes_offs)
+		return 0;
+
+	mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
+	if (mux->gate_shift < 0)
+		return 0;
+
+	/* disable clock gate */
+	if (mux->flags & CLK_MUX_SETCLR_UPD) {
+		val = BIT(mux->gate_shift);
+		writel(val, priv->base + mux->mux_set_reg);
+	} else {
+		val = readl(priv->base + mux->gate_reg);
+		val |= BIT(mux->gate_shift);
+		writel(val, priv->base + mux->gate_reg);
+	}
+
+	return 0;
+}
+
+static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (clk->id < priv->tree->muxes_offs)
+		return 0;
+
+	return mtk_clk_mux_set_parent(priv->base, parent->id,
+			&priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
+}
+
+/* CG functions */
+
+static int mtk_clk_gate_enable(struct clk *clk)
+{
+	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_gate *gate = &priv->gates[clk->id];
+	u32 bit = BIT(gate->shift);
+
+	switch (gate->flags & CLK_GATE_MASK) {
+	case CLK_GATE_SETCLR:
+		writel(bit, priv->base + gate->regs->clr_ofs);
+		break;
+	case CLK_GATE_SETCLR_INV:
+		writel(bit, priv->base + gate->regs->set_ofs);
+		break;
+	case CLK_GATE_NO_SETCLR:
+		clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
+		break;
+	case CLK_GATE_NO_SETCLR_INV:
+		clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mtk_clk_gate_disable(struct clk *clk)
+{
+	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_gate *gate = &priv->gates[clk->id];
+	u32 bit = BIT(gate->shift);
+
+	switch (gate->flags & CLK_GATE_MASK) {
+	case CLK_GATE_SETCLR:
+		writel(bit, priv->base + gate->regs->set_ofs);
+		break;
+	case CLK_GATE_SETCLR_INV:
+		writel(bit, priv->base + gate->regs->clr_ofs);
+		break;
+	case CLK_GATE_NO_SETCLR:
+		clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
+		break;
+	case CLK_GATE_NO_SETCLR_INV:
+		clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static ulong mtk_clk_gate_get_rate(struct clk *clk)
+{
+	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
+	const struct mtk_gate *gate = &priv->gates[clk->id];
+
+	switch (gate->flags & CLK_PARENT_MASK) {
+	case CLK_PARENT_APMIXED:
+		return mtk_clk_find_parent_rate(clk, gate->parent,
+				DM_DRIVER_GET(mtk_clk_apmixedsys));
+		break;
+	case CLK_PARENT_TOPCKGEN:
+		return mtk_clk_find_parent_rate(clk, gate->parent,
+				DM_DRIVER_GET(mtk_clk_topckgen));
+		break;
+
+	default:
+		return priv->tree->xtal_rate;
+	}
+}
+
+const struct clk_ops mtk_clk_apmixedsys_ops = {
+	.enable = mtk_apmixedsys_enable,
+	.disable = mtk_apmixedsys_disable,
+	.set_rate = mtk_apmixedsys_set_rate,
+	.get_rate = mtk_apmixedsys_get_rate,
+};
+
+const struct clk_ops mtk_clk_topckgen_ops = {
+	.enable = mtk_topckgen_enable,
+	.disable = mtk_topckgen_disable,
+	.get_rate = mtk_topckgen_get_rate,
+	.set_parent = mtk_topckgen_set_parent,
+};
+
+const struct clk_ops mtk_clk_gate_ops = {
+	.enable = mtk_clk_gate_enable,
+	.disable = mtk_clk_gate_disable,
+	.get_rate = mtk_clk_gate_get_rate,
+};
+
+int mtk_common_clk_init(struct udevice *dev,
+			const struct mtk_clk_tree *tree)
+{
+	struct mtk_clk_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	priv->tree = tree;
+
+	return 0;
+}
+
+int mtk_common_clk_gate_init(struct udevice *dev,
+			     const struct mtk_clk_tree *tree,
+			     const struct mtk_gate *gates)
+{
+	struct mtk_cg_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	priv->tree = tree;
+	priv->gates = gates;
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/clk/mediatek/clk-mtk.h b/roms/u-boot/drivers/clk/mediatek/clk-mtk.h
new file mode 100644
index 000000000..95a23d14a
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mediatek/clk-mtk.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#ifndef __DRV_CLK_MTK_H
+#define __DRV_CLK_MTK_H
+
+#include <linux/bitops.h>
+#define CLK_XTAL			0
+#define MHZ				(1000 * 1000)
+
+#define HAVE_RST_BAR			BIT(0)
+#define CLK_DOMAIN_SCPSYS		BIT(0)
+#define CLK_MUX_SETCLR_UPD		BIT(1)
+
+#define CLK_GATE_SETCLR			BIT(0)
+#define CLK_GATE_SETCLR_INV		BIT(1)
+#define CLK_GATE_NO_SETCLR		BIT(2)
+#define CLK_GATE_NO_SETCLR_INV		BIT(3)
+#define CLK_GATE_MASK			GENMASK(3, 0)
+
+#define CLK_PARENT_APMIXED		BIT(4)
+#define CLK_PARENT_TOPCKGEN		BIT(5)
+#define CLK_PARENT_MASK			GENMASK(5, 4)
+
+#define ETHSYS_HIFSYS_RST_CTRL_OFS	0x34
+
+/* struct mtk_pll_data - hardware-specific PLLs data */
+struct mtk_pll_data {
+	const int id;
+	u32 reg;
+	u32 pwr_reg;
+	u32 en_mask;
+	u32 pd_reg;
+	int pd_shift;
+	u32 flags;
+	u32 rst_bar_mask;
+	u64 fmax;
+	u64 fmin;
+	int pcwbits;
+	int pcwibits;
+	u32 pcw_reg;
+	int pcw_shift;
+	u32 pcw_chg_reg;
+};
+
+/**
+ * struct mtk_fixed_clk - fixed clocks
+ *
+ * @id:		index of clocks
+ * @parent:	index of parnet clocks
+ * @rate:	fixed rate
+ */
+struct mtk_fixed_clk {
+	const int id;
+	const int parent;
+	unsigned long rate;
+};
+
+#define FIXED_CLK(_id, _parent, _rate) {		\
+		.id = _id,				\
+		.parent = _parent,			\
+		.rate = _rate,				\
+	}
+
+/**
+ * struct mtk_fixed_factor - fixed multiplier and divider clocks
+ *
+ * @id:		index of clocks
+ * @parent:	index of parnet clocks
+ * @mult:	multiplier
+ * @div:	divider
+ * @flag:	hardware-specific flags
+ */
+struct mtk_fixed_factor {
+	const int id;
+	const int parent;
+	u32 mult;
+	u32 div;
+	u32 flags;
+};
+
+#define FACTOR(_id, _parent, _mult, _div, _flags) {	\
+		.id = _id,				\
+		.parent = _parent,			\
+		.mult = _mult,				\
+		.div = _div,				\
+		.flags = _flags,			\
+	}
+
+/**
+ * struct mtk_composite - aggregate clock of mux, divider and gate clocks
+ *
+ * @id:			index of clocks
+ * @parent:		index of parnet clocks
+ * @mux_reg:		hardware-specific mux register
+ * @gate_reg:		hardware-specific gate register
+ * @mux_mask:		mask to the mux bit field
+ * @mux_shift:		shift to the mux bit field
+ * @gate_shift:		shift to the gate bit field
+ * @num_parents:	number of parent clocks
+ * @flags:		hardware-specific flags
+ */
+struct mtk_composite {
+	const int id;
+	const int *parent;
+	u32 mux_reg;
+	u32 mux_set_reg;
+	u32 mux_clr_reg;
+	u32 upd_reg;
+	u32 gate_reg;
+	u32 mux_mask;
+	signed char mux_shift;
+	signed char upd_shift;
+	signed char gate_shift;
+	signed char num_parents;
+	u16 flags;
+};
+
+#define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate,	\
+		       _flags) {					\
+		.id = _id,						\
+		.mux_reg = _reg,					\
+		.mux_shift = _shift,					\
+		.mux_mask = BIT(_width) - 1,				\
+		.gate_reg = _reg,					\
+		.gate_shift = _gate,					\
+		.parent = _parents,					\
+		.num_parents = ARRAY_SIZE(_parents),			\
+		.flags = _flags,					\
+	}
+
+#define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate)		\
+	MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
+
+#define MUX(_id, _parents, _reg, _shift, _width) {			\
+		.id = _id,						\
+		.mux_reg = _reg,					\
+		.mux_shift = _shift,					\
+		.mux_mask = BIT(_width) - 1,				\
+		.gate_shift = -1,					\
+		.parent = _parents,					\
+		.num_parents = ARRAY_SIZE(_parents),			\
+		.flags = 0,						\
+	}
+
+#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
+			_mux_clr_ofs, _shift, _width, _gate,		\
+			_upd_ofs, _upd, _flags) {			\
+		.id = _id,						\
+		.mux_reg = _mux_ofs,					\
+		.mux_set_reg = _mux_set_ofs,			\
+		.mux_clr_reg = _mux_clr_ofs,			\
+		.upd_reg = _upd_ofs,					\
+		.upd_shift = _upd,					\
+		.mux_shift = _shift,					\
+		.mux_mask = BIT(_width) - 1,				\
+		.gate_reg = _mux_ofs,					\
+		.gate_shift = _gate,					\
+		.parent = _parents,					\
+		.num_parents = ARRAY_SIZE(_parents),			\
+		.flags = _flags,					\
+	}
+
+struct mtk_gate_regs {
+	u32 sta_ofs;
+	u32 clr_ofs;
+	u32 set_ofs;
+};
+
+/**
+ * struct mtk_gate - gate clocks
+ *
+ * @id:		index of gate clocks
+ * @parent:	index of parnet clocks
+ * @regs:	hardware-specific mux register
+ * @shift:	shift to the gate bit field
+ * @flags:	hardware-specific flags
+ */
+struct mtk_gate {
+	const int id;
+	const int parent;
+	const struct mtk_gate_regs *regs;
+	int shift;
+	u32 flags;
+};
+
+/* struct mtk_clk_tree - clock tree */
+struct mtk_clk_tree {
+	unsigned long xtal_rate;
+	unsigned long xtal2_rate;
+	const int fdivs_offs;
+	const int muxes_offs;
+	const struct mtk_pll_data *plls;
+	const struct mtk_fixed_clk *fclks;
+	const struct mtk_fixed_factor *fdivs;
+	const struct mtk_composite *muxes;
+};
+
+struct mtk_clk_priv {
+	void __iomem *base;
+	const struct mtk_clk_tree *tree;
+};
+
+struct mtk_cg_priv {
+	void __iomem *base;
+	const struct mtk_clk_tree *tree;
+	const struct mtk_gate *gates;
+};
+
+extern const struct clk_ops mtk_clk_apmixedsys_ops;
+extern const struct clk_ops mtk_clk_topckgen_ops;
+extern const struct clk_ops mtk_clk_gate_ops;
+
+int mtk_common_clk_init(struct udevice *dev,
+			const struct mtk_clk_tree *tree);
+int mtk_common_clk_gate_init(struct udevice *dev,
+			     const struct mtk_clk_tree *tree,
+			     const struct mtk_gate *gates);
+
+#endif /* __DRV_CLK_MTK_H */