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authorAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
committerAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
commitaf1a266670d040d2f4083ff309d732d648afba2a (patch)
tree2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/drivers/clk/mtmips
parente02cda008591317b1625707ff8e115a4841aa889 (diff)
Add submodule dependency filesHEADmaster
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/drivers/clk/mtmips')
-rw-r--r--roms/u-boot/drivers/clk/mtmips/Makefile4
-rw-r--r--roms/u-boot/drivers/clk/mtmips/clk-mt7620.c159
-rw-r--r--roms/u-boot/drivers/clk/mtmips/clk-mt7628.c158
3 files changed, 321 insertions, 0 deletions
diff --git a/roms/u-boot/drivers/clk/mtmips/Makefile b/roms/u-boot/drivers/clk/mtmips/Makefile
new file mode 100644
index 000000000..732e7f254
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mtmips/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
+obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/roms/u-boot/drivers/clk/mtmips/clk-mt7620.c b/roms/u-boot/drivers/clk/mtmips/clk-mt7620.c
new file mode 100644
index 000000000..57d2e2f04
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mtmips/clk-mt7620.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/clock/mt7620-clk.h>
+#include <misc.h>
+#include <mach/mt7620-sysc.h>
+
+/* CLKCFG1 */
+#define CLKCFG1_REG 0x30
+
+#define CLK_SRC_CPU -1
+#define CLK_SRC_CPU_D2 -2
+#define CLK_SRC_SYS -3
+#define CLK_SRC_XTAL -4
+#define CLK_SRC_PERI -5
+
+struct mt7620_clk_priv {
+ struct udevice *dev;
+ struct udevice *sysc;
+ struct mt7620_sysc_clks clks;
+};
+
+static const int mt7620_clks[] = {
+ [CLK_SYS] = CLK_SRC_SYS,
+ [CLK_CPU] = CLK_SRC_CPU,
+ [CLK_XTAL] = CLK_SRC_XTAL,
+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
+ [CLK_UARTF] = CLK_SRC_PERI,
+ [CLK_UARTL] = CLK_SRC_PERI,
+ [CLK_SPI] = CLK_SRC_SYS,
+ [CLK_I2C] = CLK_SRC_PERI,
+ [CLK_I2S] = CLK_SRC_PERI,
+};
+
+static ulong mt7620_clk_get_rate(struct clk *clk)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id >= ARRAY_SIZE(mt7620_clks))
+ return 0;
+
+ switch (mt7620_clks[clk->id]) {
+ case CLK_SRC_CPU:
+ return priv->clks.cpu_clk;
+ case CLK_SRC_CPU_D2:
+ return priv->clks.cpu_clk / 2;
+ case CLK_SRC_SYS:
+ return priv->clks.sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->clks.xtal_clk;
+ case CLK_SRC_PERI:
+ return priv->clks.peri_clk;
+ default:
+ return mt7620_clks[clk->id];
+ }
+}
+
+static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set)
+{
+ u32 val;
+ int ret;
+
+ ret = misc_read(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
+ if (ret) {
+ dev_err(priv->dev, "mt7620_clk: failed to read CLKCFG1\n");
+ return ret;
+ }
+
+ val &= ~clr;
+ val |= set;
+
+ ret = misc_write(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
+ if (ret) {
+ dev_err(priv->dev, "mt7620_clk: failed to write CLKCFG1\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt7620_clk_enable(struct clk *clk)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 30)
+ return -1;
+
+ return mt7620_clkcfg1_rmw(priv, 0, BIT(clk->id));
+}
+
+static int mt7620_clk_disable(struct clk *clk)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 30)
+ return -1;
+
+ return mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0);
+}
+
+const struct clk_ops mt7620_clk_ops = {
+ .enable = mt7620_clk_enable,
+ .disable = mt7620_clk_disable,
+ .get_rate = mt7620_clk_get_rate,
+};
+
+static int mt7620_clk_probe(struct udevice *dev)
+{
+ struct mt7620_clk_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args sysc_args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "mediatek,sysc", NULL,
+ 0, 0, &sysc_args);
+ if (ret) {
+ dev_err(dev, "mt7620_clk: sysc property not found\n");
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,
+ &priv->sysc);
+ if (ret) {
+ dev_err(dev, "mt7620_clk: failed to sysc device\n");
+ return ret;
+ }
+
+ ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CLK,
+ &priv->clks);
+ if (ret) {
+ dev_err(dev, "mt7620_clk: failed to get base clocks\n");
+ return ret;
+ }
+
+ priv->dev = dev;
+
+ return 0;
+}
+
+static const struct udevice_id mt7620_clk_ids[] = {
+ { .compatible = "mediatek,mt7620-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(mt7620_clk) = {
+ .name = "mt7620-clk",
+ .id = UCLASS_CLK,
+ .of_match = mt7620_clk_ids,
+ .probe = mt7620_clk_probe,
+ .priv_auto = sizeof(struct mt7620_clk_priv),
+ .ops = &mt7620_clk_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/clk/mtmips/clk-mt7628.c b/roms/u-boot/drivers/clk/mtmips/clk-mt7628.c
new file mode 100644
index 000000000..4d3ac847d
--- /dev/null
+++ b/roms/u-boot/drivers/clk/mtmips/clk-mt7628.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/mt7628-clk.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+/* SYSCFG0 */
+#define XTAL_40M_SEL BIT(6)
+
+/* CLKCFG0 */
+#define CLKCFG0_REG 0x0
+#define PERI_CLK_FROM_XTAL_SEL BIT(4)
+#define CPU_PLL_FROM_BBP BIT(1)
+#define CPU_PLL_FROM_XTAL BIT(0)
+
+/* CLKCFG1 */
+#define CLKCFG1_REG 0x4
+
+#define CLK_SRC_CPU -1
+#define CLK_SRC_CPU_D2 -2
+#define CLK_SRC_SYS -3
+#define CLK_SRC_XTAL -4
+#define CLK_SRC_PERI -5
+
+struct mt7628_clk_priv {
+ void __iomem *base;
+ int cpu_clk;
+ int sys_clk;
+ int xtal_clk;
+};
+
+static const int mt7628_clks[] = {
+ [CLK_SYS] = CLK_SRC_SYS,
+ [CLK_CPU] = CLK_SRC_CPU,
+ [CLK_XTAL] = CLK_SRC_XTAL,
+ [CLK_PWM] = CLK_SRC_PERI,
+ [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
+ [CLK_UART2] = CLK_SRC_PERI,
+ [CLK_UART1] = CLK_SRC_PERI,
+ [CLK_UART0] = CLK_SRC_PERI,
+ [CLK_SPI] = CLK_SRC_SYS,
+ [CLK_I2C] = CLK_SRC_PERI,
+};
+
+static ulong mt7628_clk_get_rate(struct clk *clk)
+{
+ struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ if (clk->id >= ARRAY_SIZE(mt7628_clks))
+ return 0;
+
+ switch (mt7628_clks[clk->id]) {
+ case CLK_SRC_CPU:
+ return priv->cpu_clk;
+ case CLK_SRC_CPU_D2:
+ return priv->cpu_clk / 2;
+ case CLK_SRC_SYS:
+ return priv->sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->xtal_clk;
+ case CLK_SRC_PERI:
+ val = readl(priv->base + CLKCFG0_REG);
+ if (val & PERI_CLK_FROM_XTAL_SEL)
+ return priv->xtal_clk;
+ else
+ return 40000000;
+ default:
+ return mt7628_clks[clk->id];
+ }
+}
+
+static int mt7628_clk_enable(struct clk *clk)
+{
+ struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 31)
+ return -1;
+
+ setbits_32(priv->base + CLKCFG1_REG, BIT(clk->id));
+
+ return 0;
+}
+
+static int mt7628_clk_disable(struct clk *clk)
+{
+ struct mt7628_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id > 31)
+ return -1;
+
+ clrbits_32(priv->base + CLKCFG1_REG, BIT(clk->id));
+
+ return 0;
+}
+
+const struct clk_ops mt7628_clk_ops = {
+ .enable = mt7628_clk_enable,
+ .disable = mt7628_clk_disable,
+ .get_rate = mt7628_clk_get_rate,
+};
+
+static int mt7628_clk_probe(struct udevice *dev)
+{
+ struct mt7628_clk_priv *priv = dev_get_priv(dev);
+ void __iomem *syscfg_base;
+ u32 val;
+
+ priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
+ if (!priv->base)
+ return -EINVAL;
+
+ syscfg_base = (void __iomem *)dev_remap_addr_index(dev, 1);
+ if (!syscfg_base)
+ return -EINVAL;
+
+ val = readl(syscfg_base);
+ if (val & XTAL_40M_SEL)
+ priv->xtal_clk = 40000000;
+ else
+ priv->xtal_clk = 25000000;
+
+ val = readl(priv->base + CLKCFG0_REG);
+ if (val & CPU_PLL_FROM_BBP)
+ priv->cpu_clk = 480000000;
+ else if (val & CPU_PLL_FROM_XTAL)
+ priv->cpu_clk = priv->xtal_clk;
+ else if (priv->xtal_clk == 40000000)
+ priv->cpu_clk = 580000000; /* (xtal_freq / 2) * 29 */
+ else
+ priv->cpu_clk = 575000000; /* xtal_freq * 23 */
+
+ priv->sys_clk = priv->cpu_clk / 3;
+
+ return 0;
+}
+
+static const struct udevice_id mt7628_clk_ids[] = {
+ { .compatible = "mediatek,mt7628-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(mt7628_clk) = {
+ .name = "mt7628-clk",
+ .id = UCLASS_CLK,
+ .of_match = mt7628_clk_ids,
+ .probe = mt7628_clk_probe,
+ .priv_auto = sizeof(struct mt7628_clk_priv),
+ .ops = &mt7628_clk_ops,
+};