Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

16 files changed, 1400 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/clk/sunxi/Kconfig b/roms/u-boot/drivers/clk/sunxi/Kconfig
new file mode 100644
index 000000000..bf084fa7a
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/Kconfig
@@ -0,0 +1,96 @@
+config CLK_SUNXI
+	bool "Clock support for Allwinner SoCs"
+	depends on CLK && ARCH_SUNXI
+	select DM_RESET
+	default y
+	help
+	  This enables support for common clock driver API on Allwinner
+	  SoCs.
+
+if CLK_SUNXI
+
+config CLK_SUN4I_A10
+	bool "Clock driver for Allwinner A10/A20"
+	default MACH_SUN4I || MACH_SUN7I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A10/A20 SoC.
+
+config CLK_SUN5I_A10S
+	bool "Clock driver for Allwinner A10s/A13"
+	default MACH_SUN5I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A10s/A13 SoC.
+
+config CLK_SUN6I_A31
+	bool "Clock driver for Allwinner A31/A31s"
+	default MACH_SUN6I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A31/A31s SoC.
+
+config CLK_SUN8I_A23
+	bool "Clock driver for Allwinner A23/A33"
+	default MACH_SUN8I_A23 || MACH_SUN8I_A33
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A23/A33 SoC.
+
+config CLK_SUN8I_A83T
+	bool "Clock driver for Allwinner A83T"
+	default MACH_SUN8I_A83T
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A83T SoC.
+
+config CLK_SUN8I_R40
+	bool "Clock driver for Allwinner R40"
+	default MACH_SUN8I_R40
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner R40 SoC.
+
+config CLK_SUN8I_V3S
+	bool "Clock driver for Allwinner V3S"
+	default MACH_SUN8I_V3S
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner V3S SoC.
+
+config CLK_SUN9I_A80
+	bool "Clock driver for Allwinner A80"
+	default MACH_SUN9I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A80 SoC.
+
+config CLK_SUN8I_H3
+	bool "Clock driver for Allwinner H3/H5"
+	default MACH_SUNXI_H3_H5
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H3/H5 SoC.
+
+config CLK_SUN50I_H6
+	bool "Clock driver for Allwinner H6"
+	default MACH_SUN50I_H6
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H6 SoC.
+
+config CLK_SUN50I_H616
+	bool "Clock driver for Allwinner H616"
+	default MACH_SUN50I_H616
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner H616 SoC.
+
+config CLK_SUN50I_A64
+	bool "Clock driver for Allwinner A64"
+	default MACH_SUN50I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A64 SoC.
+
+endif # CLK_SUNXI
diff --git a/roms/u-boot/drivers/clk/sunxi/Makefile b/roms/u-boot/drivers/clk/sunxi/Makefile
new file mode 100644
index 000000000..4f9282a8b
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/Makefile
@@ -0,0 +1,22 @@
+#
+# Copyright (C) 2018 Amarula Solutions.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
+
+obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
+
+obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
+obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
+obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
+obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
+obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
+obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
+obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
+obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
+obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
+obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a10.c b/roms/u-boot/drivers/clk/sunxi/clk_a10.c
new file mode 100644
index 000000000..1b5de86e2
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a10.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+#include <dt-bindings/reset/sun4i-a10-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a10_gates[] = {
+	[CLK_AHB_OTG]		= GATE(0x060, BIT(0)),
+	[CLK_AHB_EHCI0]		= GATE(0x060, BIT(1)),
+	[CLK_AHB_OHCI0]		= GATE(0x060, BIT(2)),
+	[CLK_AHB_EHCI1]		= GATE(0x060, BIT(3)),
+	[CLK_AHB_OHCI1]		= GATE(0x060, BIT(4)),
+	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
+	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
+	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_AHB_SPI2]		= GATE(0x060, BIT(22)),
+	[CLK_AHB_SPI3]		= GATE(0x060, BIT(23)),
+
+	[CLK_AHB_GMAC]		= GATE(0x064, BIT(17)),
+
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB1_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB1_UART5]	= GATE(0x06c, BIT(21)),
+	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
+	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(6)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(7)),
+	[CLK_USB_PHY]		= GATE(0x0cc, BIT(8)),
+
+	[CLK_SPI3]		= GATE(0x0d4, BIT(31)),
+};
+
+static struct ccu_reset a10_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
+};
+
+static const struct ccu_desc a10_ccu_desc = {
+	.gates = a10_gates,
+	.resets = a10_resets,
+};
+
+static int a10_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
+}
+
+static const struct udevice_id a10_ccu_ids[] = {
+	{ .compatible = "allwinner,sun4i-a10-ccu",
+	  .data = (ulong)&a10_ccu_desc },
+	{ .compatible = "allwinner,sun7i-a20-ccu",
+	  .data = (ulong)&a10_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun4i_a10) = {
+	.name		= "sun4i_a10_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a10_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a10_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a10s.c b/roms/u-boot/drivers/clk/sunxi/clk_a10s.c
new file mode 100644
index 000000000..184f61ab2
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a10s.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun5i-ccu.h>
+#include <dt-bindings/reset/sun5i-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a10s_gates[] = {
+	[CLK_AHB_OTG]		= GATE(0x060, BIT(0)),
+	[CLK_AHB_EHCI]		= GATE(0x060, BIT(1)),
+	[CLK_AHB_OHCI]		= GATE(0x060, BIT(2)),
+	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
+	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_AHB_SPI2]		= GATE(0x060, BIT(22)),
+
+	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+
+	[CLK_USB_OHCI]		= GATE(0x0cc, BIT(6)),
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+};
+
+static struct ccu_reset a10s_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+};
+
+static const struct ccu_desc a10s_ccu_desc = {
+	.gates = a10s_gates,
+	.resets = a10s_resets,
+};
+
+static int a10s_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a10s_resets));
+}
+
+static const struct udevice_id a10s_ccu_ids[] = {
+	{ .compatible = "allwinner,sun5i-a10s-ccu",
+	  .data = (ulong)&a10s_ccu_desc },
+	{ .compatible = "allwinner,sun5i-a13-ccu",
+	  .data = (ulong)&a10s_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun5i_a10s) = {
+	.name		= "sun5i_a10s_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a10s_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a10s_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a23.c b/roms/u-boot/drivers/clk/sunxi/clk_a23.c
new file mode 100644
index 000000000..5750514a7
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a23.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
+#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a23_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
+	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
+	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
+
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
+	[CLK_USB_OHCI]		= GATE(0x0cc, BIT(16)),
+};
+
+static struct ccu_reset a23_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
+
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
+	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
+};
+
+static const struct ccu_desc a23_ccu_desc = {
+	.gates = a23_gates,
+	.resets = a23_resets,
+};
+
+static int a23_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
+}
+
+static const struct udevice_id a23_clk_ids[] = {
+	{ .compatible = "allwinner,sun8i-a23-ccu",
+	  .data = (ulong)&a23_ccu_desc },
+	{ .compatible = "allwinner,sun8i-a33-ccu",
+	  .data = (ulong)&a23_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_a23) = {
+	.name		= "sun8i_a23_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a23_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a23_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a31.c b/roms/u-boot/drivers/clk/sunxi/clk_a31.c
new file mode 100644
index 000000000..9226112f4
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a31.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun6i-a31-ccu.h>
+#include <dt-bindings/reset/sun6i-a31-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a31_gates[] = {
+	[CLK_AHB1_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_AHB1_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_AHB1_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_AHB1_MMC3]		= GATE(0x060, BIT(11)),
+	[CLK_AHB1_EMAC]		= GATE(0x060, BIT(17)),
+	[CLK_AHB1_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_AHB1_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_AHB1_SPI2]		= GATE(0x060, BIT(22)),
+	[CLK_AHB1_SPI3]		= GATE(0x060, BIT(23)),
+	[CLK_AHB1_OTG]		= GATE(0x060, BIT(24)),
+	[CLK_AHB1_EHCI0]	= GATE(0x060, BIT(26)),
+	[CLK_AHB1_EHCI1]	= GATE(0x060, BIT(27)),
+	[CLK_AHB1_OHCI0]	= GATE(0x060, BIT(29)),
+	[CLK_AHB1_OHCI1]	= GATE(0x060, BIT(30)),
+	[CLK_AHB1_OHCI2]	= GATE(0x060, BIT(31)),
+
+	[CLK_APB2_UART0]	= GATE(0x06c, BIT(16)),
+	[CLK_APB2_UART1]	= GATE(0x06c, BIT(17)),
+	[CLK_APB2_UART2]	= GATE(0x06c, BIT(18)),
+	[CLK_APB2_UART3]	= GATE(0x06c, BIT(19)),
+	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
+	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+	[CLK_SPI3]		= GATE(0x0ac, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+};
+
+static struct ccu_reset a31_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
+
+	[RST_AHB1_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_AHB1_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_AHB1_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_AHB1_MMC3]		= RESET(0x2c0, BIT(11)),
+	[RST_AHB1_EMAC]		= RESET(0x2c0, BIT(17)),
+	[RST_AHB1_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_AHB1_SPI1]		= RESET(0x2c0, BIT(21)),
+	[RST_AHB1_SPI2]		= RESET(0x2c0, BIT(22)),
+	[RST_AHB1_SPI3]		= RESET(0x2c0, BIT(23)),
+	[RST_AHB1_OTG]		= RESET(0x2c0, BIT(24)),
+	[RST_AHB1_EHCI0]	= RESET(0x2c0, BIT(26)),
+	[RST_AHB1_EHCI1]	= RESET(0x2c0, BIT(27)),
+	[RST_AHB1_OHCI0]	= RESET(0x2c0, BIT(29)),
+	[RST_AHB1_OHCI1]	= RESET(0x2c0, BIT(30)),
+	[RST_AHB1_OHCI2]	= RESET(0x2c0, BIT(31)),
+
+	[RST_APB2_UART0]	= RESET(0x2d8, BIT(16)),
+	[RST_APB2_UART1]	= RESET(0x2d8, BIT(17)),
+	[RST_APB2_UART2]	= RESET(0x2d8, BIT(18)),
+	[RST_APB2_UART3]	= RESET(0x2d8, BIT(19)),
+	[RST_APB2_UART4]	= RESET(0x2d8, BIT(20)),
+	[RST_APB2_UART5]	= RESET(0x2d8, BIT(21)),
+};
+
+static const struct ccu_desc a31_ccu_desc = {
+	.gates = a31_gates,
+	.resets = a31_resets,
+};
+
+static int a31_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
+}
+
+static const struct udevice_id a31_clk_ids[] = {
+	{ .compatible = "allwinner,sun6i-a31-ccu",
+	  .data = (ulong)&a31_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31) = {
+	.name		= "sun6i_a31_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a31_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a31_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a64.c b/roms/u-boot/drivers/clk/sunxi/clk_a64.c
new file mode 100644
index 000000000..0553ffa43
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a64.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <linux/bitops.h>
+
+static const struct ccu_clk_gate a64_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
+	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
+	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
+	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
+	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
+
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+};
+
+static const struct ccu_reset a64_resets[] = {
+	[RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
+	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
+
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+	[RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
+	[RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
+	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
+	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
+};
+
+static const struct ccu_desc a64_ccu_desc = {
+	.gates = a64_gates,
+	.resets = a64_resets,
+};
+
+static int a64_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
+}
+
+static const struct udevice_id a64_ccu_ids[] = {
+	{ .compatible = "allwinner,sun50i-a64-ccu",
+	  .data = (ulong)&a64_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun50i_a64) = {
+	.name		= "sun50i_a64_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a64_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a64_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a80.c b/roms/u-boot/drivers/clk/sunxi/clk_a80.c
new file mode 100644
index 000000000..68973d528
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a80.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun9i-a80-ccu.h>
+#include <dt-bindings/reset/sun9i-a80-ccu.h>
+#include <linux/bitops.h>
+
+static const struct ccu_clk_gate a80_gates[] = {
+	[CLK_SPI0]		= GATE(0x430, BIT(31)),
+	[CLK_SPI1]		= GATE(0x434, BIT(31)),
+	[CLK_SPI2]		= GATE(0x438, BIT(31)),
+	[CLK_SPI3]		= GATE(0x43c, BIT(31)),
+
+	[CLK_BUS_MMC]		= GATE(0x580, BIT(8)),
+	[CLK_BUS_SPI0]		= GATE(0x580, BIT(20)),
+	[CLK_BUS_SPI1]		= GATE(0x580, BIT(21)),
+	[CLK_BUS_SPI2]		= GATE(0x580, BIT(22)),
+	[CLK_BUS_SPI3]		= GATE(0x580, BIT(23)),
+
+	[CLK_BUS_UART0]		= GATE(0x594, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x594, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x594, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x594, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x594, BIT(20)),
+	[CLK_BUS_UART5]		= GATE(0x594, BIT(21)),
+};
+
+static const struct ccu_reset a80_resets[] = {
+	[RST_BUS_MMC]		= RESET(0x5a0, BIT(8)),
+	[RST_BUS_SPI0]		= RESET(0x5a0, BIT(20)),
+	[RST_BUS_SPI1]		= RESET(0x5a0, BIT(21)),
+	[RST_BUS_SPI2]		= RESET(0x5a0, BIT(22)),
+	[RST_BUS_SPI3]		= RESET(0x5a0, BIT(23)),
+
+	[RST_BUS_UART0]		= RESET(0x5b4, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x5b4, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x5b4, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x5b4, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x5b4, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x5b4, BIT(21)),
+};
+
+static const struct ccu_clk_gate a80_mmc_gates[] = {
+	[0]			= GATE(0x0, BIT(16)),
+	[1]			= GATE(0x4, BIT(16)),
+	[2]			= GATE(0x8, BIT(16)),
+	[3]			= GATE(0xc, BIT(16)),
+};
+
+static const struct ccu_reset a80_mmc_resets[] = {
+	[0]			= GATE(0x0, BIT(18)),
+	[1]			= GATE(0x4, BIT(18)),
+	[2]			= GATE(0x8, BIT(18)),
+	[3]			= GATE(0xc, BIT(18)),
+};
+
+static const struct ccu_desc a80_ccu_desc = {
+	.gates = a80_gates,
+	.resets = a80_resets,
+};
+
+static const struct ccu_desc a80_mmc_clk_desc = {
+	.gates = a80_mmc_gates,
+	.resets = a80_mmc_resets,
+};
+
+static int a80_clk_bind(struct udevice *dev)
+{
+	ulong count = ARRAY_SIZE(a80_resets);
+
+	if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
+		count = ARRAY_SIZE(a80_mmc_resets);
+
+	return sunxi_reset_bind(dev, count);
+}
+
+static const struct udevice_id a80_ccu_ids[] = {
+	{ .compatible = "allwinner,sun9i-a80-ccu",
+	  .data = (ulong)&a80_ccu_desc },
+	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
+	  .data = (ulong)&a80_mmc_clk_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun9i_a80) = {
+	.name		= "sun9i_a80_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a80_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a80_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_a83t.c b/roms/u-boot/drivers/clk/sunxi/clk_a83t.c
new file mode 100644
index 000000000..880c7d759
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_a83t.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a83t_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
+	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
+	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
+	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
+
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+};
+
+static struct ccu_reset a83t_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_HSIC]		= RESET(0x0cc, BIT(2)),
+
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
+	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
+	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
+};
+
+static const struct ccu_desc a83t_ccu_desc = {
+	.gates = a83t_gates,
+	.resets = a83t_resets,
+};
+
+static int a83t_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
+}
+
+static const struct udevice_id a83t_clk_ids[] = {
+	{ .compatible = "allwinner,sun8i-a83t-ccu",
+	  .data = (ulong)&a83t_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_a83t) = {
+	.name		= "sun8i_a83t_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a83t_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a83t_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_h3.c b/roms/u-boot/drivers/clk/sunxi/clk_h3.c
new file mode 100644
index 000000000..f81633b92
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_h3.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h3_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
+	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
+	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
+	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(26)),
+	[CLK_BUS_EHCI3]		= GATE(0x060, BIT(27)),
+	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
+	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
+	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
+	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
+
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+
+	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_PHY3]		= GATE(0x0cc, BIT(11)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+	[CLK_USB_OHCI3]		= GATE(0x0cc, BIT(19)),
+};
+
+static struct ccu_reset h3_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
+	[RST_USB_PHY3]		= RESET(0x0cc, BIT(3)),
+
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+	[RST_BUS_OTG]		= RESET(0x2c0, BIT(23)),
+	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(24)),
+	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(25)),
+	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(26)),
+	[RST_BUS_EHCI3]		= RESET(0x2c0, BIT(27)),
+	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(28)),
+	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(29)),
+	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(30)),
+	[RST_BUS_OHCI3]		= RESET(0x2c0, BIT(31)),
+
+	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+};
+
+static const struct ccu_desc h3_ccu_desc = {
+	.gates = h3_gates,
+	.resets = h3_resets,
+};
+
+static int h3_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
+}
+
+static const struct udevice_id h3_ccu_ids[] = {
+	{ .compatible = "allwinner,sun8i-h3-ccu",
+	  .data = (ulong)&h3_ccu_desc },
+	{ .compatible = "allwinner,sun50i-h5-ccu",
+	  .data = (ulong)&h3_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_h3) = {
+	.name		= "sun8i_h3_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= h3_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= h3_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_h6.c b/roms/u-boot/drivers/clk/sunxi/clk_h6.c
new file mode 100644
index 000000000..df93d96b3
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_h6.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h6_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
+	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
+	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
+
+	[CLK_SPI0]		= GATE(0x940, BIT(31)),
+	[CLK_SPI1]		= GATE(0x944, BIT(31)),
+
+	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
+	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
+
+	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
+
+	[CLK_USB_PHY0]		= GATE(0xa70, BIT(29)),
+	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
+
+	[CLK_USB_PHY1]		= GATE(0xa74, BIT(29)),
+
+	[CLK_USB_HSIC]		= GATE(0xa7c, BIT(26)),
+	[CLK_USB_HSIC_12M]	= GATE(0xa7c, BIT(27)),
+	[CLK_USB_PHY3]		= GATE(0xa7c, BIT(29)),
+	[CLK_USB_OHCI3]		= GATE(0xa7c, BIT(31)),
+
+	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
+	[CLK_BUS_OHCI3]		= GATE(0xa8c, BIT(3)),
+	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
+	[CLK_BUS_XHCI]		= GATE(0xa8c, BIT(5)),
+	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
+	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+};
+
+static struct ccu_reset h6_resets[] = {
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
+
+	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
+	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
+
+	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
+
+	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
+
+	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
+
+	[RST_USB_HSIC]		= RESET(0xa7c, BIT(28)),
+	[RST_USB_PHY3]		= RESET(0xa7c, BIT(30)),
+
+	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
+	[RST_BUS_OHCI3]		= RESET(0xa8c, BIT(19)),
+	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
+	[RST_BUS_XHCI]		= RESET(0xa8c, BIT(21)),
+	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
+	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+};
+
+static const struct ccu_desc h6_ccu_desc = {
+	.gates = h6_gates,
+	.resets = h6_resets,
+};
+
+static int h6_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
+}
+
+static const struct udevice_id h6_ccu_ids[] = {
+	{ .compatible = "allwinner,sun50i-h6-ccu",
+	  .data = (ulong)&h6_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun50i_h6) = {
+	.name		= "sun50i_h6_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= h6_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= h6_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_h616.c b/roms/u-boot/drivers/clk/sunxi/clk_h616.c
new file mode 100644
index 000000000..553d7c6e5
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_h616.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun50i-h616-ccu.h>
+#include <dt-bindings/reset/sun50i-h616-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h616_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+
+	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
+	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
+	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
+	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
+	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
+
+	[CLK_SPI0]		= GATE(0x940, BIT(31)),
+	[CLK_SPI1]		= GATE(0x944, BIT(31)),
+
+	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
+	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
+
+	[CLK_BUS_EMAC0]		= GATE(0x97c, BIT(0)),
+	[CLK_BUS_EMAC1]		= GATE(0x97c, BIT(1)),
+
+	[CLK_USB_PHY0]		= GATE(0xa70, BIT(29)),
+	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
+
+	[CLK_USB_PHY1]		= GATE(0xa74, BIT(29)),
+	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
+
+	[CLK_USB_PHY2]		= GATE(0xa78, BIT(29)),
+	[CLK_USB_OHCI2]		= GATE(0xa78, BIT(31)),
+
+	[CLK_USB_PHY3]		= GATE(0xa7c, BIT(29)),
+	[CLK_USB_OHCI3]		= GATE(0xa7c, BIT(31)),
+
+	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
+	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
+	[CLK_BUS_OHCI2]		= GATE(0xa8c, BIT(2)),
+	[CLK_BUS_OHCI3]		= GATE(0xa8c, BIT(3)),
+	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
+	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
+	[CLK_BUS_EHCI2]		= GATE(0xa8c, BIT(6)),
+	[CLK_BUS_EHCI3]		= GATE(0xa8c, BIT(7)),
+	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+};
+
+static struct ccu_reset h616_resets[] = {
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+
+	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x90c, BIT(21)),
+
+	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
+	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
+
+	[RST_BUS_EMAC0]		= RESET(0x97c, BIT(16)),
+	[RST_BUS_EMAC1]		= RESET(0x97c, BIT(17)),
+
+	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
+
+	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
+
+	[RST_USB_PHY2]		= RESET(0xa78, BIT(30)),
+
+	[RST_USB_PHY3]		= RESET(0xa7c, BIT(30)),
+
+	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
+	[RST_BUS_OHCI1]		= RESET(0xa8c, BIT(17)),
+	[RST_BUS_OHCI2]		= RESET(0xa8c, BIT(18)),
+	[RST_BUS_OHCI3]		= RESET(0xa8c, BIT(19)),
+	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
+	[RST_BUS_EHCI1]		= RESET(0xa8c, BIT(21)),
+	[RST_BUS_EHCI2]		= RESET(0xa8c, BIT(22)),
+	[RST_BUS_EHCI3]		= RESET(0xa8c, BIT(23)),
+	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+};
+
+static const struct ccu_desc h616_ccu_desc = {
+	.gates = h616_gates,
+	.resets = h616_resets,
+};
+
+static int h616_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(h616_resets));
+}
+
+static const struct udevice_id h616_ccu_ids[] = {
+	{ .compatible = "allwinner,sun50i-h616-ccu",
+	  .data = (ulong)&h616_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun50i_h616) = {
+	.name		= "sun50i_h616_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= h616_ccu_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= h616_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_r40.c b/roms/u-boot/drivers/clk/sunxi/clk_r40.c
new file mode 100644
index 000000000..ee1e86d22
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_r40.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate r40_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
+	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+	[CLK_BUS_SPI2]		= GATE(0x060, BIT(22)),
+	[CLK_BUS_SPI3]		= GATE(0x060, BIT(23)),
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(25)),
+	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
+	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
+	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(28)),
+	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
+	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
+	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
+
+	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
+
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+	[CLK_BUS_UART5]		= GATE(0x06c, BIT(21)),
+	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
+	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+	[CLK_SPI3]		= GATE(0x0ac, BIT(31)),
+
+	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
+	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
+	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
+	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
+	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
+	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
+};
+
+static struct ccu_reset r40_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
+	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
+
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
+	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),
+	[RST_BUS_SPI3]		= RESET(0x2c0, BIT(23)),
+	[RST_BUS_OTG]		= RESET(0x2c0, BIT(25)),
+	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
+	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
+	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(28)),
+	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
+	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
+	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
+
+	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x2d8, BIT(21)),
+	[RST_BUS_UART6]		= RESET(0x2d8, BIT(22)),
+	[RST_BUS_UART7]		= RESET(0x2d8, BIT(23)),
+};
+
+static const struct ccu_desc r40_ccu_desc = {
+	.gates = r40_gates,
+	.resets = r40_resets,
+};
+
+static int r40_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
+}
+
+static const struct udevice_id r40_clk_ids[] = {
+	{ .compatible = "allwinner,sun8i-r40-ccu",
+	  .data = (ulong)&r40_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_r40) = {
+	.name		= "sun8i_r40_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= r40_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= r40_clk_bind,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_sun6i_rtc.c b/roms/u-boot/drivers/clk/sunxi/clk_sun6i_rtc.c
new file mode 100644
index 000000000..0c280d221
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_sun6i_rtc.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Copyright (C) 2020 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+
+static int clk_sun6i_rtc_enable(struct clk *clk)
+{
+	return 0;
+}
+
+static const struct clk_ops clk_sun6i_rtc_ops = {
+	.enable = clk_sun6i_rtc_enable,
+};
+
+static const struct udevice_id sun6i_rtc_ids[] = {
+	{ .compatible = "allwinner,sun6i-a31-rtc" },
+	{ .compatible = "allwinner,sun8i-a23-rtc" },
+	{ .compatible = "allwinner,sun8i-h3-rtc" },
+	{ .compatible = "allwinner,sun8i-r40-rtc" },
+	{ .compatible = "allwinner,sun8i-v3-rtc" },
+	{ .compatible = "allwinner,sun50i-h5-rtc" },
+	{ .compatible = "allwinner,sun50i-h6-rtc" },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun6i_rtc) = {
+	.name		= "clk_sun6i_rtc",
+	.id		= UCLASS_CLK,
+	.of_match	= sun6i_rtc_ids,
+	.ops		= &clk_sun6i_rtc_ops,
+};
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_sunxi.c b/roms/u-boot/drivers/clk/sunxi/clk_sunxi.c
new file mode 100644
index 000000000..41934cd82
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_sunxi.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/arch/ccu.h>
+#include <linux/bitops.h>
+#include <linux/log2.h>
+
+static const struct ccu_clk_gate *priv_to_gate(struct ccu_priv *priv,
+					       unsigned long id)
+{
+	return &priv->desc->gates[id];
+}
+
+static int sunxi_set_gate(struct clk *clk, bool on)
+{
+	struct ccu_priv *priv = dev_get_priv(clk->dev);
+	const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
+	u32 reg;
+
+	if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
+		printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
+		return 0;
+	}
+
+	debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
+	      clk->id, gate->off, ilog2(gate->bit));
+
+	reg = readl(priv->base + gate->off);
+	if (on)
+		reg |= gate->bit;
+	else
+		reg &= ~gate->bit;
+
+	writel(reg, priv->base + gate->off);
+
+	return 0;
+}
+
+static int sunxi_clk_enable(struct clk *clk)
+{
+	return sunxi_set_gate(clk, true);
+}
+
+static int sunxi_clk_disable(struct clk *clk)
+{
+	return sunxi_set_gate(clk, false);
+}
+
+struct clk_ops sunxi_clk_ops = {
+	.enable = sunxi_clk_enable,
+	.disable = sunxi_clk_disable,
+};
+
+int sunxi_clk_probe(struct udevice *dev)
+{
+	struct ccu_priv *priv = dev_get_priv(dev);
+	struct clk_bulk clk_bulk;
+	struct reset_ctl_bulk rst_bulk;
+	int ret;
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
+	if (!priv->desc)
+		return -EINVAL;
+
+	ret = clk_get_bulk(dev, &clk_bulk);
+	if (!ret)
+		clk_enable_bulk(&clk_bulk);
+
+	ret = reset_get_bulk(dev, &rst_bulk);
+	if (!ret)
+		reset_deassert_bulk(&rst_bulk);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/clk/sunxi/clk_v3s.c b/roms/u-boot/drivers/clk/sunxi/clk_v3s.c
new file mode 100644
index 000000000..29622199f
--- /dev/null
+++ b/roms/u-boot/drivers/clk/sunxi/clk_v3s.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate v3s_gates[] = {
+	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
+
+	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
+
+	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+
+	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
+};
+
+static struct ccu_reset v3s_resets[] = {
+	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
+
+	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+
+	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
+};
+
+static const struct ccu_desc v3s_ccu_desc = {
+	.gates = v3s_gates,
+	.resets = v3s_resets,
+};
+
+static int v3s_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(v3s_resets));
+}
+
+static const struct udevice_id v3s_clk_ids[] = {
+	{ .compatible = "allwinner,sun8i-v3s-ccu",
+	  .data = (ulong)&v3s_ccu_desc },
+	{ .compatible = "allwinner,sun8i-v3-ccu",
+	  .data = (ulong)&v3s_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_v3s) = {
+	.name		= "sun8i_v3s_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= v3s_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= v3s_clk_bind,
+};