Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

17 files changed, 5055 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/net/fsl-mc/Kconfig b/roms/u-boot/drivers/net/fsl-mc/Kconfig
new file mode 100644
index 000000000..ae4c35799
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/Kconfig
@@ -0,0 +1,37 @@
+#
+# NXP Management Complex
+#
+
+menuconfig FSL_MC_ENET
+	bool "NXP Management Complex"
+	depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
+	default y
+	select RESV_RAM
+	help
+	  Enable Management Complex (MC) network
+	  This is NXP Management Complex menuconfig
+	  that contains all MC related config options
+
+if FSL_MC_ENET
+
+config SYS_MC_RSV_MEM_ALIGN
+	hex "Management Complex reserved memory alignment"
+	depends on RESV_RAM
+	default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A
+	help
+	  Reserved memory needs to be aligned for MC to use. Default value
+	  is 512MB.
+
+config MC_DRAM_SPB_OFFSET
+	hex "Soft Parser SPB DRAM offset"
+	default 0x00F40000
+	help
+	  Set the DRAM offset for Soft Parser Blob.
+
+config MC_SPB_MAX_SIZE
+	hex "Soft Parser SPB maximum size"
+	default 0x00020000
+	help
+	  Set the maximum size for Soft Parser Blob.
+
+endif # FSL_MC_ENET
diff --git a/roms/u-boot/drivers/net/fsl-mc/Makefile b/roms/u-boot/drivers/net/fsl-mc/Makefile
new file mode 100644
index 000000000..5a1acd576
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+# Copyright 2018 NXP
+
+# Layerscape MC driver
+obj-y += mc.o \
+	mc_sys.o \
+	dpmng.o	\
+	dprc.o	\
+	dpbp.o	\
+	dpni.o	\
+	dpmac.o	\
+	dpsparser.o
+obj-y += dpio/
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpbp.c b/roms/u-boot/drivers/net/fsl-mc/dpbp.c
new file mode 100644
index 000000000..c609efb9a
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpbp.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpbp.h>
+
+int dpbp_open(struct fsl_mc_io *mc_io,
+	      uint32_t cmd_flags,
+	      int dpbp_id,
+	      uint16_t *token)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN,
+					  cmd_flags,
+					  0);
+	DPBP_CMD_OPEN(cmd, dpbp_id);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+	return err;
+}
+
+int dpbp_close(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpbp_create(struct fsl_mc_io *mc_io,
+		uint16_t dprc_token,
+		uint32_t cmd_flags,
+		const struct dpbp_cfg *cfg,
+		uint32_t *obj_id)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	(void)(cfg); /* unused */
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
+					  cmd_flags,
+					  dprc_token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+
+	return 0;
+}
+
+int dpbp_destroy(struct fsl_mc_io *mc_io,
+		 uint16_t dprc_token,
+		 uint32_t cmd_flags,
+		 uint32_t obj_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
+					  cmd_flags,
+					  dprc_token);
+
+	/* set object id to destroy */
+	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpbp_enable(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpbp_disable(struct fsl_mc_io *mc_io,
+		 uint32_t cmd_flags,
+		 uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpbp_reset(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpbp_get_attributes(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			struct dpbp_attr *attr)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPBP_RSP_GET_ATTRIBUTES(cmd, attr);
+
+	return 0;
+}
+
+int dpbp_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
+					  cmd_flags, 0);
+
+	/* send command to mc */
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpio/Makefile b/roms/u-boot/drivers/net/fsl-mc/dpio/Makefile
new file mode 100644
index 000000000..752226c73
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpio/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+
+# Layerscape MC DPIO driver
+obj-y += dpio.o	\
+	qbman_portal.o
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpio/dpio.c b/roms/u-boot/drivers/net/fsl-mc/dpio/dpio.c
new file mode 100644
index 000000000..888445596
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpio/dpio.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpio.h>
+
+int dpio_open(struct fsl_mc_io *mc_io,
+	      uint32_t cmd_flags,
+	      uint32_t dpio_id,
+	      uint16_t *token)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
+					  cmd_flags,
+					  0);
+	DPIO_CMD_OPEN(cmd, dpio_id);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+	return 0;
+}
+
+int dpio_close(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpio_create(struct fsl_mc_io *mc_io,
+		uint16_t dprc_token,
+		uint32_t cmd_flags,
+		const struct dpio_cfg *cfg,
+		uint32_t *obj_id)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE,
+					  cmd_flags,
+					  dprc_token);
+	DPIO_CMD_CREATE(cmd, cfg);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+
+	return 0;
+}
+
+int dpio_destroy(struct fsl_mc_io *mc_io,
+		 uint16_t dprc_token,
+		 uint32_t cmd_flags,
+		 uint32_t obj_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY,
+					  cmd_flags,
+					  dprc_token);
+
+	/* set object id to destroy */
+	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpio_enable(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpio_disable(struct fsl_mc_io *mc_io,
+		 uint32_t cmd_flags,
+		 uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpio_reset(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpio_get_attributes(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			struct dpio_attr *attr)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPIO_RSP_GET_ATTR(cmd, attr);
+
+	return 0;
+}
+
+int dpio_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
+					  cmd_flags, 0);
+
+	/* send command to mc */
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_portal.c b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_portal.c
new file mode 100644
index 000000000..44ce00041
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_portal.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#include <log.h>
+#include <malloc.h>
+#include <asm/arch/clock.h>
+#include <linux/bug.h>
+#include "qbman_portal.h"
+
+/* QBMan portal management command codes */
+#define QBMAN_MC_ACQUIRE       0x30
+#define QBMAN_WQCHAN_CONFIGURE 0x46
+
+/* CINH register offsets */
+#define QBMAN_CINH_SWP_EQAR    0x8c0
+#define QBMAN_CINH_SWP_DCAP    0xac0
+#define QBMAN_CINH_SWP_SDQCR   0xb00
+#define QBMAN_CINH_SWP_RAR     0xcc0
+
+/* CENA register offsets */
+#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
+#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
+#define QBMAN_CENA_SWP_RCR(n)  (0x400 + ((uint32_t)(n) << 6))
+#define QBMAN_CENA_SWP_CR      0x600
+#define QBMAN_CENA_SWP_RR(vb)  (0x700 + ((uint32_t)(vb) >> 1))
+#define QBMAN_CENA_SWP_VDQCR   0x780
+
+/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
+#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
+
+/*******************************/
+/* Pre-defined attribute codes */
+/*******************************/
+
+struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7);
+struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8);
+
+/*************************/
+/* SDQCR attribute codes */
+/*************************/
+
+/* we put these here because at least some of them are required by
+ * qbman_swp_init() */
+struct qb_attr_code code_sdqcr_dct = QB_CODE(0, 24, 2);
+struct qb_attr_code code_sdqcr_fc = QB_CODE(0, 29, 1);
+struct qb_attr_code code_sdqcr_tok = QB_CODE(0, 16, 8);
+#define CODE_SDQCR_DQSRC(n) QB_CODE(0, n, 1)
+enum qbman_sdqcr_dct {
+	qbman_sdqcr_dct_null = 0,
+	qbman_sdqcr_dct_prio_ics,
+	qbman_sdqcr_dct_active_ics,
+	qbman_sdqcr_dct_active
+};
+enum qbman_sdqcr_fc {
+	qbman_sdqcr_fc_one = 0,
+	qbman_sdqcr_fc_up_to_3 = 1
+};
+
+/*********************************/
+/* Portal constructor/destructor */
+/*********************************/
+
+/* Software portals should always be in the power-on state when we initialise,
+ * due to the CCSR-based portal reset functionality that MC has. */
+struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
+{
+	int ret;
+	struct qbman_swp *p = malloc(sizeof(struct qbman_swp));
+	u32 major = 0, minor = 0;
+
+	if (!p)
+		return NULL;
+	p->desc = d;
+#ifdef QBMAN_CHECKING
+	p->mc.check = swp_mc_can_start;
+#endif
+	p->mc.valid_bit = QB_VALID_BIT;
+	p->sdq = 0;
+	qb_attr_code_encode(&code_sdqcr_dct, &p->sdq, qbman_sdqcr_dct_prio_ics);
+	qb_attr_code_encode(&code_sdqcr_fc, &p->sdq, qbman_sdqcr_fc_up_to_3);
+	qb_attr_code_encode(&code_sdqcr_tok, &p->sdq, 0xbb);
+	atomic_set(&p->vdq.busy, 1);
+	p->vdq.valid_bit = QB_VALID_BIT;
+	p->dqrr.next_idx = 0;
+
+	qbman_version(&major, &minor);
+	if (!major) {
+		printf("invalid qbman version\n");
+		return NULL;
+	}
+
+	if (major >= 4 && minor >= 1)
+		p->dqrr.dqrr_size = QBMAN_VER_4_1_DQRR_SIZE;
+	else
+		p->dqrr.dqrr_size = QBMAN_VER_4_0_DQRR_SIZE;
+
+	p->dqrr.valid_bit = QB_VALID_BIT;
+	ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
+	if (ret) {
+		free(p);
+		printf("qbman_swp_sys_init() failed %d\n", ret);
+		return NULL;
+	}
+	qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, p->sdq);
+	return p;
+}
+
+/***********************/
+/* Management commands */
+/***********************/
+
+/*
+ * Internal code common to all types of management commands.
+ */
+
+void *qbman_swp_mc_start(struct qbman_swp *p)
+{
+	void *ret;
+	int *return_val;
+#ifdef QBMAN_CHECKING
+	BUG_ON(p->mc.check != swp_mc_can_start);
+#endif
+	ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR);
+#ifdef QBMAN_CHECKING
+	return_val = (int *)ret;
+	if (!(*return_val))
+		p->mc.check = swp_mc_can_submit;
+#endif
+	return ret;
+}
+
+void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb)
+{
+	uint32_t *v = cmd;
+#ifdef QBMAN_CHECKING
+	BUG_ON(p->mc.check != swp_mc_can_submit);
+#endif
+	lwsync();
+	/* TBD: "|=" is going to hurt performance. Need to move as many fields
+	 * out of word zero, and for those that remain, the "OR" needs to occur
+	 * at the caller side. This debug check helps to catch cases where the
+	 * caller wants to OR but has forgotten to do so. */
+	BUG_ON((*v & cmd_verb) != *v);
+	*v = cmd_verb | p->mc.valid_bit;
+	qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd);
+	/* TODO: add prefetch support for GPP */
+#ifdef QBMAN_CHECKING
+	p->mc.check = swp_mc_can_poll;
+#endif
+}
+
+void *qbman_swp_mc_result(struct qbman_swp *p)
+{
+	uint32_t *ret, verb;
+#ifdef QBMAN_CHECKING
+	BUG_ON(p->mc.check != swp_mc_can_poll);
+#endif
+	ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
+	/* Remove the valid-bit - command completed iff the rest is non-zero */
+	verb = ret[0] & ~QB_VALID_BIT;
+	if (!verb)
+		return NULL;
+#ifdef QBMAN_CHECKING
+	p->mc.check = swp_mc_can_start;
+#endif
+	p->mc.valid_bit ^= QB_VALID_BIT;
+	return ret;
+}
+
+/***********/
+/* Enqueue */
+/***********/
+
+/* These should be const, eventually */
+static struct qb_attr_code code_eq_cmd = QB_CODE(0, 0, 2);
+static struct qb_attr_code code_eq_orp_en = QB_CODE(0, 2, 1);
+static struct qb_attr_code code_eq_tgt_id = QB_CODE(2, 0, 24);
+/* static struct qb_attr_code code_eq_tag = QB_CODE(3, 0, 32); */
+static struct qb_attr_code code_eq_qd_en = QB_CODE(0, 4, 1);
+static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 16);
+static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4);
+static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1);
+static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32);
+
+enum qbman_eq_cmd_e {
+	/* No enqueue, primarily for plugging ORP gaps for dropped frames */
+	qbman_eq_cmd_empty,
+	/* DMA an enqueue response once complete */
+	qbman_eq_cmd_respond,
+	/* DMA an enqueue response only if the enqueue fails */
+	qbman_eq_cmd_respond_reject
+};
+
+void qbman_eq_desc_clear(struct qbman_eq_desc *d)
+{
+	memset(d, 0, sizeof(*d));
+}
+
+void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
+{
+	uint32_t *cl = qb_cl(d);
+
+	qb_attr_code_encode(&code_eq_orp_en, cl, 0);
+	qb_attr_code_encode(&code_eq_cmd, cl,
+			    respond_success ? qbman_eq_cmd_respond :
+					      qbman_eq_cmd_respond_reject);
+}
+
+void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
+				dma_addr_t storage_phys,
+				int stash)
+{
+	uint32_t *cl = qb_cl(d);
+
+	qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys);
+	qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
+}
+
+
+void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
+			  uint32_t qd_bin, uint32_t qd_prio)
+{
+	uint32_t *cl = qb_cl(d);
+
+	qb_attr_code_encode(&code_eq_qd_en, cl, 1);
+	qb_attr_code_encode(&code_eq_tgt_id, cl, qdid);
+	qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bin);
+	qb_attr_code_encode(&code_eq_qd_pri, cl, qd_prio);
+}
+
+#define EQAR_IDX(eqar)     ((eqar) & 0x7)
+#define EQAR_VB(eqar)      ((eqar) & 0x80)
+#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
+
+int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
+		      const struct qbman_fd *fd)
+{
+	uint32_t *p;
+	const uint32_t *cl = qb_cl(d);
+	uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR);
+	debug("EQAR=%08x\n", eqar);
+	if (!EQAR_SUCCESS(eqar))
+		return -EBUSY;
+	p = qbman_cena_write_start(&s->sys,
+				   QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
+	word_copy(&p[1], &cl[1], 7);
+	word_copy(&p[8], fd, sizeof(*fd) >> 2);
+	lwsync();
+	/* Set the verb byte, have to substitute in the valid-bit */
+	p[0] = cl[0] | EQAR_VB(eqar);
+	qbman_cena_write_complete(&s->sys,
+				  QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)),
+				  p);
+	return 0;
+}
+
+/***************************/
+/* Volatile (pull) dequeue */
+/***************************/
+
+/* These should be const, eventually */
+static struct qb_attr_code code_pull_dct = QB_CODE(0, 0, 2);
+static struct qb_attr_code code_pull_dt = QB_CODE(0, 2, 2);
+static struct qb_attr_code code_pull_rls = QB_CODE(0, 4, 1);
+static struct qb_attr_code code_pull_stash = QB_CODE(0, 5, 1);
+static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 4);
+static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8);
+static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24);
+static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32);
+
+enum qb_pull_dt_e {
+	qb_pull_dt_channel,
+	qb_pull_dt_workqueue,
+	qb_pull_dt_framequeue
+};
+
+void qbman_pull_desc_clear(struct qbman_pull_desc *d)
+{
+	memset(d, 0, sizeof(*d));
+}
+
+void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
+				 struct ldpaa_dq *storage,
+				 dma_addr_t storage_phys,
+				 int stash)
+{
+	uint32_t *cl = qb_cl(d);
+
+	/* Squiggle the pointer 'storage' into the extra 2 words of the
+	 * descriptor (which aren't copied to the hw command) */
+	*(void **)&cl[4] = storage;
+	if (!storage) {
+		qb_attr_code_encode(&code_pull_rls, cl, 0);
+		return;
+	}
+	qb_attr_code_encode(&code_pull_rls, cl, 1);
+	qb_attr_code_encode(&code_pull_stash, cl, !!stash);
+	qb_attr_code_encode_64(&code_pull_rsp_lo, (uint64_t *)cl, storage_phys);
+}
+
+void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes)
+{
+	uint32_t *cl = qb_cl(d);
+
+	BUG_ON(!numframes || (numframes > 16));
+	qb_attr_code_encode(&code_pull_numframes, cl,
+			    (uint32_t)(numframes - 1));
+}
+
+void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token)
+{
+	uint32_t *cl = qb_cl(d);
+
+	qb_attr_code_encode(&code_pull_token, cl, token);
+}
+
+void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid)
+{
+	uint32_t *cl = qb_cl(d);
+
+	qb_attr_code_encode(&code_pull_dct, cl, 1);
+	qb_attr_code_encode(&code_pull_dt, cl, qb_pull_dt_framequeue);
+	qb_attr_code_encode(&code_pull_dqsource, cl, fqid);
+}
+
+int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
+{
+	uint32_t *p;
+	uint32_t *cl = qb_cl(d);
+
+	if (!atomic_dec_and_test(&s->vdq.busy)) {
+		atomic_inc(&s->vdq.busy);
+		return -EBUSY;
+	}
+	s->vdq.storage = *(void **)&cl[4];
+	s->vdq.token = qb_attr_code_decode(&code_pull_token, cl);
+	p = qbman_cena_write_start(&s->sys, QBMAN_CENA_SWP_VDQCR);
+	word_copy(&p[1], &cl[1], 3);
+	lwsync();
+	/* Set the verb byte, have to substitute in the valid-bit */
+	p[0] = cl[0] | s->vdq.valid_bit;
+	s->vdq.valid_bit ^= QB_VALID_BIT;
+	qbman_cena_write_complete(&s->sys, QBMAN_CENA_SWP_VDQCR, p);
+	return 0;
+}
+
+/****************/
+/* Polling DQRR */
+/****************/
+
+static struct qb_attr_code code_dqrr_verb = QB_CODE(0, 0, 8);
+static struct qb_attr_code code_dqrr_response = QB_CODE(0, 0, 7);
+static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8);
+
+#define QBMAN_DQRR_RESPONSE_DQ        0x60
+#define QBMAN_DQRR_RESPONSE_FQRN      0x21
+#define QBMAN_DQRR_RESPONSE_FQRNI     0x22
+#define QBMAN_DQRR_RESPONSE_FQPN      0x24
+#define QBMAN_DQRR_RESPONSE_FQDAN     0x25
+#define QBMAN_DQRR_RESPONSE_CDAN      0x26
+#define QBMAN_DQRR_RESPONSE_CSCN_MEM  0x27
+#define QBMAN_DQRR_RESPONSE_CGCU      0x28
+#define QBMAN_DQRR_RESPONSE_BPSCN     0x29
+#define QBMAN_DQRR_RESPONSE_CSCN_WQ   0x2a
+
+
+/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
+ * only once, so repeated calls can return a sequence of DQRR entries, without
+ * requiring they be consumed immediately or in any particular order. */
+const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
+{
+	uint32_t verb;
+	uint32_t response_verb;
+	uint32_t flags;
+	const struct ldpaa_dq *dq;
+	const uint32_t *p;
+
+	dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+	p = qb_cl(dq);
+	verb = qb_attr_code_decode(&code_dqrr_verb, p);
+
+	/* If the valid-bit isn't of the expected polarity, nothing there. Note,
+	 * in the DQRR reset bug workaround, we shouldn't need to skip these
+	 * check, because we've already determined that a new entry is available
+	 * and we've invalidated the cacheline before reading it, so the
+	 * valid-bit behaviour is repaired and should tell us what we already
+	 * knew from reading PI.
+	 */
+	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
+		qbman_cena_invalidate_prefetch(&s->sys,
+					QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+		return NULL;
+	}
+	/* There's something there. Move "next_idx" attention to the next ring
+	 * entry (and prefetch it) before returning what we found. */
+	s->dqrr.next_idx++;
+	s->dqrr.next_idx &= s->dqrr.dqrr_size - 1;/* Wrap around at dqrr_size */
+	/* TODO: it's possible to do all this without conditionals, optimise it
+	 * later. */
+	if (!s->dqrr.next_idx)
+		s->dqrr.valid_bit ^= QB_VALID_BIT;
+
+	/* If this is the final response to a volatile dequeue command
+	   indicate that the vdq is no longer busy */
+	flags = ldpaa_dq_flags(dq);
+	response_verb = qb_attr_code_decode(&code_dqrr_response, &verb);
+	if ((response_verb == QBMAN_DQRR_RESPONSE_DQ) &&
+	    (flags & LDPAA_DQ_STAT_VOLATILE) &&
+	    (flags & LDPAA_DQ_STAT_EXPIRED))
+			atomic_inc(&s->vdq.busy);
+
+	qbman_cena_invalidate_prefetch(&s->sys,
+				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
+	return dq;
+}
+
+/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
+void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct ldpaa_dq *dq)
+{
+	qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
+}
+
+/*********************************/
+/* Polling user-provided storage */
+/*********************************/
+
+void qbman_dq_entry_set_oldtoken(struct ldpaa_dq *dq,
+				 unsigned int num_entries,
+				 uint8_t oldtoken)
+{
+	memset(dq, oldtoken, num_entries * sizeof(*dq));
+}
+
+int qbman_dq_entry_has_newtoken(struct qbman_swp *s,
+				const struct ldpaa_dq *dq,
+				uint8_t newtoken)
+{
+	/* To avoid converting the little-endian DQ entry to host-endian prior
+	 * to us knowing whether there is a valid entry or not (and run the
+	 * risk of corrupting the incoming hardware LE write), we detect in
+	 * hardware endianness rather than host. This means we need a different
+	 * "code" depending on whether we are BE or LE in software, which is
+	 * where DQRR_TOK_OFFSET comes in... */
+	static struct qb_attr_code code_dqrr_tok_detect =
+					QB_CODE(0, DQRR_TOK_OFFSET, 8);
+	/* The user trying to poll for a result treats "dq" as const. It is
+	 * however the same address that was provided to us non-const in the
+	 * first place, for directing hardware DMA to. So we can cast away the
+	 * const because it is mutable from our perspective. */
+	uint32_t *p = qb_cl((struct ldpaa_dq *)dq);
+	uint32_t token;
+
+	token = qb_attr_code_decode(&code_dqrr_tok_detect, &p[1]);
+	if (token != newtoken)
+		return 0;
+
+	/* Only now do we convert from hardware to host endianness. Also, as we
+	 * are returning success, the user has promised not to call us again, so
+	 * there's no risk of us converting the endianness twice... */
+	make_le32_n(p, 16);
+
+	/* VDQCR "no longer busy" hook - not quite the same as DQRR, because the
+	 * fact "VDQCR" shows busy doesn't mean that the result we're looking at
+	 * is from the same command. Eg. we may be looking at our 10th dequeue
+	 * result from our first VDQCR command, yet the second dequeue command
+	 * could have been kicked off already, after seeing the 1st result. Ie.
+	 * the result we're looking at is not necessarily proof that we can
+	 * reset "busy".  We instead base the decision on whether the current
+	 * result is sitting at the first 'storage' location of the busy
+	 * command. */
+	if (s->vdq.storage == dq) {
+		s->vdq.storage = NULL;
+			atomic_inc(&s->vdq.busy);
+	}
+	return 1;
+}
+
+/********************************/
+/* Categorising dequeue entries */
+/********************************/
+
+static inline int __qbman_dq_entry_is_x(const struct ldpaa_dq *dq, uint32_t x)
+{
+	const uint32_t *p = qb_cl(dq);
+	uint32_t response_verb = qb_attr_code_decode(&code_dqrr_response, p);
+
+	return response_verb == x;
+}
+
+int qbman_dq_entry_is_DQ(const struct ldpaa_dq *dq)
+{
+	return __qbman_dq_entry_is_x(dq, QBMAN_DQRR_RESPONSE_DQ);
+}
+
+/*********************************/
+/* Parsing frame dequeue results */
+/*********************************/
+
+/* These APIs assume qbman_dq_entry_is_DQ() is TRUE */
+
+uint32_t ldpaa_dq_flags(const struct ldpaa_dq *dq)
+{
+	const uint32_t *p = qb_cl(dq);
+
+	return qb_attr_code_decode(&code_dqrr_stat, p);
+}
+
+const struct dpaa_fd *ldpaa_dq_fd(const struct ldpaa_dq *dq)
+{
+	const uint32_t *p = qb_cl(dq);
+
+	return (const struct dpaa_fd *)&p[8];
+}
+
+/******************/
+/* Buffer release */
+/******************/
+
+/* These should be const, eventually */
+/* static struct qb_attr_code code_release_num = QB_CODE(0, 0, 3); */
+static struct qb_attr_code code_release_set_me = QB_CODE(0, 5, 1);
+static struct qb_attr_code code_release_bpid = QB_CODE(0, 16, 16);
+
+void qbman_release_desc_clear(struct qbman_release_desc *d)
+{
+	uint32_t *cl;
+
+	memset(d, 0, sizeof(*d));
+	cl = qb_cl(d);
+	qb_attr_code_encode(&code_release_set_me, cl, 1);
+}
+
+void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint32_t bpid)
+{
+	uint32_t *cl = qb_cl(d);
+
+	qb_attr_code_encode(&code_release_bpid, cl, bpid);
+}
+
+#define RAR_IDX(rar)     ((rar) & 0x7)
+#define RAR_VB(rar)      ((rar) & 0x80)
+#define RAR_SUCCESS(rar) ((rar) & 0x100)
+
+int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
+		      const uint64_t *buffers, unsigned int num_buffers)
+{
+	uint32_t *p;
+	const uint32_t *cl = qb_cl(d);
+	uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR);
+	debug("RAR=%08x\n", rar);
+	if (!RAR_SUCCESS(rar))
+		return -EBUSY;
+	BUG_ON(!num_buffers || (num_buffers > 7));
+	/* Start the release command */
+	p = qbman_cena_write_start(&s->sys,
+				   QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
+	/* Copy the caller's buffer pointers to the command */
+	u64_to_le32_copy(&p[2], buffers, num_buffers);
+	lwsync();
+	/* Set the verb byte, have to substitute in the valid-bit and the number
+	 * of buffers. */
+	p[0] = cl[0] | RAR_VB(rar) | num_buffers;
+	qbman_cena_write_complete(&s->sys,
+				  QBMAN_CENA_SWP_RCR(RAR_IDX(rar)),
+				  p);
+	return 0;
+}
+
+/*******************/
+/* Buffer acquires */
+/*******************/
+
+/* These should be const, eventually */
+static struct qb_attr_code code_acquire_bpid = QB_CODE(0, 16, 16);
+static struct qb_attr_code code_acquire_num = QB_CODE(1, 0, 3);
+static struct qb_attr_code code_acquire_r_num = QB_CODE(1, 0, 3);
+
+int qbman_swp_acquire(struct qbman_swp *s, uint32_t bpid, uint64_t *buffers,
+		      unsigned int num_buffers)
+{
+	uint32_t *p;
+	uint32_t verb, rslt, num;
+
+	BUG_ON(!num_buffers || (num_buffers > 7));
+
+	/* Start the management command */
+	p = qbman_swp_mc_start(s);
+
+	if (!p)
+		return -EBUSY;
+
+	/* Encode the caller-provided attributes */
+	qb_attr_code_encode(&code_acquire_bpid, p, bpid);
+	qb_attr_code_encode(&code_acquire_num, p, num_buffers);
+
+	/* Complete the management command */
+	p = qbman_swp_mc_complete(s, p, p[0] | QBMAN_MC_ACQUIRE);
+
+	/* Decode the outcome */
+	verb = qb_attr_code_decode(&code_generic_verb, p);
+	rslt = qb_attr_code_decode(&code_generic_rslt, p);
+	num = qb_attr_code_decode(&code_acquire_r_num, p);
+	BUG_ON(verb != QBMAN_MC_ACQUIRE);
+
+	/* Determine success or failure */
+	if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
+		printf("Acquire buffers from BPID 0x%x failed, code=0x%02x\n",
+		       bpid, rslt);
+		return -EIO;
+	}
+	BUG_ON(num > num_buffers);
+	/* Copy the acquired buffers to the caller's array */
+	u64_from_le32_copy(buffers, &p[2], num);
+	return (int)num;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_portal.h b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_portal.h
new file mode 100644
index 000000000..8cbc771a1
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_portal.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#include "qbman_private.h"
+#include <fsl-mc/fsl_qbman_portal.h>
+#include <fsl-mc/fsl_dpaa_fd.h>
+
+/* All QBMan command and result structures use this "valid bit" encoding */
+#define QB_VALID_BIT ((uint32_t)0x80)
+
+/* Management command result codes */
+#define QBMAN_MC_RSLT_OK      0xf0
+
+#define QBMAN_VER_4_0_DQRR_SIZE 4
+#define QBMAN_VER_4_1_DQRR_SIZE 8
+
+
+/* --------------------- */
+/* portal data structure */
+/* --------------------- */
+
+struct qbman_swp {
+	const struct qbman_swp_desc *desc;
+	/* The qbman_sys (ie. arch/OS-specific) support code can put anything it
+	 * needs in here. */
+	struct qbman_swp_sys sys;
+	/* Management commands */
+	struct {
+#ifdef QBMAN_CHECKING
+		enum swp_mc_check {
+			swp_mc_can_start, /* call __qbman_swp_mc_start() */
+			swp_mc_can_submit, /* call __qbman_swp_mc_submit() */
+			swp_mc_can_poll, /* call __qbman_swp_mc_result() */
+		} check;
+#endif
+		uint32_t valid_bit; /* 0x00 or 0x80 */
+	} mc;
+	/* Push dequeues */
+	uint32_t sdq;
+	/* Volatile dequeues */
+	struct {
+		/* VDQCR supports a "1 deep pipeline", meaning that if you know
+		 * the last-submitted command is already executing in the
+		 * hardware (as evidenced by at least 1 valid dequeue result),
+		 * you can write another dequeue command to the register, the
+		 * hardware will start executing it as soon as the
+		 * already-executing command terminates. (This minimises latency
+		 * and stalls.) With that in mind, this "busy" variable refers
+		 * to whether or not a command can be submitted, not whether or
+		 * not a previously-submitted command is still executing. In
+		 * other words, once proof is seen that the previously-submitted
+		 * command is executing, "vdq" is no longer "busy".
+		 */
+		atomic_t busy;
+		uint32_t valid_bit; /* 0x00 or 0x80 */
+		/* We need to determine when vdq is no longer busy. This depends
+		 * on whether the "busy" (last-submitted) dequeue command is
+		 * targeting DQRR or main-memory, and detected is based on the
+		 * presence of the dequeue command's "token" showing up in
+		 * dequeue entries in DQRR or main-memory (respectively). Debug
+		 * builds will, when submitting vdq commands, verify that the
+		 * dequeue result location is not already equal to the command's
+		 * token value. */
+		struct ldpaa_dq *storage; /* NULL if DQRR */
+		uint32_t token;
+	} vdq;
+	/* DQRR */
+	struct {
+		uint32_t next_idx;
+		uint32_t valid_bit;
+		uint8_t dqrr_size;
+	} dqrr;
+};
+
+/* -------------------------- */
+/* portal management commands */
+/* -------------------------- */
+
+/* Different management commands all use this common base layer of code to issue
+ * commands and poll for results. The first function returns a pointer to where
+ * the caller should fill in their MC command (though they should ignore the
+ * verb byte), the second function commits merges in the caller-supplied command
+ * verb (which should not include the valid-bit) and submits the command to
+ * hardware, and the third function checks for a completed response (returns
+ * non-NULL if only if the response is complete). */
+void *qbman_swp_mc_start(struct qbman_swp *p);
+void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb);
+void *qbman_swp_mc_result(struct qbman_swp *p);
+
+/* Wraps up submit + poll-for-result */
+static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
+					  uint32_t cmd_verb)
+{
+	int loopvar;
+
+	qbman_swp_mc_submit(swp, cmd, cmd_verb);
+	DBG_POLL_START(loopvar);
+	do {
+		DBG_POLL_CHECK(loopvar);
+		cmd = qbman_swp_mc_result(swp);
+	} while (!cmd);
+	return cmd;
+}
+
+/* ------------ */
+/* qb_attr_code */
+/* ------------ */
+
+/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
+ * is either serving as a configuration command or a query result. The
+ * representation is inherently little-endian, as the indexing of the words is
+ * itself little-endian in nature and layerscape is little endian for anything
+ * that crosses a word boundary too (64-bit fields are the obvious examples).
+ */
+struct qb_attr_code {
+	unsigned int word; /* which uint32_t[] array member encodes the field */
+	unsigned int lsoffset; /* encoding offset from ls-bit */
+	unsigned int width; /* encoding width. (bool must be 1.) */
+};
+
+/* Macros to define codes */
+#define QB_CODE(a, b, c) { a, b, c}
+
+/* decode a field from a cacheline */
+static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
+				      const uint32_t *cacheline)
+{
+	return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
+}
+
+
+/* encode a field to a cacheline */
+static inline void qb_attr_code_encode(const struct qb_attr_code *code,
+				       uint32_t *cacheline, uint32_t val)
+{
+	cacheline[code->word] =
+		r32_uint32_t(code->lsoffset, code->width, cacheline[code->word])
+		| e32_uint32_t(code->lsoffset, code->width, val);
+}
+
+static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
+				       uint64_t *cacheline, uint64_t val)
+{
+	cacheline[code->word / 2] = val;
+}
+
+/* ---------------------- */
+/* Descriptors/cachelines */
+/* ---------------------- */
+
+/* To avoid needless dynamic allocation, the driver API often gives the caller
+ * a "descriptor" type that the caller can instantiate however they like.
+ * Ultimately though, it is just a cacheline of binary storage (or something
+ * smaller when it is known that the descriptor doesn't need all 64 bytes) for
+ * holding pre-formatted pieces of hardware commands. The performance-critical
+ * code can then copy these descriptors directly into hardware command
+ * registers more efficiently than trying to construct/format commands
+ * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
+ * order for the compiler to know its size, but the internal details are not
+ * exposed. The following macro is used within the driver for converting *any*
+ * descriptor pointer to a usable array pointer. The use of a macro (instead of
+ * an inline) is necessary to work with different descriptor types and to work
+ * correctly with const and non-const inputs (and similarly-qualified outputs).
+ */
+#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_private.h b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_private.h
new file mode 100644
index 000000000..53f1300ea
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_private.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+/* Perform extra checking */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/types.h>
+#include <asm/atomic.h>
+#include <malloc.h>
+#include <asm/arch/soc.h>
+#include <fsl-mc/fsl_qbman_base.h>
+
+#define QBMAN_CHECKING
+
+/* Any time there is a register interface which we poll on, this provides a
+ * "break after x iterations" scheme for it. It's handy for debugging, eg.
+ * where you don't want millions of lines of log output from a polling loop
+ * that won't, because such things tend to drown out the earlier log output
+ * that might explain what caused the problem. (NB: put ";" after each macro!)
+ * TODO: we should probably remove this once we're done sanitising the
+ * simulator...
+ */
+#define DBG_POLL_START(loopvar) (loopvar = 10)
+#define DBG_POLL_CHECK(loopvar) \
+	do {if (!(loopvar--)) BUG_ON(NULL == "DBG_POLL_CHECK"); } while (0)
+
+/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets
+ * and widths, these macro-generated encode/decode/isolate/remove inlines can
+ * be used.
+ *
+ * Eg. to "d"ecode a 14-bit field out of a register (into a "uint16_t" type),
+ * where the field is located 3 bits "up" from the least-significant bit of the
+ * register (ie. the field location within the 32-bit register corresponds to a
+ * mask of 0x0001fff8), you would do;
+ *                uint16_t field = d32_uint16_t(3, 14, reg_value);
+ *
+ * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,
+ * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"
+ * operator) into a register at bit location 0x00080000 (19 bits "in" from the
+ * LS bit), do;
+ *                reg_value |= e32_int(19, 1, !!field);
+ *
+ * If you wish to read-modify-write a register, such that you leave the 14-bit
+ * field as-is but have all other fields set to zero, then "i"solate the 14-bit
+ * value using;
+ *                reg_value = i32_uint16_t(3, 14, reg_value);
+ *
+ * Alternatively, you could "r"emove the 1-bit boolean field (setting it to
+ * zero) but leaving all other fields as-is;
+ *                reg_val = r32_int(19, 1, reg_value);
+ *
+ */
+#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \
+				 (uint32_t)((1 << width) - 1))
+#define DECLARE_CODEC32(t) \
+static inline uint32_t e32_##t(uint32_t lsoffset, uint32_t width, t val) \
+{ \
+	BUG_ON(width > (sizeof(t) * 8)); \
+	return ((uint32_t)val & MAKE_MASK32(width)) << lsoffset; \
+} \
+static inline t d32_##t(uint32_t lsoffset, uint32_t width, uint32_t val) \
+{ \
+	BUG_ON(width > (sizeof(t) * 8)); \
+	return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
+} \
+static inline uint32_t i32_##t(uint32_t lsoffset, uint32_t width, \
+				uint32_t val) \
+{ \
+	BUG_ON(width > (sizeof(t) * 8)); \
+	return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
+} \
+static inline uint32_t r32_##t(uint32_t lsoffset, uint32_t width, \
+				uint32_t val) \
+{ \
+	BUG_ON(width > (sizeof(t) * 8)); \
+	return ~(MAKE_MASK32(width) << lsoffset) & val; \
+}
+DECLARE_CODEC32(uint32_t)
+DECLARE_CODEC32(uint16_t)
+DECLARE_CODEC32(uint8_t)
+DECLARE_CODEC32(int)
+
+	/*********************/
+	/* Debugging assists */
+	/*********************/
+
+static inline void __hexdump(unsigned long start, unsigned long end,
+			unsigned long p, size_t sz, const unsigned char *c)
+{
+	while (start < end) {
+		unsigned int pos = 0;
+		char buf[64];
+		int nl = 0;
+
+		pos += sprintf(buf + pos, "%08lx: ", start);
+		do {
+			if ((start < p) || (start >= (p + sz)))
+				pos += sprintf(buf + pos, "..");
+			else
+				pos += sprintf(buf + pos, "%02x", *(c++));
+			if (!(++start & 15)) {
+				buf[pos++] = '\n';
+				nl = 1;
+			} else {
+				nl = 0;
+				if (!(start & 1))
+					buf[pos++] = ' ';
+				if (!(start & 3))
+					buf[pos++] = ' ';
+			}
+		} while (start & 15);
+		if (!nl)
+			buf[pos++] = '\n';
+		buf[pos] = '\0';
+		debug("%s", buf);
+	}
+}
+static inline void hexdump(const void *ptr, size_t sz)
+{
+	unsigned long p = (unsigned long)ptr;
+	unsigned long start = p & ~(unsigned long)15;
+	unsigned long end = (p + sz + 15) & ~(unsigned long)15;
+	const unsigned char *c = ptr;
+
+	__hexdump(start, end, p, sz, c);
+}
+
+#if defined(__BIG_ENDIAN)
+#define DQRR_TOK_OFFSET 0
+#else
+#define DQRR_TOK_OFFSET 24
+#endif
+
+/* Similarly-named functions */
+#define upper32(a) upper_32_bits(a)
+#define lower32(a) lower_32_bits(a)
+
+	/****************/
+	/* arch assists */
+	/****************/
+
+static inline void dcbz(void *ptr)
+{
+	uint32_t *p = ptr;
+	BUG_ON((unsigned long)ptr & 63);
+	p[0] = 0;
+	p[1] = 0;
+	p[2] = 0;
+	p[3] = 0;
+	p[4] = 0;
+	p[5] = 0;
+	p[6] = 0;
+	p[7] = 0;
+	p[8] = 0;
+	p[9] = 0;
+	p[10] = 0;
+	p[11] = 0;
+	p[12] = 0;
+	p[13] = 0;
+	p[14] = 0;
+	p[15] = 0;
+}
+
+#define lwsync()
+
+void qbman_version(u32 *major, u32 *minor)
+{
+	u32 svr_dev_id;
+
+	/*
+	 * LS2080A SoC and its personalities has qbman cotroller version 4.0
+	 * New SoCs like LS2088A, LS1088A has qbman conroller version 4.1
+	 */
+	svr_dev_id = get_svr();
+	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) {
+		*major = 4;
+		*minor = 0;
+	} else {
+		*major = 4;
+		*minor = 1;
+	}
+}
+
+#include "qbman_sys.h"
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_sys.h b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_sys.h
new file mode 100644
index 000000000..8be38e11a
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpio/qbman_sys.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+/* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
+ * driver. They are only included via qbman_private.h, which is itself a
+ * platform-independent file and is included by all the other driver source.
+ *
+ * qbman_sys_decl.h is included prior to all other declarations and logic, and
+ * it exists to provide compatibility with any linux interfaces our
+ * single-source driver code is dependent on (eg. kmalloc). Ie. this file
+ * provides linux compatibility.
+ *
+ * This qbman_sys.h header, on the other hand, is included *after* any common
+ * and platform-neutral declarations and logic in qbman_private.h, and exists to
+ * implement any platform-specific logic of the qbman driver itself. Ie. it is
+ * *not* to provide linux compatibility.
+ */
+
+/* Trace the 3 different classes of read/write access to QBMan. #undef as
+ * required. */
+#include <linux/bug.h>
+#undef QBMAN_CCSR_TRACE
+#undef QBMAN_CINH_TRACE
+#undef QBMAN_CENA_TRACE
+
+/* Temporarily define this to get around the fact that cache enabled mapping is
+ * not working right now. Will remove this after uboot could map the cache
+ * enabled portal memory.
+ */
+#define QBMAN_CINH_ONLY
+
+static inline void word_copy(void *d, const void *s, unsigned int cnt)
+{
+	uint32_t *dd = d;
+	const uint32_t *ss = s;
+
+	while (cnt--)
+		*(dd++) = *(ss++);
+}
+
+/* Currently, the CENA support code expects each 32-bit word to be written in
+ * host order, and these are converted to hardware (little-endian) order on
+ * command submission. However, 64-bit quantities are must be written (and read)
+ * as two 32-bit words with the least-significant word first, irrespective of
+ * host endianness. */
+static inline void u64_to_le32_copy(void *d, const uint64_t *s,
+					unsigned int cnt)
+{
+	uint32_t *dd = d;
+	const uint32_t *ss = (const uint32_t *)s;
+
+	while (cnt--) {
+		/* TBD: the toolchain was choking on the use of 64-bit types up
+		 * until recently so this works entirely with 32-bit variables.
+		 * When 64-bit types become usable again, investigate better
+		 * ways of doing this. */
+#if defined(__BIG_ENDIAN)
+		*(dd++) = ss[1];
+		*(dd++) = ss[0];
+		ss += 2;
+#else
+		*(dd++) = *(ss++);
+		*(dd++) = *(ss++);
+#endif
+	}
+}
+static inline void u64_from_le32_copy(uint64_t *d, const void *s,
+					unsigned int cnt)
+{
+	const uint32_t *ss = s;
+	uint32_t *dd = (uint32_t *)d;
+
+	while (cnt--) {
+#if defined(__BIG_ENDIAN)
+		dd[1] = *(ss++);
+		dd[0] = *(ss++);
+		dd += 2;
+#else
+		*(dd++) = *(ss++);
+		*(dd++) = *(ss++);
+#endif
+	}
+}
+
+/* Convert a host-native 32bit value into little endian */
+#if defined(__BIG_ENDIAN)
+static inline uint32_t make_le32(uint32_t val)
+{
+	return ((val & 0xff) << 24) | ((val & 0xff00) << 8) |
+		((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24);
+}
+#else
+#define make_le32(val) (val)
+#endif
+static inline void make_le32_n(uint32_t *val, unsigned int num)
+{
+	while (num--) {
+		*val = make_le32(*val);
+		val++;
+	}
+}
+
+	/******************/
+	/* Portal access  */
+	/******************/
+struct qbman_swp_sys {
+	/* On GPP, the sys support for qbman_swp is here. The CENA region isi
+	 * not an mmap() of the real portal registers, but an allocated
+	 * place-holder, because the actual writes/reads to/from the portal are
+	 * marshalled from these allocated areas using QBMan's "MC access
+	 * registers". CINH accesses are atomic so there's no need for a
+	 * place-holder. */
+	void *cena;
+	void __iomem *addr_cena;
+	void __iomem *addr_cinh;
+};
+
+/* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
+ * C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
+ * SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
+ * P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
+ * T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
+ * E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
+ */
+
+static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
+				    uint32_t val)
+{
+	__raw_writel(val, s->addr_cinh + offset);
+#ifdef QBMAN_CINH_TRACE
+	pr_info("qbman_cinh_write(%p:0x%03x) 0x%08x\n",
+		s->addr_cinh, offset, val);
+#endif
+}
+
+static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
+{
+	uint32_t reg = __raw_readl(s->addr_cinh + offset);
+
+#ifdef QBMAN_CINH_TRACE
+	pr_info("qbman_cinh_read(%p:0x%03x) 0x%08x\n",
+		s->addr_cinh, offset, reg);
+#endif
+	return reg;
+}
+
+static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
+						uint32_t offset)
+{
+	void *shadow = s->cena + offset;
+
+#ifdef QBMAN_CENA_TRACE
+	pr_info("qbman_cena_write_start(%p:0x%03x) %p\n",
+		s->addr_cena, offset, shadow);
+#endif
+	BUG_ON(offset & 63);
+	dcbz(shadow);
+	return shadow;
+}
+
+static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
+						uint32_t offset, void *cmd)
+{
+	const uint32_t *shadow = cmd;
+	int loop;
+
+#ifdef QBMAN_CENA_TRACE
+	pr_info("qbman_cena_write_complete(%p:0x%03x) %p\n",
+		s->addr_cena, offset, shadow);
+	hexdump(cmd, 64);
+#endif
+	for (loop = 15; loop >= 0; loop--)
+#ifdef QBMAN_CINH_ONLY
+		__raw_writel(shadow[loop], s->addr_cinh +
+					 offset + loop * 4);
+#else
+		__raw_writel(shadow[loop], s->addr_cena +
+					 offset + loop * 4);
+#endif
+}
+
+static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
+{
+	uint32_t *shadow = s->cena + offset;
+	unsigned int loop;
+
+#ifdef QBMAN_CENA_TRACE
+	pr_info("qbman_cena_read(%p:0x%03x) %p\n",
+		s->addr_cena, offset, shadow);
+#endif
+
+	for (loop = 0; loop < 16; loop++)
+#ifdef QBMAN_CINH_ONLY
+		shadow[loop] = __raw_readl(s->addr_cinh + offset
+					+ loop * 4);
+#else
+		shadow[loop] = __raw_readl(s->addr_cena + offset
+					+ loop * 4);
+#endif
+#ifdef QBMAN_CENA_TRACE
+	hexdump(shadow, 64);
+#endif
+	return shadow;
+}
+
+static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
+						  uint32_t offset)
+{
+}
+
+	/******************/
+	/* Portal support */
+	/******************/
+
+/* The SWP_CFG portal register is special, in that it is used by the
+ * platform-specific code rather than the platform-independent code in
+ * qbman_portal.c. So use of it is declared locally here. */
+#define QBMAN_CINH_SWP_CFG   0xd00
+
+/* For MC portal use, we always configure with
+ * DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4)
+ * EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x0)
+ * RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3)
+ * DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2)
+ * EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x3)
+ * SD is (SWP_CFG,5,1) - memory stashing drop enable (<- FALSE)
+ * SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE)
+ * SE is (SWP_CFG,3,1) - memory stashing enable (<- 0x0)
+ * DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE)
+ * DE is (SWP_CFG,1,1) - dequeue stashing enable (<- 0x0)
+ * EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- FALSE)
+ */
+static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
+					uint8_t est, uint8_t rpm, uint8_t dcm,
+					uint8_t epm, int sd, int sp, int se,
+					int dp, int de, int ep)
+{
+	uint32_t reg;
+
+	reg = e32_uint8_t(20, (uint32_t)(3 + (max_fill >> 3)), max_fill) |
+		e32_uint8_t(16, 3, est) | e32_uint8_t(12, 2, rpm) |
+		e32_uint8_t(10, 2, dcm) | e32_uint8_t(8, 2, epm) |
+		e32_int(5, 1, sd) | e32_int(4, 1, sp) | e32_int(3, 1, se) |
+		e32_int(2, 1, dp) | e32_int(1, 1, de) | e32_int(0, 1, ep) |
+		e32_uint8_t(14, 1, wn);
+	return reg;
+}
+
+static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
+				     const struct qbman_swp_desc *d,
+				     uint8_t dqrr_size)
+{
+	uint32_t reg;
+
+	s->addr_cena = d->cena_bar;
+	s->addr_cinh = d->cinh_bar;
+	s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
+	if (!s->cena) {
+		printf("Could not allocate page for cena shadow\n");
+		return -1;
+	}
+	memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
+
+#ifdef QBMAN_CHECKING
+	/* We should never be asked to initialise for a portal that isn't in
+	 * the power-on state. (Ie. don't forget to reset portals when they are
+	 * decommissioned!)
+	 */
+	reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
+	BUG_ON(reg);
+#endif
+#ifdef QBMAN_CINH_ONLY
+	reg = qbman_set_swp_cfg(dqrr_size, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
+#else
+	reg = qbman_set_swp_cfg(dqrr_size, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
+#endif
+	qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
+	reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
+	if (!reg) {
+		printf("The portal is not enabled!\n");
+		free(s->cena);
+		return -1;
+	}
+	return 0;
+}
+
+static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
+{
+	free((void *)s->cena);
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpmac.c b/roms/u-boot/drivers/net/fsl-mc/dpmac.c
new file mode 100644
index 000000000..43a2ff43f
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpmac.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmac.h>
+
+int dpmac_open(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       int dpmac_id,
+	       uint16_t *token)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
+					  cmd_flags,
+					  0);
+	DPMAC_CMD_OPEN(cmd, dpmac_id);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+	return err;
+}
+
+int dpmac_close(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_create(struct fsl_mc_io *mc_io,
+		 uint16_t dprc_token,
+		 uint32_t cmd_flags,
+		 const struct dpmac_cfg *cfg,
+		 uint32_t *obj_id)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
+					  cmd_flags,
+					  dprc_token);
+	DPMAC_CMD_CREATE(cmd, cfg);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+
+	return 0;
+}
+
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+		  uint16_t dprc_token,
+		  uint32_t cmd_flags,
+		  uint32_t obj_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
+					  cmd_flags,
+					  dprc_token);
+
+	/* set object id to destroy */
+	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 struct dpmac_attr *attr)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPMAC_RSP_GET_ATTRIBUTES(cmd, attr);
+
+	return 0;
+}
+
+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
+		    uint32_t cmd_flags,
+		    uint16_t token,
+		    struct dpmac_mdio_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ,
+					  cmd_flags,
+					  token);
+	DPMAC_CMD_MDIO_READ(cmd, cfg);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPMAC_RSP_MDIO_READ(cmd, cfg->data);
+
+	return 0;
+}
+
+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
+		     uint32_t cmd_flags,
+		     uint16_t token,
+		     struct dpmac_mdio_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE,
+					  cmd_flags,
+					  token);
+	DPMAC_CMD_MDIO_WRITE(cmd, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       struct dpmac_link_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+	int err = 0;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	DPMAC_RSP_GET_LINK_CFG(cmd, cfg);
+
+	return 0;
+}
+
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 struct dpmac_link_state *link_state)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
+					  cmd_flags,
+					  token);
+	DPMAC_CMD_SET_LINK_STATE(cmd, link_state);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+		      uint32_t cmd_flags,
+		      uint16_t token,
+		      enum dpmac_counter type,
+		      uint64_t *counter)
+{
+	struct mc_command cmd = { 0 };
+	int err = 0;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
+					  cmd_flags,
+					  token);
+	DPMAC_CMD_GET_COUNTER(cmd, type);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	DPMAC_RSP_GET_COUNTER(cmd, *counter);
+
+	return 0;
+}
+
+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
+					  cmd_flags, 0);
+
+	/* send command to mc */
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpmng.c b/roms/u-boot/drivers/net/fsl-mc/dpmng.c
new file mode 100644
index 000000000..8314243f3
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpmng.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright 2013-2015 Freescale Semiconductor Inc.
+ */
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmng.h>
+#include "fsl_dpmng_cmd.h"
+
+int mc_get_version(struct fsl_mc_io *mc_io,
+		   uint32_t cmd_flags,
+		   struct mc_version *mc_ver_info)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
+					  cmd_flags,
+					  0);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPMNG_RSP_GET_VERSION(cmd, mc_ver_info);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpni.c b/roms/u-boot/drivers/net/fsl-mc/dpni.c
new file mode 100644
index 000000000..443e43069
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpni.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpni.h>
+
+int dpni_prepare_cfg(const struct dpni_cfg	*cfg,
+		     uint8_t			*cfg_buf)
+{
+	uint64_t *params = (uint64_t *)cfg_buf;
+
+	DPNI_PREP_CFG(params, cfg);
+
+	return 0;
+}
+
+int dpni_extract_cfg(struct dpni_cfg	*cfg,
+		     const uint8_t	*cfg_buf)
+{
+	uint64_t *params = (uint64_t *)cfg_buf;
+
+	DPNI_EXT_CFG(params, cfg);
+
+	return 0;
+}
+
+int dpni_open(struct fsl_mc_io *mc_io,
+	      uint32_t cmd_flags,
+	      int dpni_id,
+	      uint16_t *token)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN,
+					  cmd_flags,
+					  0);
+	DPNI_CMD_OPEN(cmd, dpni_id);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+	return 0;
+}
+
+int dpni_close(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_create(struct fsl_mc_io *mc_io,
+		uint16_t dprc_token,
+		uint32_t cmd_flags,
+		const struct dpni_cfg *cfg,
+		uint32_t *obj_id)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
+					  cmd_flags,
+					  dprc_token);
+	DPNI_CMD_CREATE(cmd, cfg);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	 MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+
+	return 0;
+}
+
+int dpni_destroy(struct fsl_mc_io *mc_io,
+		 uint16_t dprc_token,
+		 uint32_t cmd_flags,
+		 uint32_t obj_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
+					  cmd_flags,
+					  dprc_token);
+
+	/* set object id to destroy */
+	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_set_pools(struct fsl_mc_io *mc_io,
+		   uint32_t cmd_flags,
+		   uint16_t token,
+		   const struct dpni_pools_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_SET_POOLS(cmd, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_enable(struct fsl_mc_io *mc_io,
+		uint32_t cmd_flags,
+		uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_disable(struct fsl_mc_io *mc_io,
+		 uint32_t cmd_flags,
+		 uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_reset(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_attributes(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			struct dpni_attr *attr)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
+					  cmd_flags,
+					  token);
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_ATTR(cmd, attr);
+
+	return 0;
+}
+
+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
+			     uint32_t cmd_flags,
+			     uint16_t token,
+			      struct dpni_error_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   const struct dpni_buffer_layout *layout,
+			   enum dpni_queue_type type)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, type);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_qdid(struct fsl_mc_io *mc_io,
+		  uint32_t cmd_flags,
+		  uint16_t token,
+		  uint16_t *qdid)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_QDID(cmd, *qdid);
+
+	return 0;
+}
+
+int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
+			    uint32_t cmd_flags,
+			    uint16_t token,
+			    uint16_t *data_offset)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_DATA_OFFSET,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset);
+
+	return 0;
+}
+
+int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
+		      uint32_t cmd_flags,
+		      uint16_t token,
+		      const struct dpni_link_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_SET_LINK_CFG(cmd, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_link_state(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			struct dpni_link_state *state)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_LINK_STATE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_LINK_STATE(cmd, state);
+
+	return 0;
+}
+
+
+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
+			      uint32_t cmd_flags,
+			      uint16_t token,
+			      const uint8_t mac_addr[6])
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
+			      uint32_t cmd_flags,
+			      uint16_t token,
+			      uint8_t mac_addr[6])
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr);
+
+	return 0;
+}
+
+int dpni_add_mac_addr(struct fsl_mc_io *mc_io,
+		      uint32_t cmd_flags,
+		      uint16_t token,
+		      const uint8_t mac_addr[6])
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_remove_mac_addr(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 const uint8_t mac_addr[6])
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION,
+					  cmd_flags, 0);
+
+	/* send command to mc */
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+	return 0;
+}
+
+int dpni_set_queue(struct fsl_mc_io *mc_io,
+	uint32_t cmd_flags,
+	uint16_t token,
+	enum dpni_queue_type type,
+	uint8_t tc,
+	uint8_t index,
+	const struct dpni_queue *queue)
+{
+	struct mc_command cmd = { 0 };
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_queue(struct fsl_mc_io *mc_io,
+	uint32_t cmd_flags,
+	uint16_t token,
+	enum dpni_queue_type type,
+	uint8_t tc,
+	uint8_t index,
+	struct dpni_queue *queue)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE,
+					  cmd_flags,
+					  token);
+	DPNI_CMD_GET_QUEUE(cmd, type, tc, index);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_QUEUE(cmd, queue);
+	return 0;
+}
+
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io,
+	uint32_t cmd_flags,
+	uint16_t token,
+	enum dpni_confirmation_mode mode)
+{
+	struct dpni_tx_confirmation_mode *cmd_params;
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONFIRMATION_MODE,
+					  cmd_flags,
+					  token);
+
+	cmd_params = (struct dpni_tx_confirmation_mode *)cmd.params;
+	cmd_params->confirmation_mode = mode;
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_statistics(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			uint8_t  page,
+			struct dpni_statistics *stat)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_STATISTICS,
+					  cmd_flags, token);
+	DPNI_CMD_GET_STATISTICS(cmd, page);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPNI_RSP_GET_STATISTICS(cmd, stat);
+
+	return 0;
+}
+
+int dpni_reset_statistics(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS,
+					  cmd_flags, token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
diff --git a/roms/u-boot/drivers/net/fsl-mc/dprc.c b/roms/u-boot/drivers/net/fsl-mc/dprc.c
new file mode 100644
index 000000000..e0a2865ab
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dprc.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dprc.h>
+
+int dprc_get_container_id(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  int *container_id)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
+					  cmd_flags,
+					  0);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_CONTAINER_ID(cmd, *container_id);
+
+	return 0;
+}
+
+int dprc_open(struct fsl_mc_io *mc_io,
+	      uint32_t cmd_flags,
+	      int container_id,
+	      uint16_t *token)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags,
+					  0);
+	DPRC_CMD_OPEN(cmd, container_id);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+	return 0;
+}
+
+int dprc_close(struct fsl_mc_io *mc_io,
+	       uint32_t cmd_flags,
+	       uint16_t token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dprc_create_container(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  uint16_t token,
+			  struct dprc_cfg *cfg,
+			  int *child_container_id,
+			  uint64_t *child_portal_paddr)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	DPRC_CMD_CREATE_CONTAINER(cmd, cfg);
+
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id,
+				  *child_portal_paddr);
+
+	return 0;
+}
+
+int dprc_destroy_container(struct fsl_mc_io *mc_io,
+			   uint32_t cmd_flags,
+			   uint16_t token,
+			   int child_container_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dprc_reset_container(struct fsl_mc_io *mc_io,
+			 uint32_t cmd_flags,
+			 uint16_t token,
+			 int child_container_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_RESET_CONTAINER(cmd, child_container_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dprc_get_attributes(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			struct dprc_attributes *attr)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_ATTRIBUTES(cmd, attr);
+
+	return 0;
+}
+
+int dprc_get_obj_count(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       int *obj_count)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_OBJ_COUNT(cmd, *obj_count);
+
+	return 0;
+}
+
+int dprc_get_obj(struct fsl_mc_io *mc_io,
+		 uint32_t cmd_flags,
+		 uint16_t token,
+		 int obj_index,
+		 struct dprc_obj_desc *obj_desc)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_GET_OBJ(cmd, obj_index);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_OBJ(cmd, obj_desc);
+
+	return 0;
+}
+
+int dprc_get_res_count(struct fsl_mc_io *mc_io,
+		       uint32_t cmd_flags,
+		       uint16_t token,
+		       char *type,
+		       int *res_count)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	*res_count = 0;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_GET_RES_COUNT(cmd, type);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_RES_COUNT(cmd, *res_count);
+
+	return 0;
+}
+
+int dprc_get_res_ids(struct fsl_mc_io *mc_io,
+		     uint32_t cmd_flags,
+		     uint16_t token,
+		     char *type,
+		     struct dprc_res_ids_range_desc *range_desc)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_GET_RES_IDS(cmd, range_desc, type);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_RES_IDS(cmd, range_desc);
+
+	return 0;
+}
+
+int dprc_get_obj_region(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			char *obj_type,
+			int obj_id,
+			uint8_t region_index,
+			struct dprc_region_desc *region_desc)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_OBJ_REGION(cmd, region_desc);
+
+	return 0;
+}
+
+int dprc_connect(struct fsl_mc_io *mc_io,
+		 uint32_t cmd_flags,
+		 uint16_t token,
+		 const struct dprc_endpoint *endpoint1,
+		 const struct dprc_endpoint *endpoint2,
+		 const struct dprc_connection_cfg *cfg)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dprc_disconnect(struct fsl_mc_io *mc_io,
+		    uint32_t cmd_flags,
+		    uint16_t token,
+		    const struct dprc_endpoint *endpoint)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_DISCONNECT(cmd, endpoint);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dprc_get_connection(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			const struct dprc_endpoint *endpoint1,
+			struct dprc_endpoint *endpoint2,
+			int *state)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
+					  cmd_flags,
+					  token);
+	DPRC_CMD_GET_CONNECTION(cmd, endpoint1);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	DPRC_RSP_GET_CONNECTION(cmd, endpoint2, *state);
+
+	return 0;
+}
+
+int dprc_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
+					  cmd_flags, 0);
+
+	/* send command to mc */
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/dpsparser.c b/roms/u-boot/drivers/net/fsl-mc/dpsparser.c
new file mode 100644
index 000000000..cfd1ba66a
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/dpsparser.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Data Path Soft Parser
+ *
+ * Copyright 2018 NXP
+ */
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpsparser.h>
+
+int dpsparser_open(struct fsl_mc_io *mc_io,
+		   u32 cmd_flags,
+		   u16 *token)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_OPEN,
+					  cmd_flags,
+					  0);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	*token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+	return err;
+}
+
+int dpsparser_close(struct fsl_mc_io *mc_io,
+		    u32 cmd_flags,
+		    u16 token)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_CLOSE, cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpsparser_create(struct fsl_mc_io *mc_io,
+		     u16 token,
+		     u32 cmd_flags,
+		     u32 *obj_id)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_CREATE,
+					  cmd_flags,
+					  token);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	MC_CMD_READ_OBJ_ID(cmd, *obj_id);
+
+	return 0;
+}
+
+int dpsparser_destroy(struct fsl_mc_io *mc_io,
+		      u16 token,
+		      u32 cmd_flags,
+		      u32 obj_id)
+{
+	struct mc_command cmd = { 0 };
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_DESTROY,
+					  cmd_flags,
+					  token);
+
+	/* set object id to destroy */
+	CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id);
+
+	/* send command to mc*/
+	return mc_send_command(mc_io, &cmd);
+}
+
+int dpsparser_apply_spb(struct fsl_mc_io *mc_io,
+			u32 cmd_flags,
+			u16 token,
+			u64 blob_addr,
+			u16 *error)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_APPLY_SPB,
+					  cmd_flags,
+					  token);
+	DPSPARSER_CMD_BLOB_SET_ADDR(cmd, blob_addr);
+
+	/* send command to mc*/
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters: MC error code */
+	DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, *error);
+
+	return 0;
+}
+
+int dpsparser_get_api_version(struct fsl_mc_io *mc_io,
+			      u32 cmd_flags,
+			      u16 *major_ver,
+			      u16 *minor_ver)
+{
+	struct mc_command cmd = { 0 };
+	int err;
+
+	/* prepare command */
+	cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_GET_API_VERSION,
+					  cmd_flags, 0);
+
+	/* send command to mc */
+	err = mc_send_command(mc_io, &cmd);
+	if (err)
+		return err;
+
+	/* retrieve response parameters */
+	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/roms/u-boot/drivers/net/fsl-mc/fsl_dpmng_cmd.h
new file mode 100644
index 000000000..e18c88da0
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/fsl_dpmng_cmd.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+#ifndef __FSL_DPMNG_CMD_H
+#define __FSL_DPMNG_CMD_H
+
+/* Command IDs */
+#define DPMNG_CMDID_GET_VERSION			0x8311
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, uint32_t, mc_ver_info->revision); \
+	MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, mc_ver_info->minor); \
+} while (0)
+
+#endif /* __FSL_DPMNG_CMD_H */
diff --git a/roms/u-boot/drivers/net/fsl-mc/mc.c b/roms/u-boot/drivers/net/fsl-mc/mc.c
new file mode 100644
index 000000000..972db4cf3
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/mc.c
@@ -0,0 +1,1955 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018, 2020 NXP
+ */
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <image.h>
+#include <log.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+#include <linux/bug.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <net.h>
+#include <fdt_support.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_private.h>
+#include <fsl-mc/fsl_dpmng.h>
+#include <fsl-mc/fsl_dprc.h>
+#include <fsl-mc/fsl_dpio.h>
+#include <fsl-mc/fsl_dpni.h>
+#include <fsl-mc/fsl_dpsparser.h>
+#include <fsl-mc/fsl_qbman_portal.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#define MC_RAM_BASE_ADDR_ALIGNMENT  (512UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK	(~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
+#define MC_RAM_SIZE_ALIGNMENT	    (256UL * 1024 * 1024)
+
+#define MC_MEM_SIZE_ENV_VAR	"mcmemsize"
+#define MC_BOOT_TIMEOUT_ENV_VAR	"mcboottimeout"
+#define MC_BOOT_ENV_VAR		"mcinitcmd"
+#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
+
+DECLARE_GLOBAL_DATA_PTR;
+static int mc_memset_resv_ram;
+static struct mc_version mc_ver_info;
+static int mc_boot_status = -1;
+static int mc_dpl_applied = -1;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+static int mc_aiop_applied = -1;
+#endif
+struct fsl_mc_io *root_mc_io = NULL;
+struct fsl_mc_io *dflt_mc_io = NULL; /* child container */
+uint16_t root_dprc_handle = 0;
+uint16_t dflt_dprc_handle = 0;
+int child_dprc_id;
+struct fsl_dpbp_obj *dflt_dpbp = NULL;
+struct fsl_dpio_obj *dflt_dpio = NULL;
+struct fsl_dpni_obj *dflt_dpni = NULL;
+static u64 mc_lazy_dpl_addr;
+static u32 dpsparser_obj_id;
+static u16 dpsparser_handle;
+static char *mc_err_msg_apply_spb[] = MC_ERROR_MSG_APPLY_SPB;
+
+#ifdef DEBUG
+void dump_ram_words(const char *title, void *addr)
+{
+	int i;
+	uint32_t *words = addr;
+
+	printf("Dumping beginning of %s (%p):\n", title, addr);
+	for (i = 0; i < 16; i++)
+		printf("%#x ", words[i]);
+
+	printf("\n");
+}
+
+void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
+{
+	printf("MC CCSR registers:\n"
+		"reg_gcr1 %#x\n"
+		"reg_gsr %#x\n"
+		"reg_sicbalr %#x\n"
+		"reg_sicbahr %#x\n"
+		"reg_sicapr %#x\n"
+		"reg_mcfbalr %#x\n"
+		"reg_mcfbahr %#x\n"
+		"reg_mcfapr %#x\n"
+		"reg_psr %#x\n",
+		mc_ccsr_regs->reg_gcr1,
+		mc_ccsr_regs->reg_gsr,
+		mc_ccsr_regs->reg_sicbalr,
+		mc_ccsr_regs->reg_sicbahr,
+		mc_ccsr_regs->reg_sicapr,
+		mc_ccsr_regs->reg_mcfbalr,
+		mc_ccsr_regs->reg_mcfbahr,
+		mc_ccsr_regs->reg_mcfapr,
+		mc_ccsr_regs->reg_psr);
+}
+#else
+
+#define dump_ram_words(title, addr)
+#define dump_mc_ccsr_regs(mc_ccsr_regs)
+
+#endif /* DEBUG */
+
+/**
+ * Copying MC firmware or DPL image to DDR
+ */
+static int mc_copy_image(const char *title,
+			 u64 image_addr, u32 image_size, u64 mc_ram_addr)
+{
+	debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
+	memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
+	flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
+	return 0;
+}
+
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
+/**
+ * MC firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates
+ * raw image address and size values.
+ * Returns 0 on success and a negative errno on error.
+ * task fail.
+ **/
+int parse_mc_firmware_fit_image(u64 mc_fw_addr,
+				const void **raw_image_addr,
+				size_t *raw_image_size)
+{
+	int format;
+	void *fit_hdr;
+	int node_offset;
+	const void *data;
+	size_t size;
+	const char *uname = "firmware";
+
+	fit_hdr = (void *)mc_fw_addr;
+
+	/* Check if Image is in FIT format */
+	format = genimg_get_format(fit_hdr);
+
+	if (format != IMAGE_FORMAT_FIT) {
+		printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
+		return -EINVAL;
+	}
+
+	if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+		printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
+		return -EINVAL;
+	}
+
+	node_offset = fit_image_get_node(fit_hdr, uname);
+
+	if (node_offset < 0) {
+		printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
+		return -ENOENT;
+	}
+
+	/* Verify MC firmware image */
+	if (!(fit_image_verify(fit_hdr, node_offset))) {
+		printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
+		return -EINVAL;
+	}
+
+	/* Get address and size of raw image */
+	fit_image_get_data(fit_hdr, node_offset, &data, &size);
+
+	*raw_image_addr = data;
+	*raw_image_size = size;
+
+	return 0;
+}
+#endif
+
+#define MC_DT_INCREASE_SIZE	64
+
+enum mc_fixup_type {
+	MC_FIXUP_DPL,
+	MC_FIXUP_DPC
+};
+
+static int mc_fixup_mac_addr(void *blob, int nodeoffset,
+#ifdef CONFIG_DM_ETH
+			     const char *propname, struct udevice *eth_dev,
+#else
+			     const char *propname, struct eth_device *eth_dev,
+#endif
+			     enum mc_fixup_type type)
+{
+#ifdef CONFIG_DM_ETH
+	struct eth_pdata *plat = dev_get_plat(eth_dev);
+	unsigned char *enetaddr = plat->enetaddr;
+	int eth_index = dev_seq(eth_dev);
+#else
+	unsigned char *enetaddr = eth_dev->enetaddr;
+	int eth_index = eth_dev->index;
+#endif
+	int err = 0, len = 0, size, i;
+	unsigned char env_enetaddr[ARP_HLEN];
+	unsigned int enetaddr_32[ARP_HLEN];
+	void *val = NULL;
+
+	switch (type) {
+	case MC_FIXUP_DPL:
+		/* DPL likes its addresses on 32 * ARP_HLEN bits */
+		for (i = 0; i < ARP_HLEN; i++)
+			enetaddr_32[i] = cpu_to_fdt32(enetaddr[i]);
+		val = enetaddr_32;
+		len = sizeof(enetaddr_32);
+		break;
+	case MC_FIXUP_DPC:
+		val = enetaddr;
+		len = ARP_HLEN;
+		break;
+	}
+
+	/* MAC address property present */
+	if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
+		/* u-boot MAC addr randomly assigned - leave the present one */
+		if (!eth_env_get_enetaddr_by_index("eth", eth_index,
+						   env_enetaddr))
+			return err;
+	} else {
+		size = MC_DT_INCREASE_SIZE + strlen(propname) + len;
+		/* make room for mac address property */
+		err = fdt_increase_size(blob, size);
+		if (err) {
+			printf("fdt_increase_size: err=%s\n",
+			       fdt_strerror(err));
+			return err;
+		}
+	}
+
+	err = fdt_setprop(blob, nodeoffset, propname, val, len);
+	if (err) {
+		printf("fdt_setprop: err=%s\n", fdt_strerror(err));
+		return err;
+	}
+
+	return err;
+}
+
+#define is_dpni(s) (s != NULL ? !strncmp(s, "dpni@", 5) : 0)
+
+const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
+{
+	int connoffset = fdt_path_offset(blob, "/connections"), off;
+	const char *s1, *s2;
+
+	for (off = fdt_first_subnode(blob, connoffset);
+	     off >= 0;
+	     off = fdt_next_subnode(blob, off)) {
+		s1 = fdt_stringlist_get(blob, off, "endpoint1", 0, NULL);
+		s2 = fdt_stringlist_get(blob, off, "endpoint2", 0, NULL);
+
+		if (!s1 || !s2)
+			continue;
+
+		if (strcmp(endpoint, s1) == 0)
+			return s2;
+
+		if (strcmp(endpoint, s2) == 0)
+			return s1;
+	}
+
+	return NULL;
+}
+
+static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
+#ifdef CONFIG_DM_ETH
+				 struct udevice *eth_dev)
+#else
+				 struct eth_device *eth_dev)
+#endif
+{
+	int objoff = fdt_path_offset(blob, "/objects");
+	int dpmacoff = -1, dpnioff = -1;
+	const char *endpoint;
+	char mac_name[10];
+	int err;
+
+	sprintf(mac_name, "dpmac@%d", dpmac_id);
+	dpmacoff = fdt_subnode_offset(blob, objoff, mac_name);
+	if (dpmacoff < 0)
+		/* dpmac not defined in DPL, so skip it. */
+		return 0;
+
+	err = mc_fixup_mac_addr(blob, dpmacoff, "mac_addr", eth_dev,
+				MC_FIXUP_DPL);
+	if (err) {
+		printf("Error fixing up dpmac mac_addr in DPL\n");
+		return err;
+	}
+
+	/* now we need to figure out if there is any
+	 * DPNI connected to this MAC, so we walk the
+	 * connection list
+	 */
+	endpoint = dpl_get_connection_endpoint(blob, mac_name);
+	if (!is_dpni(endpoint))
+		return 0;
+
+	/* let's see if we can fixup the DPNI as well */
+	dpnioff = fdt_subnode_offset(blob, objoff, endpoint);
+	if (dpnioff < 0)
+		/* DPNI not defined in DPL in the objects area */
+		return 0;
+
+	return mc_fixup_mac_addr(blob, dpnioff, "mac_addr", eth_dev,
+				 MC_FIXUP_DPL);
+}
+
+void fdt_fixup_mc_ddr(u64 *base, u64 *size)
+{
+	u64 mc_size = mc_get_dram_block_size();
+
+	if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
+		*base = mc_get_dram_addr() + mc_size;
+		*size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
+	}
+}
+
+void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
+{
+	u32 *prop;
+	u32 iommu_map[4], phandle;
+	int offset;
+	int lenp;
+
+	/* find fsl-mc node */
+	offset = fdt_path_offset(blob, "/soc/fsl-mc");
+	if (offset < 0)
+		offset = fdt_path_offset(blob, "/fsl-mc");
+	if (offset < 0) {
+		printf("%s: fsl-mc: ERR: fsl-mc node not found in DT, err %d\n",
+		       __func__, offset);
+		return;
+	}
+
+	prop = fdt_getprop_w(blob, offset, "iommu-map", &lenp);
+	if (!prop) {
+		debug("%s: fsl-mc: ERR: missing iommu-map in fsl-mc bus node\n",
+		      __func__);
+		return;
+	}
+
+	iommu_map[0] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
+	iommu_map[1] = *++prop;
+	iommu_map[2] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
+	iommu_map[3] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_END -
+		FSL_DPAA2_STREAM_ID_START + 1);
+
+	fdt_setprop_inplace(blob, offset, "iommu-map",
+			    iommu_map, sizeof(iommu_map));
+
+	/* get phandle to MSI controller */
+	prop = (u32 *)fdt_getprop(blob, offset, "msi-parent", 0);
+	if (!prop) {
+		debug("\n%s: ERROR: missing msi-parent\n", __func__);
+		return;
+	}
+	phandle = fdt32_to_cpu(*prop);
+
+	/* also set msi-map property */
+	fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
+	fdt_appendprop_u32(blob, offset, "msi-map", phandle);
+	fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
+	fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_END -
+			   FSL_DPAA2_STREAM_ID_START + 1);
+}
+
+static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
+#ifdef CONFIG_DM_ETH
+				 struct udevice *eth_dev)
+#else
+				 struct eth_device *eth_dev)
+#endif
+{
+	int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
+	int err = 0;
+	char mac_name[10];
+	const char link_type_mode[] = "MAC_LINK_TYPE_FIXED";
+
+	sprintf(mac_name, "mac@%d", dpmac_id);
+
+	/* node not found - create it */
+	noff = fdt_subnode_offset(blob, nodeoffset, (const char *)mac_name);
+	if (noff < 0) {
+		err = fdt_increase_size(blob, 200);
+		if (err) {
+			printf("fdt_increase_size: err=%s\n",
+				fdt_strerror(err));
+			return err;
+		}
+
+		noff = fdt_add_subnode(blob, nodeoffset, mac_name);
+		if (noff < 0) {
+			printf("fdt_add_subnode: err=%s\n",
+			       fdt_strerror(err));
+			return err;
+		}
+
+		/* add default property of fixed link */
+		err = fdt_appendprop_string(blob, noff,
+					    "link_type", link_type_mode);
+		if (err) {
+			printf("fdt_appendprop_string: err=%s\n",
+				fdt_strerror(err));
+			return err;
+		}
+	}
+
+	return mc_fixup_mac_addr(blob, noff, "port_mac_address", eth_dev,
+				 MC_FIXUP_DPC);
+}
+
+static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
+{
+	int i, err = 0, ret = 0;
+#ifdef CONFIG_DM_ETH
+#define ETH_NAME_LEN 20
+	struct udevice *eth_dev;
+#else
+	struct eth_device *eth_dev;
+#endif
+	char ethname[ETH_NAME_LEN];
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+		/* port not enabled */
+		if (wriop_is_enabled_dpmac(i) != 1)
+			continue;
+
+		snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", i,
+			 phy_interface_strings[wriop_get_enet_if(i)]);
+
+		eth_dev = eth_get_dev_by_name(ethname);
+		if (eth_dev == NULL)
+			continue;
+
+		switch (type) {
+		case MC_FIXUP_DPL:
+			err = mc_fixup_dpl_mac_addr(blob, i, eth_dev);
+			break;
+		case MC_FIXUP_DPC:
+			err = mc_fixup_dpc_mac_addr(blob, i, eth_dev);
+			break;
+		default:
+			break;
+		}
+
+		if (err)
+			printf("fsl-mc: ERROR fixing mac address for %s\n",
+			       ethname);
+		ret |= err;
+	}
+
+	return ret;
+}
+
+static int mc_fixup_dpc(u64 dpc_addr)
+{
+	void *blob = (void *)dpc_addr;
+	int nodeoffset, err = 0;
+
+	/* delete any existing ICID pools */
+	nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
+	if (fdt_del_node(blob, nodeoffset) < 0)
+		printf("\nfsl-mc: WARNING: could not delete ICID pool\n");
+
+	/* add a new pool */
+	nodeoffset = fdt_path_offset(blob, "/resources");
+	if (nodeoffset < 0) {
+		printf("\nfsl-mc: ERROR: DPC is missing /resources\n");
+		return -EINVAL;
+	}
+	nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools");
+	nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0");
+	do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
+			     "base_icid", FSL_DPAA2_STREAM_ID_START, 1);
+	do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
+			     "num",
+			     FSL_DPAA2_STREAM_ID_END -
+			     FSL_DPAA2_STREAM_ID_START + 1, 1);
+
+	/* fixup MAC addresses for dpmac ports */
+	nodeoffset = fdt_path_offset(blob, "/board_info/ports");
+	if (nodeoffset < 0) {
+		err = fdt_increase_size(blob, 512);
+		if (err) {
+			printf("fdt_increase_size: err=%s\n",
+			       fdt_strerror(err));
+			goto out;
+		}
+		nodeoffset = fdt_path_offset(blob, "/board_info");
+		if (nodeoffset < 0)
+			nodeoffset = fdt_add_subnode(blob, 0, "board_info");
+
+		nodeoffset = fdt_add_subnode(blob, nodeoffset, "ports");
+	}
+
+	err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
+
+out:
+	flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
+
+	return err;
+}
+
+static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
+{
+	u64 mc_dpc_offset;
+#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
+	int error;
+	void *dpc_fdt_hdr;
+	int dpc_size;
+#endif
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
+	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
+		     CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
+
+	mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
+#else
+#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
+#endif
+
+	/*
+	 * Load the MC DPC blob in the MC private DRAM block:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
+	printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
+#else
+	/*
+	 * Get address and size of the DPC blob stored in flash:
+	 */
+	dpc_fdt_hdr = (void *)mc_dpc_addr;
+
+	error = fdt_check_header(dpc_fdt_hdr);
+	if (error != 0) {
+		/*
+		 * Don't return with error here, since the MC firmware can
+		 * still boot without a DPC
+		 */
+		printf("\nfsl-mc: WARNING: No DPC image found");
+		return 0;
+	}
+
+	dpc_size = fdt_totalsize(dpc_fdt_hdr);
+	if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
+		printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
+		       dpc_size);
+		return -EINVAL;
+	}
+
+	mc_copy_image("MC DPC blob",
+		      (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
+#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
+
+	if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset))
+		return -EINVAL;
+
+	dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
+	return 0;
+}
+
+
+static int mc_fixup_dpl(u64 dpl_addr)
+{
+	void *blob = (void *)dpl_addr;
+	u32 ver = fdt_getprop_u32_default(blob, "/", "dpl-version", 0);
+	int err = 0;
+
+	/* The DPL fixup for mac addresses is only relevant
+	 * for old-style DPLs
+	 */
+	if (ver >= 10)
+		return 0;
+
+	err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPL);
+	flush_dcache_range(dpl_addr, dpl_addr + fdt_totalsize(blob));
+
+	return err;
+}
+
+static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
+{
+	u64 mc_dpl_offset;
+#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
+	int error;
+	void *dpl_fdt_hdr;
+	int dpl_size;
+#endif
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
+	BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+		     CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+
+	mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+#else
+#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
+#endif
+
+	/*
+	 * Load the MC DPL blob in the MC private DRAM block:
+	 */
+#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
+	printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
+#else
+	/*
+	 * Get address and size of the DPL blob stored in flash:
+	 */
+	dpl_fdt_hdr = (void *)mc_dpl_addr;
+
+	error = fdt_check_header(dpl_fdt_hdr);
+	if (error != 0) {
+		printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
+		return error;
+	}
+
+	dpl_size = fdt_totalsize(dpl_fdt_hdr);
+	if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+		printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
+		       dpl_size);
+		return -EINVAL;
+	}
+
+	mc_copy_image("MC DPL blob",
+		      (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
+#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
+
+	if (mc_fixup_dpl(mc_ram_addr + mc_dpl_offset))
+		return -EINVAL;
+	dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
+	return 0;
+}
+
+/**
+ * Return the MC boot timeout value in milliseconds
+ */
+static unsigned long get_mc_boot_timeout_ms(void)
+{
+	unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+
+	char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
+
+	if (timeout_ms_env_var) {
+		timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
+		if (timeout_ms == 0) {
+			printf("fsl-mc: WARNING: Invalid value for \'"
+			       MC_BOOT_TIMEOUT_ENV_VAR
+			       "\' environment variable: %lu\n",
+			       timeout_ms);
+
+			timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+		}
+	}
+
+	return timeout_ms;
+}
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+
+__weak bool soc_has_aiop(void)
+{
+	return false;
+}
+
+static int load_mc_aiop_img(u64 aiop_fw_addr)
+{
+	u64 mc_ram_addr = mc_get_dram_addr();
+#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
+	void *aiop_img;
+#endif
+
+	/* Check if AIOP is available */
+	if (!soc_has_aiop())
+		return -ENODEV;
+	/*
+	 * Load the MC AIOP image in the MC private DRAM block:
+	 */
+
+#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
+	printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
+	       CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+#else
+	aiop_img = (void *)aiop_fw_addr;
+	mc_copy_image("MC AIOP image",
+		      (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+		      mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+#endif
+	mc_aiop_applied = 0;
+
+	return 0;
+}
+#endif
+
+static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
+{
+	u32 reg_gsr;
+	u32 mc_fw_boot_status;
+	unsigned long timeout_ms = get_mc_boot_timeout_ms();
+	struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+
+	dmb();
+	assert(timeout_ms > 0);
+	for (;;) {
+		udelay(1000);	/* throttle polling */
+		reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
+		mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
+		if (mc_fw_boot_status & 0x1)
+			break;
+
+		timeout_ms--;
+		if (timeout_ms == 0)
+			break;
+	}
+
+	if (timeout_ms == 0) {
+		printf("ERROR: timeout\n");
+
+		/* TODO: Get an error status from an MC CCSR register */
+		return -ETIMEDOUT;
+	}
+
+	if (mc_fw_boot_status != 0x1) {
+		/*
+		 * TODO: Identify critical errors from the GSR register's FS
+		 * field and for those errors, set error to -ENODEV or other
+		 * appropriate errno, so that the status property is set to
+		 * failure in the fsl,dprc device tree node.
+		 */
+		printf("WARNING: Firmware returned an error (GSR: %#x)\n",
+		       reg_gsr);
+	} else {
+		printf("SUCCESS\n");
+	}
+
+
+	*final_reg_gsr = reg_gsr;
+	return 0;
+}
+
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
+{
+	int error = 0;
+	int portal_id = 0;
+	struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+	u64 mc_ram_addr = mc_get_dram_addr();
+	u32 reg_gsr;
+	u32 reg_mcfbalr;
+#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
+	const void *raw_image_addr;
+	size_t raw_image_size = 0;
+#endif
+	u8 mc_ram_num_256mb_blocks;
+	size_t mc_ram_size = mc_get_dram_block_size();
+
+	mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
+
+	if (mc_ram_num_256mb_blocks >= 0xff) {
+		error = -EINVAL;
+		printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
+		       mc_ram_size);
+		goto out;
+	}
+
+	/*
+	 * To support 128 MB DDR Size for MC
+	 */
+	if (mc_ram_num_256mb_blocks == 0)
+		mc_ram_num_256mb_blocks = 0xFF;
+
+	/*
+	 * Management Complex cores should be held at reset out of POR.
+	 * U-Boot should be the first software to touch MC. To be safe,
+	 * we reset all cores again by setting GCR1 to 0. It doesn't do
+	 * anything if they are held at reset. After we setup the firmware
+	 * we kick off MC by deasserting the reset bit for core 0, and
+	 * deasserting the reset bits for Command Portal Managers.
+	 * The stop bits are not touched here. They are used to stop the
+	 * cores when they are active. Setting stop bits doesn't stop the
+	 * cores from fetching instructions when they are released from
+	 * reset.
+	 */
+	out_le32(&mc_ccsr_regs->reg_gcr1, 0);
+	dmb();
+
+#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
+	printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
+#else
+	error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
+					    &raw_image_size);
+	if (error != 0)
+		goto out;
+	/*
+	 * Load the MC FW at the beginning of the MC private DRAM block:
+	 */
+	mc_copy_image("MC Firmware",
+		      (u64)raw_image_addr, raw_image_size, mc_ram_addr);
+#endif
+	dump_ram_words("firmware", (void *)mc_ram_addr);
+
+	error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
+	if (error != 0)
+		goto out;
+
+	debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
+	dump_mc_ccsr_regs(mc_ccsr_regs);
+
+	/*
+	 * Tell MC what is the address range of the DRAM block assigned to it:
+	 */
+	if (mc_ram_num_256mb_blocks < 0xFF) {
+		reg_mcfbalr = (u32)mc_ram_addr |
+				(mc_ram_num_256mb_blocks - 1);
+	} else {
+		reg_mcfbalr = (u32)mc_ram_addr |
+				(mc_ram_num_256mb_blocks);
+	}
+
+	out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
+	out_le32(&mc_ccsr_regs->reg_mcfbahr,
+		 (u32)(mc_ram_addr >> 32));
+	out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
+
+	/*
+	 * Tell the MC that we want delayed DPL deployment.
+	 */
+	out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
+
+	printf("\nfsl-mc: Booting Management Complex ... ");
+
+	/*
+	 * Deassert reset and release MC core 0 to run
+	 */
+	out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
+	error = wait_for_mc(true, &reg_gsr);
+	if (error != 0)
+		goto out;
+
+	/*
+	 * TODO: need to obtain the portal_id for the root container from the
+	 * DPL
+	 */
+	portal_id = 0;
+
+	/*
+	 * Initialize the global default MC portal
+	 * And check that the MC firmware is responding portal commands:
+	 */
+	root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
+	if (!root_mc_io) {
+		printf(" No memory: calloc() failed\n");
+		return -ENOMEM;
+	}
+
+	root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
+	debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
+	      portal_id, root_mc_io->mmio_regs);
+
+	error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
+	if (error != 0) {
+		printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
+		       error);
+		goto out;
+	}
+
+	printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
+	       mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
+	       reg_gsr & GSR_FS_MASK);
+
+out:
+	if (error != 0)
+		mc_boot_status = error;
+	else
+		mc_boot_status = 0;
+
+	return error;
+}
+
+int mc_apply_dpl(u64 mc_dpl_addr)
+{
+	struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+	int error = 0;
+	u32 reg_gsr;
+	u64 mc_ram_addr = mc_get_dram_addr();
+	size_t mc_ram_size = mc_get_dram_block_size();
+
+	if (!mc_dpl_addr)
+		return -1;
+
+	error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
+	if (error != 0)
+		return error;
+
+	/*
+	 * Tell the MC to deploy the DPL:
+	 */
+	out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
+	printf("fsl-mc: Deploying data path layout ... ");
+	error = wait_for_mc(false, &reg_gsr);
+
+	if (!error)
+		mc_dpl_applied = 0;
+
+	return error;
+}
+
+int get_mc_boot_status(void)
+{
+	return mc_boot_status;
+}
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+int get_aiop_apply_status(void)
+{
+	return mc_aiop_applied;
+}
+#endif
+
+int get_dpl_apply_status(void)
+{
+	return mc_dpl_applied;
+}
+
+int is_lazy_dpl_addr_valid(void)
+{
+	return !!mc_lazy_dpl_addr;
+}
+
+/*
+ * Return the MC address of private DRAM block.
+ * As per MC design document, MC initial base address
+ * should be least significant 512MB address of MC private
+ * memory, i.e. address should point to end address masked
+ * with 512MB offset in private DRAM block.
+ */
+u64 mc_get_dram_addr(void)
+{
+	size_t mc_ram_size = mc_get_dram_block_size();
+
+	if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) {
+		mc_memset_resv_ram = 1;
+		memset((void *)gd->arch.resv_ram, 0, mc_ram_size);
+	}
+
+	return (gd->arch.resv_ram + mc_ram_size - 1) &
+		MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
+}
+
+/**
+ * Return the actual size of the MC private DRAM block.
+ */
+unsigned long mc_get_dram_block_size(void)
+{
+	unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+
+	char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
+
+	if (dram_block_size_env_var) {
+		dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
+						 16);
+
+		if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
+			printf("fsl-mc: WARNING: Invalid value for \'"
+			       MC_MEM_SIZE_ENV_VAR
+			       "\' environment variable: %lu\n",
+			       dram_block_size);
+
+			dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
+		}
+	}
+
+	return dram_block_size;
+}
+
+int fsl_mc_ldpaa_init(struct bd_info *bis)
+{
+	int i;
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
+		if (wriop_is_enabled_dpmac(i) == 1)
+			ldpaa_eth_init(i, wriop_get_enet_if(i));
+	return 0;
+}
+
+static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
+{
+	int error;
+	uint16_t major_ver, minor_ver;
+
+	error = dprc_get_api_version(mc_io, 0,
+				     &major_ver,
+				     &minor_ver);
+	if (error < 0) {
+		printf("dprc_get_api_version() failed: %d\n", error);
+		return error;
+	}
+
+	if (major_ver < DPRC_VER_MAJOR || (major_ver == DPRC_VER_MAJOR &&
+					   minor_ver < DPRC_VER_MINOR)) {
+		printf("DPRC version mismatch found %u.%u,",
+		       major_ver, minor_ver);
+		printf("supported version is %u.%u\n",
+		       DPRC_VER_MAJOR, DPRC_VER_MINOR);
+	}
+
+	return error;
+}
+
+static int dpio_init(void)
+{
+	struct qbman_swp_desc p_des;
+	struct dpio_attr attr;
+	struct dpio_cfg dpio_cfg;
+	int err = 0;
+	uint16_t major_ver, minor_ver;
+
+	dflt_dpio = (struct fsl_dpio_obj *)calloc(
+					sizeof(struct fsl_dpio_obj), 1);
+	if (!dflt_dpio) {
+		printf("No memory: calloc() failed\n");
+		err = -ENOMEM;
+		goto err_calloc;
+	}
+	dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
+	dpio_cfg.num_priorities = 8;
+
+	err = dpio_create(dflt_mc_io,
+			  dflt_dprc_handle,
+			  MC_CMD_NO_FLAGS,
+			  &dpio_cfg,
+			  &dflt_dpio->dpio_id);
+	if (err < 0) {
+		printf("dpio_create() failed: %d\n", err);
+		err = -ENODEV;
+		goto err_create;
+	}
+
+	err = dpio_get_api_version(dflt_mc_io, 0,
+				   &major_ver,
+				   &minor_ver);
+	if (err < 0) {
+		printf("dpio_get_api_version() failed: %d\n", err);
+		goto err_get_api_ver;
+	}
+
+	if (major_ver < DPIO_VER_MAJOR || (major_ver == DPIO_VER_MAJOR &&
+					   minor_ver < DPIO_VER_MINOR)) {
+		printf("DPRC version mismatch found %u.%u,",
+		       major_ver,
+		       minor_ver);
+	}
+
+	err = dpio_open(dflt_mc_io,
+			MC_CMD_NO_FLAGS,
+			dflt_dpio->dpio_id,
+			&dflt_dpio->dpio_handle);
+	if (err) {
+		printf("dpio_open() failed\n");
+		goto err_open;
+	}
+
+	memset(&attr, 0, sizeof(struct dpio_attr));
+	err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
+				  dflt_dpio->dpio_handle, &attr);
+	if (err < 0) {
+		printf("dpio_get_attributes() failed: %d\n", err);
+		goto err_get_attr;
+	}
+
+	if (dflt_dpio->dpio_id != attr.id) {
+		printf("dnpi object id and attribute id are not same\n");
+		goto err_attr_not_same;
+	}
+
+#ifdef DEBUG
+	printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+#endif
+	err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+	if (err < 0) {
+		printf("dpio_enable() failed %d\n", err);
+		goto err_get_enable;
+	}
+	debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
+	      attr.qbman_portal_ce_offset,
+	      attr.qbman_portal_ci_offset,
+	      attr.qbman_portal_id,
+	      attr.num_priorities);
+
+	p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
+					+ attr.qbman_portal_ce_offset);
+	p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
+					+ attr.qbman_portal_ci_offset);
+
+	dflt_dpio->sw_portal = qbman_swp_init(&p_des);
+	if (dflt_dpio->sw_portal == NULL) {
+		printf("qbman_swp_init() failed\n");
+		goto err_get_swp_init;
+	}
+	return 0;
+
+err_get_swp_init:
+	dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+err_get_enable:
+err_get_attr:
+err_attr_not_same:
+	dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+err_open:
+err_get_api_ver:
+	dpio_destroy(dflt_mc_io,
+		     dflt_dprc_handle,
+		     MC_CMD_NO_FLAGS,
+		     dflt_dpio->dpio_id);
+err_create:
+	free(dflt_dpio);
+err_calloc:
+	return err;
+}
+
+static int dpio_exit(void)
+{
+	int err;
+
+	err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+	if (err < 0) {
+		printf("dpio_disable() failed: %d\n", err);
+		goto err;
+	}
+
+	dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+	if (err < 0) {
+		printf("dpio_close() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpio_destroy(dflt_mc_io,
+			   dflt_dprc_handle,
+			   MC_CMD_NO_FLAGS,
+			   dflt_dpio->dpio_id);
+	if (err < 0) {
+		printf("dpio_destroy() failed: %d\n", err);
+		goto err;
+	}
+
+#ifdef DEBUG
+	printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+#endif
+
+	if (dflt_dpio)
+		free(dflt_dpio);
+
+	return 0;
+err:
+	return err;
+}
+
+static int dprc_init(void)
+{
+	int err, child_portal_id, container_id;
+	struct dprc_cfg cfg;
+	uint64_t mc_portal_offset;
+
+	/* Open root container */
+	err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id);
+	if (err < 0) {
+		printf("dprc_get_container_id(): Root failed: %d\n", err);
+		goto err_root_container_id;
+	}
+
+#ifdef DEBUG
+	printf("Root container id = %d\n", container_id);
+#endif
+	err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id,
+			&root_dprc_handle);
+	if (err < 0) {
+		printf("dprc_open(): Root Container failed: %d\n", err);
+		goto err_root_open;
+	}
+
+	if (!root_dprc_handle) {
+		printf("dprc_open(): Root Container Handle is not valid\n");
+		goto err_root_open;
+	}
+
+	err = dprc_version_check(root_mc_io, root_dprc_handle);
+	if (err < 0) {
+		printf("dprc_version_check() failed: %d\n", err);
+		goto err_root_open;
+	}
+
+	memset(&cfg, 0, sizeof(struct dprc_cfg));
+	cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
+		      DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
+		      DPRC_CFG_OPT_ALLOC_ALLOWED;
+	cfg.icid = DPRC_GET_ICID_FROM_POOL;
+	cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
+	err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
+			root_dprc_handle,
+			&cfg,
+			&child_dprc_id,
+			&mc_portal_offset);
+	if (err < 0) {
+		printf("dprc_create_container() failed: %d\n", err);
+		goto err_create;
+	}
+
+	dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1);
+	if (!dflt_mc_io) {
+		err  = -ENOMEM;
+		printf(" No memory: calloc() failed\n");
+		goto err_calloc;
+	}
+
+	child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
+	dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
+
+#ifdef DEBUG
+	printf("MC portal of child DPRC container: %d, physical addr %p)\n",
+	       child_dprc_id, dflt_mc_io->mmio_regs);
+#endif
+
+	err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id,
+			&dflt_dprc_handle);
+	if (err < 0) {
+		printf("dprc_open(): Child container failed: %d\n", err);
+		goto err_child_open;
+	}
+
+	if (!dflt_dprc_handle) {
+		printf("dprc_open(): Child container Handle is not valid\n");
+		goto err_child_open;
+	}
+
+	return 0;
+err_child_open:
+	free(dflt_mc_io);
+err_calloc:
+	dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
+			       root_dprc_handle, child_dprc_id);
+err_create:
+	dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
+err_root_open:
+err_root_container_id:
+	return err;
+}
+
+static int dprc_exit(void)
+{
+	int err;
+
+	err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
+	if (err < 0) {
+		printf("dprc_close(): Child failed: %d\n", err);
+		goto err;
+	}
+
+	err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
+				     root_dprc_handle, child_dprc_id);
+	if (err < 0) {
+		printf("dprc_destroy_container() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
+	if (err < 0) {
+		printf("dprc_close(): Root failed: %d\n", err);
+		goto err;
+	}
+
+	if (dflt_mc_io)
+		free(dflt_mc_io);
+
+	if (root_mc_io)
+		free(root_mc_io);
+
+	return 0;
+
+err:
+	return err;
+}
+
+static int dpbp_init(void)
+{
+	int err;
+	struct dpbp_attr dpbp_attr;
+	struct dpbp_cfg dpbp_cfg;
+	uint16_t major_ver, minor_ver;
+
+	dflt_dpbp = (struct fsl_dpbp_obj *)calloc(
+					sizeof(struct fsl_dpbp_obj), 1);
+	if (!dflt_dpbp) {
+		printf("No memory: calloc() failed\n");
+		err = -ENOMEM;
+		goto err_calloc;
+	}
+
+	dpbp_cfg.options = 512;
+
+	err = dpbp_create(dflt_mc_io,
+			  dflt_dprc_handle,
+			  MC_CMD_NO_FLAGS,
+			  &dpbp_cfg,
+			  &dflt_dpbp->dpbp_id);
+
+	if (err < 0) {
+		err = -ENODEV;
+		printf("dpbp_create() failed: %d\n", err);
+		goto err_create;
+	}
+
+	err = dpbp_get_api_version(dflt_mc_io, 0,
+				   &major_ver,
+				   &minor_ver);
+	if (err < 0) {
+		printf("dpbp_get_api_version() failed: %d\n", err);
+		goto err_get_api_ver;
+	}
+
+	if (major_ver < DPBP_VER_MAJOR || (major_ver == DPBP_VER_MAJOR &&
+					   minor_ver < DPBP_VER_MINOR)) {
+		printf("DPBP version mismatch found %u.%u,",
+		       major_ver, minor_ver);
+		printf("supported version is %u.%u\n",
+		       DPBP_VER_MAJOR, DPBP_VER_MINOR);
+	}
+
+	err = dpbp_open(dflt_mc_io,
+			MC_CMD_NO_FLAGS,
+			dflt_dpbp->dpbp_id,
+			&dflt_dpbp->dpbp_handle);
+	if (err) {
+		printf("dpbp_open() failed\n");
+		goto err_open;
+	}
+
+	memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
+	err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
+				  dflt_dpbp->dpbp_handle,
+				  &dpbp_attr);
+	if (err < 0) {
+		printf("dpbp_get_attributes() failed: %d\n", err);
+		goto err_get_attr;
+	}
+
+	if (dflt_dpbp->dpbp_id != dpbp_attr.id) {
+		printf("dpbp object id and attribute id are not same\n");
+		goto err_attr_not_same;
+	}
+
+#ifdef DEBUG
+	printf("Init: DPBP id=0x%x\n", dflt_dpbp->dpbp_attr.id);
+#endif
+
+	err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+	if (err < 0) {
+		printf("dpbp_close() failed: %d\n", err);
+		goto err_close;
+	}
+
+	return 0;
+
+err_get_attr:
+err_attr_not_same:
+	dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+	dpbp_destroy(dflt_mc_io,
+		     dflt_dprc_handle,
+		     MC_CMD_NO_FLAGS,
+		     dflt_dpbp->dpbp_id);
+err_get_api_ver:
+err_close:
+err_open:
+err_create:
+	free(dflt_dpbp);
+err_calloc:
+	return err;
+}
+
+static int dpbp_exit(void)
+{
+	int err;
+
+	err = dpbp_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
+			   dflt_dpbp->dpbp_id);
+	if (err < 0) {
+		printf("dpbp_destroy() failed: %d\n", err);
+		goto err;
+	}
+
+#ifdef DEBUG
+	printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+#endif
+
+	if (dflt_dpbp)
+		free(dflt_dpbp);
+	return 0;
+
+err:
+	return err;
+}
+
+static int dpni_init(void)
+{
+	int err;
+	uint8_t	cfg_buf[256] = {0};
+	struct dpni_cfg dpni_cfg;
+	uint16_t major_ver, minor_ver;
+
+	dflt_dpni = (struct fsl_dpni_obj *)calloc(
+					sizeof(struct fsl_dpni_obj), 1);
+	if (!dflt_dpni) {
+		printf("No memory: calloc() failed\n");
+		err = -ENOMEM;
+		goto err_calloc;
+	}
+
+	memset(&dpni_cfg, 0, sizeof(dpni_cfg));
+	err = dpni_prepare_cfg(&dpni_cfg, &cfg_buf[0]);
+	if (err < 0) {
+		err = -ENODEV;
+		printf("dpni_prepare_cfg() failed: %d\n", err);
+		goto err_prepare_cfg;
+	}
+
+	err = dpni_create(dflt_mc_io,
+			  dflt_dprc_handle,
+			  MC_CMD_NO_FLAGS,
+			  &dpni_cfg,
+			  &dflt_dpni->dpni_id);
+	if (err < 0) {
+		err = -ENODEV;
+		printf("dpni create() failed: %d\n", err);
+		goto err_create;
+	}
+
+	err = dpni_get_api_version(dflt_mc_io, 0,
+				   &major_ver,
+				   &minor_ver);
+	if (err < 0) {
+		printf("dpni_get_api_version() failed: %d\n", err);
+		goto err_get_version;
+	}
+
+	if (major_ver < DPNI_VER_MAJOR || (major_ver == DPNI_VER_MAJOR &&
+					   minor_ver < DPNI_VER_MINOR)) {
+		printf("DPNI version mismatch found %u.%u,",
+		       major_ver, minor_ver);
+		printf("supported version is %u.%u\n",
+		       DPNI_VER_MAJOR, DPNI_VER_MINOR);
+	}
+
+	err = dpni_open(dflt_mc_io,
+			MC_CMD_NO_FLAGS,
+			dflt_dpni->dpni_id,
+			&dflt_dpni->dpni_handle);
+	if (err) {
+		printf("dpni_open() failed\n");
+		goto err_open;
+	}
+
+#ifdef DEBUG
+	printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+#endif
+	err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+	if (err < 0) {
+		printf("dpni_close() failed: %d\n", err);
+		goto err_close;
+	}
+
+	return 0;
+
+err_close:
+	dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+err_open:
+err_get_version:
+	dpni_destroy(dflt_mc_io,
+		     dflt_dprc_handle,
+		     MC_CMD_NO_FLAGS,
+		     dflt_dpni->dpni_id);
+err_create:
+err_prepare_cfg:
+	free(dflt_dpni);
+err_calloc:
+	return err;
+}
+
+static int dpni_exit(void)
+{
+	int err;
+
+	err = dpni_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
+			   dflt_dpni->dpni_id);
+	if (err < 0) {
+		printf("dpni_destroy() failed: %d\n", err);
+		goto err;
+	}
+
+#ifdef DEBUG
+	printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+#endif
+
+	if (dflt_dpni)
+		free(dflt_dpni);
+	return 0;
+
+err:
+	return err;
+}
+
+static bool is_dpsparser_supported(void)
+{
+	/* dpsparser support was first introduced in MC version: 10.12.0 */
+	if (mc_ver_info.major < 10)
+		return false;
+	if (mc_ver_info.major == 10)
+		return (mc_ver_info.minor >= 12);
+	return true;
+}
+
+static int dpsparser_version_check(struct fsl_mc_io *mc_io)
+{
+	int error;
+	u16 major_ver, minor_ver;
+
+	if (!is_dpsparser_supported())
+		return 0;
+
+	error = dpsparser_get_api_version(mc_io, 0,
+					  &major_ver,
+					  &minor_ver);
+	if (error < 0) {
+		printf("dpsparser_get_api_version() failed: %d\n", error);
+		return error;
+	}
+
+	if (major_ver < DPSPARSER_VER_MAJOR || (major_ver ==
+	    DPSPARSER_VER_MAJOR && minor_ver < DPSPARSER_VER_MINOR)) {
+		printf("DPSPARSER version mismatch found %u.%u,",
+		       major_ver, minor_ver);
+		printf("supported version is %u.%u\n",
+		       DPSPARSER_VER_MAJOR, DPSPARSER_VER_MINOR);
+	}
+
+	return error;
+}
+
+static int dpsparser_init(void)
+{
+	int err = 0;
+
+	if (!is_dpsparser_supported())
+		return 0;
+
+	err = dpsparser_create(dflt_mc_io,
+			       dflt_dprc_handle,
+			       MC_CMD_NO_FLAGS,
+			       &dpsparser_obj_id);
+	if (err)
+		printf("dpsparser_create() failed\n");
+
+	err = dpsparser_version_check(dflt_mc_io);
+	if (err < 0) {
+		printf("dpsparser_version_check() failed: %d\n", err);
+		goto err_version_check;
+	}
+
+	err = dpsparser_open(dflt_mc_io,
+			     MC_CMD_NO_FLAGS,
+			     &dpsparser_handle);
+	if (err < 0) {
+		printf("dpsparser_open() failed: %d\n", err);
+		goto err_open;
+	}
+
+	return err;
+
+err_open:
+err_version_check:
+	dpsparser_destroy(dflt_mc_io,
+			  dflt_dprc_handle,
+			  MC_CMD_NO_FLAGS, dpsparser_obj_id);
+
+	return err;
+}
+
+#ifdef DPSPARSER_DESTROY
+/* TODO: refactoring needed in the future to allow DPSPARSER object destroy
+ * Workaround: DO NOT destroy DPSPARSER object because it needs to be available
+ * on Apply DPL
+ */
+static int dpsparser_exit(void)
+{
+	int err;
+
+	if (!is_dpsparser_supported())
+		return 0;
+
+	dpsparser_close(dflt_mc_io, MC_CMD_NO_FLAGS, dpsparser_handle);
+	if (err < 0) {
+		printf("dpsparser_close() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpsparser_destroy(dflt_mc_io, dflt_dprc_handle,
+				MC_CMD_NO_FLAGS, dpsparser_obj_id);
+	if (err < 0) {
+		printf("dpsparser_destroy() failed: %d\n", err);
+		goto err;
+	}
+	return 0;
+
+err:
+	return err;
+}
+#endif
+
+int mc_apply_spb(u64 mc_spb_addr)
+{
+	int err = 0;
+	u16 error, err_arr_size;
+	u64 mc_spb_offset;
+	u32 spb_size;
+	struct sp_blob_header *sp_blob;
+	u64 mc_ram_addr = mc_get_dram_addr();
+
+	if (!is_dpsparser_supported())
+		return 0;
+
+	if (!mc_spb_addr) {
+		printf("fsl-mc: Invalid Blob address\n");
+		return -1;
+	}
+
+#ifdef CONFIG_MC_DRAM_SPB_OFFSET
+	mc_spb_offset = CONFIG_MC_DRAM_SPB_OFFSET;
+#else
+#error "CONFIG_MC_DRAM_SPB_OFFSET not defined"
+#endif
+
+	// Read blob header and get size of SPB blob
+	sp_blob = (struct sp_blob_header *)mc_spb_addr;
+	spb_size = le32_to_cpu(sp_blob->length);
+	if (spb_size > CONFIG_MC_SPB_MAX_SIZE) {
+		printf("\nfsl-mc: ERROR: Bad SPB image (too large: %d)\n",
+		       spb_size);
+		return -EINVAL;
+	}
+
+	mc_copy_image("MC SP Blob", mc_spb_addr, spb_size,
+		      mc_ram_addr + mc_spb_offset);
+
+	//Invoke MC command to apply SPB blob
+	printf("fsl-mc: Applying soft parser blob... ");
+	err = dpsparser_apply_spb(dflt_mc_io, MC_CMD_NO_FLAGS, dpsparser_handle,
+				  mc_spb_offset, &error);
+	if (err)
+		return err;
+
+	if (error == 0) {
+		printf("SUCCESS\n");
+	} else {
+		printf("FAILED with error code = %d:\n", error);
+		err_arr_size = (u16)ARRAY_SIZE(mc_err_msg_apply_spb);
+
+		if (error > 0 && error < err_arr_size)
+			printf(mc_err_msg_apply_spb[error]);
+		else
+			printf(MC_ERROR_MSG_SPB_UNKNOWN);
+	}
+
+	return err;
+}
+
+static int mc_init_object(void)
+{
+	int err = 0;
+
+	err = dprc_init();
+	if (err < 0) {
+		printf("dprc_init() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpbp_init();
+	if (err < 0) {
+		printf("dpbp_init() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpio_init();
+	if (err < 0) {
+		printf("dpio_init() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpni_init();
+	if (err < 0) {
+		printf("dpni_init() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpsparser_init();
+	if (err < 0) {
+		printf("dpsparser_init() failed: %d\n", err);
+		goto err;
+	}
+
+	return 0;
+err:
+	return err;
+}
+
+int fsl_mc_ldpaa_exit(struct bd_info *bd)
+{
+	int err = 0;
+	bool is_dpl_apply_status = false;
+	bool mc_boot_status = false;
+
+	if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
+		err = mc_apply_dpl(mc_lazy_dpl_addr);
+		if (!err)
+			fdt_fixup_board_enet(working_fdt);
+		mc_lazy_dpl_addr = 0;
+	}
+
+	if (!get_mc_boot_status())
+		mc_boot_status = true;
+
+	/* MC is not loaded intentionally, So return success. */
+	if (bd && !mc_boot_status)
+		return 0;
+
+	/* If DPL is deployed, set is_dpl_apply_status as TRUE. */
+	if (!get_dpl_apply_status())
+		is_dpl_apply_status = true;
+
+	/*
+	 * For case MC is loaded but DPL is not deployed, return success and
+	 * print message on console. Else FDT fix-up code execution hanged.
+	 */
+	if (bd && mc_boot_status && !is_dpl_apply_status) {
+		printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
+		goto mc_obj_cleanup;
+	}
+
+	if (bd && mc_boot_status && is_dpl_apply_status)
+		return 0;
+
+mc_obj_cleanup:
+	err = dpbp_exit();
+	if (err < 0) {
+		printf("dpbp_exit() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpio_exit();
+	if (err < 0) {
+		printf("dpio_exit() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dpni_exit();
+	if (err < 0) {
+		printf("dpni_exit() failed: %d\n", err);
+		goto err;
+	}
+
+	err = dprc_exit();
+	if (err < 0) {
+		printf("dprc_exit() failed: %d\n", err);
+		goto err;
+	}
+
+	return 0;
+err:
+	return err;
+}
+
+static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc,
+		     char *const argv[])
+{
+	int err = 0;
+	if (argc < 3)
+		goto usage;
+
+	switch (argv[1][0]) {
+	case 's': {
+			char sub_cmd;
+			u64 mc_fw_addr, mc_dpc_addr;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+			u64 aiop_fw_addr;
+#endif
+
+			sub_cmd = argv[2][0];
+
+			switch (sub_cmd) {
+			case 'm':
+				if (argc < 5)
+					goto usage;
+
+				if (get_mc_boot_status() == 0) {
+					printf("fsl-mc: MC is already booted");
+					printf("\n");
+					return err;
+				}
+				mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
+				mc_dpc_addr = simple_strtoull(argv[4], NULL,
+							      16);
+
+				if (!mc_init(mc_fw_addr, mc_dpc_addr))
+					err = mc_init_object();
+				break;
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+			case 'a':
+				if (argc < 4)
+					goto usage;
+				if (get_aiop_apply_status() == 0) {
+					printf("fsl-mc: AIOP FW is already");
+					printf(" applied\n");
+					return err;
+				}
+
+				aiop_fw_addr = simple_strtoull(argv[3], NULL,
+							       16);
+
+				/* if SoC doesn't have AIOP, err = -ENODEV */
+				err = load_mc_aiop_img(aiop_fw_addr);
+				if (!err)
+					printf("fsl-mc: AIOP FW applied\n");
+				break;
+#endif
+			default:
+				printf("Invalid option: %s\n", argv[2]);
+				goto usage;
+
+				break;
+			}
+		}
+		break;
+
+	case 'l': {
+		/* lazyapply */
+		u64 mc_dpl_addr;
+
+		if (argc < 4)
+			goto usage;
+
+		if (get_dpl_apply_status() == 0) {
+			printf("fsl-mc: DPL already applied\n");
+			return err;
+		}
+
+		mc_dpl_addr = simple_strtoull(argv[3], NULL, 16);
+
+		if (get_mc_boot_status() != 0) {
+			printf("fsl-mc: Deploying data path layout ..");
+			printf("ERROR (MC is not booted)\n");
+			return -ENODEV;
+		}
+
+		/*
+		 * We will do the actual dpaa exit and dpl apply
+		 * later from announce_and_cleanup().
+		 */
+		mc_lazy_dpl_addr = mc_dpl_addr;
+		break;
+		}
+
+	case 'a': {
+		/* apply */
+		char sub_cmd;
+		u64 mc_apply_addr;
+
+		if (argc < 4)
+			goto usage;
+
+		sub_cmd = argv[2][0];
+
+		switch (sub_cmd) {
+		case 'd':
+		case 'D':
+			if (get_dpl_apply_status() == 0) {
+				printf("fsl-mc: DPL already applied\n");
+				return err;
+			}
+			if (get_mc_boot_status() != 0) {
+				printf("fsl-mc: Deploying data path layout ..");
+				printf("ERROR (MC is not booted)\n");
+				return -ENODEV;
+			}
+
+			mc_apply_addr = simple_strtoull(argv[3], NULL, 16);
+
+			/* The user wants DPL applied now */
+			if (!fsl_mc_ldpaa_exit(NULL))
+				err = mc_apply_dpl(mc_apply_addr);
+			break;
+
+		case 's':
+			if (!is_dpsparser_supported()) {
+				printf("fsl-mc: apply spb command .. ");
+				printf("ERROR: requires at least MC 10.12.0\n");
+				return err;
+			}
+			if (get_mc_boot_status() != 0) {
+				printf("fsl-mc: Deploying Soft Parser Blob...");
+				printf("ERROR (MC is not booted)\n");
+				return err;
+			}
+
+			mc_apply_addr = simple_strtoull(argv[3], NULL, 16);
+
+			/* Apply spb (Soft Parser Blob) */
+			err = mc_apply_spb(mc_apply_addr);
+			break;
+
+		default:
+			printf("Invalid option: %s\n", argv[2]);
+			goto usage;
+		}
+		break;
+		}
+	default:
+		printf("Invalid option: %s\n", argv[1]);
+		goto usage;
+		break;
+	}
+	return err;
+ usage:
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	fsl_mc,  CONFIG_SYS_MAXARGS,  1,   do_fsl_mc,
+	"DPAA2 command to manage Management Complex (MC)",
+	"start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
+	"fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
+	"fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
+	"fsl_mc apply spb [spb_addr] - Apply SPB Soft Parser Blob\n"
+	"fsl_mc start aiop [FW_addr] - Start AIOP\n"
+);
+
+void mc_env_boot(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	char *mc_boot_env_var;
+	/* The MC may only be initialized in the reset PHY function
+	 * because otherwise U-Boot has not yet set up all the MAC
+	 * address info properly. Without MAC addresses, the MC code
+	 * can not properly initialize the DPC.
+	 */
+	mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
+	if (mc_boot_env_var)
+		run_command_list(mc_boot_env_var, -1, 0);
+#endif /* CONFIG_FSL_MC_ENET */
+}
diff --git a/roms/u-boot/drivers/net/fsl-mc/mc_sys.c b/roms/u-boot/drivers/net/fsl-mc/mc_sys.c
new file mode 100644
index 000000000..b5ae2ea3e
--- /dev/null
+++ b/roms/u-boot/drivers/net/fsl-mc/mc_sys.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
+ * Author: German Rivera <German.Rivera@freescale.com>
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define MC_CMD_HDR_READ_CMDID(_hdr) \
+	((uint16_t)mc_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S))
+
+/**
+ * mc_send_command - Send MC command and wait for response
+ *
+ * @mc_io: Pointer to MC I/O object to be used
+ * @cmd: MC command buffer. On input, it contains the command to send to the MC.
+ * On output, it contains the response from the MC if any.
+ *
+ * Depending on the sharing option specified when creating the MC portal
+ * wrapper, this function will use a spinlock or mutex to ensure exclusive
+ * access to the MC portal from the point when the command is sent until a
+ * response is received from the MC.
+ */
+int mc_send_command(struct fsl_mc_io *mc_io,
+		    struct mc_command *cmd)
+{
+	enum mc_cmd_status status;
+	int timeout = 12000;
+
+	mc_write_command(mc_io->mmio_regs, cmd);
+
+	for ( ; ; ) {
+		status = mc_read_response(mc_io->mmio_regs, cmd);
+		if (status != MC_CMD_STATUS_READY)
+			break;
+
+		if (--timeout == 0) {
+			printf("Error: Timeout waiting for MC response\n");
+			return -ETIMEDOUT;
+		}
+
+		udelay(500);
+	}
+
+	if (status != MC_CMD_STATUS_OK) {
+		printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n",
+		       mc_io->mmio_regs,
+			(unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header),
+		       (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header),
+		       (unsigned int)status);
+
+		return -EIO;
+	}
+
+	return 0;
+}