Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

13 files changed, 2067 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/pinctrl/uniphier/Kconfig b/roms/u-boot/drivers/pinctrl/uniphier/Kconfig
new file mode 100644
index 000000000..b6abcd12f
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/Kconfig
@@ -0,0 +1,60 @@
+if ARCH_UNIPHIER
+
+config PINCTRL_UNIPHIER
+	bool
+
+config PINCTRL_UNIPHIER_LD4
+	bool "UniPhier LD4 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_LD4
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_PRO4
+	bool "UniPhier Pro4 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_PRO4
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_SLD8
+	bool "UniPhier sLD8 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_SLD8
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_PRO5
+	bool "UniPhier Pro5 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_PRO5
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_PXS2
+	bool "UniPhier PXs2 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_PXS2
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_LD6B
+	bool "UniPhier LD6b SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_LD6B
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_LD11
+	bool "UniPhier LD11 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_LD11
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_LD20
+	bool "UniPhier LD20 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_LD20
+	default y
+	select PINCTRL_UNIPHIER
+
+config PINCTRL_UNIPHIER_PXS3
+	bool "UniPhier PXs3 SoC pinctrl driver"
+	depends on ARCH_UNIPHIER_PXS3
+	default y
+	select PINCTRL_UNIPHIER
+
+endif
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/Makefile b/roms/u-boot/drivers/pinctrl/uniphier/Makefile
new file mode 100644
index 000000000..d3088d875
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y					+= pinctrl-uniphier-core.o
+
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD4)	+= pinctrl-uniphier-ld4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4)	+= pinctrl-uniphier-pro4.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8)	+= pinctrl-uniphier-sld8.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5)	+= pinctrl-uniphier-pro5.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2)	+= pinctrl-uniphier-pxs2.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B)	+= pinctrl-uniphier-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD11)	+= pinctrl-uniphier-ld11.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD20)	+= pinctrl-uniphier-ld20.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3)	+= pinctrl-uniphier-pxs3.o
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
new file mode 100644
index 000000000..631bb1f96
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -0,0 +1,436 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+#define UNIPHIER_PINCTRL_PINMUX_BASE	0x1000
+#define UNIPHIER_PINCTRL_LOAD_PINMUX	0x1700
+#define UNIPHIER_PINCTRL_DRVCTRL_BASE	0x1800
+#define UNIPHIER_PINCTRL_DRV2CTRL_BASE	0x1900
+#define UNIPHIER_PINCTRL_DRV3CTRL_BASE	0x1980
+#define UNIPHIER_PINCTRL_PUPDCTRL_BASE	0x1a00
+#define UNIPHIER_PINCTRL_IECTRL		0x1d00
+
+static const char *uniphier_pinctrl_dummy_name = "_dummy";
+
+static int uniphier_pinctrl_get_pins_count(struct udevice *dev)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
+	int pins_count = priv->socdata->pins_count;
+
+	/*
+	 * We do not list all pins in the pin table to save memory footprint.
+	 * Report the max pin number + 1 to fake the framework.
+	 */
+	return pins[pins_count - 1].number + 1;
+}
+
+static const char *uniphier_pinctrl_get_pin_name(struct udevice *dev,
+						 unsigned int selector)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
+	int pins_count = priv->socdata->pins_count;
+	int i;
+
+	for (i = 0; i < pins_count; i++)
+		if (pins[i].number == selector)
+			return pins[i].name;
+
+	return uniphier_pinctrl_dummy_name;
+}
+
+static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->socdata->groups_count;
+}
+
+static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
+						   unsigned selector)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+	if (!priv->socdata->groups[selector].name)
+		return uniphier_pinctrl_dummy_name;
+
+	return priv->socdata->groups[selector].name;
+}
+
+static int uniphier_pinmux_get_functions_count(struct udevice *dev)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+	return priv->socdata->functions_count;
+}
+
+static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
+						     unsigned selector)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+	if (!priv->socdata->functions[selector])
+		return uniphier_pinctrl_dummy_name;
+
+	return priv->socdata->functions[selector];
+}
+
+static int uniphier_pinconf_input_enable_perpin(struct udevice *dev,
+						unsigned int pin, int enable)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	unsigned reg;
+	u32 mask, tmp;
+
+	reg = UNIPHIER_PINCTRL_IECTRL + pin / 32 * 4;
+	mask = BIT(pin % 32);
+
+	tmp = readl(priv->base + reg);
+	if (enable)
+		tmp |= mask;
+	else
+		tmp &= ~mask;
+	writel(tmp, priv->base + reg);
+
+	return 0;
+}
+
+static int uniphier_pinconf_input_enable_legacy(struct udevice *dev,
+						unsigned int pin, int enable)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+	/*
+	 * Multiple pins share one input enable, per-pin disabling is
+	 * impossible.
+	 */
+	if (!enable)
+		return -EINVAL;
+
+	/* Set all bits instead of having a bunch of pin data */
+	writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
+
+	return 0;
+}
+
+static int uniphier_pinconf_input_enable(struct udevice *dev,
+					 unsigned int pin, int enable)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+
+	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
+		return uniphier_pinconf_input_enable_perpin(dev, pin, enable);
+	else
+		return uniphier_pinconf_input_enable_legacy(dev, pin, enable);
+}
+
+#if CONFIG_IS_ENABLED(PINCONF)
+
+static const struct pinconf_param uniphier_pinconf_params[] = {
+	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+	{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
+	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+	{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+	{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
+};
+
+static const struct uniphier_pinctrl_pin *
+uniphier_pinctrl_pin_get(struct uniphier_pinctrl_priv *priv, unsigned int pin)
+{
+	const struct uniphier_pinctrl_pin *pins = priv->socdata->pins;
+	int pins_count = priv->socdata->pins_count;
+	int i;
+
+	for (i = 0; i < pins_count; i++)
+		if (pins[i].number == pin)
+			return &pins[i];
+
+	return NULL;
+}
+
+static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin,
+				     unsigned int param, unsigned int arg)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	unsigned int enable = 1;
+	unsigned int reg;
+	u32 mask, tmp;
+
+	if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE))
+		return -ENOTSUPP;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+		enable = 0;
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		if (arg == 0)	/* total bias is not supported */
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+		if (arg == 0)	/* configuration ignored */
+			return 0;
+	default:
+		BUG();
+	}
+
+	reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pin / 32 * 4;
+	mask = BIT(pin % 32);
+
+	tmp = readl(priv->base + reg);
+	if (enable)
+		tmp |= mask;
+	else
+		tmp &= ~mask;
+	writel(tmp, priv->base + reg);
+
+	return 0;
+}
+
+static const unsigned int uniphier_pinconf_drv_strengths_1bit[] = {
+	4, 8,
+};
+
+static const unsigned int uniphier_pinconf_drv_strengths_2bit[] = {
+	8, 12, 16, 20,
+};
+
+static const unsigned int uniphier_pinconf_drv_strengths_3bit[] = {
+	4, 5, 7, 9, 11, 12, 14, 16,
+};
+
+static int uniphier_pinconf_drive_set(struct udevice *dev, unsigned int pin,
+				      unsigned int strength)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct uniphier_pinctrl_pin *desc;
+	const unsigned int *strengths;
+	unsigned int base, stride, width, drvctrl, reg, shift;
+	u32 val, mask, tmp;
+
+	desc = uniphier_pinctrl_pin_get(priv, pin);
+	if (WARN_ON(!desc))
+		return -EINVAL;
+
+	switch (uniphier_pin_get_drv_type(desc->data)) {
+	case UNIPHIER_PIN_DRV_1BIT:
+		strengths = uniphier_pinconf_drv_strengths_1bit;
+		base = UNIPHIER_PINCTRL_DRVCTRL_BASE;
+		stride = 1;
+		width = 1;
+		break;
+	case UNIPHIER_PIN_DRV_2BIT:
+		strengths = uniphier_pinconf_drv_strengths_2bit;
+		base = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
+		stride = 2;
+		width = 2;
+		break;
+	case UNIPHIER_PIN_DRV_3BIT:
+		strengths = uniphier_pinconf_drv_strengths_3bit;
+		base = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
+		stride = 4;
+		width = 3;
+		break;
+	default:
+		/* drive strength control is not supported for this pin */
+		return -EINVAL;
+	}
+
+	drvctrl = uniphier_pin_get_drvctrl(desc->data);
+	drvctrl *= stride;
+
+	reg = base + drvctrl / 32 * 4;
+	shift = drvctrl % 32;
+	mask = (1U << width) - 1;
+
+	for (val = 0; val <= mask; val++) {
+		if (strengths[val] > strength)
+			break;
+	}
+
+	if (val == 0) {
+		dev_err(dev, "unsupported drive strength %u mA for pin %s\n",
+			strength, desc->name);
+		return -EINVAL;
+	}
+
+	if (!mask)
+		return 0;
+
+	val--;
+
+	tmp = readl(priv->base + reg);
+	tmp &= ~(mask << shift);
+	tmp |= (mask & val) << shift;
+	writel(tmp, priv->base + reg);
+
+	return 0;
+}
+
+static int uniphier_pinconf_set(struct udevice *dev, unsigned int pin,
+				unsigned int param, unsigned int arg)
+{
+	int ret;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+	case PIN_CONFIG_BIAS_PULL_UP:
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+		ret = uniphier_pinconf_bias_set(dev, pin, param, arg);
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		ret = uniphier_pinconf_drive_set(dev, pin, arg);
+		break;
+	case PIN_CONFIG_INPUT_ENABLE:
+		ret = uniphier_pinconf_input_enable(dev, pin, arg);
+		break;
+	default:
+		dev_err(dev, "unsupported configuration parameter %u\n", param);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int uniphier_pinconf_group_set(struct udevice *dev,
+				      unsigned int group_selector,
+				      unsigned int param, unsigned int arg)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct uniphier_pinctrl_group *grp =
+					&priv->socdata->groups[group_selector];
+	int i, ret;
+
+	for (i = 0; i < grp->num_pins; i++) {
+		ret = uniphier_pinconf_set(dev, grp->pins[i], param, arg);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#endif /* CONFIG_IS_ENABLED(PINCONF) */
+
+static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
+				    int muxval)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	unsigned reg, reg_end, shift, mask;
+	unsigned mux_bits = 8;
+	unsigned reg_stride = 4;
+	bool load_pinctrl = false;
+	u32 tmp;
+
+	/* some pins need input-enabling */
+	uniphier_pinconf_input_enable(dev, pin, 1);
+
+	if (muxval < 0)
+		return;		/* dedicated pin; nothing to do for pin-mux */
+
+	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
+		mux_bits = 4;
+
+	if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
+		/*
+		 *  Mode       offset        bit
+		 *  Normal     4 * n     shift+3:shift
+		 *  Debug      4 * n     shift+7:shift+4
+		 */
+		mux_bits /= 2;
+		reg_stride = 8;
+		load_pinctrl = true;
+	}
+
+	reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
+	reg_end = reg + reg_stride;
+	shift = pin * mux_bits % 32;
+	mask = (1U << mux_bits) - 1;
+
+	/*
+	 * If reg_stride is greater than 4, the MSB of each pinsel shall be
+	 * stored in the offset+4.
+	 */
+	for (; reg < reg_end; reg += 4) {
+		tmp = readl(priv->base + reg);
+		tmp &= ~(mask << shift);
+		tmp |= (mask & muxval) << shift;
+		writel(tmp, priv->base + reg);
+
+		muxval >>= mux_bits;
+	}
+
+	if (load_pinctrl)
+		writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
+}
+
+static int uniphier_pinmux_group_set(struct udevice *dev,
+				     unsigned group_selector,
+				     unsigned func_selector)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct uniphier_pinctrl_group *grp =
+					&priv->socdata->groups[group_selector];
+	int i;
+
+	for (i = 0; i < grp->num_pins; i++)
+		uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]);
+
+	return 0;
+}
+
+const struct pinctrl_ops uniphier_pinctrl_ops = {
+	.get_pins_count = uniphier_pinctrl_get_pins_count,
+	.get_pin_name = uniphier_pinctrl_get_pin_name,
+	.get_groups_count = uniphier_pinctrl_get_groups_count,
+	.get_group_name = uniphier_pinctrl_get_group_name,
+	.get_functions_count = uniphier_pinmux_get_functions_count,
+	.get_function_name = uniphier_pinmux_get_function_name,
+	.pinmux_group_set = uniphier_pinmux_group_set,
+#if CONFIG_IS_ENABLED(PINCONF)
+	.pinconf_num_params = ARRAY_SIZE(uniphier_pinconf_params),
+	.pinconf_params = uniphier_pinconf_params,
+	.pinconf_set = uniphier_pinconf_set,
+	.pinconf_group_set = uniphier_pinconf_group_set,
+#endif
+	.set_state = pinctrl_generic_set_state,
+};
+
+int uniphier_pinctrl_probe(struct udevice *dev,
+			   struct uniphier_pinctrl_socdata *socdata)
+{
+	struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev->parent);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = devm_ioremap(dev, addr, SZ_4K);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->socdata = socdata;
+
+	return 0;
+}
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
new file mode 100644
index 000000000..a1a3cd738
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+					   16, 17};
+static const int ether_rmii_muxvals[] = {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4};
+static const unsigned i2c0_pins[] = {63, 64};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const int i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const int i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+				     15, 16, 17};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {56, 57, 58, 59};
+static const int spi0_muxvals[] = {0, 0, 0, 0};
+static const unsigned spi1_pins[] = {169, 170, 171, 172};
+static const int spi1_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+					   14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+					 2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned uart0_pins[] = {54, 55};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const int uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const int uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const int uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const int usb2_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
+	UNIPHIER_PINCTRL_GROUP(emmc),
+	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(i2c4),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(uart0),
+	UNIPHIER_PINCTRL_GROUP(uart1),
+	UNIPHIER_PINCTRL_GROUP(uart2),
+	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const uniphier_ld11_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c4),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION(uart0),
+	UNIPHIER_PINMUX_FUNCTION(uart1),
+	UNIPHIER_PINMUX_FUNCTION(uart2),
+	UNIPHIER_PINMUX_FUNCTION(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld11_pinctrl_socdata = {
+	.groups = uniphier_ld11_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld11_groups),
+	.functions = uniphier_ld11_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld11_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+		UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_ld11_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_ld11_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_ld11_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-ld11-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_ld11_pinctrl) = {
+	.name = "uniphier-ld11-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_ld11_pinctrl_match),
+	.probe = uniphier_ld11_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
new file mode 100644
index 000000000..7a92a46c1
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct uniphier_pinctrl_pin uniphier_ld20_pins[] = {
+	UNIPHIER_PINCTRL_PIN(40, "RGMII_TXCLK", 28, UNIPHIER_PIN_DRV_3BIT),
+	UNIPHIER_PINCTRL_PIN(41, "RGMII_TXD0", 29, UNIPHIER_PIN_DRV_3BIT),
+	UNIPHIER_PINCTRL_PIN(42, "RGMII_TXD1", 30, UNIPHIER_PIN_DRV_3BIT),
+	UNIPHIER_PINCTRL_PIN(43, "RGMII_TXD2", 31, UNIPHIER_PIN_DRV_3BIT),
+	UNIPHIER_PINCTRL_PIN(44, "RGMII_TXD3", 32, UNIPHIER_PIN_DRV_3BIT),
+	UNIPHIER_PINCTRL_PIN(45, "RGMII_TXCTL", 33, UNIPHIER_PIN_DRV_3BIT),
+};
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38,
+					    39, 40, 41, 42, 43, 44, 45};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
+					   41, 42, 45};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {63, 64};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const int i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const int i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+				     15, 16, 17};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
+static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3};  /* No SDVOLC */
+static const unsigned spi0_pins[] = {56, 57, 58, 59};
+static const int spi0_muxvals[] = {0, 0, 0, 0};
+static const unsigned spi1_pins[] = {169, 170, 171, 172};
+static const int spi1_muxvals[] = {1, 1, 1, 1};
+static const unsigned spi2_pins[] = {86, 87, 88, 89};
+static const int spi2_muxvals[] = {1, 1, 1, 1};
+static const unsigned spi3_pins[] = {74, 75, 76, 77};
+static const int spi3_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+					   14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+					 2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned uart0_pins[] = {54, 55};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const int uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const int uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const int uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const int usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {52, 53};
+static const int usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
+	UNIPHIER_PINCTRL_GROUP(emmc),
+	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(i2c4),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(spi2),
+	UNIPHIER_PINCTRL_GROUP(spi3),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(uart0),
+	UNIPHIER_PINCTRL_GROUP(uart1),
+	UNIPHIER_PINCTRL_GROUP(uart2),
+	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const uniphier_ld20_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c4),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(spi2),
+	UNIPHIER_PINMUX_FUNCTION(spi3),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION(uart0),
+	UNIPHIER_PINMUX_FUNCTION(uart1),
+	UNIPHIER_PINMUX_FUNCTION(uart2),
+	UNIPHIER_PINMUX_FUNCTION(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld20_pinctrl_socdata = {
+	.pins = uniphier_ld20_pins,
+	.pins_count = ARRAY_SIZE(uniphier_ld20_pins),
+	.groups = uniphier_ld20_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld20_groups),
+	.functions = uniphier_ld20_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld20_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+		UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_ld20_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_ld20_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_ld20_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-ld20-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_ld20_pinctrl) = {
+	.name = "uniphier-ld20-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_ld20_pinctrl_match),
+	.probe = uniphier_ld20_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
new file mode 100644
index 000000000..d33e4d7dd
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+					  41, 42, 43, 136, 137, 138, 139, 140,
+					  141, 142};
+static const int ether_mii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					4, 4, 4, 4, 4, 4, 4};
+static const unsigned ether_rmii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+					   41, 42, 43};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {102, 103};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const int i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const int i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
+				     160, 161, 162, 163, 164};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const int nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {135, 136, 137, 138};
+static const int spi0_muxvals[] = {12, 12, 12, 12};
+static const unsigned system_bus_pins[] = {16, 17, 18, 19, 20, 165, 166, 167,
+					   168, 169, 170, 171, 172, 173};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1,
+					 -1, -1, -1};
+static const unsigned system_bus_cs0_pins[] = {155};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {174};
+static const int system_bus_cs1_muxvals[] = {-1};
+static const unsigned system_bus_cs2_pins[] = {64};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {156};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned uart0_pins[] = {85, 88};
+static const int uart0_muxvals[] = {1, 1};
+static const unsigned uart1_pins[] = {155, 156};
+static const int uart1_muxvals[] = {13, 13};
+static const unsigned uart1b_pins[] = {69, 70};
+static const int uart1b_muxvals[] = {23, 23};
+static const unsigned uart2_pins[] = {128, 129};
+static const int uart2_muxvals[] = {13, 13};
+static const unsigned uart3_pins[] = {110, 111};
+static const int uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {53, 54};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {55, 56};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {155, 156};
+static const int usb2_muxvals[] = {4, 4};
+static const unsigned usb2b_pins[] = {67, 68};
+static const int usb2b_muxvals[] = {23, 23};
+
+static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb2b),
+};
+
+static const char * const uniphier_ld4_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld4_pinctrl_socdata = {
+	.groups = uniphier_ld4_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld4_groups),
+	.functions = uniphier_ld4_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld4_functions),
+};
+
+static int uniphier_ld4_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_ld4_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_ld4_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-ld4-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_ld4_pinctrl) = {
+	.name = "uniphier-ld4-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_ld4_pinctrl_match),
+	.probe = uniphier_ld4_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
new file mode 100644
index 000000000..0e3eb131e
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_rgmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					    150, 151, 152, 153, 154, 155, 156,
+					    157, 158};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					   150, 152, 154, 155, 158};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {109, 110};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {111, 112};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {115, 116};
+static const int i2c2_muxvals[] = {1, 1};
+static const unsigned i2c3_pins[] = {118, 119};
+static const int i2c3_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+				     42, 43, 44, 45, 46};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const int nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {199, 200, 201, 202};
+static const int spi0_muxvals[] = {8, 8, 8, 8};
+static const unsigned spi1_pins[] = {93, 94, 95, 96};
+static const int spi1_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+					   11, 12, 13};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					 0};
+static const unsigned system_bus_cs1_pins[] = {14};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {37};
+static const int system_bus_cs2_muxvals[] = {6};
+static const unsigned system_bus_cs3_pins[] = {38};
+static const int system_bus_cs3_muxvals[] = {6};
+static const unsigned system_bus_cs4_pins[] = {115};
+static const int system_bus_cs4_muxvals[] = {6};
+static const unsigned system_bus_cs5_pins[] = {55};
+static const int system_bus_cs5_muxvals[] = {6};
+static const unsigned uart0_pins[] = {135, 136};
+static const int uart0_muxvals[] = {3, 3};
+static const unsigned uart0b_pins[] = {11, 12};
+static const int uart0b_muxvals[] = {2, 2};
+static const unsigned uart1_pins[] = {115, 116};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned uart1b_pins[] = {113, 114};
+static const int uart1b_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {113, 114};
+static const int uart2_muxvals[] = {2, 2};
+static const unsigned uart2b_pins[] = {86, 87};
+static const int uart2b_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {56, 57};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {58, 59};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {60, 61};
+static const int usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {62, 63};
+static const int usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2b),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const uniphier_ld6b_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld6b_pinctrl_socdata = {
+	.groups = uniphier_ld6b_groups,
+	.groups_count = ARRAY_SIZE(uniphier_ld6b_groups),
+	.functions = uniphier_ld6b_functions,
+	.functions_count = ARRAY_SIZE(uniphier_ld6b_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE,
+};
+
+static int uniphier_ld6b_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_ld6b_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_ld6b_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-ld6b-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_ld6b_pinctrl) = {
+	.name = "uniphier-ld6b-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_ld6b_pinctrl_match),
+	.probe = uniphier_ld6b_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
new file mode 100644
index 000000000..7ba226609
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {160, 161, 162, 163, 164, 165, 166,
+					  167, 168, 169, 170, 171, 172, 173,
+					  174, 175, 176, 177, 178, 179};
+static const int ether_mii_muxvals[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					0, 0, 0, 0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {160, 161, 162, 163, 164, 165, 167,
+					    168, 169, 170, 171, 172, 176, 177,
+					    178, 179};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {160, 161, 162, 165, 168, 169, 172,
+					   173, 176, 177, 178, 179};
+static const int ether_rmii_muxvals[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned ether_rmiib_pins[] = {161, 162, 165, 167, 168, 169, 172,
+					    173, 176, 177, 178, 179};
+static const int ether_rmiib_muxvals[] = {0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {142, 143};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {144, 145};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {146, 147};
+static const int i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {148, 149};
+static const int i2c3_muxvals[] = {0, 0};
+static const unsigned i2c6_pins[] = {308, 309};
+static const int i2c6_muxvals[] = {6, 6};
+static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
+				     50, 51, 52, 53, 54};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned nand_cs1_pins[] = {131, 132};
+static const int nand_cs1_muxvals[] = {1, 1};
+static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
+				    327};
+static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {199, 200, 201, 202};
+static const int spi0_muxvals[] = {11, 11, 11, 11};
+static const unsigned spi1_pins[] = {195, 196, 197, 198, 235, 238, 239};
+static const int spi1_muxvals[] = {11, 11, 11, 11, 11, 11, 11};
+static const unsigned system_bus_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33,
+					   34, 35, 36, 37, 38};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					 0};
+static const unsigned system_bus_cs0_pins[] = {318};
+static const int system_bus_cs0_muxvals[] = {5};
+static const unsigned system_bus_cs1_pins[] = {24};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {315};
+static const int system_bus_cs2_muxvals[] = {5};
+static const unsigned system_bus_cs3_pins[] = {313};
+static const int system_bus_cs3_muxvals[] = {5};
+static const unsigned system_bus_cs4_pins[] = {305};
+static const int system_bus_cs4_muxvals[] = {5};
+static const unsigned system_bus_cs5_pins[] = {303};
+static const int system_bus_cs5_muxvals[] = {6};
+static const unsigned system_bus_cs6_pins[] = {307};
+static const int system_bus_cs6_muxvals[] = {6};
+static const unsigned system_bus_cs7_pins[] = {312};
+static const int system_bus_cs7_muxvals[] = {6};
+static const unsigned uart0_pins[] = {127, 128};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {129, 130};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {131, 132};
+static const int uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {88, 89};
+static const int uart3_muxvals[] = {2, 2};
+static const unsigned usb0_pins[] = {180, 181};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {182, 183};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {184, 185};
+static const int usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {186, 187};
+static const int usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmiib),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(i2c6),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(sd1),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const uniphier_pro4_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c6),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(sd1),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_pro4_pinctrl_socdata = {
+	.groups = uniphier_pro4_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pro4_groups),
+	.functions = uniphier_pro4_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pro4_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
+};
+
+static int uniphier_pro4_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_pro4_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_pro4_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-pro4-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_pro4_pinctrl) = {
+	.name = "uniphier-pro4-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_pro4_pinctrl_match),
+	.probe = uniphier_pro4_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+	.flags = DM_FLAG_PRE_RELOC,
+#endif
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
new file mode 100644
index 000000000..9ce2e2c27
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned i2c0_pins[] = {112, 113};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {114, 115};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {116, 117};
+static const int i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {118, 119};
+static const int i2c3_muxvals[] = {0, 0};
+static const unsigned i2c5_pins[] = {87, 88};
+static const int i2c5_muxvals[] = {2, 2};
+static const unsigned i2c5b_pins[] = {196, 197};
+static const int i2c5b_muxvals[] = {2, 2};
+static const unsigned i2c5c_pins[] = {215, 216};
+static const int i2c5c_muxvals[] = {2, 2};
+static const unsigned i2c6_pins[] = {101, 102};
+static const int i2c6_muxvals[] = {2, 2};
+static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
+				     31, 32, 33, 34, 35};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned nand_cs1_pins[] = {26, 27};
+static const int nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {120, 121, 122, 123};
+static const int spi0_muxvals[] = {0, 0, 0, 0};
+static const unsigned spi1_pins[] = {134, 139, 85, 86};
+static const int spi1_muxvals[] = {1, 1, 1, 1};
+static const unsigned spi2_pins[] = {55, 56, 57, 58, 82, 83, 84};
+static const int spi2_muxvals[] = {0, 0, 0, 0, 1, 1, 1};
+static const unsigned system_bus_pins[] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+					   14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					 0};
+static const unsigned system_bus_cs0_pins[] = {105};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {18};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {106};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {100};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {101};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {102};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned system_bus_cs6_pins[] = {69};
+static const int system_bus_cs6_muxvals[] = {5};
+static const unsigned system_bus_cs7_pins[] = {70};
+static const int system_bus_cs7_muxvals[] = {5};
+static const unsigned uart0_pins[] = {47, 48};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart0b_pins[] = {227, 228};
+static const int uart0b_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {49, 50};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {51, 52};
+static const int uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {53, 54};
+static const int uart3_muxvals[] = {0, 0};
+static const unsigned usb0_pins[] = {124, 125};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {126, 127};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {128, 129};
+static const int usb2_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(i2c5),
+	UNIPHIER_PINCTRL_GROUP(i2c5b),
+	UNIPHIER_PINCTRL_GROUP(i2c5c),
+	UNIPHIER_PINCTRL_GROUP(i2c6),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(spi2),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const uniphier_pro5_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c5),
+	UNIPHIER_PINMUX_FUNCTION(i2c6),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(spi2),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_pro5_pinctrl_socdata = {
+	.groups = uniphier_pro5_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pro5_groups),
+	.functions = uniphier_pro5_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pro5_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+		UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
+};
+
+static int uniphier_pro5_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_pro5_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_pro5_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-pro5-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_pro5_pinctrl) = {
+	.name = "uniphier-pro5-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_pro5_pinctrl_match),
+	.probe = uniphier_pro5_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+	.flags = DM_FLAG_PRE_RELOC,
+#endif
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
new file mode 100644
index 000000000..e8c201809
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
+static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
+static const int emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned ether_mii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					  150, 151, 152, 153, 154, 155, 156,
+					  158, 159, 199, 200, 201, 202};
+static const int ether_mii_muxvals[] = {8, 8, 8, 8, 10, 10, 10, 10, 10, 10, 10,
+					10, 10, 10, 10, 10, 12, 12, 12, 12};
+static const unsigned ether_rgmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					    150, 151, 152, 153, 154, 155, 156,
+					    157, 158};
+static const int ether_rgmii_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+					  8, 8, 8, 8};
+static const unsigned ether_rmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+					   150, 152, 154, 155, 158};
+static const int ether_rmii_muxvals[] = {8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9};
+static const unsigned i2c0_pins[] = {109, 110};
+static const int i2c0_muxvals[] = {8, 8};
+static const unsigned i2c1_pins[] = {111, 112};
+static const int i2c1_muxvals[] = {8, 8};
+static const unsigned i2c2_pins[] = {171, 172};
+static const int i2c2_muxvals[] = {8, 8};
+static const unsigned i2c3_pins[] = {159, 160};
+static const int i2c3_muxvals[] = {8, 8};
+static const unsigned i2c5_pins[] = {183, 184};
+static const int i2c5_muxvals[] = {11, 11};
+static const unsigned i2c6_pins[] = {185, 186};
+static const int i2c6_muxvals[] = {11, 11};
+static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
+				     42, 43, 44, 45, 46};
+static const int nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned nand_cs1_pins[] = {37, 38};
+static const int nand_cs1_muxvals[] = {8, 8};
+static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
+static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned spi0_pins[] = {199, 200, 201, 202};
+static const int spi0_muxvals[] = {8, 8, 8, 8};
+static const unsigned spi1_pins[] = {93, 94, 95, 96};
+static const int spi1_muxvals[] = {1, 1, 1, 1};
+static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+					   11, 12, 13};
+static const int system_bus_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+					 8};
+static const unsigned system_bus_cs1_pins[] = {14};
+static const int system_bus_cs1_muxvals[] = {8};
+static const unsigned uart0_pins[] = {217, 218};
+static const int uart0_muxvals[] = {8, 8};
+static const unsigned uart0b_pins[] = {179, 180};
+static const int uart0b_muxvals[] = {10, 10};
+static const unsigned uart1_pins[] = {115, 116};
+static const int uart1_muxvals[] = {8, 8};
+static const unsigned uart2_pins[] = {113, 114};
+static const int uart2_muxvals[] = {8, 8};
+static const unsigned uart3_pins[] = {219, 220};
+static const int uart3_muxvals[] = {8, 8};
+static const unsigned uart3b_pins[] = {181, 182};
+static const int uart3b_muxvals[] = {10, 10};
+static const unsigned usb0_pins[] = {56, 57};
+static const int usb0_muxvals[] = {8, 8};
+static const unsigned usb1_pins[] = {58, 59};
+static const int usb1_muxvals[] = {8, 8};
+static const unsigned usb2_pins[] = {60, 61};
+static const int usb2_muxvals[] = {8, 8};
+static const unsigned usb3_pins[] = {62, 63};
+static const int usb3_muxvals[] = {8, 8};
+
+static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(i2c5),
+	UNIPHIER_PINCTRL_GROUP(i2c6),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0b),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3b),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const uniphier_pxs2_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(i2c5),
+	UNIPHIER_PINMUX_FUNCTION(i2c6),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_pxs2_pinctrl_socdata = {
+	.groups = uniphier_pxs2_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pxs2_groups),
+	.functions = uniphier_pxs2_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pxs2_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE,
+};
+
+static int uniphier_pxs2_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_pxs2_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_pxs2_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-pxs2-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_pxs2_pinctrl) = {
+	.name = "uniphier-pxs2-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_pxs2_pinctrl_match),
+	.probe = uniphier_pxs2_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
new file mode 100644
index 000000000..1fc7bdb5c
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {39, 40, 41, 42};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59, 60,
+					    61, 62, 63, 64, 65, 66, 67};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					  0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59, 61,
+					   63, 64, 67};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned ether1_rgmii_pins[] = {68, 69, 70, 71, 72, 73, 74, 75, 76,
+					     77, 78, 79, 80, 81, 82, 83};
+static const int ether1_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					   0, 0, 0, 0};
+static const unsigned ether1_rmii_pins[] = {68, 69, 70, 71, 72, 73, 74, 75, 77,
+					    79, 80, 83};
+static const int ether1_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {104, 105};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {106, 107};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const int i2c2_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {110, 111};
+static const int i2c3_muxvals[] = {0, 0};
+static const unsigned nand_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+				     27, 28, 29, 30};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd_pins[] = {43, 44, 45, 46, 47, 48, 49, 50, 51};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {100, 101, 102, 103};
+static const int spi0_muxvals[] = {0, 0, 0, 0};
+static const unsigned spi1_pins[] = {112, 113, 114, 115};
+static const int spi1_muxvals[] = {2, 2, 2, 2};
+static const unsigned system_bus_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
+					   12, 13, 14};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+					 0};
+static const unsigned system_bus_cs1_pins[] = {15};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned uart0_pins[] = {92, 93};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {94, 95};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {96, 97};
+static const int uart2_muxvals[] = {0, 0};
+static const unsigned uart3_pins[] = {98, 99};
+static const int uart3_muxvals[] = {0, 0};
+static const unsigned usb0_pins[] = {84, 85};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {86, 87};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {88, 89};
+static const int usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {90, 91};
+static const int usb3_muxvals[] = {0, 0};
+
+static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
+	UNIPHIER_PINCTRL_GROUP(emmc),
+	UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(ether1_rgmii),
+	UNIPHIER_PINCTRL_GROUP(ether1_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(spi1),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(uart0),
+	UNIPHIER_PINCTRL_GROUP(uart1),
+	UNIPHIER_PINCTRL_GROUP(uart2),
+	UNIPHIER_PINCTRL_GROUP(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+	UNIPHIER_PINCTRL_GROUP(usb3),
+};
+
+static const char * const uniphier_pxs3_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(ether1_rgmii),
+	UNIPHIER_PINMUX_FUNCTION(ether1_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(spi1),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION(uart0),
+	UNIPHIER_PINMUX_FUNCTION(uart1),
+	UNIPHIER_PINMUX_FUNCTION(uart2),
+	UNIPHIER_PINMUX_FUNCTION(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+	UNIPHIER_PINMUX_FUNCTION(usb3),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_pxs3_pinctrl_socdata = {
+	.groups = uniphier_pxs3_groups,
+	.groups_count = ARRAY_SIZE(uniphier_pxs3_groups),
+	.functions = uniphier_pxs3_functions,
+	.functions_count = ARRAY_SIZE(uniphier_pxs3_functions),
+	.caps = UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE |
+		UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_pxs3_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_pxs3_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_pxs3_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-pxs3-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_pxs3_pinctrl) = {
+	.name = "uniphier-pxs3-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_pxs3_pinctrl_match),
+	.probe = uniphier_pxs3_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
new file mode 100644
index 000000000..04c06fb28
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-uniphier.h"
+
+static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14,
+					  61, 63, 64, 65, 66, 67, 68};
+static const int ether_mii_muxvals[] = {13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+					13, 13, 27, 27, 27, 27, 27, 27, 27};
+static const unsigned ether_rmii_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13,
+					   14};
+static const int ether_rmii_muxvals[] = {13, 13, 13, 13, 13, 13, 13, 13, 13,
+					 13, 13, 13};
+static const unsigned i2c0_pins[] = {102, 103};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {104, 105};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c2_pins[] = {108, 109};
+static const int i2c2_muxvals[] = {2, 2};
+static const unsigned i2c3_pins[] = {108, 109};
+static const int i2c3_muxvals[] = {3, 3};
+static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
+				     27, 28, 29, 30, 31};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned nand_cs1_pins[] = {22, 23};
+static const int nand_cs1_muxvals[] = {0, 0};
+static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {118, 119, 120, 121};
+static const int spi0_muxvals[] = {3, 3, 3, 3};
+static const unsigned system_bus_pins[] = {136, 137, 138, 139, 140, 141, 142,
+					   143, 144, 145, 146, 147, 148, 149};
+static const int system_bus_muxvals[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1,
+					 -1, -1, -1, -1, -1};
+static const unsigned system_bus_cs1_pins[] = {150};
+static const int system_bus_cs1_muxvals[] = {-1};
+static const unsigned system_bus_cs2_pins[] = {10};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {11};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {12};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {13};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned uart0_pins[] = {70, 71};
+static const int uart0_muxvals[] = {3, 3};
+static const unsigned uart1_pins[] = {114, 115};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned uart2_pins[] = {112, 113};
+static const int uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {110, 111};
+static const int uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {41, 42};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {43, 44};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {114, 115};
+static const int usb2_muxvals[] = {1, 1};
+
+static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
+	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
+	UNIPHIER_PINCTRL_GROUP(ether_mii),
+	UNIPHIER_PINCTRL_GROUP(ether_rmii),
+	UNIPHIER_PINCTRL_GROUP(i2c0),
+	UNIPHIER_PINCTRL_GROUP(i2c1),
+	UNIPHIER_PINCTRL_GROUP(i2c2),
+	UNIPHIER_PINCTRL_GROUP(i2c3),
+	UNIPHIER_PINCTRL_GROUP(nand),
+	UNIPHIER_PINCTRL_GROUP(nand_cs1),
+	UNIPHIER_PINCTRL_GROUP(sd),
+	UNIPHIER_PINCTRL_GROUP(spi0),
+	UNIPHIER_PINCTRL_GROUP(system_bus),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+	UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
+	UNIPHIER_PINCTRL_GROUP_SPL(uart3),
+	UNIPHIER_PINCTRL_GROUP(usb0),
+	UNIPHIER_PINCTRL_GROUP(usb1),
+	UNIPHIER_PINCTRL_GROUP(usb2),
+};
+
+static const char * const uniphier_sld8_functions[] = {
+	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
+	UNIPHIER_PINMUX_FUNCTION(ether_mii),
+	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+	UNIPHIER_PINMUX_FUNCTION(i2c0),
+	UNIPHIER_PINMUX_FUNCTION(i2c1),
+	UNIPHIER_PINMUX_FUNCTION(i2c2),
+	UNIPHIER_PINMUX_FUNCTION(i2c3),
+	UNIPHIER_PINMUX_FUNCTION(nand),
+	UNIPHIER_PINMUX_FUNCTION(sd),
+	UNIPHIER_PINMUX_FUNCTION(spi0),
+	UNIPHIER_PINMUX_FUNCTION(system_bus),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
+	UNIPHIER_PINMUX_FUNCTION_SPL(uart3),
+	UNIPHIER_PINMUX_FUNCTION(usb0),
+	UNIPHIER_PINMUX_FUNCTION(usb1),
+	UNIPHIER_PINMUX_FUNCTION(usb2),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_sld8_pinctrl_socdata = {
+	.groups = uniphier_sld8_groups,
+	.groups_count = ARRAY_SIZE(uniphier_sld8_groups),
+	.functions = uniphier_sld8_functions,
+	.functions_count = ARRAY_SIZE(uniphier_sld8_functions),
+};
+
+static int uniphier_sld8_pinctrl_probe(struct udevice *dev)
+{
+	return uniphier_pinctrl_probe(dev, &uniphier_sld8_pinctrl_socdata);
+}
+
+static const struct udevice_id uniphier_sld8_pinctrl_match[] = {
+	{ .compatible = "socionext,uniphier-sld8-pinctrl" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_sld8_pinctrl) = {
+	.name = "uniphier-sld8-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(uniphier_sld8_pinctrl_match),
+	.probe = uniphier_sld8_pinctrl_probe,
+	.priv_auto	= sizeof(struct uniphier_pinctrl_priv),
+	.ops = &uniphier_pinctrl_ops,
+};
diff --git a/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier.h
new file mode 100644
index 000000000..5951835d6
--- /dev/null
+++ b/roms/u-boot/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef __PINCTRL_UNIPHIER_H__
+#define __PINCTRL_UNIPHIER_H__
+
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/build_bug.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+/* drive strength control register number */
+#define UNIPHIER_PIN_DRVCTRL_SHIFT	0
+#define UNIPHIER_PIN_DRVCTRL_BITS	9
+#define UNIPHIER_PIN_DRVCTRL_MASK	((1U << (UNIPHIER_PIN_DRVCTRL_BITS)) \
+					 - 1)
+
+/* drive control type */
+#define UNIPHIER_PIN_DRV_TYPE_SHIFT	((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
+					 (UNIPHIER_PIN_DRVCTRL_BITS))
+#define UNIPHIER_PIN_DRV_TYPE_BITS	2
+#define UNIPHIER_PIN_DRV_TYPE_MASK	((1U << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
+					 - 1)
+
+/* drive control type */
+enum uniphier_pin_drv_type {
+	UNIPHIER_PIN_DRV_1BIT,		/* 2 level control: 4/8 mA */
+	UNIPHIER_PIN_DRV_2BIT,		/* 4 level control: 8/12/16/20 mA */
+	UNIPHIER_PIN_DRV_3BIT,		/* 8 level control: 4/5/7/9/11/12/14/16 mA */
+};
+
+#define UNIPHIER_PIN_DRVCTRL(x) \
+	(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
+#define UNIPHIER_PIN_DRV_TYPE(x) \
+	(((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
+
+#define UNIPHIER_PIN_ATTR_PACKED(drvctrl, drv_type)	\
+	UNIPHIER_PIN_DRVCTRL(drvctrl) |			\
+	UNIPHIER_PIN_DRV_TYPE(drv_type)
+
+static inline unsigned int uniphier_pin_get_drvctrl(unsigned int data)
+{
+	return (data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & UNIPHIER_PIN_DRVCTRL_MASK;
+}
+
+static inline unsigned int uniphier_pin_get_drv_type(unsigned int data)
+{
+	return (data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
+						UNIPHIER_PIN_DRV_TYPE_MASK;
+}
+
+/**
+ * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
+ *
+ * @number: pin number
+ * @data: additional per-pin data
+ */
+struct uniphier_pinctrl_pin {
+	unsigned number;
+	const char *name;
+	unsigned int data;
+};
+
+/**
+ * struct uniphier_pinctrl_group - pin group data for UniPhier SoC
+ *
+ * @name: pin group name
+ * @pins: array of pins that belong to the group
+ * @num_pins: number of pins in the group
+ * @muxvals: array of values to be set to pinmux registers
+ */
+struct uniphier_pinctrl_group {
+	const char *name;
+	const unsigned *pins;
+	unsigned num_pins;
+	const int *muxvals;
+};
+
+/**
+ * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller
+ *
+ * @pins: array of pin data
+ * @pins_count: number of pin data
+ * @groups: array of pin group data
+ * @groups_count: number of pin group data
+ * @functions: array of pinmux function names
+ * @functions_count: number of pinmux functions
+ * @mux_bits: bit width of each pinmux register
+ * @reg_stride: stride of pinmux register address
+ * @caps: SoC-specific capability flag
+ */
+struct uniphier_pinctrl_socdata {
+	const struct uniphier_pinctrl_pin *pins;
+	int pins_count;
+	const struct uniphier_pinctrl_group *groups;
+	int groups_count;
+	const char * const *functions;
+	int functions_count;
+	unsigned caps;
+#define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE	BIT(3)
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL	BIT(2)
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE	BIT(1)
+#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT		BIT(0)
+};
+
+#define UNIPHIER_PINCTRL_PIN(a, b, c, d)				\
+{									\
+	.number = a,							\
+	.name = b,							\
+	.data = UNIPHIER_PIN_ATTR_PACKED(c, d),				\
+}
+
+#define __UNIPHIER_PINCTRL_GROUP(grp)					\
+	{								\
+		.name = #grp,						\
+		.pins = grp##_pins,					\
+		.num_pins = ARRAY_SIZE(grp##_pins),			\
+		.muxvals = grp##_muxvals +				\
+			BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) !=	\
+					  ARRAY_SIZE(grp##_muxvals)),	\
+	}
+
+#define __UNIPHIER_PINMUX_FUNCTION(func)	#func
+
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
+	 * suppressing "defined but not used" warnings.
+	 */
+#define UNIPHIER_PINCTRL_GROUP(grp)					\
+	{ .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
+#define UNIPHIER_PINMUX_FUNCTION(func)		NULL
+#else
+#define UNIPHIER_PINCTRL_GROUP(grp)		__UNIPHIER_PINCTRL_GROUP(grp)
+#define UNIPHIER_PINMUX_FUNCTION(func)		__UNIPHIER_PINMUX_FUNCTION(func)
+#endif
+
+#define UNIPHIER_PINCTRL_GROUP_SPL(grp)		__UNIPHIER_PINCTRL_GROUP(grp)
+#define UNIPHIER_PINMUX_FUNCTION_SPL(func)	__UNIPHIER_PINMUX_FUNCTION(func)
+
+/**
+ * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
+ *
+ * @base: base address of the pinctrl device
+ * @socdata: SoC specific data
+ */
+struct uniphier_pinctrl_priv {
+	void __iomem *base;
+	struct uniphier_pinctrl_socdata *socdata;
+};
+
+extern const struct pinctrl_ops uniphier_pinctrl_ops;
+
+int uniphier_pinctrl_probe(struct udevice *dev,
+			   struct uniphier_pinctrl_socdata *socdata);
+
+#endif /* __PINCTRL_UNIPHIER_H__ */