Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

28 files changed, 4122 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/reset/Kconfig b/roms/u-boot/drivers/reset/Kconfig
new file mode 100644
index 000000000..a42b3f007
--- /dev/null
+++ b/roms/u-boot/drivers/reset/Kconfig
@@ -0,0 +1,200 @@
+menu "Reset Controller Support"
+
+config DM_RESET
+	bool "Enable reset controllers using Driver Model"
+	depends on DM && OF_CONTROL
+	help
+	  Enable support for the reset controller driver class. Many hardware
+	  modules are equipped with a reset signal, typically driven by some
+	  reset controller hardware module within the chip. In U-Boot, reset
+	  controller drivers allow control over these reset signals. In some
+	  cases this API is applicable to chips outside the CPU as well,
+	  although driving such reset isgnals using GPIOs may be more
+	  appropriate in this case.
+
+config SANDBOX_RESET
+	bool "Enable the sandbox reset test driver"
+	depends on DM_MAILBOX && SANDBOX
+	help
+	  Enable support for a test reset controller implementation, which
+	  simply accepts requests to reset various HW modules without actually
+	  doing anything beyond a little error checking.
+
+config STI_RESET
+	bool "Enable the STi reset"
+	depends on ARCH_STI
+	help
+	  Support for reset controllers on STMicroelectronics STiH407 family SoCs.
+	  Say Y if you want to control reset signals provided by system config
+	  block.
+
+config STM32_RESET
+	bool "Enable the STM32 reset"
+	depends on ARCH_STM32 || ARCH_STM32MP
+	help
+	  Support for reset controllers on STMicroelectronics STM32 family SoCs.
+	  This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
+
+config TEGRA_CAR_RESET
+	bool "Enable Tegra CAR-based reset driver"
+	depends on TEGRA_CAR
+	help
+	  Enable support for manipulating Tegra's on-SoC reset signals via
+	  direct register access to the Tegra CAR (Clock And Reset controller).
+
+config TEGRA186_RESET
+	bool "Enable Tegra186 BPMP-based reset driver"
+	depends on TEGRA186_BPMP
+	help
+	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
+	  requests to the BPMP (Boot and Power Management Processor).
+
+config RESET_TI_SCI
+	bool "TI System Control Interface (TI SCI) reset driver"
+	depends on DM_RESET && TI_SCI_PROTOCOL
+	help
+	  This enables the reset driver support over TI System Control Interface
+	  available on some new TI's SoCs. If you wish to use reset resources
+	  managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config RESET_BCM6345
+	bool "Reset controller driver for BCM6345"
+	depends on DM_RESET && ARCH_BMIPS
+	help
+	  Support reset controller on BCM6345.
+
+config RESET_UNIPHIER
+	bool "Reset controller driver for UniPhier SoCs"
+	depends on ARCH_UNIPHIER
+	default y
+	help
+	  Support for reset controllers on UniPhier SoCs.
+	  Say Y if you want to control reset signals provided by System Control
+	  block, Media I/O block, Peripheral Block.
+
+config RESET_AST2500
+	bool "Reset controller driver for AST2500 SoCs"
+	depends on DM_RESET
+	default y if ASPEED_AST2500
+	help
+	  Support for reset controller on AST2500 SoC.
+	  Say Y if you want to control reset signals of different peripherals
+	  through System Control Unit (SCU).
+
+config RESET_AST2600
+	bool "Reset controller driver for AST2600 SoCs"
+	depends on DM_RESET
+	default y if ASPEED_AST2600
+	help
+	  Support for reset controller on AST2600 SoC.
+	  Say Y if you want to control reset signals of different peripherals
+	  through System Control Unit (SCU).
+
+config RESET_ROCKCHIP
+	bool "Reset controller driver for Rockchip SoCs"
+	depends on DM_RESET && ARCH_ROCKCHIP && CLK
+	default y
+	help
+	  Support for reset controller on rockchip SoC. The main limitation
+	  though is that some reset signals, like I2C or MISC reset multiple
+	  devices.
+
+config RESET_HSDK
+	bool "Synopsys HSDK Reset Driver"
+	depends on DM_RESET && TARGET_HSDK
+	default y
+	help
+	  This enables the reset controller driver for HSDK board.
+
+config RESET_MESON
+	bool "Reset controller driver for Amlogic Meson SoCs"
+	depends on DM_RESET && ARCH_MESON
+	imply REGMAP
+	default y
+	help
+	  Support for reset controller on Amlogic Meson SoC.
+
+config RESET_SOCFPGA
+	bool "Reset controller driver for SoCFPGA"
+	depends on DM_RESET && ARCH_SOCFPGA
+	default y
+	help
+	  Support for reset controller on SoCFPGA platform.
+
+config RESET_MEDIATEK
+	bool "Reset controller driver for MediaTek SoCs"
+	depends on DM_RESET && ARCH_MEDIATEK && CLK
+	default y
+	help
+	  Support for reset controller on MediaTek SoCs.
+
+config RESET_MTMIPS
+	bool "Reset controller driver for MediaTek MIPS platform"
+	depends on DM_RESET && ARCH_MTMIPS
+	default y
+	help
+	  Support for reset controller on MediaTek MIPS platform.
+
+config RESET_SUNXI
+	bool "RESET support for Allwinner SoCs"
+	depends on DM_RESET && ARCH_SUNXI
+	default y
+	help
+	  This enables support for common reset driver for
+	  Allwinner SoCs.
+
+config RESET_HISILICON
+	bool "Reset controller driver for HiSilicon SoCs"
+	depends on DM_RESET
+	help
+	  Support for reset controller on HiSilicon SoCs.
+
+config RESET_IMX7
+	bool "i.MX7/8 Reset Driver"
+	depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
+	default y
+	help
+	  Support for reset controller on i.MX7/8 SoCs.
+
+config RESET_IPQ419
+	bool "Reset driver for Qualcomm IPQ40xx SoCs"
+	depends on DM_RESET && ARCH_IPQ40XX
+	default y
+	help
+	  Support for reset controller on Qualcomm
+	  IPQ40xx SoCs.
+
+config RESET_SIFIVE
+	bool "Reset Driver for SiFive SoC's"
+	depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
+	default y
+	help
+	  PRCI module within SiFive SoC's provides mechanism to reset
+	  different hw blocks like DDR, gemgxl. With this driver we leverage
+	  U-Boot's reset framework to reset these hardware blocks.
+
+config RESET_SYSCON
+	bool "Enable generic syscon reset driver support"
+	depends on DM_RESET
+	help
+	  Support generic syscon mapped register reset devices.
+
+config RESET_RASPBERRYPI
+	bool "Raspberry Pi 4 Firmware Reset Controller Driver"
+	depends on DM_RESET && ARCH_BCM283X
+	default USB_XHCI_PCI
+	help
+	  Raspberry Pi 4's co-processor controls some of the board's HW
+	  initialization process, but it's up to Linux to trigger it when
+	  relevant. This driver provides a reset controller capable of
+	  interfacing with RPi4's co-processor and model these firmware
+	  initialization routines as reset lines.
+
+config RESET_SCMI
+	bool "Enable SCMI reset domain driver"
+	select SCMI_FIRMWARE
+	help
+	  Enable this option if you want to support reset controller
+	  devices exposed by a SCMI agent based on SCMI reset domain
+	  protocol communication with a SCMI server.
+endmenu
diff --git a/roms/u-boot/drivers/reset/Makefile b/roms/u-boot/drivers/reset/Makefile
new file mode 100644
index 000000000..8a0f52807
--- /dev/null
+++ b/roms/u-boot/drivers/reset/Makefile
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+
+obj-$(CONFIG_DM_RESET) += reset-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_STI_RESET) += sti-reset.o
+obj-$(CONFIG_STM32_RESET) += stm32-reset.o
+obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
+obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
+obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
+obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
+obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
+obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
+obj-$(CONFIG_RESET_MESON) += reset-meson.o
+obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
+obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
+obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
+obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
+obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
+obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
+obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
+obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
diff --git a/roms/u-boot/drivers/reset/reset-ast2500.c b/roms/u-boot/drivers/reset/reset-ast2500.c
new file mode 100644
index 000000000..c3d650fc6
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-ast2500.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+
+struct ast2500_reset_priv {
+	struct ast2500_scu *scu;
+};
+
+static int ast2500_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2500_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
+}
+
+static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
+}
+
+static int ast2500_reset_probe(struct udevice *dev)
+{
+	int rc;
+	struct ast2500_reset_priv *priv = dev_get_priv(dev);
+	struct udevice *scu_dev;
+
+	/* get SCU base from clock device */
+	rc = uclass_get_device_by_driver(UCLASS_CLK,
+					 DM_DRIVER_GET(aspeed_ast2500_scu), &scu_dev);
+	if (rc) {
+		debug("%s: clock device not found, rc=%d\n", __func__, rc);
+		return rc;
+	}
+
+	priv->scu = devfdt_get_addr_ptr(scu_dev);
+	if (IS_ERR_OR_NULL(priv->scu)) {
+		debug("%s: invalid SCU base pointer\n", __func__);
+		return PTR_ERR(priv->scu);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ast2500_reset_ids[] = {
+	{ .compatible = "aspeed,ast2500-reset" },
+	{ }
+};
+
+struct reset_ops ast2500_reset_ops = {
+	.request = ast2500_reset_request,
+	.rfree = ast2500_reset_free,
+	.rst_assert = ast2500_reset_assert,
+	.rst_deassert = ast2500_reset_deassert,
+};
+
+U_BOOT_DRIVER(ast2500_reset) = {
+	.name = "ast2500_reset",
+	.id = UCLASS_RESET,
+	.of_match = ast2500_reset_ids,
+	.probe = ast2500_reset_probe,
+	.ops = &ast2500_reset_ops,
+	.priv_auto	= sizeof(struct ast2500_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-ast2600.c b/roms/u-boot/drivers/reset/reset-ast2600.c
new file mode 100644
index 000000000..f64adaf74
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-ast2600.c
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2600.h>
+
+struct ast2600_reset_priv {
+	struct ast2600_scu *scu;
+};
+
+static int ast2600_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2600_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2600_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2600_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		writel(BIT(reset_ctl->id), scu->modrst_ctrl1);
+	else
+		writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2);
+
+	return 0;
+}
+
+static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2600_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		writel(BIT(reset_ctl->id), scu->modrst_clr1);
+	else
+		writel(BIT(reset_ctl->id - 32), scu->modrst_clr2);
+
+	return 0;
+}
+
+static int ast2600_reset_probe(struct udevice *dev)
+{
+	int rc;
+	struct ast2600_reset_priv *priv = dev_get_priv(dev);
+	struct udevice *scu_dev;
+
+	/* get SCU base from clock device */
+	rc = uclass_get_device_by_driver(UCLASS_CLK,
+					 DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
+	if (rc) {
+		debug("%s: clock device not found, rc=%d\n", __func__, rc);
+		return rc;
+	}
+
+	priv->scu = devfdt_get_addr_ptr(scu_dev);
+	if (IS_ERR_OR_NULL(priv->scu)) {
+		debug("%s: invalid SCU base pointer\n", __func__);
+		return PTR_ERR(priv->scu);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ast2600_reset_ids[] = {
+	{ .compatible = "aspeed,ast2600-reset" },
+	{ }
+};
+
+struct reset_ops ast2600_reset_ops = {
+	.request = ast2600_reset_request,
+	.rfree = ast2600_reset_free,
+	.rst_assert = ast2600_reset_assert,
+	.rst_deassert = ast2600_reset_deassert,
+};
+
+U_BOOT_DRIVER(ast2600_reset) = {
+	.name = "ast2600_reset",
+	.id = UCLASS_RESET,
+	.of_match = ast2600_reset_ids,
+	.probe = ast2600_reset_probe,
+	.ops = &ast2600_reset_ops,
+	.priv_auto = sizeof(struct ast2600_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-bcm6345.c b/roms/u-boot/drivers/reset/reset-bcm6345.c
new file mode 100644
index 000000000..f69189822
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-bcm6345.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/reset.c:
+ *	Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#define MAX_RESETS	32
+
+struct bcm6345_reset_priv {
+	void __iomem *regs;
+};
+
+static int bcm6345_reset_assert(struct reset_ctl *rst)
+{
+	struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
+
+	clrbits_be32(priv->regs, BIT(rst->id));
+	mdelay(20);
+
+	return 0;
+}
+
+static int bcm6345_reset_deassert(struct reset_ctl *rst)
+{
+	struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
+
+	setbits_be32(priv->regs, BIT(rst->id));
+	mdelay(20);
+
+	return 0;
+}
+
+static int bcm6345_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int bcm6345_reset_request(struct reset_ctl *rst)
+{
+	if (rst->id >= MAX_RESETS)
+		return -EINVAL;
+
+	return bcm6345_reset_assert(rst);
+}
+
+struct reset_ops bcm6345_reset_reset_ops = {
+	.rfree = bcm6345_reset_free,
+	.request = bcm6345_reset_request,
+	.rst_assert = bcm6345_reset_assert,
+	.rst_deassert = bcm6345_reset_deassert,
+};
+
+static const struct udevice_id bcm6345_reset_ids[] = {
+	{ .compatible = "brcm,bcm6345-reset" },
+	{ /* sentinel */ }
+};
+
+static int bcm6345_reset_probe(struct udevice *dev)
+{
+	struct bcm6345_reset_priv *priv = dev_get_priv(dev);
+
+	priv->regs = dev_remap_addr(dev);
+	if (!priv->regs)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(bcm6345_reset) = {
+	.name = "bcm6345-reset",
+	.id = UCLASS_RESET,
+	.of_match = bcm6345_reset_ids,
+	.ops = &bcm6345_reset_reset_ops,
+	.probe = bcm6345_reset_probe,
+	.priv_auto	= sizeof(struct bcm6345_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-hisilicon.c b/roms/u-boot/drivers/reset/reset-hisilicon.c
new file mode 100644
index 000000000..3f9da8cc8
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-hisilicon.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/ti-syscon.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+
+struct hisi_reset_priv {
+	void __iomem *base;
+};
+
+static int hisi_reset_deassert(struct reset_ctl *rst)
+{
+	struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
+	u32 val;
+
+	val = readl(priv->base + rst->data);
+	if (rst->polarity & DEASSERT_SET)
+		val |= BIT(rst->id);
+	else
+		val &= ~BIT(rst->id);
+	writel(val, priv->base + rst->data);
+
+	return 0;
+}
+
+static int hisi_reset_assert(struct reset_ctl *rst)
+{
+	struct hisi_reset_priv *priv = dev_get_priv(rst->dev);
+	u32 val;
+
+	val = readl(priv->base + rst->data);
+	if (rst->polarity & ASSERT_SET)
+		val |= BIT(rst->id);
+	else
+		val &= ~BIT(rst->id);
+	writel(val, priv->base + rst->data);
+
+	return 0;
+}
+
+static int hisi_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int hisi_reset_request(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int hisi_reset_of_xlate(struct reset_ctl *rst,
+			       struct ofnode_phandle_args *args)
+{
+	if (args->args_count != 3) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	/* Use .data field as register offset and .id field as bit shift */
+	rst->data = args->args[0];
+	rst->id = args->args[1];
+	rst->polarity = args->args[2];
+
+	return 0;
+}
+
+static const struct reset_ops hisi_reset_reset_ops = {
+	.of_xlate = hisi_reset_of_xlate,
+	.request = hisi_reset_request,
+	.rfree = hisi_reset_free,
+	.rst_assert = hisi_reset_assert,
+	.rst_deassert = hisi_reset_deassert,
+};
+
+static const struct udevice_id hisi_reset_ids[] = {
+	{ .compatible = "hisilicon,hi3798cv200-reset" },
+	{ }
+};
+
+static int hisi_reset_probe(struct udevice *dev)
+{
+	struct hisi_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(hisi_reset) = {
+	.name = "hisilicon_reset",
+	.id = UCLASS_RESET,
+	.of_match = hisi_reset_ids,
+	.ops = &hisi_reset_reset_ops,
+	.probe = hisi_reset_probe,
+	.priv_auto	= sizeof(struct hisi_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-hsdk.c b/roms/u-boot/drivers/reset/reset-hsdk.c
new file mode 100644
index 000000000..8318d0a20
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-hsdk.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * HSDK SoC Reset Controller driver
+ *
+ * Copyright (C) 2019 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+
+#include <log.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <reset-uclass.h>
+
+struct hsdk_rst {
+	void __iomem		*regs_ctl;
+	void __iomem		*regs_rst;
+};
+
+static const u32 rst_map[] = {
+	BIT(16), /* APB_RST  */
+	BIT(17), /* AXI_RST  */
+	BIT(18), /* ETH_RST  */
+	BIT(19), /* USB_RST  */
+	BIT(20), /* SDIO_RST */
+	BIT(21), /* HDMI_RST */
+	BIT(22), /* GFX_RST  */
+	BIT(25), /* DMAC_RST */
+	BIT(31), /* EBI_RST  */
+};
+
+#define HSDK_MAX_RESETS			ARRAY_SIZE(rst_map)
+
+#define CGU_SYS_RST_CTRL		0x0
+#define CGU_IP_SW_RESET			0x0
+#define CGU_IP_SW_RESET_DELAY_SHIFT	16
+#define CGU_IP_SW_RESET_DELAY_MASK	GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
+#define CGU_IP_SW_RESET_DELAY		0
+#define CGU_IP_SW_RESET_RESET		BIT(0)
+#define SW_RESET_TIMEOUT		10000
+
+static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
+{
+	writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
+}
+
+static int hsdk_reset_do(struct hsdk_rst *rst)
+{
+	u32 reg;
+
+	reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
+	reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
+	reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
+	reg |= CGU_IP_SW_RESET_RESET;
+	writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
+
+	/* wait till reset bit is back to 0 */
+	return readl_poll_timeout(rst->regs_rst + CGU_IP_SW_RESET, reg,
+		!(reg & CGU_IP_SW_RESET_RESET), SW_RESET_TIMEOUT);
+}
+
+static int hsdk_reset_reset(struct reset_ctl *rst_ctl)
+{
+	struct udevice *dev = rst_ctl->dev;
+	struct hsdk_rst *rst = dev_get_priv(dev);
+
+	if (rst_ctl->id >= HSDK_MAX_RESETS)
+		return -EINVAL;
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, rst_ctl,
+	      rst_ctl->dev, rst_ctl->id);
+
+	hsdk_reset_config(rst, rst_ctl->id);
+	return hsdk_reset_do(rst);
+}
+
+static int hsdk_reset_noop(struct reset_ctl *rst_ctl)
+{
+	return 0;
+}
+
+static const struct reset_ops hsdk_reset_ops = {
+	.request	= hsdk_reset_noop,
+	.rfree		= hsdk_reset_noop,
+	.rst_assert	= hsdk_reset_noop,
+	.rst_deassert	= hsdk_reset_reset,
+};
+
+static const struct udevice_id hsdk_reset_dt_match[] = {
+	{ .compatible = "snps,hsdk-reset" },
+	{ },
+};
+
+static int hsdk_reset_probe(struct udevice *dev)
+{
+	struct hsdk_rst *rst = dev_get_priv(dev);
+
+	rst->regs_ctl = dev_remap_addr_index(dev, 0);
+	if (!rst->regs_ctl)
+		return -EINVAL;
+
+	rst->regs_rst = dev_remap_addr_index(dev, 1);
+	if (!rst->regs_rst)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(hsdk_reset) = {
+	.name = "hsdk-reset",
+	.id = UCLASS_RESET,
+	.of_match = hsdk_reset_dt_match,
+	.ops = &hsdk_reset_ops,
+	.probe = hsdk_reset_probe,
+	.priv_auto	= sizeof(struct hsdk_rst),
+};
diff --git a/roms/u-boot/drivers/reset/reset-imx7.c b/roms/u-boot/drivers/reset/reset-imx7.c
new file mode 100644
index 000000000..e5085ae17
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-imx7.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017, Impinj, Inc.
+ */
+
+#include <log.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/imx7-reset.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+struct imx7_reset_priv {
+	void __iomem *base;
+	struct reset_ops ops;
+};
+
+struct imx7_src_signal {
+	unsigned int offset, bit;
+};
+
+enum imx7_src_registers {
+	SRC_A7RCR0		= 0x0004,
+	SRC_M4RCR		= 0x000c,
+	SRC_ERCR		= 0x0014,
+	SRC_HSICPHY_RCR		= 0x001c,
+	SRC_USBOPHY1_RCR	= 0x0020,
+	SRC_USBOPHY2_RCR	= 0x0024,
+	SRC_MIPIPHY_RCR		= 0x0028,
+	SRC_PCIEPHY_RCR		= 0x002c,
+	SRC_DDRC_RCR		= 0x1000,
+};
+
+static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
+	[IMX7_RESET_A7_CORE_POR_RESET0]	= { SRC_A7RCR0, BIT(0) },
+	[IMX7_RESET_A7_CORE_POR_RESET1]	= { SRC_A7RCR0, BIT(1) },
+	[IMX7_RESET_A7_CORE_RESET0]	= { SRC_A7RCR0, BIT(4) },
+	[IMX7_RESET_A7_CORE_RESET1]	= { SRC_A7RCR0, BIT(5) },
+	[IMX7_RESET_A7_DBG_RESET0]	= { SRC_A7RCR0, BIT(8) },
+	[IMX7_RESET_A7_DBG_RESET1]	= { SRC_A7RCR0, BIT(9) },
+	[IMX7_RESET_A7_ETM_RESET0]	= { SRC_A7RCR0, BIT(12) },
+	[IMX7_RESET_A7_ETM_RESET1]	= { SRC_A7RCR0, BIT(13) },
+	[IMX7_RESET_A7_SOC_DBG_RESET]	= { SRC_A7RCR0, BIT(20) },
+	[IMX7_RESET_A7_L2RESET]		= { SRC_A7RCR0, BIT(21) },
+	[IMX7_RESET_SW_M4C_RST]		= { SRC_M4RCR, BIT(1) },
+	[IMX7_RESET_SW_M4P_RST]		= { SRC_M4RCR, BIT(2) },
+	[IMX7_RESET_EIM_RST]		= { SRC_ERCR, BIT(0) },
+	[IMX7_RESET_HSICPHY_PORT_RST]	= { SRC_HSICPHY_RCR, BIT(1) },
+	[IMX7_RESET_USBPHY1_POR]	= { SRC_USBOPHY1_RCR, BIT(0) },
+	[IMX7_RESET_USBPHY1_PORT_RST]	= { SRC_USBOPHY1_RCR, BIT(1) },
+	[IMX7_RESET_USBPHY2_POR]	= { SRC_USBOPHY2_RCR, BIT(0) },
+	[IMX7_RESET_USBPHY2_PORT_RST]	= { SRC_USBOPHY2_RCR, BIT(1) },
+	[IMX7_RESET_MIPI_PHY_MRST]	= { SRC_MIPIPHY_RCR, BIT(1) },
+	[IMX7_RESET_MIPI_PHY_SRST]	= { SRC_MIPIPHY_RCR, BIT(2) },
+	[IMX7_RESET_PCIEPHY]		= { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
+	[IMX7_RESET_PCIEPHY_PERST]	= { SRC_PCIEPHY_RCR, BIT(3) },
+	[IMX7_RESET_PCIE_CTRL_APPS_EN]	= { SRC_PCIEPHY_RCR, BIT(6) },
+	[IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+	[IMX7_RESET_DDRC_PRST]		= { SRC_DDRC_RCR, BIT(0) },
+	[IMX7_RESET_DDRC_CORE_RST]	= { SRC_DDRC_RCR, BIT(1) },
+};
+
+static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct imx7_src_signal *sig = imx7_src_signals;
+	u32 val;
+
+	if (rst->id >= IMX7_RESET_NUM)
+		return -EINVAL;
+
+	if (rst->id == IMX7_RESET_PCIEPHY) {
+		/*
+		 * wait for more than 10us to release phy g_rst and
+		 * btnrst
+		 */
+		udelay(10);
+	}
+
+	val = readl(priv->base + sig[rst->id].offset);
+	switch (rst->id) {
+	case IMX7_RESET_PCIE_CTRL_APPS_EN:
+		val |= sig[rst->id].bit;
+		break;
+	default:
+		val &= ~sig[rst->id].bit;
+		break;
+	}
+	writel(val, priv->base + sig[rst->id].offset);
+
+	return 0;
+}
+
+static int imx7_reset_assert_imx7(struct reset_ctl *rst)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct imx7_src_signal *sig = imx7_src_signals;
+	u32 val;
+
+	if (rst->id >= IMX7_RESET_NUM)
+		return -EINVAL;
+
+	val = readl(priv->base + sig[rst->id].offset);
+	switch (rst->id) {
+	case IMX7_RESET_PCIE_CTRL_APPS_EN:
+		val &= ~sig[rst->id].bit;
+		break;
+	default:
+		val |= sig[rst->id].bit;
+		break;
+	}
+	writel(val, priv->base + sig[rst->id].offset);
+
+	return 0;
+}
+
+enum imx8mq_src_registers {
+	SRC_A53RCR0		= 0x0004,
+	SRC_HDMI_RCR		= 0x0030,
+	SRC_DISP_RCR		= 0x0034,
+	SRC_GPU_RCR		= 0x0040,
+	SRC_VPU_RCR		= 0x0044,
+	SRC_PCIE2_RCR		= 0x0048,
+	SRC_MIPIPHY1_RCR	= 0x004c,
+	SRC_MIPIPHY2_RCR	= 0x0050,
+	SRC_DDRC2_RCR		= 0x1004,
+};
+
+static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
+	[IMX8MQ_RESET_A53_CORE_POR_RESET0]	= { SRC_A53RCR0, BIT(0) },
+	[IMX8MQ_RESET_A53_CORE_POR_RESET1]	= { SRC_A53RCR0, BIT(1) },
+	[IMX8MQ_RESET_A53_CORE_POR_RESET2]	= { SRC_A53RCR0, BIT(2) },
+	[IMX8MQ_RESET_A53_CORE_POR_RESET3]	= { SRC_A53RCR0, BIT(3) },
+	[IMX8MQ_RESET_A53_CORE_RESET0]		= { SRC_A53RCR0, BIT(4) },
+	[IMX8MQ_RESET_A53_CORE_RESET1]		= { SRC_A53RCR0, BIT(5) },
+	[IMX8MQ_RESET_A53_CORE_RESET2]		= { SRC_A53RCR0, BIT(6) },
+	[IMX8MQ_RESET_A53_CORE_RESET3]		= { SRC_A53RCR0, BIT(7) },
+	[IMX8MQ_RESET_A53_DBG_RESET0]		= { SRC_A53RCR0, BIT(8) },
+	[IMX8MQ_RESET_A53_DBG_RESET1]		= { SRC_A53RCR0, BIT(9) },
+	[IMX8MQ_RESET_A53_DBG_RESET2]		= { SRC_A53RCR0, BIT(10) },
+	[IMX8MQ_RESET_A53_DBG_RESET3]		= { SRC_A53RCR0, BIT(11) },
+	[IMX8MQ_RESET_A53_ETM_RESET0]		= { SRC_A53RCR0, BIT(12) },
+	[IMX8MQ_RESET_A53_ETM_RESET1]		= { SRC_A53RCR0, BIT(13) },
+	[IMX8MQ_RESET_A53_ETM_RESET2]		= { SRC_A53RCR0, BIT(14) },
+	[IMX8MQ_RESET_A53_ETM_RESET3]		= { SRC_A53RCR0, BIT(15) },
+	[IMX8MQ_RESET_A53_SOC_DBG_RESET]	= { SRC_A53RCR0, BIT(20) },
+	[IMX8MQ_RESET_A53_L2RESET]		= { SRC_A53RCR0, BIT(21) },
+	[IMX8MQ_RESET_SW_NON_SCLR_M4C_RST]	= { SRC_M4RCR, BIT(0) },
+	[IMX8MQ_RESET_OTG1_PHY_RESET]		= { SRC_USBOPHY1_RCR, BIT(0) },
+	[IMX8MQ_RESET_OTG2_PHY_RESET]		= { SRC_USBOPHY2_RCR, BIT(0) },
+	[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N]	= { SRC_MIPIPHY_RCR, BIT(1) },
+	[IMX8MQ_RESET_MIPI_DSI_RESET_N]		= { SRC_MIPIPHY_RCR, BIT(2) },
+	[IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N]	= { SRC_MIPIPHY_RCR, BIT(3) },
+	[IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N]	= { SRC_MIPIPHY_RCR, BIT(4) },
+	[IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N]	= { SRC_MIPIPHY_RCR, BIT(5) },
+	[IMX8MQ_RESET_PCIEPHY]			= { SRC_PCIEPHY_RCR,
+						    BIT(2) | BIT(1) },
+	[IMX8MQ_RESET_PCIEPHY_PERST]		= { SRC_PCIEPHY_RCR, BIT(3) },
+	[IMX8MQ_RESET_PCIE_CTRL_APPS_EN]	= { SRC_PCIEPHY_RCR, BIT(6) },
+	[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF]	= { SRC_PCIEPHY_RCR, BIT(11) },
+	[IMX8MQ_RESET_HDMI_PHY_APB_RESET]	= { SRC_HDMI_RCR, BIT(0) },
+	[IMX8MQ_RESET_DISP_RESET]		= { SRC_DISP_RCR, BIT(0) },
+	[IMX8MQ_RESET_GPU_RESET]		= { SRC_GPU_RCR, BIT(0) },
+	[IMX8MQ_RESET_VPU_RESET]		= { SRC_VPU_RCR, BIT(0) },
+	[IMX8MQ_RESET_PCIEPHY2]			= { SRC_PCIE2_RCR,
+						    BIT(2) | BIT(1) },
+	[IMX8MQ_RESET_PCIEPHY2_PERST]		= { SRC_PCIE2_RCR, BIT(3) },
+	[IMX8MQ_RESET_PCIE2_CTRL_APPS_EN]	= { SRC_PCIE2_RCR, BIT(6) },
+	[IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF]	= { SRC_PCIE2_RCR, BIT(11) },
+	[IMX8MQ_RESET_MIPI_CSI1_CORE_RESET]	= { SRC_MIPIPHY1_RCR, BIT(0) },
+	[IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET]	= { SRC_MIPIPHY1_RCR, BIT(1) },
+	[IMX8MQ_RESET_MIPI_CSI1_ESC_RESET]	= { SRC_MIPIPHY1_RCR, BIT(2) },
+	[IMX8MQ_RESET_MIPI_CSI2_CORE_RESET]	= { SRC_MIPIPHY2_RCR, BIT(0) },
+	[IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET]	= { SRC_MIPIPHY2_RCR, BIT(1) },
+	[IMX8MQ_RESET_MIPI_CSI2_ESC_RESET]	= { SRC_MIPIPHY2_RCR, BIT(2) },
+	[IMX8MQ_RESET_DDRC1_PRST]		= { SRC_DDRC_RCR, BIT(0) },
+	[IMX8MQ_RESET_DDRC1_CORE_RESET]		= { SRC_DDRC_RCR, BIT(1) },
+	[IMX8MQ_RESET_DDRC1_PHY_RESET]		= { SRC_DDRC_RCR, BIT(2) },
+	[IMX8MQ_RESET_DDRC2_PHY_RESET]		= { SRC_DDRC2_RCR, BIT(0) },
+	[IMX8MQ_RESET_DDRC2_CORE_RESET]		= { SRC_DDRC2_RCR, BIT(1) },
+	[IMX8MQ_RESET_DDRC2_PRST]		= { SRC_DDRC2_RCR, BIT(2) },
+};
+
+static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct imx7_src_signal *sig = imx8mq_src_signals;
+	u32 val;
+
+	if (rst->id >= IMX8MQ_RESET_NUM)
+		return -EINVAL;
+
+	if (rst->id == IMX8MQ_RESET_PCIEPHY ||
+	    rst->id == IMX8MQ_RESET_PCIEPHY2) {
+		/*
+		 * wait for more than 10us to release phy g_rst and
+		 * btnrst
+		 */
+		udelay(10);
+	}
+
+	val = readl(priv->base + sig[rst->id].offset);
+	switch (rst->id) {
+	case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
+	case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N:	/* fallthrough */
+		val |= sig[rst->id].bit;
+		break;
+	default:
+		val &= ~sig[rst->id].bit;
+		break;
+	}
+	writel(val, priv->base + sig[rst->id].offset);
+
+	return 0;
+}
+
+static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct imx7_src_signal *sig = imx8mq_src_signals;
+	u32 val;
+
+	if (rst->id >= IMX8MQ_RESET_NUM)
+		return -EINVAL;
+
+	val = readl(priv->base + sig[rst->id].offset);
+	switch (rst->id) {
+	case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
+	case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_RESET_N:	/* fallthrough */
+	case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N:	/* fallthrough */
+		val &= ~sig[rst->id].bit;
+		break;
+	default:
+		val |= sig[rst->id].bit;
+		break;
+	}
+	writel(val, priv->base + sig[rst->id].offset);
+
+	return 0;
+}
+
+static int imx7_reset_assert(struct reset_ctl *rst)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+	return priv->ops.rst_assert(rst);
+}
+
+static int imx7_reset_deassert(struct reset_ctl *rst)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+	return priv->ops.rst_deassert(rst);
+}
+
+static int imx7_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int imx7_reset_request(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops imx7_reset_reset_ops = {
+	.request = imx7_reset_request,
+	.rfree = imx7_reset_free,
+	.rst_assert = imx7_reset_assert,
+	.rst_deassert = imx7_reset_deassert,
+};
+
+static const struct udevice_id imx7_reset_ids[] = {
+	{ .compatible = "fsl,imx7d-src" },
+	{ .compatible = "fsl,imx8mq-src" },
+	{ }
+};
+
+static int imx7_reset_probe(struct udevice *dev)
+{
+	struct imx7_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	if (device_is_compatible(dev, "fsl,imx8mq-src")) {
+		priv->ops.rst_assert = imx7_reset_assert_imx8mq;
+		priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
+	} else if (device_is_compatible(dev, "fsl,imx7d-src")) {
+		priv->ops.rst_assert = imx7_reset_assert_imx7;
+		priv->ops.rst_deassert = imx7_reset_deassert_imx7;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(imx7_reset) = {
+	.name = "imx7_reset",
+	.id = UCLASS_RESET,
+	.of_match = imx7_reset_ids,
+	.ops = &imx7_reset_reset_ops,
+	.probe = imx7_reset_probe,
+	.priv_auto	= sizeof(struct imx7_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-ipq4019.c b/roms/u-boot/drivers/reset/reset-ipq4019.c
new file mode 100644
index 000000000..15858f3cb
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-ipq4019.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <dt-bindings/reset/qcom,ipq4019-reset.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <malloc.h>
+
+struct ipq4019_reset_priv {
+	phys_addr_t base;
+};
+
+struct qcom_reset_map {
+	unsigned int reg;
+	u8 bit;
+};
+
+static const struct qcom_reset_map gcc_ipq4019_resets[] = {
+	[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
+	[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
+	[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
+	[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
+	[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
+	[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
+	[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
+	[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
+	[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
+	[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
+	[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
+	[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
+	[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
+	[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
+	[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
+	[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
+	[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
+	[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
+	[PCIE_AHB_ARES] = { 0x1d010, 10 },
+	[PCIE_PWR_ARES] = { 0x1d010, 9 },
+	[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
+	[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
+	[PCIE_PHY_ARES] = { 0x1d010, 6 },
+	[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
+	[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
+	[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
+	[PCIE_PIPE_ARES] = { 0x1d010, 2 },
+	[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
+	[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
+	[ESS_RESET] = { 0x12008, 0},
+	[GCC_BLSP1_BCR] = {0x01000, 0},
+	[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
+	[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
+	[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
+	[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
+	[GCC_BIMC_BCR] = {0x04000, 0},
+	[GCC_TLMM_BCR] = {0x05000, 0},
+	[GCC_IMEM_BCR] = {0x0E000, 0},
+	[GCC_ESS_BCR] = {0x12008, 0},
+	[GCC_PRNG_BCR] = {0x13000, 0},
+	[GCC_BOOT_ROM_BCR] = {0x13008, 0},
+	[GCC_CRYPTO_BCR] = {0x16000, 0},
+	[GCC_SDCC1_BCR] = {0x18000, 0},
+	[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
+	[GCC_AUDIO_BCR] = {0x1B008, 0},
+	[GCC_QPIC_BCR] = {0x1C000, 0},
+	[GCC_PCIE_BCR] = {0x1D000, 0},
+	[GCC_USB2_BCR] = {0x1E008, 0},
+	[GCC_USB2_PHY_BCR] = {0x1E018, 0},
+	[GCC_USB3_BCR] = {0x1E024, 0},
+	[GCC_USB3_PHY_BCR] = {0x1E034, 0},
+	[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
+	[GCC_PCNOC_BCR] = {0x2102C, 0},
+	[GCC_DCD_BCR] = {0x21038, 0},
+	[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
+	[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
+	[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
+	[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
+	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
+	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
+	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
+	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
+	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
+	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
+	[GCC_TCSR_BCR] = {0x22000, 0},
+	[GCC_MPM_BCR] = {0x24000, 0},
+	[GCC_SPDM_BCR] = {0x25000, 0},
+};
+
+static int ipq4019_reset_assert(struct reset_ctl *rst)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+	const struct qcom_reset_map *map;
+	u32 value;
+
+	map = &reset_map[rst->id];
+
+	value = readl(priv->base + map->reg);
+	value |= BIT(map->bit);
+	writel(value, priv->base + map->reg);
+
+	return 0;
+}
+
+static int ipq4019_reset_deassert(struct reset_ctl *rst)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
+	const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
+	const struct qcom_reset_map *map;
+	u32 value;
+
+	map = &reset_map[rst->id];
+
+	value = readl(priv->base + map->reg);
+	value &= ~BIT(map->bit);
+	writel(value, priv->base + map->reg);
+
+	return 0;
+}
+
+static int ipq4019_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int ipq4019_reset_request(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops ipq4019_reset_ops = {
+	.request = ipq4019_reset_request,
+	.rfree = ipq4019_reset_free,
+	.rst_assert = ipq4019_reset_assert,
+	.rst_deassert = ipq4019_reset_deassert,
+};
+
+static const struct udevice_id ipq4019_reset_ids[] = {
+	{ .compatible = "qcom,gcc-reset-ipq4019" },
+	{ }
+};
+
+static int ipq4019_reset_probe(struct udevice *dev)
+{
+	struct ipq4019_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(ipq4019_reset) = {
+	.name = "ipq4019_reset",
+	.id = UCLASS_RESET,
+	.of_match = ipq4019_reset_ids,
+	.ops = &ipq4019_reset_ops,
+	.probe = ipq4019_reset_probe,
+	.priv_auto	= sizeof(struct ipq4019_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-mediatek.c b/roms/u-boot/drivers/reset/reset-mediatek.c
new file mode 100644
index 000000000..7427013ab
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-mediatek.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *	   Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <dm/lists.h>
+#include <regmap.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+#include <dm/device-internal.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+struct mediatek_reset_priv {
+	struct regmap *regmap;
+	u32 regofs;
+	u32 nr_resets;
+};
+
+static int mediatek_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int mediatek_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int mediatek_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	if (id >= priv->nr_resets)
+		return -EINVAL;
+
+	return regmap_update_bits(priv->regmap,
+		priv->regofs + ((id / 32) << 2), BIT(id % 32), BIT(id % 32));
+}
+
+static int mediatek_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	if (id >= priv->nr_resets)
+		return -EINVAL;
+
+	return regmap_update_bits(priv->regmap,
+		priv->regofs + ((id / 32) << 2), BIT(id % 32), 0);
+}
+
+struct reset_ops mediatek_reset_ops = {
+	.request = mediatek_reset_request,
+	.rfree = mediatek_reset_free,
+	.rst_assert = mediatek_reset_assert,
+	.rst_deassert = mediatek_reset_deassert,
+};
+
+static int mediatek_reset_probe(struct udevice *dev)
+{
+	struct mediatek_reset_priv *priv = dev_get_priv(dev);
+
+	if (!priv->regofs && !priv->nr_resets)
+		return -EINVAL;
+
+	priv->regmap = syscon_node_to_regmap(dev_ofnode(dev));
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
+
+	return 0;
+}
+
+int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs)
+{
+	struct udevice *rst_dev;
+	struct mediatek_reset_priv *priv;
+	int ret;
+
+	ret = device_bind_driver_to_node(pdev, "mediatek_reset", "reset",
+					 dev_ofnode(pdev), &rst_dev);
+	if (ret)
+		return ret;
+
+	priv = malloc(sizeof(struct mediatek_reset_priv));
+	priv->regofs = regofs;
+	priv->nr_resets = num_regs * 32;
+	dev_set_priv(rst_dev, priv);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(mediatek_reset) = {
+	.name = "mediatek_reset",
+	.id = UCLASS_RESET,
+	.probe = mediatek_reset_probe,
+	.ops = &mediatek_reset_ops,
+	.priv_auto	= sizeof(struct mediatek_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-meson.c b/roms/u-boot/drivers/reset/reset-meson.c
new file mode 100644
index 000000000..d4e0745d0
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-meson.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Amlogic Meson Reset Controller driver
+ *
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <regmap.h>
+#include <linux/bitops.h>
+
+#define REG_COUNT	8
+#define BITS_PER_REG	32
+#define LEVEL_OFFSET	0x7c
+
+struct meson_reset_priv {
+	struct regmap *regmap;
+};
+
+static int meson_reset_request(struct reset_ctl *reset_ctl)
+{
+	if (reset_ctl->id > (REG_COUNT * BITS_PER_REG))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int meson_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert)
+{
+	struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	uint bank = reset_ctl->id / BITS_PER_REG;
+	uint offset = reset_ctl->id % BITS_PER_REG;
+	uint reg_offset = LEVEL_OFFSET + (bank << 2);
+	uint val;
+
+	regmap_read(priv->regmap, reg_offset, &val);
+	if (assert)
+		val &= ~BIT(offset);
+	else
+		val |= BIT(offset);
+	regmap_write(priv->regmap, reg_offset, val);
+
+	return 0;
+}
+
+static int meson_reset_assert(struct reset_ctl *reset_ctl)
+{
+	return meson_reset_level(reset_ctl, true);
+}
+
+static int meson_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return meson_reset_level(reset_ctl, false);
+}
+
+struct reset_ops meson_reset_ops = {
+	.request = meson_reset_request,
+	.rfree = meson_reset_free,
+	.rst_assert = meson_reset_assert,
+	.rst_deassert = meson_reset_deassert,
+};
+
+static const struct udevice_id meson_reset_ids[] = {                          
+	{ .compatible = "amlogic,meson-gxbb-reset" },                                  
+	{ .compatible = "amlogic,meson-axg-reset" },
+	{ }                                                                     
+};  
+
+static int meson_reset_probe(struct udevice *dev)
+{
+	struct meson_reset_priv *priv = dev_get_priv(dev);
+	
+	return regmap_init_mem(dev_ofnode(dev), &priv->regmap);
+}
+
+U_BOOT_DRIVER(meson_reset) = {
+	.name = "meson_reset",
+	.id = UCLASS_RESET,
+	.of_match = meson_reset_ids,
+	.probe = meson_reset_probe,
+	.ops = &meson_reset_ops,
+	.priv_auto	= sizeof(struct meson_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-mtmips.c b/roms/u-boot/drivers/reset/reset-mtmips.c
new file mode 100644
index 000000000..4e71d5255
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-mtmips.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+struct mtmips_reset_priv {
+	void __iomem *base;
+};
+
+static int mtmips_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int mtmips_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int mtmips_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	setbits_32(priv->base, BIT(reset_ctl->id));
+
+	return 0;
+}
+
+static int mtmips_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	clrbits_32(priv->base, BIT(reset_ctl->id));
+
+	return 0;
+}
+
+static const struct reset_ops mtmips_reset_ops = {
+	.request	= mtmips_reset_request,
+	.rfree		= mtmips_reset_free,
+	.rst_assert	= mtmips_reset_assert,
+	.rst_deassert	= mtmips_reset_deassert,
+};
+
+static int mtmips_reset_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static int mtmips_reset_of_to_plat(struct udevice *dev)
+{
+	struct mtmips_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id mtmips_reset_ids[] = {
+	{ .compatible = "mediatek,mtmips-reset" },
+	{ }
+};
+
+U_BOOT_DRIVER(mtmips_reset) = {
+	.name = "mtmips-reset",
+	.id = UCLASS_RESET,
+	.of_match = mtmips_reset_ids,
+	.of_to_plat = mtmips_reset_of_to_plat,
+	.probe = mtmips_reset_probe,
+	.priv_auto	= sizeof(struct mtmips_reset_priv),
+	.ops = &mtmips_reset_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/roms/u-boot/drivers/reset/reset-raspberrypi.c b/roms/u-boot/drivers/reset/reset-raspberrypi.c
new file mode 100644
index 000000000..e2d284e5a
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-raspberrypi.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Raspberry Pi 4 firmware reset driver
+ *
+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+ */
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/arch/msg.h>
+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
+
+static int raspberrypi_reset_request(struct reset_ctl *reset_ctl)
+{
+	if (reset_ctl->id >= RASPBERRYPI_FIRMWARE_RESET_NUM_IDS)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int raspberrypi_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl)
+{
+	switch (reset_ctl->id) {
+	case RASPBERRYPI_FIRMWARE_RESET_ID_USB:
+		bcm2711_notify_vl805_reset();
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int raspberrypi_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+struct reset_ops raspberrypi_reset_ops = {
+	.request = raspberrypi_reset_request,
+	.rfree = raspberrypi_reset_free,
+	.rst_assert = raspberrypi_reset_assert,
+	.rst_deassert = raspberrypi_reset_deassert,
+};
+
+static const struct udevice_id raspberrypi_reset_ids[] = {
+	{ .compatible = "raspberrypi,firmware-reset" },
+	{ }
+};
+
+U_BOOT_DRIVER(raspberrypi_reset) = {
+	.name = "raspberrypi-reset",
+	.id = UCLASS_RESET,
+	.of_match = raspberrypi_reset_ids,
+	.ops = &raspberrypi_reset_ops,
+};
+
diff --git a/roms/u-boot/drivers/reset/reset-rockchip.c b/roms/u-boot/drivers/reset/reset-rockchip.c
new file mode 100644
index 000000000..eeb3d2eea
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-rockchip.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+/*
+ * Each reg has 16 bits reset signal for devices
+ * Note: Not including rk2818 and older SoCs
+ */
+#define ROCKCHIP_RESET_NUM_IN_REG	16
+
+struct rockchip_reset_priv {
+	void __iomem *base;
+	/* Rockchip reset reg locate at cru controller */
+	u32 reset_reg_offset;
+	/* Rockchip reset reg number */
+	u32 reset_reg_num;
+};
+
+static int rockchip_reset_request(struct reset_ctl *reset_ctl)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
+
+	if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int rockchip_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int bank =  reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+	int offset =  reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id,
+	      priv->base + (bank * 4));
+
+	rk_setreg(priv->base + (bank * 4), BIT(offset));
+
+	return 0;
+}
+
+static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int bank =  reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+	int offset =  reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id,
+	      priv->base + (bank * 4));
+
+	rk_clrreg(priv->base + (bank * 4), BIT(offset));
+
+	return 0;
+}
+
+struct reset_ops rockchip_reset_ops = {
+	.request = rockchip_reset_request,
+	.rfree = rockchip_reset_free,
+	.rst_assert = rockchip_reset_assert,
+	.rst_deassert = rockchip_reset_deassert,
+};
+
+static int rockchip_reset_probe(struct udevice *dev)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+
+	addr = dev_read_addr_size(dev, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
+		return -EINVAL;
+
+	addr += priv->reset_reg_offset;
+	priv->base = ioremap(addr, size);
+
+	debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
+	      priv->base, priv->reset_reg_offset, priv->reset_reg_num);
+
+	return 0;
+}
+
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+	struct udevice *rst_dev;
+	struct rockchip_reset_priv *priv;
+	int ret;
+
+	 ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
+					  dev_ofnode(pdev), &rst_dev);
+	if (ret) {
+		debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+		return ret;
+	}
+	priv = malloc(sizeof(struct rockchip_reset_priv));
+	priv->reset_reg_offset = reg_offset;
+	priv->reset_reg_num = reg_number;
+	dev_set_priv(rst_dev, priv);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_reset) = {
+	.name = "rockchip_reset",
+	.id = UCLASS_RESET,
+	.probe = rockchip_reset_probe,
+	.ops = &rockchip_reset_ops,
+	.priv_auto	= sizeof(struct rockchip_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-scmi.c b/roms/u-boot/drivers/reset/reset-scmi.c
new file mode 100644
index 000000000..1bff8075e
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-scmi.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-2020 Linaro Limited
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset-uclass.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <asm/types.h>
+
+static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert)
+{
+	struct scmi_rd_reset_in in = {
+		.domain_id = rst->id,
+		.flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0,
+		.reset_state = 0,
+	};
+	struct scmi_rd_reset_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN,
+					  SCMI_RESET_DOMAIN_RESET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(rst->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_reset_assert(struct reset_ctl *rst)
+{
+	return scmi_reset_set_level(rst, true);
+}
+
+static int scmi_reset_deassert(struct reset_ctl *rst)
+{
+	return scmi_reset_set_level(rst, false);
+}
+
+static int scmi_reset_request(struct reset_ctl *rst)
+{
+	struct scmi_rd_attr_in in = {
+		.domain_id = rst->id,
+	};
+	struct scmi_rd_attr_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN,
+					  SCMI_RESET_DOMAIN_ATTRIBUTES,
+					  in, out);
+	int ret;
+
+	/*
+	 * We don't really care about the attribute, just check
+	 * the reset domain exists.
+	 */
+	ret = devm_scmi_process_msg(rst->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_reset_rfree(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops scmi_reset_domain_ops = {
+	.request	= scmi_reset_request,
+	.rfree		= scmi_reset_rfree,
+	.rst_assert	= scmi_reset_assert,
+	.rst_deassert	= scmi_reset_deassert,
+};
+
+U_BOOT_DRIVER(scmi_reset_domain) = {
+	.name = "scmi_reset_domain",
+	.id = UCLASS_RESET,
+	.ops = &scmi_reset_domain_ops,
+};
diff --git a/roms/u-boot/drivers/reset/reset-sifive.c b/roms/u-boot/drivers/reset/reset-sifive.c
new file mode 100644
index 000000000..eec840d67
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-sifive.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sifive, Inc.
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/bitops.h>
+
+#define PRCI_RESETREG_OFFSET 0x28
+
+struct sifive_reset_priv {
+	void *base;
+	/* number of reset signals */
+	int nr_reset;
+};
+
+static int sifive_rst_trigger(struct reset_ctl *rst, bool level)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
+	int id = rst->id;
+	int regval = readl(priv->base + PRCI_RESETREG_OFFSET);
+
+	/* Derive bitposition from rst id */
+	if (level)
+		/* Reset deassert */
+		regval |= BIT(id);
+	else
+		/* Reset assert */
+		regval &= ~BIT(id);
+
+	writel(regval, priv->base + PRCI_RESETREG_OFFSET);
+
+	return 0;
+}
+
+static int sifive_reset_assert(struct reset_ctl *rst)
+{
+	return sifive_rst_trigger(rst, false);
+}
+
+static int sifive_reset_deassert(struct reset_ctl *rst)
+{
+	return sifive_rst_trigger(rst, true);
+}
+
+static int sifive_reset_request(struct reset_ctl *rst)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
+
+	debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
+	      rst, rst->dev, rst->id, priv->nr_reset);
+
+	if (rst->id > priv->nr_reset)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sifive_reset_free(struct reset_ctl *rst)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
+
+	debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
+	      rst, rst->dev, rst->id, priv->nr_reset);
+
+	return 0;
+}
+
+static int sifive_reset_probe(struct udevice *dev)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+int sifive_reset_bind(struct udevice *dev, ulong count)
+{
+	struct udevice *rst_dev;
+	struct sifive_reset_priv *priv;
+	int ret;
+
+	ret = device_bind_driver_to_node(dev, "sifive-reset", "reset",
+					 dev_ofnode(dev), &rst_dev);
+	if (ret) {
+		dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret);
+		return ret;
+	}
+	priv = malloc(sizeof(struct sifive_reset_priv));
+	priv->nr_reset = count;
+	dev_set_priv(rst_dev, priv);
+
+	return 0;
+}
+
+const struct reset_ops sifive_reset_ops = {
+	.request = sifive_reset_request,
+	.rfree = sifive_reset_free,
+	.rst_assert = sifive_reset_assert,
+	.rst_deassert = sifive_reset_deassert,
+};
+
+U_BOOT_DRIVER(sifive_reset) = {
+	.name		= "sifive-reset",
+	.id		= UCLASS_RESET,
+	.ops		= &sifive_reset_ops,
+	.probe		= sifive_reset_probe,
+	.priv_auto	= sizeof(struct sifive_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-socfpga.c b/roms/u-boot/drivers/reset/reset-socfpga.c
new file mode 100644
index 000000000..98450db94
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-socfpga.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Socfpga Reset Controller Driver
+ *
+ * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * based on
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
+#include <env.h>
+#include <reset-uclass.h>
+#include <wait_bit.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define BANK_INCREMENT		4
+#define NR_BANKS		8
+
+struct socfpga_reset_data {
+	void __iomem *modrst_base;
+};
+
+/*
+ * For compatibility with Kernels that don't support peripheral reset, this
+ * driver can keep the old behaviour of not asserting peripheral reset before
+ * starting the OS and deasserting all peripheral resets (enabling all
+ * peripherals).
+ *
+ * For that, the reset driver checks the environment variable
+ * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
+ * reset again once taken out of reset and all peripherals in 'permodrst' are
+ * taken out of reset before booting into the OS.
+ * Note that this should be required for gen5 systems only that are running
+ * Linux kernels without proper peripheral reset support for all drivers used.
+ */
+static bool socfpga_reset_keep_enabled(void)
+{
+#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
+	const char *env_str;
+	long val;
+
+	env_str = env_get("socfpga_legacy_reset_compat");
+	if (env_str) {
+		val = simple_strtol(env_str, NULL, 0);
+		if (val == 1)
+			return true;
+	}
+#endif
+
+	return false;
+}
+
+static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
+
+	setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
+	return 0;
+}
+
+static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
+
+	clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
+
+	return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
+				 BIT(offset),
+				 false, 500, false);
+}
+
+static int socfpga_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int socfpga_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static const struct reset_ops socfpga_reset_ops = {
+	.request = socfpga_reset_request,
+	.rfree = socfpga_reset_free,
+	.rst_assert = socfpga_reset_assert,
+	.rst_deassert = socfpga_reset_deassert,
+};
+
+static int socfpga_reset_probe(struct udevice *dev)
+{
+	struct socfpga_reset_data *data = dev_get_priv(dev);
+	u32 modrst_offset;
+	void __iomem *membase;
+
+	membase = dev_read_addr_ptr(dev);
+
+	modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
+	data->modrst_base = membase + modrst_offset;
+
+	return 0;
+}
+
+static int socfpga_reset_remove(struct udevice *dev)
+{
+	struct socfpga_reset_data *data = dev_get_priv(dev);
+
+	if (socfpga_reset_keep_enabled()) {
+		puts("Deasserting all peripheral resets\n");
+		writel(0, data->modrst_base + 4);
+	}
+
+	return 0;
+}
+
+static int socfpga_reset_bind(struct udevice *dev)
+{
+	int ret;
+	struct udevice *sys_child;
+
+	/*
+	 * The sysreset driver does not have a device node, so bind it here.
+	 * Bind it to the node, too, so that it can get its base address.
+	 */
+	ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
+					 dev_ofnode(dev), &sys_child);
+	if (ret)
+		debug("Warning: No sysreset driver: ret=%d\n", ret);
+
+	return 0;
+}
+
+static const struct udevice_id socfpga_reset_match[] = {
+	{ .compatible = "altr,rst-mgr" },
+	{ /* sentinel */ },
+};
+
+U_BOOT_DRIVER(socfpga_reset) = {
+	.name = "socfpga-reset",
+	.id = UCLASS_RESET,
+	.of_match = socfpga_reset_match,
+	.bind = socfpga_reset_bind,
+	.probe = socfpga_reset_probe,
+	.priv_auto	= sizeof(struct socfpga_reset_data),
+	.ops = &socfpga_reset_ops,
+	.remove = socfpga_reset_remove,
+	.flags	= DM_FLAG_OS_PREPARE,
+};
diff --git a/roms/u-boot/drivers/reset/reset-sunxi.c b/roms/u-boot/drivers/reset/reset-sunxi.c
new file mode 100644
index 000000000..264337ed8
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-sunxi.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/bitops.h>
+#include <linux/log2.h>
+#include <asm/arch/ccu.h>
+
+struct sunxi_reset_priv {
+	void *base;
+	ulong count;
+	const struct ccu_desc *desc;
+};
+
+static const struct ccu_reset *priv_to_reset(struct sunxi_reset_priv *priv,
+					     unsigned long id)
+{
+	return	&priv->desc->resets[id];
+}
+
+static int sunxi_reset_request(struct reset_ctl *reset_ctl)
+{
+	struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	debug("%s: (RST#%ld)\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id >= priv->count)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sunxi_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s: (RST#%ld)\n", __func__, reset_ctl->id);
+
+	return 0;
+}
+
+static int sunxi_set_reset(struct reset_ctl *reset_ctl, bool on)
+{
+	struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	const struct ccu_reset *reset = priv_to_reset(priv, reset_ctl->id);
+	u32 reg;
+
+	if (!(reset->flags & CCU_RST_F_IS_VALID)) {
+		printf("%s: (RST#%ld) unhandled\n", __func__, reset_ctl->id);
+		return 0;
+	}
+
+	debug("%s: (RST#%ld) off#0x%x, BIT(%d)\n", __func__,
+	      reset_ctl->id, reset->off, ilog2(reset->bit));
+
+	reg = readl(priv->base + reset->off);
+	if (on)
+		reg |= reset->bit;
+	else
+		reg &= ~reset->bit;
+
+	writel(reg, priv->base + reset->off);
+
+	return 0;
+}
+
+static int sunxi_reset_assert(struct reset_ctl *reset_ctl)
+{
+	return sunxi_set_reset(reset_ctl, false);
+}
+
+static int sunxi_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return sunxi_set_reset(reset_ctl, true);
+}
+
+struct reset_ops sunxi_reset_ops = {
+	.request = sunxi_reset_request,
+	.rfree = sunxi_reset_free,
+	.rst_assert = sunxi_reset_assert,
+	.rst_deassert = sunxi_reset_deassert,
+};
+
+static int sunxi_reset_probe(struct udevice *dev)
+{
+	struct sunxi_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+
+	return 0;
+}
+
+int sunxi_reset_bind(struct udevice *dev, ulong count)
+{
+	struct udevice *rst_dev;
+	struct sunxi_reset_priv *priv;
+	int ret;
+
+	ret = device_bind_driver_to_node(dev, "sunxi_reset", "reset",
+					 dev_ofnode(dev), &rst_dev);
+	if (ret) {
+		debug("failed to bind sunxi_reset driver (ret=%d)\n", ret);
+		return ret;
+	}
+	priv = malloc(sizeof(struct sunxi_reset_priv));
+	priv->count = count;
+	priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
+	dev_set_priv(rst_dev, priv);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(sunxi_reset) = {
+	.name		= "sunxi_reset",
+	.id		= UCLASS_RESET,
+	.ops		= &sunxi_reset_ops,
+	.probe		= sunxi_reset_probe,
+	.priv_auto	= sizeof(struct sunxi_reset_priv),
+};
diff --git a/roms/u-boot/drivers/reset/reset-syscon.c b/roms/u-boot/drivers/reset/reset-syscon.c
new file mode 100644
index 000000000..ff387ab6b
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-syscon.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Sean Anderson
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+struct syscon_reset_priv {
+	struct regmap *regmap;
+	uint offset;
+	uint mask;
+	bool assert_high;
+};
+
+static int syscon_reset_request(struct reset_ctl *rst)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+	if (BIT(rst->id) & priv->mask)
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int syscon_reset_assert(struct reset_ctl *rst)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+	return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+				  priv->assert_high ? BIT(rst->id) : 0);
+}
+
+static int syscon_reset_deassert(struct reset_ctl *rst)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(rst->dev);
+
+	return regmap_update_bits(priv->regmap, priv->offset, BIT(rst->id),
+				  priv->assert_high ? 0 : BIT(rst->id));
+}
+
+static const struct reset_ops syscon_reset_ops = {
+	.request = syscon_reset_request,
+	.rst_assert = syscon_reset_assert,
+	.rst_deassert = syscon_reset_deassert,
+};
+
+int syscon_reset_probe(struct udevice *dev)
+{
+	struct syscon_reset_priv *priv = dev_get_priv(dev);
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+	if (IS_ERR(priv->regmap))
+		return -ENODEV;
+
+	priv->offset = dev_read_u32_default(dev, "offset", 0);
+	priv->mask = dev_read_u32_default(dev, "mask", 0);
+	priv->assert_high = dev_read_u32_default(dev, "assert-high", true);
+
+	return 0;
+}
+
+static const struct udevice_id syscon_reset_ids[] = {
+	{ .compatible = "syscon-reset" },
+	{ },
+};
+
+U_BOOT_DRIVER(syscon_reset) = {
+	.name = "syscon_reset",
+	.id = UCLASS_RESET,
+	.of_match = syscon_reset_ids,
+	.probe = syscon_reset_probe,
+	.priv_auto	= sizeof(struct syscon_reset_priv),
+	.ops = &syscon_reset_ops,
+};
diff --git a/roms/u-boot/drivers/reset/reset-ti-sci.c b/roms/u-boot/drivers/reset/reset-ti-sci.c
new file mode 100644
index 000000000..d8510a4ab
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-ti-sci.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments System Control Interface (TI SCI) reset driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Andreas Dannenberg <dannenberg@ti.com>
+ *
+ * Loosely based on Linux kernel reset-ti-sci.c...
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <dm/device_compat.h>
+#include <linux/err.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+
+/**
+ * struct ti_sci_reset_data - reset controller information structure
+ * @sci: TI SCI handle used for communication with system controller
+ */
+struct ti_sci_reset_data {
+	const struct ti_sci_handle *sci;
+};
+
+static int ti_sci_reset_probe(struct udevice *dev)
+{
+	struct ti_sci_reset_data *data = dev_get_priv(dev);
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	if (!data)
+		return -ENOMEM;
+
+	/* Store handle for communication with the system controller */
+	data->sci = ti_sci_get_handle(dev);
+	if (IS_ERR(data->sci))
+		return PTR_ERR(data->sci);
+
+	return 0;
+}
+
+static int ti_sci_reset_of_xlate(struct reset_ctl *rst,
+				 struct ofnode_phandle_args *args)
+{
+	debug("%s(rst=%p, args_count=%d)\n", __func__, rst, args->args_count);
+
+	if (args->args_count != 2) {
+		debug("Invalid args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	/*
+	 * On TI SCI-based devices, the reset provider id field is used as a
+	 * device ID, and the data field is used as the associated reset mask.
+	 */
+	rst->id = args->args[0];
+	rst->data = args->args[1];
+
+	return 0;
+}
+
+static int ti_sci_reset_request(struct reset_ctl *rst)
+{
+	debug("%s(rst=%p)\n", __func__, rst);
+	return 0;
+}
+
+static int ti_sci_reset_free(struct reset_ctl *rst)
+{
+	debug("%s(rst=%p)\n", __func__, rst);
+	return 0;
+}
+
+/**
+ * ti_sci_reset_set() - program a device's reset
+ * @rst: Handle to a single reset signal
+ * @assert: boolean flag to indicate assert or deassert
+ *
+ * This is a common internal function used to assert or deassert a device's
+ * reset using the TI SCI protocol. The device's reset is asserted if the
+ * @assert argument is true, or deasserted if @assert argument is false.
+ * The mechanism itself is a read-modify-write procedure, the current device
+ * reset register is read using a TI SCI device operation, the new value is
+ * set or un-set using the reset's mask, and the new reset value written by
+ * using another TI SCI device operation.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_set(struct reset_ctl *rst, bool assert)
+{
+	struct ti_sci_reset_data *data = dev_get_priv(rst->dev);
+	const struct ti_sci_handle *sci = data->sci;
+	const struct ti_sci_dev_ops *dops = &sci->ops.dev_ops;
+	u32 reset_state;
+	int ret;
+
+	ret = dops->get_device_resets(sci, rst->id, &reset_state);
+	if (ret) {
+		dev_err(rst->dev, "%s: get_device_resets failed (%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	if (assert)
+		reset_state |= rst->data;
+	else
+		reset_state &= ~rst->data;
+
+	ret = dops->set_device_resets(sci, rst->id, reset_state);
+	if (ret) {
+		dev_err(rst->dev, "%s: set_device_resets failed (%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * ti_sci_reset_assert() - assert device reset
+ * @rst: Handle to a single reset signal
+ *
+ * This function implements the reset driver op to assert a device's reset
+ * using the TI SCI protocol. This invokes the function ti_sci_reset_set()
+ * with the corresponding parameters as passed in, but with the @assert
+ * argument set to true for asserting the reset.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_assert(struct reset_ctl *rst)
+{
+	debug("%s(rst=%p)\n", __func__, rst);
+	return ti_sci_reset_set(rst, true);
+}
+
+/**
+ * ti_sci_reset_deassert() - deassert device reset
+ * @rst: Handle to a single reset signal
+ *
+ * This function implements the reset driver op to deassert a device's reset
+ * using the TI SCI protocol. This invokes the function ti_sci_reset_set()
+ * with the corresponding parameters as passed in, but with the @assert
+ * argument set to false for deasserting the reset.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_deassert(struct reset_ctl *rst)
+{
+	debug("%s(rst=%p)\n", __func__, rst);
+	return ti_sci_reset_set(rst, false);
+}
+
+/**
+ * ti_sci_reset_status() - check device reset status
+ * @rst: Handle to a single reset signal
+ *
+ * This function implements the reset driver op to return the status of a
+ * device's reset using the TI SCI protocol. The reset register value is read
+ * by invoking the TI SCI device operation .get_device_resets(), and the
+ * status of the specific reset is extracted and returned using this reset's
+ * reset mask.
+ *
+ * Return: 0 if reset is deasserted, or a non-zero value if reset is asserted
+ */
+static int ti_sci_reset_status(struct reset_ctl *rst)
+{
+	struct ti_sci_reset_data *data = dev_get_priv(rst->dev);
+	const struct ti_sci_handle *sci = data->sci;
+	const struct ti_sci_dev_ops *dops = &sci->ops.dev_ops;
+	u32 reset_state;
+	int ret;
+
+	debug("%s(rst=%p)\n", __func__, rst);
+
+	ret = dops->get_device_resets(sci, rst->id, &reset_state);
+	if (ret) {
+		dev_err(rst->dev, "%s: get_device_resets failed (%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	return reset_state & rst->data;
+}
+
+static const struct udevice_id ti_sci_reset_of_match[] = {
+	{ .compatible = "ti,sci-reset", },
+	{ /* sentinel */ },
+};
+
+static struct reset_ops ti_sci_reset_ops = {
+	.of_xlate = ti_sci_reset_of_xlate,
+	.request = ti_sci_reset_request,
+	.rfree = ti_sci_reset_free,
+	.rst_assert = ti_sci_reset_assert,
+	.rst_deassert = ti_sci_reset_deassert,
+	.rst_status = ti_sci_reset_status,
+};
+
+U_BOOT_DRIVER(ti_sci_reset) = {
+	.name = "ti-sci-reset",
+	.id = UCLASS_RESET,
+	.of_match = ti_sci_reset_of_match,
+	.probe = ti_sci_reset_probe,
+	.priv_auto	= sizeof(struct ti_sci_reset_data),
+	.ops = &ti_sci_reset_ops,
+};
diff --git a/roms/u-boot/drivers/reset/reset-uclass.c b/roms/u-boot/drivers/reset/reset-uclass.c
new file mode 100644
index 000000000..ac89eaf09
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-uclass.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+
+static inline struct reset_ops *reset_dev_ops(struct udevice *dev)
+{
+	return (struct reset_ops *)dev->driver->ops;
+}
+
+static int reset_of_xlate_default(struct reset_ctl *reset_ctl,
+				  struct ofnode_phandle_args *args)
+{
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	if (args->args_count != 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	reset_ctl->id = args->args[0];
+
+	return 0;
+}
+
+static int reset_get_by_index_tail(int ret, ofnode node,
+				   struct ofnode_phandle_args *args,
+				   const char *list_name, int index,
+				   struct reset_ctl *reset_ctl)
+{
+	struct udevice *dev_reset;
+	struct reset_ops *ops;
+
+	assert(reset_ctl);
+	reset_ctl->dev = NULL;
+	if (ret)
+		return ret;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node,
+					  &dev_reset);
+	if (ret) {
+		debug("%s: uclass_get_device_by_ofnode() failed: %d\n",
+		      __func__, ret);
+		debug("%s %d\n", ofnode_get_name(args->node), args->args[0]);
+		return ret;
+	}
+	ops = reset_dev_ops(dev_reset);
+
+	reset_ctl->dev = dev_reset;
+	if (ops->of_xlate)
+		ret = ops->of_xlate(reset_ctl, args);
+	else
+		ret = reset_of_xlate_default(reset_ctl, args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ops->request(reset_ctl);
+	if (ret) {
+		debug("ops->request() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int reset_get_by_index(struct udevice *dev, int index,
+		       struct reset_ctl *reset_ctl)
+{
+	struct ofnode_phandle_args args;
+	int ret;
+
+	ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
+					 index, &args);
+
+	return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets",
+				       index > 0, reset_ctl);
+}
+
+int reset_get_by_index_nodev(ofnode node, int index,
+			     struct reset_ctl *reset_ctl)
+{
+	struct ofnode_phandle_args args;
+	int ret;
+
+	ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
+					     index, &args);
+
+	return reset_get_by_index_tail(ret, node, &args, "resets",
+				       index > 0, reset_ctl);
+}
+
+static int __reset_get_bulk(struct udevice *dev, ofnode node,
+			    struct reset_ctl_bulk *bulk)
+{
+	int i, ret, err, count;
+
+	bulk->count = 0;
+
+	count = ofnode_count_phandle_with_args(node, "resets", "#reset-cells",
+					       0);
+	if (count < 1)
+		return count;
+
+	bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl),
+				    GFP_KERNEL);
+	if (!bulk->resets)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = reset_get_by_index_nodev(node, i, &bulk->resets[i]);
+		if (ret < 0)
+			goto bulk_get_err;
+
+		++bulk->count;
+	}
+
+	return 0;
+
+bulk_get_err:
+	err = reset_release_all(bulk->resets, bulk->count);
+	if (err)
+		debug("%s: could release all resets for %p\n",
+		      __func__, dev);
+
+	return ret;
+}
+
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
+{
+	return __reset_get_bulk(dev, dev_ofnode(dev), bulk);
+}
+
+int reset_get_by_name(struct udevice *dev, const char *name,
+		     struct reset_ctl *reset_ctl)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
+	      reset_ctl);
+	reset_ctl->dev = NULL;
+
+	index = dev_read_stringlist_search(dev, "reset-names", name);
+	if (index < 0) {
+		debug("fdt_stringlist_search() failed: %d\n", index);
+		return index;
+	}
+
+	return reset_get_by_index(dev, index, reset_ctl);
+}
+
+int reset_request(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->request(reset_ctl);
+}
+
+int reset_free(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->rfree(reset_ctl);
+}
+
+int reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->rst_assert(reset_ctl);
+}
+
+int reset_assert_bulk(struct reset_ctl_bulk *bulk)
+{
+	int i, ret;
+
+	for (i = 0; i < bulk->count; i++) {
+		ret = reset_assert(&bulk->resets[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+int reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->rst_deassert(reset_ctl);
+}
+
+int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
+{
+	int i, ret;
+
+	for (i = 0; i < bulk->count; i++) {
+		ret = reset_deassert(&bulk->resets[i]);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+int reset_status(struct reset_ctl *reset_ctl)
+{
+	struct reset_ops *ops = reset_dev_ops(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	return ops->rst_status(reset_ctl);
+}
+
+int reset_release_all(struct reset_ctl *reset_ctl, int count)
+{
+	int i, ret;
+
+	for (i = 0; i < count; i++) {
+		debug("%s(reset_ctl[%d]=%p)\n", __func__, i, &reset_ctl[i]);
+
+		/* check if reset has been previously requested */
+		if (!reset_ctl[i].dev)
+			continue;
+
+		ret = reset_assert(&reset_ctl[i]);
+		if (ret)
+			return ret;
+
+		ret = reset_free(&reset_ctl[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static void devm_reset_release(struct udevice *dev, void *res)
+{
+	reset_free(res);
+}
+
+struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev,
+						  int index)
+{
+	int rc;
+	struct reset_ctl *reset_ctl;
+
+	reset_ctl = devres_alloc(devm_reset_release, sizeof(struct reset_ctl),
+				 __GFP_ZERO);
+	if (unlikely(!reset_ctl))
+		return ERR_PTR(-ENOMEM);
+
+	rc = reset_get_by_index(dev, index, reset_ctl);
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, reset_ctl);
+	return reset_ctl;
+}
+
+struct reset_ctl *devm_reset_control_get(struct udevice *dev, const char *id)
+{
+	int rc;
+	struct reset_ctl *reset_ctl;
+
+	reset_ctl = devres_alloc(devm_reset_release, sizeof(struct reset_ctl),
+				 __GFP_ZERO);
+	if (unlikely(!reset_ctl))
+		return ERR_PTR(-ENOMEM);
+
+	rc = reset_get_by_name(dev, id, reset_ctl);
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, reset_ctl);
+	return reset_ctl;
+}
+
+struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev,
+						  const char *id)
+{
+	struct reset_ctl *r = devm_reset_control_get(dev, id);
+
+	if (IS_ERR(r))
+		return NULL;
+
+	return r;
+}
+
+static void devm_reset_bulk_release(struct udevice *dev, void *res)
+{
+	struct reset_ctl_bulk *bulk = res;
+
+	reset_release_all(bulk->resets, bulk->count);
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev,
+						   ofnode node)
+{
+	int rc;
+	struct reset_ctl_bulk *bulk;
+
+	bulk = devres_alloc(devm_reset_bulk_release,
+			    sizeof(struct reset_ctl_bulk),
+			    __GFP_ZERO);
+	if (unlikely(!bulk))
+		return ERR_PTR(-ENOMEM);
+
+	rc = __reset_get_bulk(dev, node, bulk);
+	if (rc)
+		return ERR_PTR(rc);
+
+	devres_add(dev, bulk);
+	return bulk;
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev,
+							    ofnode node)
+{
+	struct reset_ctl_bulk *bulk;
+
+	bulk = devm_reset_bulk_get_by_node(dev, node);
+
+	if (IS_ERR(bulk))
+		return NULL;
+
+	return bulk;
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev)
+{
+	return devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
+}
+
+struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev)
+{
+	return devm_reset_bulk_get_optional_by_node(dev, dev_ofnode(dev));
+}
+
+UCLASS_DRIVER(reset) = {
+	.id		= UCLASS_RESET,
+	.name		= "reset",
+};
diff --git a/roms/u-boot/drivers/reset/reset-uniphier.c b/roms/u-boot/drivers/reset/reset-uniphier.c
new file mode 100644
index 000000000..2694d130b
--- /dev/null
+++ b/roms/u-boot/drivers/reset/reset-uniphier.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+struct uniphier_reset_data {
+	unsigned int id;
+	unsigned int reg;
+	unsigned int bit;
+	unsigned int flags;
+#define UNIPHIER_RESET_ACTIVE_LOW		BIT(0)
+};
+
+#define UNIPHIER_RESET_ID_END		(unsigned int)(-1)
+
+#define UNIPHIER_RESET_END				\
+	{ .id = UNIPHIER_RESET_ID_END }
+
+#define UNIPHIER_RESET(_id, _reg, _bit)			\
+	{						\
+		.id = (_id),				\
+		.reg = (_reg),				\
+		.bit = (_bit),				\
+	}
+
+#define UNIPHIER_RESETX(_id, _reg, _bit)		\
+	{						\
+		.id = (_id),				\
+		.reg = (_reg),				\
+		.bit = (_bit),				\
+		.flags = UNIPHIER_RESET_ACTIVE_LOW,	\
+	}
+
+/* System reset data */
+static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
+	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
+	UNIPHIER_RESETX(6, 0x2000, 12),		/* ETHER */
+	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC */
+	UNIPHIER_RESETX(12, 0x2000, 6),		/* GIO */
+	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
+	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
+	UNIPHIER_RESET_END,
+};
+
+static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
+	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
+	UNIPHIER_RESETX(6, 0x2000, 12),		/* ETHER */
+	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC */
+	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
+	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
+	UNIPHIER_RESETX(16, 0x2014, 4),		/* USB30-PHY0 */
+	UNIPHIER_RESETX(17, 0x2014, 0),		/* USB30-PHY1 */
+	UNIPHIER_RESETX(18, 0x2014, 2),		/* USB30-PHY2 */
+	UNIPHIER_RESETX(20, 0x2014, 5),		/* USB31-PHY0 */
+	UNIPHIER_RESETX(21, 0x2014, 1),		/* USB31-PHY1 */
+	UNIPHIER_RESETX(28, 0x2014, 12),	/* SATA */
+	UNIPHIER_RESET(29, 0x2014, 8),		/* SATA-PHY (active high) */
+	UNIPHIER_RESET_END,
+};
+
+static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
+	UNIPHIER_RESETX(2, 0x200c, 0),		/* NAND */
+	UNIPHIER_RESETX(4, 0x200c, 2),		/* eMMC */
+	UNIPHIER_RESETX(6, 0x200c, 6),		/* ETHER */
+	UNIPHIER_RESETX(8, 0x200c, 8),		/* STDMAC */
+	UNIPHIER_RESETX(14, 0x200c, 5),		/* USB30 */
+	UNIPHIER_RESETX(16, 0x200c, 12),	/* USB30-PHY0 */
+	UNIPHIER_RESETX(17, 0x200c, 13),	/* USB30-PHY1 */
+	UNIPHIER_RESETX(18, 0x200c, 14),	/* USB30-PHY2 */
+	UNIPHIER_RESETX(19, 0x200c, 15),	/* USB30-PHY3 */
+	UNIPHIER_RESET_END,
+};
+
+static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
+	UNIPHIER_RESETX(2, 0x200c, 0),		/* NAND */
+	UNIPHIER_RESETX(4, 0x200c, 2),		/* eMMC */
+	UNIPHIER_RESETX(6, 0x200c, 9),		/* ETHER0 */
+	UNIPHIER_RESETX(7, 0x200c, 10),		/* ETHER1 */
+	UNIPHIER_RESETX(8, 0x200c, 12),		/* STDMAC */
+	UNIPHIER_RESETX(12, 0x200c, 4),		/* USB30 link */
+	UNIPHIER_RESETX(13, 0x200c, 5),		/* USB31 link */
+	UNIPHIER_RESETX(16, 0x200c, 16),	/* USB30-PHY0 */
+	UNIPHIER_RESETX(17, 0x200c, 18),	/* USB30-PHY1 */
+	UNIPHIER_RESETX(18, 0x200c, 20),	/* USB30-PHY2 */
+	UNIPHIER_RESETX(20, 0x200c, 17),	/* USB31-PHY0 */
+	UNIPHIER_RESETX(21, 0x200c, 19),	/* USB31-PHY1 */
+	UNIPHIER_RESET_END,
+};
+
+/* Media I/O reset data */
+#define UNIPHIER_MIO_RESET_SD(id, ch)			\
+	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch)		\
+	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
+
+#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch)	\
+	UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_USB2(id, ch)			\
+	UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
+
+#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch)		\
+	UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
+
+#define UNIPHIER_MIO_RESET_DMAC(id)			\
+	UNIPHIER_RESETX((id), 0x110, 17)
+
+static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
+	UNIPHIER_MIO_RESET_SD(0, 0),
+	UNIPHIER_MIO_RESET_SD(1, 1),
+	UNIPHIER_MIO_RESET_SD(2, 2),
+	UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
+	UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
+	UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
+	UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
+	UNIPHIER_MIO_RESET_DMAC(7),
+	UNIPHIER_MIO_RESET_USB2(8, 0),
+	UNIPHIER_MIO_RESET_USB2(9, 1),
+	UNIPHIER_MIO_RESET_USB2(10, 2),
+	UNIPHIER_MIO_RESET_USB2(11, 3),
+	UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
+	UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
+	UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
+	UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
+	UNIPHIER_RESET_END,
+};
+
+/* Peripheral reset data */
+#define UNIPHIER_PERI_RESET_UART(id, ch)		\
+	UNIPHIER_RESETX((id), 0x114, 19 + (ch))
+
+#define UNIPHIER_PERI_RESET_I2C(id, ch)			\
+	UNIPHIER_RESETX((id), 0x114, 5 + (ch))
+
+#define UNIPHIER_PERI_RESET_FI2C(id, ch)		\
+	UNIPHIER_RESETX((id), 0x114, 24 + (ch))
+
+static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
+	UNIPHIER_PERI_RESET_UART(0, 0),
+	UNIPHIER_PERI_RESET_UART(1, 1),
+	UNIPHIER_PERI_RESET_UART(2, 2),
+	UNIPHIER_PERI_RESET_UART(3, 3),
+	UNIPHIER_PERI_RESET_I2C(4, 0),
+	UNIPHIER_PERI_RESET_I2C(5, 1),
+	UNIPHIER_PERI_RESET_I2C(6, 2),
+	UNIPHIER_PERI_RESET_I2C(7, 3),
+	UNIPHIER_PERI_RESET_I2C(8, 4),
+	UNIPHIER_RESET_END,
+};
+
+static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
+	UNIPHIER_PERI_RESET_UART(0, 0),
+	UNIPHIER_PERI_RESET_UART(1, 1),
+	UNIPHIER_PERI_RESET_UART(2, 2),
+	UNIPHIER_PERI_RESET_UART(3, 3),
+	UNIPHIER_PERI_RESET_FI2C(4, 0),
+	UNIPHIER_PERI_RESET_FI2C(5, 1),
+	UNIPHIER_PERI_RESET_FI2C(6, 2),
+	UNIPHIER_PERI_RESET_FI2C(7, 3),
+	UNIPHIER_PERI_RESET_FI2C(8, 4),
+	UNIPHIER_PERI_RESET_FI2C(9, 5),
+	UNIPHIER_PERI_RESET_FI2C(10, 6),
+	UNIPHIER_RESET_END,
+};
+
+/* core implementaton */
+struct uniphier_reset_priv {
+	void __iomem *base;
+	const struct uniphier_reset_data *data;
+};
+
+static int uniphier_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int uniphier_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
+{
+	struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	unsigned long id = reset_ctl->id;
+	const struct uniphier_reset_data *p;
+
+	for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
+		u32 mask, val;
+
+		if (p->id != id)
+			continue;
+
+		val = readl(priv->base + p->reg);
+
+		if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
+			assert = !assert;
+
+		mask = BIT(p->bit);
+
+		if (assert)
+			val |= mask;
+		else
+			val &= ~mask;
+
+		writel(val, priv->base + p->reg);
+
+		return 0;
+	}
+
+	dev_err(reset_ctl->dev, "reset_id=%lu was not handled\n", id);
+
+	return -EINVAL;
+}
+
+static int uniphier_reset_assert(struct reset_ctl *reset_ctl)
+{
+	return uniphier_reset_update(reset_ctl, 1);
+}
+
+static int uniphier_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return uniphier_reset_update(reset_ctl, 0);
+}
+
+static const struct reset_ops uniphier_reset_ops = {
+	.request = uniphier_reset_request,
+	.rfree = uniphier_reset_free,
+	.rst_assert = uniphier_reset_assert,
+	.rst_deassert = uniphier_reset_deassert,
+};
+
+static int uniphier_reset_probe(struct udevice *dev)
+{
+	struct uniphier_reset_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev->parent);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = devm_ioremap(dev, addr, SZ_4K);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->data = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct udevice_id uniphier_reset_match[] = {
+	/* System reset */
+	{
+		.compatible = "socionext,uniphier-ld4-reset",
+		.data = (ulong)uniphier_pro4_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-reset",
+		.data = (ulong)uniphier_pro4_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-reset",
+		.data = (ulong)uniphier_pro4_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-reset",
+		.data = (ulong)uniphier_pro4_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-reset",
+		.data = (ulong)uniphier_pxs2_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-reset",
+		.data = (ulong)uniphier_ld20_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-reset",
+		.data = (ulong)uniphier_ld20_sys_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs3-reset",
+		.data = (ulong)uniphier_pxs3_sys_reset_data,
+	},
+	/* Media I/O reset */
+	{
+		.compatible = "socionext,uniphier-ld4-mio-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-mio-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-mio-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-mio-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-mio-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-mio-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-sd-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-sd-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs3-sd-reset",
+		.data = (ulong)uniphier_mio_reset_data,
+	},
+	/* Peripheral reset */
+	{
+		.compatible = "socionext,uniphier-ld4-peri-reset",
+		.data = (ulong)uniphier_ld4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro4-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-sld8-peri-reset",
+		.data = (ulong)uniphier_ld4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pro5-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs2-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld11-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-ld20-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
+	{
+		.compatible = "socionext,uniphier-pxs3-peri-reset",
+		.data = (ulong)uniphier_pro4_peri_reset_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_reset) = {
+	.name = "uniphier-reset",
+	.id = UCLASS_RESET,
+	.of_match = uniphier_reset_match,
+	.probe = uniphier_reset_probe,
+	.priv_auto	= sizeof(struct uniphier_reset_priv),
+	.ops = &uniphier_reset_ops,
+};
diff --git a/roms/u-boot/drivers/reset/sandbox-reset-test.c b/roms/u-boot/drivers/reset/sandbox-reset-test.c
new file mode 100644
index 000000000..51b79810c
--- /dev/null
+++ b/roms/u-boot/drivers/reset/sandbox-reset-test.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/reset.h>
+#include <linux/err.h>
+
+struct sandbox_reset_test {
+	struct reset_ctl ctl;
+	struct reset_ctl_bulk bulk;
+
+	struct reset_ctl *ctlp;
+	struct reset_ctl_bulk *bulkp;
+};
+
+int sandbox_reset_test_get(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	sbrt->ctlp = &sbrt->ctl;
+	return reset_get_by_name(dev, "test", &sbrt->ctl);
+}
+
+int sandbox_reset_test_get_devm(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+	struct reset_ctl *r;
+
+	r = devm_reset_control_get(dev, "not-a-valid-reset-ctl");
+	if (!IS_ERR(r))
+		return -EINVAL;
+
+	r = devm_reset_control_get_optional(dev, "not-a-valid-reset-ctl");
+	if (r)
+		return -EINVAL;
+
+	sbrt->ctlp = devm_reset_control_get(dev, "test");
+	if (IS_ERR(sbrt->ctlp))
+		return PTR_ERR(sbrt->ctlp);
+
+	return 0;
+}
+
+int sandbox_reset_test_get_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	sbrt->bulkp = &sbrt->bulk;
+	return reset_get_bulk(dev, &sbrt->bulk);
+}
+
+int sandbox_reset_test_get_bulk_devm(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+	struct reset_ctl_bulk *r;
+
+	r = devm_reset_bulk_get_optional(dev);
+	if (IS_ERR(r))
+		return PTR_ERR(r);
+
+	sbrt->bulkp = r;
+	return 0;
+}
+
+int sandbox_reset_test_assert(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_assert(sbrt->ctlp);
+}
+
+int sandbox_reset_test_assert_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_assert_bulk(sbrt->bulkp);
+}
+
+int sandbox_reset_test_deassert(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_deassert(sbrt->ctlp);
+}
+
+int sandbox_reset_test_deassert_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_deassert_bulk(sbrt->bulkp);
+}
+
+int sandbox_reset_test_free(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_free(sbrt->ctlp);
+}
+
+int sandbox_reset_test_release_bulk(struct udevice *dev)
+{
+	struct sandbox_reset_test *sbrt = dev_get_priv(dev);
+
+	return reset_release_bulk(sbrt->bulkp);
+}
+
+static const struct udevice_id sandbox_reset_test_ids[] = {
+	{ .compatible = "sandbox,reset-ctl-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_reset_test) = {
+	.name = "sandbox_reset_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_reset_test_ids,
+	.priv_auto	= sizeof(struct sandbox_reset_test),
+};
diff --git a/roms/u-boot/drivers/reset/sandbox-reset.c b/roms/u-boot/drivers/reset/sandbox-reset.c
new file mode 100644
index 000000000..97b1b92e4
--- /dev/null
+++ b/roms/u-boot/drivers/reset/sandbox-reset.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <asm/reset.h>
+
+#define SANDBOX_RESET_SIGNALS 101
+
+struct sandbox_reset_signal {
+	bool asserted;
+	bool requested;
+};
+
+struct sandbox_reset {
+	struct sandbox_reset_signal signals[SANDBOX_RESET_SIGNALS];
+};
+
+static int sandbox_reset_request(struct reset_ctl *reset_ctl)
+{
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	if (reset_ctl->id >= SANDBOX_RESET_SIGNALS)
+		return -EINVAL;
+
+	sbr->signals[reset_ctl->id].requested = true;
+	return 0;
+}
+
+static int sandbox_reset_free(struct reset_ctl *reset_ctl)
+{
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	sbr->signals[reset_ctl->id].requested = false;
+	return 0;
+}
+
+static int sandbox_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	sbr->signals[reset_ctl->id].asserted = true;
+
+	return 0;
+}
+
+static int sandbox_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p)\n", __func__, reset_ctl);
+
+	sbr->signals[reset_ctl->id].asserted = false;
+
+	return 0;
+}
+
+static int sandbox_reset_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int sandbox_reset_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_reset_ids[] = {
+	{ .compatible = "sandbox,reset-ctl" },
+	{ }
+};
+
+struct reset_ops sandbox_reset_reset_ops = {
+	.request = sandbox_reset_request,
+	.rfree = sandbox_reset_free,
+	.rst_assert = sandbox_reset_assert,
+	.rst_deassert = sandbox_reset_deassert,
+};
+
+U_BOOT_DRIVER(sandbox_reset) = {
+	.name = "sandbox_reset",
+	.id = UCLASS_RESET,
+	.of_match = sandbox_reset_ids,
+	.bind = sandbox_reset_bind,
+	.probe = sandbox_reset_probe,
+	.priv_auto	= sizeof(struct sandbox_reset),
+	.ops = &sandbox_reset_reset_ops,
+};
+
+int sandbox_reset_query(struct udevice *dev, unsigned long id)
+{
+	struct sandbox_reset *sbr = dev_get_priv(dev);
+
+	debug("%s(dev=%p, id=%ld)\n", __func__, dev, id);
+
+	if (id >= SANDBOX_RESET_SIGNALS)
+		return -EINVAL;
+
+	return sbr->signals[id].asserted;
+}
+
+int sandbox_reset_is_requested(struct udevice *dev, unsigned long id)
+{
+	struct sandbox_reset *sbr = dev_get_priv(dev);
+
+	debug("%s(dev=%p, id=%ld)\n", __func__, dev, id);
+
+	if (id >= SANDBOX_RESET_SIGNALS)
+		return -EINVAL;
+
+	return sbr->signals[id].requested;
+}
diff --git a/roms/u-boot/drivers/reset/sti-reset.c b/roms/u-boot/drivers/reset/sti-reset.c
new file mode 100644
index 000000000..9287f2895
--- /dev/null
+++ b/roms/u-boot/drivers/reset/sti-reset.c
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <wait_bit.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <dt-bindings/reset/stih407-resets.h>
+#include <linux/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sti_reset {
+	const struct syscfg_reset_controller_data *data;
+};
+
+/**
+ * Reset channel description for a system configuration register based
+ * reset controller.
+ *
+ * @compatible: Compatible string of the syscon containing this
+ *              channel's control and ack (status) bits.
+ * @reset_offset: Reset register offset in sysconf bank.
+ * @reset_bit: Bit number in reset register.
+ * @ack_offset: Ack reset register offset in syscon bank.
+ * @ack_bit: Bit number in Ack reset register.
+ * @deassert_cnt: incremented when reset is deasserted, reset can only be
+ *                asserted when equal to 0
+ */
+
+struct syscfg_reset_channel_data {
+	const char *compatible;
+	int reset_offset;
+	int reset_bit;
+	int ack_offset;
+	int ack_bit;
+	int deassert_cnt;
+};
+
+/**
+ * Description of a system configuration register based reset controller.
+ *
+ * @wait_for_ack: The controller will wait for reset assert and de-assert to
+ *                be "ack'd" in a channel's ack field.
+ * @active_low: Are the resets in this controller active low, i.e. clearing
+ *              the reset bit puts the hardware into reset.
+ * @nr_channels: The number of reset channels in this controller.
+ * @channels: An array of reset channel descriptions.
+ */
+struct syscfg_reset_controller_data {
+	bool wait_for_ack;
+	bool active_low;
+	int nr_channels;
+	struct syscfg_reset_channel_data *channels;
+};
+
+/* STiH407 Peripheral powerdown definitions. */
+static const char stih407_core[] = "st,stih407-core-syscfg";
+static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
+static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
+
+#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab)		\
+	{ .compatible	= _c,				\
+	  .reset_offset	= _rr,				\
+	  .reset_bit	= _rb,				\
+	  .ack_offset	= _ar,				\
+	  .ack_bit	= _ab,				}
+
+#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb)		\
+	{ .compatible	= _c,				\
+	  .reset_offset	= _rr,				\
+	  .reset_bit	= _rb,				}
+
+#define STIH407_SRST_CORE(_reg, _bit) \
+	_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
+
+#define STIH407_SRST_SBC(_reg, _bit) \
+	_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
+
+#define STIH407_SRST_LPM(_reg, _bit) \
+	_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
+
+#define STIH407_PDN_0(_bit) \
+	_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
+#define STIH407_PDN_1(_bit) \
+	_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
+#define STIH407_PDN_ETH(_bit, _stat) \
+	_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
+
+/* Powerdown requests control 0 */
+#define SYSCFG_5000	0x0
+#define SYSSTAT_5500	0x7d0
+/* Powerdown requests control 1 (High Speed Links) */
+#define SYSCFG_5001	0x4
+#define SYSSTAT_5501	0x7d4
+
+/* Ethernet powerdown/status/reset */
+#define SYSCFG_4032	0x80
+#define SYSSTAT_4520	0x820
+#define SYSCFG_4002	0x8
+
+static struct syscfg_reset_channel_data stih407_powerdowns[] = {
+	[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
+	[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
+	[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
+	[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
+	[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
+	[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
+	[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
+	[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
+	[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
+	[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
+};
+
+/* Reset Generator control 0/1 */
+#define SYSCFG_5128	0x200
+#define SYSCFG_5131	0x20c
+#define SYSCFG_5132	0x210
+
+#define LPM_SYSCFG_1	0x4	/* Softreset IRB & SBC UART */
+
+static struct syscfg_reset_channel_data stih407_softresets[] = {
+	[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
+	[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
+	[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
+	[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
+	[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
+	[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
+	[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
+	[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
+	[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
+	[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
+	[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
+	[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
+	[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
+	[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
+	[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
+	[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
+	[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
+	[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
+	[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
+	[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
+	[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
+	[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
+	[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
+	[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
+	[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
+	[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
+	[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
+	[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
+	[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
+	[STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
+	[STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
+	[STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
+	[STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
+};
+
+/* PicoPHY reset/control */
+#define SYSCFG_5061	0x0f4
+
+static struct syscfg_reset_channel_data stih407_picophyresets[] = {
+	[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
+	[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
+	[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
+};
+
+static const struct
+syscfg_reset_controller_data stih407_powerdown_controller = {
+	.wait_for_ack = true,
+	.nr_channels = ARRAY_SIZE(stih407_powerdowns),
+	.channels = stih407_powerdowns,
+};
+
+static const struct
+syscfg_reset_controller_data stih407_softreset_controller = {
+	.wait_for_ack = false,
+	.active_low = true,
+	.nr_channels = ARRAY_SIZE(stih407_softresets),
+	.channels = stih407_softresets,
+};
+
+static const struct
+syscfg_reset_controller_data stih407_picophyreset_controller = {
+	.wait_for_ack = false,
+	.nr_channels = ARRAY_SIZE(stih407_picophyresets),
+	.channels = stih407_picophyresets,
+};
+
+phys_addr_t sti_reset_get_regmap(const char *compatible)
+{
+	struct udevice *syscon;
+	struct regmap *regmap;
+	int node, ret;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+					     compatible);
+	if (node < 0) {
+		pr_err("unable to find %s node\n", compatible);
+		return node;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
+	if (ret) {
+		pr_err("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	regmap = syscon_get_regmap(syscon);
+	if (!regmap) {
+		pr_err("unable to get regmap for %s\n", syscon->name);
+		return -ENODEV;
+	}
+
+	return regmap->ranges[0].start;
+}
+
+static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
+{
+	struct udevice *dev = reset_ctl->dev;
+	struct syscfg_reset_controller_data *reset_desc =
+		(struct syscfg_reset_controller_data *)(dev->driver_data);
+	struct syscfg_reset_channel_data *ch;
+	phys_addr_t base;
+	u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
+	void __iomem *reg;
+
+	/* check if reset id is inside available range */
+	if (reset_ctl->id >= reset_desc->nr_channels)
+		return -EINVAL;
+
+	/* get reset sysconf register base address */
+	base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
+
+	ch = &reset_desc->channels[reset_ctl->id];
+
+	/* check the deassert counter to assert reset when it reaches 0 */
+	if (!assert) {
+		ch->deassert_cnt++;
+		if (ch->deassert_cnt > 1)
+			return 0;
+	} else {
+		if (ch->deassert_cnt > 0) {
+			ch->deassert_cnt--;
+			if (ch->deassert_cnt > 0)
+				return 0;
+		} else
+			pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n",
+			      reset_ctl, reset_ctl->dev, reset_ctl->id);
+	}
+
+	reg = (void __iomem *)base + ch->reset_offset;
+
+	if (ctrl_val)
+		generic_set_bit(ch->reset_bit, reg);
+	else
+		generic_clear_bit(ch->reset_bit, reg);
+
+	if (!reset_desc->wait_for_ack)
+		return 0;
+
+	reg = (void __iomem *)base + ch->ack_offset;
+	if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
+			      1000, false)) {
+		pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
+		      reset_ctl, reset_ctl->dev, reset_ctl->id);
+
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int sti_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int sti_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int sti_reset_assert(struct reset_ctl *reset_ctl)
+{
+	return sti_reset_program_hw(reset_ctl, true);
+}
+
+static int sti_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return sti_reset_program_hw(reset_ctl, false);
+}
+
+struct reset_ops sti_reset_ops = {
+	.request = sti_reset_request,
+	.rfree = sti_reset_free,
+	.rst_assert = sti_reset_assert,
+	.rst_deassert = sti_reset_deassert,
+};
+
+static int sti_reset_probe(struct udevice *dev)
+{
+	struct sti_reset *priv = dev_get_priv(dev);
+
+	priv->data = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct udevice_id sti_reset_ids[] = {
+	{
+		.compatible = "st,stih407-picophyreset",
+		.data = (ulong)&stih407_picophyreset_controller,
+	},
+	{
+		.compatible = "st,stih407-powerdown",
+		.data = (ulong)&stih407_powerdown_controller,
+	},
+	{
+		.compatible = "st,stih407-softreset",
+		.data = (ulong)&stih407_softreset_controller,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(sti_reset) = {
+	.name = "sti_reset",
+	.id = UCLASS_RESET,
+	.of_match = sti_reset_ids,
+	.probe = sti_reset_probe,
+	.priv_auto	= sizeof(struct sti_reset),
+	.ops = &sti_reset_ops,
+};
diff --git a/roms/u-boot/drivers/reset/stm32-reset.c b/roms/u-boot/drivers/reset/stm32-reset.c
new file mode 100644
index 000000000..bbc6b135a
--- /dev/null
+++ b/roms/u-boot/drivers/reset/stm32-reset.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#define LOG_CATEGORY UCLASS_RESET
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <stm32_rcc.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+
+/* offset of register without set/clear management */
+#define RCC_MP_GCR_OFFSET 0x10C
+
+/* reset clear offset for STM32MP RCC */
+#define RCC_CL 0x4
+
+struct stm32_reset_priv {
+	fdt_addr_t base;
+};
+
+static int stm32_reset_request(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int stm32_reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static int stm32_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
+	int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
+
+	dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
+		reset_ctl->id, bank, offset);
+
+	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
+		if (bank != RCC_MP_GCR_OFFSET)
+			/* reset assert is done in rcc set register */
+			writel(BIT(offset), priv->base + bank);
+		else
+			clrbits_le32(priv->base + bank, BIT(offset));
+	else
+		setbits_le32(priv->base + bank, BIT(offset));
+
+	return 0;
+}
+
+static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
+	int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
+
+	dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
+		reset_ctl->id, bank, offset);
+
+	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
+		if (bank != RCC_MP_GCR_OFFSET)
+			/* reset deassert is done in rcc clr register */
+			writel(BIT(offset), priv->base + bank + RCC_CL);
+		else
+			setbits_le32(priv->base + bank, BIT(offset));
+	else
+		clrbits_le32(priv->base + bank, BIT(offset));
+
+	return 0;
+}
+
+static const struct reset_ops stm32_reset_ops = {
+	.request	= stm32_reset_request,
+	.rfree		= stm32_reset_free,
+	.rst_assert	= stm32_reset_assert,
+	.rst_deassert	= stm32_reset_deassert,
+};
+
+static int stm32_reset_probe(struct udevice *dev)
+{
+	struct stm32_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE) {
+		/* for MFD, get address of parent */
+		priv->base = dev_read_addr(dev->parent);
+		if (priv->base == FDT_ADDR_T_NONE)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(stm32_rcc_reset) = {
+	.name			= "stm32_rcc_reset",
+	.id			= UCLASS_RESET,
+	.probe			= stm32_reset_probe,
+	.priv_auto	= sizeof(struct stm32_reset_priv),
+	.ops			= &stm32_reset_ops,
+};
diff --git a/roms/u-boot/drivers/reset/tegra-car-reset.c b/roms/u-boot/drivers/reset/tegra-car-reset.c
new file mode 100644
index 000000000..a33d4533a
--- /dev/null
+++ b/roms/u-boot/drivers/reset/tegra-car-reset.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset-uclass.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+static int tegra_car_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	/* PERIPH_ID_COUNT varies per SoC */
+	if (reset_ctl->id >= PERIPH_ID_COUNT)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int tegra_car_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int tegra_car_reset_assert(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	reset_set_enable(reset_ctl->id, 1);
+
+	return 0;
+}
+
+static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	reset_set_enable(reset_ctl->id, 0);
+
+	return 0;
+}
+
+struct reset_ops tegra_car_reset_ops = {
+	.request = tegra_car_reset_request,
+	.rfree = tegra_car_reset_free,
+	.rst_assert = tegra_car_reset_assert,
+	.rst_deassert = tegra_car_reset_deassert,
+};
+
+static int tegra_car_reset_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_reset) = {
+	.name = "tegra_car_reset",
+	.id = UCLASS_RESET,
+	.probe = tegra_car_reset_probe,
+	.ops = &tegra_car_reset_ops,
+};
diff --git a/roms/u-boot/drivers/reset/tegra186-reset.c b/roms/u-boot/drivers/reset/tegra186-reset.c
new file mode 100644
index 000000000..c60a03f0b
--- /dev/null
+++ b/roms/u-boot/drivers/reset/tegra186-reset.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <misc.h>
+#include <reset-uclass.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+static int tegra186_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int tegra186_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int tegra186_reset_common(struct reset_ctl *reset_ctl,
+				 enum mrq_reset_commands cmd)
+{
+	struct mrq_reset_request req;
+	int ret;
+
+	req.cmd = cmd;
+	req.reset_id = reset_ctl->id;
+
+	ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
+			NULL, 0);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
+}
+
+static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
+}
+
+struct reset_ops tegra186_reset_ops = {
+	.request = tegra186_reset_request,
+	.rfree = tegra186_reset_free,
+	.rst_assert = tegra186_reset_assert,
+	.rst_deassert = tegra186_reset_deassert,
+};
+
+static int tegra186_reset_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(tegra186_reset) = {
+	.name		= "tegra186_reset",
+	.id		= UCLASS_RESET,
+	.probe		= tegra186_reset_probe,
+	.ops = &tegra186_reset_ops,
+};