Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

9 files changed, 986 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/rng/Kconfig b/roms/u-boot/drivers/rng/Kconfig
new file mode 100644
index 000000000..94915d45b
--- /dev/null
+++ b/roms/u-boot/drivers/rng/Kconfig
@@ -0,0 +1,55 @@
+config DM_RNG
+	bool "Driver support for Random Number Generator devices"
+	depends on DM
+	help
+	  Enable driver model for random number generator(rng) devices.
+	  This interface is used to initialise the rng device and to
+	  read the random seed from the device.
+
+if DM_RNG
+
+config RNG_MESON
+	bool "Amlogic Meson Random Number Generator support"
+	depends on ARCH_MESON
+	default y
+	help
+	  Enable support for hardware random number generator
+	  of Amlogic Meson SoCs.
+
+config RNG_SANDBOX
+	bool "Sandbox random number generator"
+	depends on SANDBOX
+	default y
+	help
+	  Enable random number generator for sandbox. This is an
+	  emulation of a rng device.
+
+config RNG_MSM
+	bool "Qualcomm SoCs Random Number Generator support"
+	depends on DM_RNG
+	help
+	  This driver provides support for the Random Number
+	  Generator hardware found on Qualcomm SoCs.
+
+config RNG_STM32MP1
+	bool "Enable random number generator for STM32MP1"
+	depends on ARCH_STM32MP
+	default n
+	help
+	  Enable STM32MP1 rng driver.
+
+config RNG_ROCKCHIP
+	bool "Enable random number generator for rockchip crypto rng"
+	depends on ARCH_ROCKCHIP && DM_RNG
+	default n
+	help
+	  Enable random number generator for rockchip.This driver is
+	  support rng module of crypto v1 and crypto v2.
+
+config RNG_IPROC200
+	bool "Broadcom iProc RNG200 random number generator"
+	depends on DM_RNG
+	default n
+	help
+	  Enable random number generator for RPI4.
+endif
diff --git a/roms/u-boot/drivers/rng/Makefile b/roms/u-boot/drivers/rng/Makefile
new file mode 100644
index 000000000..39f7ee3f0
--- /dev/null
+++ b/roms/u-boot/drivers/rng/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019, Linaro Limited
+#
+
+obj-$(CONFIG_DM_RNG) += rng-uclass.o
+obj-$(CONFIG_RNG_MESON) += meson-rng.o
+obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
+obj-$(CONFIG_RNG_MSM) += msm_rng.o
+obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
+obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
+obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
diff --git a/roms/u-boot/drivers/rng/iproc_rng200.c b/roms/u-boot/drivers/rng/iproc_rng200.c
new file mode 100644
index 000000000..85ac15bf9
--- /dev/null
+++ b/roms/u-boot/drivers/rng/iproc_rng200.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020, Matthias Brugger <mbrugger@suse.com>
+ *
+ * Driver for Raspberry Pi hardware random number generator
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <rng.h>
+#include <asm/io.h>
+
+#define usleep_range(a, b) udelay((b))
+
+#define RNG_CTRL_OFFSET					0x00
+#define RNG_CTRL_RNG_RBGEN_MASK				0x00001FFF
+#define RNG_CTRL_RNG_RBGEN_ENABLE			0x00000001
+#define RNG_CTRL_RNG_RBGEN_DISABLE			0x00000000
+
+#define RNG_SOFT_RESET_OFFSET				0x04
+#define RNG_SOFT_RESET					0x00000001
+
+#define RBG_SOFT_RESET_OFFSET				0x08
+#define RBG_SOFT_RESET					0x00000001
+
+#define RNG_INT_STATUS_OFFSET				0x18
+#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK	0x80000000
+#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK		0x00000020
+
+#define RNG_FIFO_DATA_OFFSET				0x20
+
+#define RNG_FIFO_COUNT_OFFSET				0x24
+#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK		0x000000FF
+
+struct iproc_rng200_plat {
+	void __iomem *base;
+};
+
+static void iproc_rng200_enable(struct iproc_rng200_plat *pdata, bool enable)
+{
+	void __iomem *rng_base = pdata->base;
+	u32 val;
+
+	val = readl(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	if (enable)
+		val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	else
+		val &= ~RNG_CTRL_RNG_RBGEN_ENABLE;
+
+	writel(val, rng_base + RNG_CTRL_OFFSET);
+}
+
+static void iproc_rng200_restart(struct iproc_rng200_plat *pdata)
+{
+	void __iomem *rng_base = pdata->base;
+	u32 val;
+
+	iproc_rng200_enable(pdata, false);
+
+	/* Clear all interrupt status */
+	writel(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
+
+	/* Reset RNG and RBG */
+	val = readl(rng_base + RBG_SOFT_RESET_OFFSET);
+	val |= RBG_SOFT_RESET;
+	writel(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	val = readl(rng_base + RNG_SOFT_RESET_OFFSET);
+	val |= RNG_SOFT_RESET;
+	writel(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = readl(rng_base + RNG_SOFT_RESET_OFFSET);
+	val &= ~RNG_SOFT_RESET;
+	writel(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = readl(rng_base + RBG_SOFT_RESET_OFFSET);
+	val &= ~RBG_SOFT_RESET;
+	writel(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	iproc_rng200_enable(pdata, true);
+}
+
+static int iproc_rng200_read(struct udevice *dev, void *data, size_t len)
+{
+	struct iproc_rng200_plat *priv = dev_get_plat(dev);
+	char *buf = (char *)data;
+	u32 num_remaining = len;
+	u32 status;
+
+	#define MAX_RESETS_PER_READ	1
+	u32 num_resets = 0;
+
+	while (num_remaining > 0) {
+
+		/* Is RNG sane? If not, reset it. */
+		status = readl(priv->base + RNG_INT_STATUS_OFFSET);
+		if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
+			RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
+
+			if (num_resets >= MAX_RESETS_PER_READ)
+				return len - num_remaining;
+
+			iproc_rng200_restart(priv);
+			num_resets++;
+		}
+
+		/* Are there any random numbers available? */
+		if ((readl(priv->base + RNG_FIFO_COUNT_OFFSET) &
+				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
+
+			if (num_remaining >= sizeof(u32)) {
+				/* Buffer has room to store entire word */
+				*(u32 *)buf = readl(priv->base +
+							RNG_FIFO_DATA_OFFSET);
+				buf += sizeof(u32);
+				num_remaining -= sizeof(u32);
+			} else {
+				/* Buffer can only store partial word */
+				u32 rnd_number = readl(priv->base +
+							RNG_FIFO_DATA_OFFSET);
+				memcpy(buf, &rnd_number, num_remaining);
+				buf += num_remaining;
+				num_remaining = 0;
+			}
+
+		} else {
+			/* Can wait, give others chance to run */
+			usleep_range(min(num_remaining * 10, 500U), 500);
+		}
+	}
+
+	return 0;
+}
+
+static int iproc_rng200_probe(struct udevice *dev)
+{
+	struct iproc_rng200_plat *priv = dev_get_plat(dev);
+
+	iproc_rng200_enable(priv, true);
+
+	return 0;
+}
+
+static int iproc_rng200_remove(struct udevice *dev)
+{
+	struct iproc_rng200_plat *priv = dev_get_plat(dev);
+
+	iproc_rng200_enable(priv, false);
+
+	return 0;
+}
+
+static int iproc_rng200_of_to_plat(struct udevice *dev)
+{
+	struct iproc_rng200_plat *pdata = dev_get_plat(dev);
+
+	pdata->base = devfdt_map_physmem(dev, sizeof(void *));
+	if (!pdata->base)
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct dm_rng_ops iproc_rng200_ops = {
+	.read = iproc_rng200_read,
+};
+
+static const struct udevice_id iproc_rng200_rng_match[] = {
+	{ .compatible = "brcm,bcm2711-rng200", },
+	{ .compatible = "brcm,iproc-rng200", },
+	{},
+};
+
+U_BOOT_DRIVER(iproc_rng200_rng) = {
+	.name = "iproc_rng200-rng",
+	.id = UCLASS_RNG,
+	.of_match = iproc_rng200_rng_match,
+	.ops = &iproc_rng200_ops,
+	.probe = iproc_rng200_probe,
+	.remove = iproc_rng200_remove,
+	.priv_auto = sizeof(struct iproc_rng200_plat),
+	.of_to_plat = iproc_rng200_of_to_plat,
+};
diff --git a/roms/u-boot/drivers/rng/meson-rng.c b/roms/u-boot/drivers/rng/meson-rng.c
new file mode 100644
index 000000000..5a4f45ad5
--- /dev/null
+++ b/roms/u-boot/drivers/rng/meson-rng.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * Driver for Amlogic hardware random number generator
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <rng.h>
+#include <asm/io.h>
+
+struct meson_rng_plat {
+	fdt_addr_t base;
+	struct clk clk;
+};
+
+/**
+ * meson_rng_read() - fill buffer with random bytes
+ *
+ * @buffer:	buffer to receive data
+ * @size:	size of buffer
+ *
+ * Return:	0
+ */
+static int meson_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct meson_rng_plat *pdata = dev_get_plat(dev);
+	char *buffer = (char *)data;
+
+	while (len) {
+		u32 rand = readl(pdata->base);
+		size_t step;
+
+		if (len >= 4)
+			step = 4;
+		else
+			step = len;
+		memcpy(buffer, &rand, step);
+		buffer += step;
+		len -= step;
+	}
+	return 0;
+}
+
+/**
+ * meson_rng_probe() - probe rng device
+ *
+ * @dev:	device
+ * Return:	0 if ok
+ */
+static int meson_rng_probe(struct udevice *dev)
+{
+	struct meson_rng_plat *pdata = dev_get_plat(dev);
+	int err;
+
+	err = clk_enable(&pdata->clk);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+/**
+ * meson_rng_remove() - deinitialize rng device
+ *
+ * @dev:	device
+ * Return:	0 if ok
+ */
+static int meson_rng_remove(struct udevice *dev)
+{
+	struct meson_rng_plat *pdata = dev_get_plat(dev);
+
+	return clk_disable(&pdata->clk);
+}
+
+/**
+ * meson_rng_of_to_plat() - transfer device tree data to plaform data
+ *
+ * @dev:	device
+ * Return:	0 if ok
+ */
+static int meson_rng_of_to_plat(struct udevice *dev)
+{
+	struct meson_rng_plat *pdata = dev_get_plat(dev);
+	int err;
+
+	pdata->base = dev_read_addr(dev);
+	if (!pdata->base)
+		return -ENODEV;
+
+	/* Get optional "core" clock */
+	err = clk_get_by_name(dev, "core", &pdata->clk);
+	if (err && err != -ENODATA)
+		return err;
+
+	return 0;
+}
+
+static const struct dm_rng_ops meson_rng_ops = {
+	.read = meson_rng_read,
+};
+
+static const struct udevice_id meson_rng_match[] = {
+	{
+		.compatible = "amlogic,meson-rng",
+	},
+	{},
+};
+
+U_BOOT_DRIVER(meson_rng) = {
+	.name = "meson-rng",
+	.id = UCLASS_RNG,
+	.of_match = meson_rng_match,
+	.ops = &meson_rng_ops,
+	.probe = meson_rng_probe,
+	.remove = meson_rng_remove,
+	.plat_auto	= sizeof(struct meson_rng_plat),
+	.of_to_plat = meson_rng_of_to_plat,
+};
diff --git a/roms/u-boot/drivers/rng/msm_rng.c b/roms/u-boot/drivers/rng/msm_rng.c
new file mode 100644
index 000000000..29e7354ec
--- /dev/null
+++ b/roms/u-boot/drivers/rng/msm_rng.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PRNG driver for Qualcomm IPQ40xx
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <rng.h>
+
+/* Device specific register offsets */
+#define PRNG_DATA_OUT		0x0000
+#define PRNG_STATUS			0x0004
+#define PRNG_LFSR_CFG		0x0100
+#define PRNG_CONFIG			0x0104
+
+/* Device specific register masks and config values */
+#define PRNG_LFSR_CFG_MASK		0x0000ffff
+#define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
+#define PRNG_CONFIG_HW_ENABLE	BIT(1)
+#define PRNG_STATUS_DATA_AVAIL	BIT(0)
+
+#define MAX_HW_FIFO_DEPTH		16
+#define MAX_HW_FIFO_SIZE		(MAX_HW_FIFO_DEPTH * 4)
+#define WORD_SZ					4
+
+struct msm_rng_priv {
+	phys_addr_t base;
+	struct clk clk;
+};
+
+static int msm_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+	size_t currsize = 0;
+	u32 *retdata = data;
+	size_t maxsize;
+	u32 val;
+
+	/* calculate max size bytes to transfer back to caller */
+	maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
+
+	/* read random data from hardware */
+	do {
+		val = readl_relaxed(priv->base + PRNG_STATUS);
+		if (!(val & PRNG_STATUS_DATA_AVAIL))
+			break;
+
+		val = readl_relaxed(priv->base + PRNG_DATA_OUT);
+		if (!val)
+			break;
+
+		*retdata++ = val;
+		currsize += WORD_SZ;
+
+		/* make sure we stay on 32bit boundary */
+		if ((maxsize - currsize) < WORD_SZ)
+			break;
+	} while (currsize < maxsize);
+
+	return 0;
+}
+
+static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
+{
+	u32 val;
+
+	if (enable) {
+		/* Enable PRNG only if it is not already enabled */
+		val = readl_relaxed(priv->base + PRNG_CONFIG);
+		if (val & PRNG_CONFIG_HW_ENABLE) {
+			val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
+			val &= ~PRNG_LFSR_CFG_MASK;
+			val |= PRNG_LFSR_CFG_CLOCKS;
+			writel(val, priv->base + PRNG_LFSR_CFG);
+
+			val = readl_relaxed(priv->base + PRNG_CONFIG);
+			val |= PRNG_CONFIG_HW_ENABLE;
+			writel(val, priv->base + PRNG_CONFIG);
+		}
+	} else {
+		val = readl_relaxed(priv->base + PRNG_CONFIG);
+		val &= ~PRNG_CONFIG_HW_ENABLE;
+		writel(val, priv->base + PRNG_CONFIG);
+	}
+
+	return 0;
+}
+
+static int msm_rng_probe(struct udevice *dev)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	return msm_rng_enable(priv, 1);
+}
+
+static int msm_rng_remove(struct udevice *dev)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+
+	return msm_rng_enable(priv, 0);
+}
+
+static const struct dm_rng_ops msm_rng_ops = {
+	.read = msm_rng_read,
+};
+
+static const struct udevice_id msm_rng_match[] = {
+	{ .compatible = "qcom,prng", },
+	{},
+};
+
+U_BOOT_DRIVER(msm_rng) = {
+	.name = "msm-rng",
+	.id = UCLASS_RNG,
+	.of_match = msm_rng_match,
+	.ops = &msm_rng_ops,
+	.probe = msm_rng_probe,
+	.remove = msm_rng_remove,
+	.priv_auto	= sizeof(struct msm_rng_priv),
+};
diff --git a/roms/u-boot/drivers/rng/rng-uclass.c b/roms/u-boot/drivers/rng/rng-uclass.c
new file mode 100644
index 000000000..b6af3b860
--- /dev/null
+++ b/roms/u-boot/drivers/rng/rng-uclass.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <rng.h>
+
+int dm_rng_read(struct udevice *dev, void *buffer, size_t size)
+{
+	const struct dm_rng_ops *ops = device_get_ops(dev);
+
+	if (!ops->read)
+		return -ENOSYS;
+
+	return ops->read(dev, buffer, size);
+}
+
+UCLASS_DRIVER(rng) = {
+	.name = "rng",
+	.id = UCLASS_RNG,
+};
diff --git a/roms/u-boot/drivers/rng/rockchip_rng.c b/roms/u-boot/drivers/rng/rockchip_rng.c
new file mode 100644
index 000000000..800150f11
--- /dev/null
+++ b/roms/u-boot/drivers/rng/rockchip_rng.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <linux/string.h>
+#include <rng.h>
+
+#define RK_HW_RNG_MAX 32
+
+#define _SBF(s, v)	((v) << (s))
+
+/* start of CRYPTO V1 register define */
+#define CRYPTO_V1_CTRL				0x0008
+#define CRYPTO_V1_RNG_START			BIT(8)
+#define CRYPTO_V1_RNG_FLUSH			BIT(9)
+
+#define CRYPTO_V1_TRNG_CTRL			0x0200
+#define CRYPTO_V1_OSC_ENABLE			BIT(16)
+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
+
+#define CRYPTO_V1_TRNG_DOUT_0			0x0204
+/* end of CRYPTO V1 register define */
+
+/* start of CRYPTO V2 register define */
+#define CRYPTO_V2_RNG_CTL			0x0400
+#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
+#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
+#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
+#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
+#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
+#define CRYPTO_V2_RNG_ENABLE			BIT(1)
+#define CRYPTO_V2_RNG_START			BIT(0)
+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
+#define CRYPTO_V2_RNG_DOUT_0			0x0410
+/* end of CRYPTO V2 register define */
+
+#define RK_RNG_TIME_OUT	50000  /* max 50ms */
+
+struct rk_rng_soc_data {
+	int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
+};
+
+struct rk_rng_plat {
+	fdt_addr_t base;
+	struct rk_rng_soc_data *soc_data;
+};
+
+static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
+{
+	u32 count = RK_HW_RNG_MAX / sizeof(u32);
+	u32 reg, tmp_len;
+
+	if (size > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	while (size && count) {
+		reg = readl(addr);
+		tmp_len = min(size, sizeof(u32));
+		memcpy(buf, &reg, tmp_len);
+		addr += sizeof(u32);
+		buf += tmp_len;
+		size -= tmp_len;
+		count--;
+	}
+
+	return 0;
+}
+
+static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+	u32 reg = 0;
+	int retval;
+
+	if (len > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	/* enable osc_ring to get entropy, sample period is set as 100 */
+	writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
+	       pdata->base + CRYPTO_V1_TRNG_CTRL);
+
+	rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
+		     CRYPTO_V1_RNG_START);
+
+	retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
+				    !(reg & CRYPTO_V1_RNG_START),
+				    RK_RNG_TIME_OUT);
+	if (retval)
+		goto exit;
+
+	rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
+
+exit:
+	/* close TRNG */
+	rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
+
+	return 0;
+}
+
+static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+	u32 reg = 0;
+	int retval;
+
+	if (len > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	/* enable osc_ring to get entropy, sample period is set as 100 */
+	writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
+
+	reg |= CRYPTO_V2_RNG_256_BIT_LEN;
+	reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
+	reg |= CRYPTO_V2_RNG_ENABLE;
+	reg |= CRYPTO_V2_RNG_START;
+
+	rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
+
+	retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
+				    !(reg & CRYPTO_V2_RNG_START),
+				    RK_RNG_TIME_OUT);
+	if (retval)
+		goto exit;
+
+	rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
+
+exit:
+	/* close TRNG */
+	rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
+
+	return retval;
+}
+
+static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	unsigned char *buf = data;
+	unsigned int i;
+	int ret = -EIO;
+
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+
+	if (!len)
+		return 0;
+
+	if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
+		return -EINVAL;
+
+	for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
+		ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
+		if (ret)
+			goto exit;
+	}
+
+	if (len % RK_HW_RNG_MAX)
+		ret = pdata->soc_data->rk_rng_read(dev, buf,
+						   len % RK_HW_RNG_MAX);
+
+exit:
+	return ret;
+}
+
+static int rockchip_rng_of_to_plat(struct udevice *dev)
+{
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+
+	memset(pdata, 0x00, sizeof(*pdata));
+
+	pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
+	if (!pdata->base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int rockchip_rng_probe(struct udevice *dev)
+{
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+
+	pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
+	.rk_rng_read = rk_v1_rng_read,
+};
+
+static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
+	.rk_rng_read = rk_v2_rng_read,
+};
+
+static const struct dm_rng_ops rockchip_rng_ops = {
+	.read = rockchip_rng_read,
+};
+
+static const struct udevice_id rockchip_rng_match[] = {
+	{
+		.compatible = "rockchip,cryptov1-rng",
+		.data = (ulong)&rk_rng_v1_soc_data,
+	},
+	{
+		.compatible = "rockchip,cryptov2-rng",
+		.data = (ulong)&rk_rng_v2_soc_data,
+	},
+	{},
+};
+
+U_BOOT_DRIVER(rockchip_rng) = {
+	.name = "rockchip-rng",
+	.id = UCLASS_RNG,
+	.of_match = rockchip_rng_match,
+	.ops = &rockchip_rng_ops,
+	.probe = rockchip_rng_probe,
+	.of_to_plat = rockchip_rng_of_to_plat,
+	.priv_auto	= sizeof(struct rk_rng_plat),
+};
diff --git a/roms/u-boot/drivers/rng/sandbox_rng.c b/roms/u-boot/drivers/rng/sandbox_rng.c
new file mode 100644
index 000000000..cc5e1f6e2
--- /dev/null
+++ b/roms/u-boot/drivers/rng/sandbox_rng.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <rand.h>
+#include <rng.h>
+
+#include <linux/string.h>
+
+static int sandbox_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	unsigned int i, seed, random;
+	unsigned char *buf = data;
+	size_t nrem, nloops;
+
+	if (!len)
+		return 0;
+
+	nloops = len / sizeof(random);
+	seed = get_timer(0) ^ rand();
+	srand(seed);
+
+	for (i = 0, nrem = len; i < nloops; i++) {
+		random = rand();
+		memcpy(buf, &random, sizeof(random));
+		buf += sizeof(random);
+		nrem -= sizeof(random);
+	}
+
+	if (nrem) {
+		random = rand();
+		memcpy(buf, &random, nrem);
+	}
+
+	return 0;
+}
+
+static const struct dm_rng_ops sandbox_rng_ops = {
+	.read = sandbox_rng_read,
+};
+
+static const struct udevice_id sandbox_rng_match[] = {
+	{
+		.compatible = "sandbox,sandbox-rng",
+	},
+	{},
+};
+
+U_BOOT_DRIVER(sandbox_rng) = {
+	.name = "sandbox-rng",
+	.id = UCLASS_RNG,
+	.of_match = sandbox_rng_match,
+	.ops = &sandbox_rng_ops,
+};
diff --git a/roms/u-boot/drivers/rng/stm32mp1_rng.c b/roms/u-boot/drivers/rng/stm32mp1_rng.c
new file mode 100644
index 000000000..8ea00e3e8
--- /dev/null
+++ b/roms/u-boot/drivers/rng/stm32mp1_rng.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <reset.h>
+#include <rng.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+
+#define RNG_CR 0x00
+#define RNG_CR_RNGEN BIT(2)
+#define RNG_CR_CED BIT(5)
+
+#define RNG_SR 0x04
+#define RNG_SR_SEIS BIT(6)
+#define RNG_SR_CEIS BIT(5)
+#define RNG_SR_SECS BIT(2)
+#define RNG_SR_DRDY BIT(0)
+
+#define RNG_DR 0x08
+
+struct stm32_rng_plat {
+	fdt_addr_t base;
+	struct clk clk;
+	struct reset_ctl rst;
+};
+
+static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	int retval, i;
+	u32 sr, count, reg;
+	size_t increment;
+	struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+	while (len > 0) {
+		retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
+					    sr & RNG_SR_DRDY, 10000);
+		if (retval)
+			return retval;
+
+		if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) {
+			/* As per SoC TRM */
+			clrbits_le32(pdata->base + RNG_SR, RNG_SR_SEIS);
+			for (i = 0; i < 12; i++)
+				readl(pdata->base + RNG_DR);
+			if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) {
+				log_err("RNG Noise");
+				return -EIO;
+			}
+			/* start again */
+			continue;
+		}
+
+		/*
+		 * Once the DRDY bit is set, the RNG_DR register can
+		 * be read four consecutive times.
+		 */
+		count = 4;
+		while (len && count) {
+			reg = readl(pdata->base + RNG_DR);
+			memcpy(data, &reg, min(len, sizeof(u32)));
+			increment = min(len, sizeof(u32));
+			data += increment;
+			len -= increment;
+			count--;
+		}
+	}
+
+	return 0;
+}
+
+static int stm32_rng_init(struct stm32_rng_plat *pdata)
+{
+	int err;
+
+	err = clk_enable(&pdata->clk);
+	if (err)
+		return err;
+
+	/* Disable CED */
+	writel(RNG_CR_RNGEN | RNG_CR_CED, pdata->base + RNG_CR);
+
+	/* clear error indicators */
+	writel(0, pdata->base + RNG_SR);
+
+	return 0;
+}
+
+static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
+{
+	writel(0, pdata->base + RNG_CR);
+
+	return clk_disable(&pdata->clk);
+}
+
+static int stm32_rng_probe(struct udevice *dev)
+{
+	struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+	reset_assert(&pdata->rst);
+	udelay(20);
+	reset_deassert(&pdata->rst);
+
+	return stm32_rng_init(pdata);
+}
+
+static int stm32_rng_remove(struct udevice *dev)
+{
+	struct stm32_rng_plat *pdata = dev_get_plat(dev);
+
+	return stm32_rng_cleanup(pdata);
+}
+
+static int stm32_rng_of_to_plat(struct udevice *dev)
+{
+	struct stm32_rng_plat *pdata = dev_get_plat(dev);
+	int err;
+
+	pdata->base = dev_read_addr(dev);
+	if (!pdata->base)
+		return -ENOMEM;
+
+	err = clk_get_by_index(dev, 0, &pdata->clk);
+	if (err)
+		return err;
+
+	err = reset_get_by_index(dev, 0, &pdata->rst);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static const struct dm_rng_ops stm32_rng_ops = {
+	.read = stm32_rng_read,
+};
+
+static const struct udevice_id stm32_rng_match[] = {
+	{
+		.compatible = "st,stm32-rng",
+	},
+	{},
+};
+
+U_BOOT_DRIVER(stm32_rng) = {
+	.name = "stm32-rng",
+	.id = UCLASS_RNG,
+	.of_match = stm32_rng_match,
+	.ops = &stm32_rng_ops,
+	.probe = stm32_rng_probe,
+	.remove = stm32_rng_remove,
+	.plat_auto	= sizeof(struct stm32_rng_plat),
+	.of_to_plat = stm32_rng_of_to_plat,
+};