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author | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
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committer | Angelos Mouzakitis <a.mouzakitis@virtualopensystems.com> | 2023-10-10 14:33:42 +0000 |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/drivers/timer/andes_plmt_timer.c | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/drivers/timer/andes_plmt_timer.c')
-rw-r--r-- | roms/u-boot/drivers/timer/andes_plmt_timer.c | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/roms/u-boot/drivers/timer/andes_plmt_timer.c b/roms/u-boot/drivers/timer/andes_plmt_timer.c new file mode 100644 index 000000000..a3797b22c --- /dev/null +++ b/roms/u-boot/drivers/timer/andes_plmt_timer.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Rick Chen <rick@andestech.com> + * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> + * + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT). + * The PLMT block holds memory-mapped mtime register + * associated with timer tick. + */ + +#include <common.h> +#include <dm.h> +#include <timer.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <linux/err.h> + +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base)) + +static u64 notrace andes_plmt_get_count(struct udevice *dev) +{ + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); +} + +#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_MMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); +} +#endif + +static const struct timer_ops andes_plmt_ops = { + .get_count = andes_plmt_get_count, +}; + +static int andes_plmt_probe(struct udevice *dev) +{ + dev_set_priv(dev, dev_read_addr_ptr(dev)); + if (!dev_get_priv(dev)) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + +static const struct udevice_id andes_plmt_ids[] = { + { .compatible = "riscv,plmt0" }, + { } +}; + +U_BOOT_DRIVER(andes_plmt) = { + .name = "andes_plmt", + .id = UCLASS_TIMER, + .of_match = andes_plmt_ids, + .ops = &andes_plmt_ops, + .probe = andes_plmt_probe, + .flags = DM_FLAG_PRE_RELOC, +}; |