Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

4 files changed, 1061 insertions, 0 deletions

diff --git a/roms/u-boot/drivers/video/stm32/Kconfig b/roms/u-boot/drivers/video/stm32/Kconfig
new file mode 100644
index 000000000..95d51bb4e
--- /dev/null
+++ b/roms/u-boot/drivers/video/stm32/Kconfig
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) STMicroelectronics SA 2017
+#
+# Authors: Philippe Cornu <philippe.cornu@st.com>
+#          Yannick Fertre <yannick.fertre@st.com>
+
+menuconfig VIDEO_STM32
+	bool "Enable STM32 video support"
+	depends on DM_VIDEO
+	help
+	  STM32 supports many video output options including RGB and
+	  DSI. This option enables these supports which can be used on
+	  devices which have RGB TFT or DSI display connected.
+
+config VIDEO_STM32_DSI
+	bool "Enable STM32 DSI video support"
+	depends on VIDEO_STM32
+	select VIDEO_BRIDGE
+	select VIDEO_DW_MIPI_DSI
+	help
+	  This option enables support DSI internal bridge which can be used on
+	  devices which have DSI devices connected.
+
+config VIDEO_STM32_MAX_XRES
+	int "Maximum horizontal resolution (for memory allocation purposes)"
+	depends on VIDEO_STM32
+	default 640
+	help
+	  The maximum horizontal resolution to support for the framebuffer.
+	  This configuration is used for reserving/allocating memory for the
+	  framebuffer during device-model binding/probing.
+
+config VIDEO_STM32_MAX_YRES
+	int "Maximum vertical resolution (for memory allocation purposes)"
+	depends on VIDEO_STM32
+	default 480
+	help
+	  The maximum vertical resolution to support for the framebuffer.
+	  This configuration is used for reserving/allocating memory for the
+	  framebuffer during device-model binding/probing.
+
+config VIDEO_STM32_MAX_BPP
+	int "Maximum bits per pixel (for memory allocation purposes)"
+	depends on VIDEO_STM32
+	default 16
+	help
+	  The maximum bits per pixel to support for the framebuffer.
+	  This configuration is used for reserving/allocating memory for the
+	  framebuffer during device-model binding/probing.
+
diff --git a/roms/u-boot/drivers/video/stm32/Makefile b/roms/u-boot/drivers/video/stm32/Makefile
new file mode 100644
index 000000000..f8b42d1a4
--- /dev/null
+++ b/roms/u-boot/drivers/video/stm32/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) STMicroelectronics SA 2017
+#
+# Authors: Philippe Cornu <philippe.cornu@st.com>
+#          Yannick Fertre <yannick.fertre@st.com>
+
+obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/roms/u-boot/drivers/video/stm32/stm32_dsi.c b/roms/u-boot/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000000000..4027e978c
--- /dev/null
+++ b/roms/u-boot/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *	      Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ *
+ * This MIPI DSI controller driver is based on the Linux Kernel driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
+ */
+
+#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dsi_host.h>
+#include <log.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <reset.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <power/regulator.h>
+
+#define HWVER_130			0x31333000	/* IP version 1.30 */
+#define HWVER_131			0x31333100	/* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION			0x00
+#define VERSION				GENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR	0x0400		/* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM	BIT(0)		/* DSI Mode */
+#define WCFGR_COLMUX	GENMASK(3, 1)	/* COLor MUltipleXing */
+
+#define DSI_WCR		0x0404		/* Wrapper Control Reg */
+#define WCR_DSIEN	BIT(3)		/* DSI ENable */
+
+#define DSI_WISR	0x040C		/* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS	BIT(8)		/* PLL Lock Status */
+#define WISR_RRS	BIT(12)		/* Regulator Ready Status */
+
+#define DSI_WPCR0	0x0418		/* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4	GENMASK(5, 0)	/* Unit Interval X 4 */
+#define WPCR0_TDDL	BIT(16)		/* Turn Disable Data Lanes */
+
+#define DSI_WRPCR	0x0430		/* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLEN	BIT(0)		/* PLL ENable */
+#define WRPCR_NDIV	GENMASK(8, 2)	/* pll loop DIVision Factor */
+#define WRPCR_IDF	GENMASK(14, 11)	/* pll Input Division Factor */
+#define WRPCR_ODF	GENMASK(17, 16)	/* pll Output Division Factor */
+#define WRPCR_REGEN	BIT(24)		/* REGulator ENable */
+#define WRPCR_BGREN	BIT(28)		/* BandGap Reference ENable */
+#define IDF_MIN		1
+#define IDF_MAX		7
+#define NDIV_MIN	10
+#define NDIV_MAX	125
+#define ODF_MIN		1
+#define ODF_MAX		8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+	DSI_RGB565_CONF1,
+	DSI_RGB565_CONF2,
+	DSI_RGB565_CONF3,
+	DSI_RGB666_CONF1,
+	DSI_RGB666_CONF2,
+	DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS	31250
+#define LANE_MAX_KBPS	500000
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US	200000
+
+struct stm32_dsi_priv {
+	struct mipi_dsi_device device;
+	void __iomem *base;
+	struct udevice *panel;
+	u32 pllref_clk;
+	u32 hw_version;
+	int lane_min_kbps;
+	int lane_max_kbps;
+	struct udevice *vdd_reg;
+	struct udevice *dsi_host;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+	writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+	return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
+{
+	dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
+}
+
+static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
+{
+	dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
+}
+
+static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg,
+				   u32 mask, u32 val)
+{
+	dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
+}
+
+static enum dsi_color dsi_color_from_mipi(u32 fmt)
+{
+	switch (fmt) {
+	case MIPI_DSI_FMT_RGB888:
+		return DSI_RGB888;
+	case MIPI_DSI_FMT_RGB666:
+		return DSI_RGB666_CONF2;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		return DSI_RGB666_CONF1;
+	case MIPI_DSI_FMT_RGB565:
+		return DSI_RGB565_CONF1;
+	default:
+		log_err("MIPI color invalid, so we use rgb888\n");
+	}
+	return DSI_RGB888;
+}
+
+static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
+{
+	int divisor = idf * odf;
+
+	/* prevent from division by 0 */
+	if (!divisor)
+		return 0;
+
+	return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
+}
+
+static int dsi_pll_get_params(struct stm32_dsi_priv *dsi,
+			      int clkin_khz, int clkout_khz,
+			      int *idf, int *ndiv, int *odf)
+{
+	int i, o, n, n_min, n_max;
+	int fvco_min, fvco_max, delta, best_delta; /* all in khz */
+
+	/* Early checks preventing division by 0 & odd results */
+	if (clkin_khz <= 0 || clkout_khz <= 0)
+		return -EINVAL;
+
+	fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
+	fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
+
+	best_delta = 1000000; /* big started value (1000000khz) */
+
+	for (i = IDF_MIN; i <= IDF_MAX; i++) {
+		/* Compute ndiv range according to Fvco */
+		n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1;
+		n_max = (fvco_max * i) / (2 * clkin_khz);
+
+		/* No need to continue idf loop if we reach ndiv max */
+		if (n_min >= NDIV_MAX)
+			break;
+
+		/* Clamp ndiv to valid values */
+		if (n_min < NDIV_MIN)
+			n_min = NDIV_MIN;
+		if (n_max > NDIV_MAX)
+			n_max = NDIV_MAX;
+
+		for (o = ODF_MIN; o <= ODF_MAX; o *= 2) {
+			n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz);
+			/* Check ndiv according to vco range */
+			if (n < n_min || n > n_max)
+				continue;
+			/* Check if new delta is better & saves parameters */
+			delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
+				clkout_khz;
+			if (delta < 0)
+				delta = -delta;
+			if (delta < best_delta) {
+				*idf = i;
+				*ndiv = n;
+				*odf = o;
+				best_delta = delta;
+			}
+			/* fast return in case of "perfect result" */
+			if (!delta)
+				return 0;
+		}
+	}
+
+	return 0;
+}
+
+static int dsi_phy_init(void *priv_data)
+{
+	struct mipi_dsi_device *device = priv_data;
+	struct udevice *dev = device->dev;
+	struct stm32_dsi_priv *dsi = dev_get_priv(dev);
+	u32 val;
+	int ret;
+
+	dev_dbg(dev, "Initialize DSI physical layer\n");
+
+	/* Enable the regulator */
+	dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
+	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
+				 TIMEOUT_US);
+	if (ret) {
+		dev_dbg(dev, "!TIMEOUT! waiting REGU\n");
+		return ret;
+	}
+
+	/* Enable the DSI PLL & wait for its lock */
+	dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
+	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
+				 TIMEOUT_US);
+	if (ret) {
+		dev_dbg(dev, "!TIMEOUT! waiting PLL\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
+{
+	struct mipi_dsi_device *device = priv_data;
+	struct udevice *dev = device->dev;
+	struct stm32_dsi_priv *dsi = dev_get_priv(dev);
+
+	dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
+		mode_flags & MIPI_DSI_MODE_VIDEO);
+
+	if (!dsi)
+		return;
+
+	/*
+	 * DSI wrapper must be enabled in video mode & disabled in command mode.
+	 * If wrapper is enabled in command mode, the display controller
+	 * register access will hang.
+	 */
+
+	if (mode_flags & MIPI_DSI_MODE_VIDEO)
+		dsi_set(dsi, DSI_WCR, WCR_DSIEN);
+	else
+		dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
+}
+
+static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
+			     u32 lanes, u32 format, unsigned int *lane_mbps)
+{
+	struct mipi_dsi_device *device = priv_data;
+	struct udevice *dev = device->dev;
+	struct stm32_dsi_priv *dsi = dev_get_priv(dev);
+	int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+	int ret, bpp;
+	u32 val;
+
+	/* Update lane capabilities according to hw version */
+	dsi->lane_min_kbps = LANE_MIN_KBPS;
+	dsi->lane_max_kbps = LANE_MAX_KBPS;
+	if (dsi->hw_version == HWVER_131) {
+		dsi->lane_min_kbps *= 2;
+		dsi->lane_max_kbps *= 2;
+	}
+
+	pll_in_khz = dsi->pllref_clk / 1000;
+
+	/* Compute requested pll out */
+	bpp = mipi_dsi_pixel_format_to_bpp(format);
+	pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes;
+	/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
+	pll_out_khz = (pll_out_khz * 12) / 10;
+	if (pll_out_khz > dsi->lane_max_kbps) {
+		pll_out_khz = dsi->lane_max_kbps;
+		dev_warn(dev, "Warning max phy mbps is used\n");
+	}
+	if (pll_out_khz < dsi->lane_min_kbps) {
+		pll_out_khz = dsi->lane_min_kbps;
+		dev_warn(dev, "Warning min phy mbps is used\n");
+	}
+
+	/* Compute best pll parameters */
+	idf = 0;
+	ndiv = 0;
+	odf = 0;
+	ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
+				 &idf, &ndiv, &odf);
+	if (ret) {
+		dev_err(dev, "Warning dsi_pll_get_params(): bad params\n");
+		return ret;
+	}
+
+	/* Get the adjusted pll out value */
+	pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
+
+	/* Set the PLL division factors */
+	dsi_update_bits(dsi, DSI_WRPCR,	WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF,
+			(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
+
+	/* Compute uix4 & set the bit period in high-speed mode */
+	val = 4000000 / pll_out_khz;
+	dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val);
+
+	/* Select video mode by resetting DSIM bit */
+	dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
+
+	/* Select the color coding */
+	dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
+			dsi_color_from_mipi(format) << 1);
+
+	*lane_mbps = pll_out_khz / 1000;
+
+	dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
+		pll_in_khz, pll_out_khz, *lane_mbps);
+
+	return 0;
+}
+
+static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = {
+	.init = dsi_phy_init,
+	.get_lane_mbps = dsi_get_lane_mbps,
+	.post_set_mode = dsi_phy_post_set_mode,
+};
+
+static int stm32_dsi_attach(struct udevice *dev)
+{
+	struct stm32_dsi_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	struct mipi_dsi_panel_plat *mplat;
+	struct display_timing timings;
+	int ret;
+
+	ret = uclass_first_device(UCLASS_PANEL, &priv->panel);
+	if (ret) {
+		dev_err(dev, "panel device error %d\n", ret);
+		return ret;
+	}
+
+	mplat = dev_get_plat(priv->panel);
+	mplat->device = &priv->device;
+	device->lanes = mplat->lanes;
+	device->format = mplat->format;
+	device->mode_flags = mplat->mode_flags;
+
+	ret = panel_get_display_timing(priv->panel, &timings);
+	if (ret) {
+		ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
+						   0, &timings);
+		if (ret) {
+			dev_err(dev, "decode display timing error %d\n", ret);
+			return ret;
+		}
+	}
+
+	ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "No video dsi host detected %d\n", ret);
+		return ret;
+	}
+
+	ret = dsi_host_init(priv->dsi_host, device, &timings, 2,
+			    &dsi_stm_phy_ops);
+	if (ret) {
+		dev_err(dev, "failed to initialize mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int stm32_dsi_set_backlight(struct udevice *dev, int percent)
+{
+	struct stm32_dsi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		dev_err(dev, "panel %s enable backlight error %d\n",
+			priv->panel->name, ret);
+		return ret;
+	}
+
+	ret = dsi_host_enable(priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "failed to enable mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int stm32_dsi_bind(struct udevice *dev)
+{
+	int ret;
+
+	ret = device_bind_driver_to_node(dev, "dw_mipi_dsi", "dsihost",
+					 dev_ofnode(dev), NULL);
+	if (ret)
+		return ret;
+
+	return dm_scan_fdt_dev(dev);
+}
+
+static int stm32_dsi_probe(struct udevice *dev)
+{
+	struct stm32_dsi_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	struct reset_ctl rst;
+	struct clk clk;
+	int ret;
+
+	device->dev = dev;
+
+	priv->base = (void *)dev_read_addr(dev);
+	if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "dsi dt register address error\n");
+		return -EINVAL;
+	}
+
+	if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		ret =  device_get_supply_regulator(dev, "phy-dsi-supply",
+						   &priv->vdd_reg);
+		if (ret && ret != -ENOENT) {
+			dev_err(dev, "Warning: cannot get phy dsi supply\n");
+			return -ENODEV;
+		}
+
+		if (ret != -ENOENT) {
+			ret = regulator_set_enable(priv->vdd_reg, true);
+			if (ret)
+				return ret;
+		}
+	}
+
+	ret = clk_get_by_name(device->dev, "pclk", &clk);
+	if (ret) {
+		dev_err(dev, "peripheral clock get error %d\n", ret);
+		goto err_reg;
+	}
+
+	ret = clk_enable(&clk);
+	if (ret) {
+		dev_err(dev, "peripheral clock enable error %d\n", ret);
+		goto err_reg;
+	}
+
+	ret = clk_get_by_name(dev, "ref", &clk);
+	if (ret) {
+		dev_err(dev, "pll reference clock get error %d\n", ret);
+		goto err_clk;
+	}
+
+	priv->pllref_clk = (unsigned int)clk_get_rate(&clk);
+
+	ret = reset_get_by_index(device->dev, 0, &rst);
+	if (ret) {
+		dev_err(dev, "missing dsi hardware reset\n");
+		goto err_clk;
+	}
+
+	/* Reset */
+	reset_deassert(&rst);
+
+	/* check hardware version */
+	priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION;
+	if (priv->hw_version != HWVER_130 &&
+	    priv->hw_version != HWVER_131) {
+		dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version);
+		dev_dbg(dev, "remove and unbind all DSI child\n");
+		device_chld_remove(dev, NULL, DM_REMOVE_NORMAL);
+		device_chld_unbind(dev, NULL);
+		ret = -ENODEV;
+		goto err_clk;
+	}
+
+	return 0;
+err_clk:
+	clk_disable(&clk);
+err_reg:
+	if (IS_ENABLED(CONFIG_DM_REGULATOR))
+		regulator_set_enable(priv->vdd_reg, false);
+
+	return ret;
+}
+
+struct video_bridge_ops stm32_dsi_ops = {
+	.attach = stm32_dsi_attach,
+	.set_backlight = stm32_dsi_set_backlight,
+};
+
+static const struct udevice_id stm32_dsi_ids[] = {
+	{ .compatible = "st,stm32-dsi"},
+	{ }
+};
+
+U_BOOT_DRIVER(stm32_dsi) = {
+	.name				= "stm32-display-dsi",
+	.id				= UCLASS_VIDEO_BRIDGE,
+	.of_match			= stm32_dsi_ids,
+	.bind				= stm32_dsi_bind,
+	.probe				= stm32_dsi_probe,
+	.ops				= &stm32_dsi_ops,
+	.priv_auto		= sizeof(struct stm32_dsi_priv),
+};
diff --git a/roms/u-boot/drivers/video/stm32/stm32_ltdc.c b/roms/u-boot/drivers/video/stm32/stm32_ltdc.c
new file mode 100644
index 000000000..f55a39498
--- /dev/null
+++ b/roms/u-boot/drivers/video/stm32/stm32_ltdc.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *	      Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ */
+
+#define LOG_CATEGORY UCLASS_VIDEO
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <log.h>
+#include <panel.h>
+#include <reset.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+
+struct stm32_ltdc_priv {
+	void __iomem *regs;
+	enum video_log2_bpp l2bpp;
+	u32 bg_col_argb;
+	u32 crop_x, crop_y, crop_w, crop_h;
+	u32 alpha;
+};
+
+/* LTDC main registers */
+#define LTDC_IDR	0x00	/* IDentification */
+#define LTDC_LCR	0x04	/* Layer Count */
+#define LTDC_SSCR	0x08	/* Synchronization Size Configuration */
+#define LTDC_BPCR	0x0C	/* Back Porch Configuration */
+#define LTDC_AWCR	0x10	/* Active Width Configuration */
+#define LTDC_TWCR	0x14	/* Total Width Configuration */
+#define LTDC_GCR	0x18	/* Global Control */
+#define LTDC_GC1R	0x1C	/* Global Configuration 1 */
+#define LTDC_GC2R	0x20	/* Global Configuration 2 */
+#define LTDC_SRCR	0x24	/* Shadow Reload Configuration */
+#define LTDC_GACR	0x28	/* GAmma Correction */
+#define LTDC_BCCR	0x2C	/* Background Color Configuration */
+#define LTDC_IER	0x34	/* Interrupt Enable */
+#define LTDC_ISR	0x38	/* Interrupt Status */
+#define LTDC_ICR	0x3C	/* Interrupt Clear */
+#define LTDC_LIPCR	0x40	/* Line Interrupt Position Conf. */
+#define LTDC_CPSR	0x44	/* Current Position Status */
+#define LTDC_CDSR	0x48	/* Current Display Status */
+
+/* LTDC layer 1 registers */
+#define LTDC_L1LC1R	0x80	/* L1 Layer Configuration 1 */
+#define LTDC_L1LC2R	0x84	/* L1 Layer Configuration 2 */
+#define LTDC_L1CR	0x84	/* L1 Control */
+#define LTDC_L1WHPCR	0x88	/* L1 Window Hor Position Config */
+#define LTDC_L1WVPCR	0x8C	/* L1 Window Vert Position Config */
+#define LTDC_L1CKCR	0x90	/* L1 Color Keying Configuration */
+#define LTDC_L1PFCR	0x94	/* L1 Pixel Format Configuration */
+#define LTDC_L1CACR	0x98	/* L1 Constant Alpha Config */
+#define LTDC_L1DCCR	0x9C	/* L1 Default Color Configuration */
+#define LTDC_L1BFCR	0xA0	/* L1 Blend Factors Configuration */
+#define LTDC_L1FBBCR	0xA4	/* L1 FrameBuffer Bus Control */
+#define LTDC_L1AFBCR	0xA8	/* L1 AuxFB Control */
+#define LTDC_L1CFBAR	0xAC	/* L1 Color FrameBuffer Address */
+#define LTDC_L1CFBLR	0xB0	/* L1 Color FrameBuffer Length */
+#define LTDC_L1CFBLNR	0xB4	/* L1 Color FrameBuffer Line Nb */
+#define LTDC_L1AFBAR	0xB8	/* L1 AuxFB Address */
+#define LTDC_L1AFBLR	0xBC	/* L1 AuxFB Length */
+#define LTDC_L1AFBLNR	0xC0	/* L1 AuxFB Line Number */
+#define LTDC_L1CLUTWR	0xC4	/* L1 CLUT Write */
+
+/* Bit definitions */
+#define SSCR_VSH	GENMASK(10, 0)	/* Vertical Synchronization Height */
+#define SSCR_HSW	GENMASK(27, 16)	/* Horizontal Synchronization Width */
+
+#define BPCR_AVBP	GENMASK(10, 0)	/* Accumulated Vertical Back Porch */
+#define BPCR_AHBP	GENMASK(27, 16)	/* Accumulated Horizontal Back Porch */
+
+#define AWCR_AAH	GENMASK(10, 0)	/* Accumulated Active Height */
+#define AWCR_AAW	GENMASK(27, 16)	/* Accumulated Active Width */
+
+#define TWCR_TOTALH	GENMASK(10, 0)	/* TOTAL Height */
+#define TWCR_TOTALW	GENMASK(27, 16)	/* TOTAL Width */
+
+#define GCR_LTDCEN	BIT(0)		/* LTDC ENable */
+#define GCR_DEN		BIT(16)		/* Dither ENable */
+#define GCR_PCPOL	BIT(28)		/* Pixel Clock POLarity-Inverted */
+#define GCR_DEPOL	BIT(29)		/* Data Enable POLarity-High */
+#define GCR_VSPOL	BIT(30)		/* Vertical Synchro POLarity-High */
+#define GCR_HSPOL	BIT(31)		/* Horizontal Synchro POLarity-High */
+
+#define GC1R_WBCH	GENMASK(3, 0)	/* Width of Blue CHannel output */
+#define GC1R_WGCH	GENMASK(7, 4)	/* Width of Green Channel output */
+#define GC1R_WRCH	GENMASK(11, 8)	/* Width of Red Channel output */
+#define GC1R_PBEN	BIT(12)		/* Precise Blending ENable */
+#define GC1R_DT		GENMASK(15, 14)	/* Dithering Technique */
+#define GC1R_GCT	GENMASK(19, 17)	/* Gamma Correction Technique */
+#define GC1R_SHREN	BIT(21)		/* SHadow Registers ENabled */
+#define GC1R_BCP	BIT(22)		/* Background Colour Programmable */
+#define GC1R_BBEN	BIT(23)		/* Background Blending ENabled */
+#define GC1R_LNIP	BIT(24)		/* Line Number IRQ Position */
+#define GC1R_TP		BIT(25)		/* Timing Programmable */
+#define GC1R_IPP	BIT(26)		/* IRQ Polarity Programmable */
+#define GC1R_SPP	BIT(27)		/* Sync Polarity Programmable */
+#define GC1R_DWP	BIT(28)		/* Dither Width Programmable */
+#define GC1R_STREN	BIT(29)		/* STatus Registers ENabled */
+#define GC1R_BMEN	BIT(31)		/* Blind Mode ENabled */
+
+#define GC2R_EDCA	BIT(0)		/* External Display Control Ability  */
+#define GC2R_STSAEN	BIT(1)		/* Slave Timing Sync Ability ENabled */
+#define GC2R_DVAEN	BIT(2)		/* Dual-View Ability ENabled */
+#define GC2R_DPAEN	BIT(3)		/* Dual-Port Ability ENabled */
+#define GC2R_BW		GENMASK(6, 4)	/* Bus Width (log2 of nb of bytes) */
+#define GC2R_EDCEN	BIT(7)		/* External Display Control ENabled */
+
+#define SRCR_IMR	BIT(0)		/* IMmediate Reload */
+#define SRCR_VBR	BIT(1)		/* Vertical Blanking Reload */
+
+#define LXCR_LEN	BIT(0)		/* Layer ENable */
+#define LXCR_COLKEN	BIT(1)		/* Color Keying Enable */
+#define LXCR_CLUTEN	BIT(4)		/* Color Look-Up Table ENable */
+
+#define LXWHPCR_WHSTPOS	GENMASK(11, 0)	/* Window Horizontal StarT POSition */
+#define LXWHPCR_WHSPPOS	GENMASK(27, 16)	/* Window Horizontal StoP POSition */
+
+#define LXWVPCR_WVSTPOS	GENMASK(10, 0)	/* Window Vertical StarT POSition */
+#define LXWVPCR_WVSPPOS	GENMASK(26, 16)	/* Window Vertical StoP POSition */
+
+#define LXPFCR_PF	GENMASK(2, 0)	/* Pixel Format */
+
+#define LXCACR_CONSTA	GENMASK(7, 0)	/* CONSTant Alpha */
+
+#define LXBFCR_BF2	GENMASK(2, 0)	/* Blending Factor 2 */
+#define LXBFCR_BF1	GENMASK(10, 8)	/* Blending Factor 1 */
+
+#define LXCFBLR_CFBLL	GENMASK(12, 0)	/* Color Frame Buffer Line Length */
+#define LXCFBLR_CFBP	GENMASK(28, 16)	/* Color Frame Buffer Pitch in bytes */
+
+#define LXCFBLNR_CFBLN	GENMASK(10, 0)	/* Color Frame Buffer Line Number */
+
+#define BF1_PAXCA	0x600		/* Pixel Alpha x Constant Alpha */
+#define BF1_CA		0x400		/* Constant Alpha */
+#define BF2_1PAXCA	0x007		/* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA		0x005		/* 1 - Constant Alpha */
+
+enum stm32_ltdc_pix_fmt {
+	PF_ARGB8888 = 0,
+	PF_RGB888,
+	PF_RGB565,
+	PF_ARGB1555,
+	PF_ARGB4444,
+	PF_L8,
+	PF_AL44,
+	PF_AL88
+};
+
+/* TODO add more color format support */
+static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
+{
+	enum stm32_ltdc_pix_fmt pf;
+
+	switch (l2bpp) {
+	case VIDEO_BPP16:
+		pf = PF_RGB565;
+		break;
+
+	case VIDEO_BPP32:
+		pf = PF_ARGB8888;
+		break;
+
+	case VIDEO_BPP8:
+		pf = PF_L8;
+		break;
+
+	case VIDEO_BPP1:
+	case VIDEO_BPP2:
+	case VIDEO_BPP4:
+	default:
+		log_warning("warning %dbpp not supported yet, %dbpp instead\n",
+			    VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+		pf = PF_RGB565;
+		break;
+	}
+
+	log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
+
+	return (u32)pf;
+}
+
+static bool has_alpha(u32 fmt)
+{
+	switch (fmt) {
+	case PF_ARGB8888:
+	case PF_ARGB1555:
+	case PF_ARGB4444:
+	case PF_AL44:
+	case PF_AL88:
+		return true;
+	case PF_RGB888:
+	case PF_RGB565:
+	case PF_L8:
+	default:
+		return false;
+	}
+}
+
+static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
+{
+	/* Reload configuration immediately & enable LTDC */
+	setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
+	setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
+}
+
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+				struct display_timing *timings)
+{
+	void __iomem *regs = priv->regs;
+	u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
+	u32 total_w, total_h;
+	u32 val;
+
+	/* Convert video timings to ltdc timings */
+	hsync = timings->hsync_len.typ - 1;
+	vsync = timings->vsync_len.typ - 1;
+	acc_hbp = hsync + timings->hback_porch.typ;
+	acc_vbp = vsync + timings->vback_porch.typ;
+	acc_act_w = acc_hbp + timings->hactive.typ;
+	acc_act_h = acc_vbp + timings->vactive.typ;
+	total_w = acc_act_w + timings->hfront_porch.typ;
+	total_h = acc_act_h + timings->vfront_porch.typ;
+
+	/* Synchronization sizes */
+	val = (hsync << 16) | vsync;
+	clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
+
+	/* Accumulated back porch */
+	val = (acc_hbp << 16) | acc_vbp;
+	clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
+
+	/* Accumulated active width */
+	val = (acc_act_w << 16) | acc_act_h;
+	clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
+
+	/* Total width & height */
+	val = (total_w << 16) | total_h;
+	clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+
+	setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
+	/* Signal polarities */
+	val = 0;
+	log_debug("timing->flags 0x%08x\n", timings->flags);
+	if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+		val |= GCR_HSPOL;
+	if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+		val |= GCR_VSPOL;
+	if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
+		val |= GCR_DEPOL;
+	if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+		val |= GCR_PCPOL;
+	clrsetbits_le32(regs + LTDC_GCR,
+			GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
+
+	/* Overall background color */
+	writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
+}
+
+static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
+{
+	void __iomem *regs = priv->regs;
+	u32 x0, x1, y0, y1;
+	u32 pitch_in_bytes;
+	u32 line_length;
+	u32 bus_width;
+	u32 val, tmp, bpp;
+	u32 format;
+
+	x0 = priv->crop_x;
+	x1 = priv->crop_x + priv->crop_w - 1;
+	y0 = priv->crop_y;
+	y1 = priv->crop_y + priv->crop_h - 1;
+
+	/* Horizontal start and stop position */
+	tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
+	val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
+	clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
+			val);
+
+	/* Vertical start & stop position */
+	tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
+	val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
+	clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
+			val);
+
+	/* Layer background color */
+	writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
+
+	/* Color frame buffer pitch in bytes & line length */
+	bpp = VNBITS(priv->l2bpp);
+	pitch_in_bytes = priv->crop_w * (bpp >> 3);
+	bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
+	line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
+	val = (pitch_in_bytes << 16) | line_length;
+	clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
+
+	/* Pixel format */
+	format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+	clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
+
+	/* Constant alpha value */
+	clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
+
+	/* Specifies the blending factors : with or without pixel alpha */
+	/* Manage hw-specific capabilities */
+	val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
+	/* Blending factors */
+	clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
+
+	/* Frame buffer line number */
+	clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
+
+	/* Frame buffer address */
+	writel(fb_addr, regs + LTDC_L1CFBAR);
+
+	/* Enable layer 1 */
+	setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
+}
+
+static int stm32_ltdc_probe(struct udevice *dev)
+{
+	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct stm32_ltdc_priv *priv = dev_get_priv(dev);
+	struct udevice *bridge = NULL;
+	struct udevice *panel = NULL;
+	struct display_timing timings;
+	struct clk pclk;
+	struct reset_ctl rst;
+	int ret;
+
+	priv->regs = (void *)dev_read_addr(dev);
+	if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
+		dev_err(dev, "ltdc dt register address error\n");
+		return -EINVAL;
+	}
+
+	ret = clk_get_by_index(dev, 0, &pclk);
+	if (ret) {
+		dev_err(dev, "peripheral clock get error %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(&pclk);
+	if (ret) {
+		dev_err(dev, "peripheral clock enable error %d\n", ret);
+		return ret;
+	}
+
+	ret = uclass_first_device_err(UCLASS_PANEL, &panel);
+	if (ret) {
+		if (ret != -ENODEV)
+			dev_err(dev, "panel device error %d\n", ret);
+		return ret;
+	}
+
+	ret = panel_get_display_timing(panel, &timings);
+	if (ret) {
+		ret = ofnode_decode_display_timing(dev_ofnode(panel),
+						   0, &timings);
+		if (ret) {
+			dev_err(dev, "decode display timing error %d\n", ret);
+			return ret;
+		}
+	}
+
+	ret = clk_set_rate(&pclk, timings.pixelclock.typ);
+	if (ret)
+		dev_warn(dev, "fail to set pixel clock %d hz\n",
+			 timings.pixelclock.typ);
+
+	dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
+		timings.pixelclock.typ, clk_get_rate(&pclk));
+
+	ret = reset_get_by_index(dev, 0, &rst);
+	if (ret) {
+		dev_err(dev, "missing ltdc hardware reset\n");
+		return ret;
+	}
+
+	/* Reset */
+	reset_deassert(&rst);
+
+	if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
+		ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
+		if (ret)
+			dev_dbg(dev,
+				"No video bridge, or no backlight on bridge\n");
+
+		if (bridge) {
+			ret = video_bridge_attach(bridge);
+			if (ret) {
+				dev_err(bridge, "fail to attach bridge\n");
+				return ret;
+			}
+		}
+	}
+
+	/* TODO Below parameters are hard-coded for the moment... */
+	priv->l2bpp = VIDEO_BPP16;
+	priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
+	priv->crop_x = 0;
+	priv->crop_y = 0;
+	priv->crop_w = timings.hactive.typ;
+	priv->crop_h = timings.vactive.typ;
+	priv->alpha = 0xFF;
+
+	dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
+		timings.hactive.typ, timings.vactive.typ,
+		VNBITS(priv->l2bpp), uc_plat->base);
+	dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
+		priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
+		priv->bg_col_argb, priv->alpha);
+
+	/* Configure & start LTDC */
+	stm32_ltdc_set_mode(priv, &timings);
+	stm32_ltdc_set_layer1(priv, uc_plat->base);
+	stm32_ltdc_enable(priv);
+
+	uc_priv->xsize = timings.hactive.typ;
+	uc_priv->ysize = timings.vactive.typ;
+	uc_priv->bpix = priv->l2bpp;
+
+	if (!bridge) {
+		ret = panel_enable_backlight(panel);
+		if (ret) {
+			dev_err(dev, "panel %s enable backlight error %d\n",
+				panel->name, ret);
+			return ret;
+		}
+	} else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
+		ret = video_bridge_set_backlight(bridge, 80);
+		if (ret) {
+			dev_err(dev, "fail to set backlight\n");
+			return ret;
+		}
+	}
+
+	video_set_flush_dcache(dev, true);
+
+	return 0;
+}
+
+static int stm32_ltdc_bind(struct udevice *dev)
+{
+	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+	uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
+			CONFIG_VIDEO_STM32_MAX_YRES *
+			(CONFIG_VIDEO_STM32_MAX_BPP >> 3);
+	dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size);
+
+	return 0;
+}
+
+static const struct udevice_id stm32_ltdc_ids[] = {
+	{ .compatible = "st,stm32-ltdc" },
+	{ }
+};
+
+U_BOOT_DRIVER(stm32_ltdc) = {
+	.name			= "stm32_display",
+	.id			= UCLASS_VIDEO,
+	.of_match		= stm32_ltdc_ids,
+	.probe			= stm32_ltdc_probe,
+	.bind			= stm32_ltdc_bind,
+	.priv_auto	= sizeof(struct stm32_ltdc_priv),
+};