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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/include/configs/aspenite.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/include/configs/aspenite.h')
-rw-r--r-- | roms/u-boot/include/configs/aspenite.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/roms/u-boot/include/configs/aspenite.h b/roms/u-boot/include/configs/aspenite.h new file mode 100644 index 000000000..88e1bf177 --- /dev/null +++ b/roms/u-boot/include/configs/aspenite.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * Contributor: Mahavir Jain <mjain@marvell.com> + */ + +#ifndef __CONFIG_ASPENITE_H +#define __CONFIG_ASPENITE_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ +#define CONFIG_ARMADA100 1 /* SOC Family Name */ +#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * There is no internal RAM in ARMADA100, using DRAM + * TBD: dcache to be used for this + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) + +#include "mv-common.h" + +/* + * Environment variables configurations + */ + +#endif /* __CONFIG_ASPENITE_H */ |