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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/include/configs/imx6_spl.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/include/configs/imx6_spl.h')
-rw-r--r-- | roms/u-boot/include/configs/imx6_spl.h | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/roms/u-boot/include/configs/imx6_spl.h b/roms/u-boot/include/configs/imx6_spl.h new file mode 100644 index 000000000..ede81cca1 --- /dev/null +++ b/roms/u-boot/include/configs/imx6_spl.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey <tharvey@gateworks.com> + */ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#ifdef CONFIG_MX6_OCRAM_256KB +/* + * see Figure 8.4.1 in IMX6DQ Reference manuals: + * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF + * - BOOT ROM stack is at 0x0093FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to + * fit between 0x00907000 and 0x00938000. + * - Additionally the BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 + * or 192KB + */ +#define CONFIG_SPL_MAX_SIZE 0x30000 +#define CONFIG_SPL_STACK 0x0093FFB8 +/* + * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x31000 +#else +/* + * see Figure 8-3 in IMX6SDL Reference manuals: + * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF + * - BOOT ROM stack is at 0x0091FFB8 + * - if icache/dcache is enabled (eFuse/strapping controlled) then the + * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + * fit between 0x00907000 and 0x00918000. + * - Additionally the BOOT ROM loads what they consider the firmware image + * which consists of a 4K header in front of us that contains the IVT, DCD + * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + * or 64KB + */ +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_STACK 0x0091FFB8 +/* + * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x11000 + +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT) +#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT) +#define CONFIG_SPL_SATA_BOOT_DEVICE 0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) +# ifdef CONFIG_OF_CONTROL +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +# else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# endif +#endif + +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ + defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) +#define CONFIG_SPL_BSS_START_ADDR 0x88200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#else +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#endif +#endif + +#endif |