Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

8 files changed, 1178 insertions, 0 deletions

diff --git a/roms/u-boot/include/configs/km/keymile-common.h b/roms/u-boot/include/configs/km/keymile-common.h
new file mode 100644
index 000000000..d321ebdb6
--- /dev/null
+++ b/roms/u-boot/include/configs/km/keymile-common.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_KEYMILE_H
+#define __CONFIG_KEYMILE_H
+
+#include <linux/stringify.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_HUSH_INIT_VAR
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
+#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
+	"actual_bank=0\0"
+#endif
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+
+#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		""
+#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
+/* one flash chip only called boot */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
+#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+/* two flash chips called boot and app */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+/* app:  CONFIG_KM_UBI_PARTITION_NAME_APP */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS " "				\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=if test ${boot_bank} -eq 0; then; "			\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; "	\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+
+#ifdef CONFIG_NAND_ECC_BCH
+#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0"
+#define CONFIG_KM_ECC_MODE    " eccmode=bch"
+#else
+#define CONFIG_KM_UIMAGE_NAME "uImage\0"
+#define CONFIG_KM_ECC_MODE
+#endif
+
+/*
+ * boottargets
+ * - set 'subbootcmds'
+ * - set 'bootcmd' and 'altbootcmd'
+ * available targets:
+ * - 'release': for a standalone system		kernel/rootfs from flash
+ */
+#define CONFIG_KM_DEF_ENV_BOOTTARGETS					\
+	"subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt "		\
+		"set_fdthigh cramfsloadkernel flashargs add_default "	\
+		"addpanic boot\0"					\
+	"develop="							\
+		"tftp ${load_addr_r} scripts/develop-${arch}.txt && "	\
+		"env import -t ${load_addr_r} ${filesize} && "		\
+		"run setup_debug_env\0"					\
+	"ramfs="							\
+		"tftp ${load_addr_r} scripts/ramfs-${arch}.txt && "	\
+		"env import -t ${load_addr_r} ${filesize} && "		\
+		"run setup_debug_env\0"					\
+	""
+
+/*
+ * bootargs
+ * - modify 'bootargs'
+ *
+ * - 'add_default': default bootargs common for all arm/ppc boards
+ * - 'addpanic': add kernel panic options
+ * - 'flashargs': defaults arguments for flash base boot
+ *
+ */
+#define CONFIG_KM_DEF_ENV_BOOTARGS					\
+	"add_default="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off:"				\
+		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
+		" mem=${kernelmem} init=${init}"			\
+		CONFIG_KM_ECC_MODE					\
+		" phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
+		" " CONFIG_KM_UBI_LINUX_MTD " "				\
+		CONFIG_KM_DEF_BOOT_ARGS_CPU				\
+		"\0"							\
+	"addpanic="							\
+		"setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0"	\
+	"flashargs="							\
+		"setenv bootargs "					\
+		"root=mtdblock:rootfs${boot_bank} "			\
+		"rootfstype=squashfs ro\0"				\
+	""
+
+/*
+ * flash_boot
+ * - commands for booting from flash
+ *
+ * - 'cramfsloadkernel': copy kernel from a cramfs to ram
+ * - 'ubiattach': attach ubi partition
+ * - 'ubicopy': copy ubi volume to ram
+ *              - volume names: bootfs0, bootfs1, bootfs2, ...
+ *
+ * processor specific settings
+ * - 'cramfsloadfdt': copy fdt from a cramfs to ram
+ */
+#define CONFIG_KM_DEF_ENV_FLASH_BOOT					\
+	"cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0"		\
+	"cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0"	\
+	"ubicopy=ubi read ${cramfsaddr} bootfs${boot_bank}\0"		\
+	"uimage=" CONFIG_KM_UIMAGE_NAME					\
+	CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
+
+/*
+ * constants
+ * - KM specific constants and commands
+ *
+ * - 'default': setup default environment
+ */
+#define CONFIG_KM_DEF_ENV_CONSTANTS					\
+	"backup_bank=0\0"						\
+	"release=run newenv; reset\0"					\
+	"pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0"		\
+	"testbootcmd=setenv boot_bank ${test_bank}; "			\
+		"run ${subbootcmds}; reset\0"				\
+	"env_version=1\0"						\
+	""
+
+#ifndef CONFIG_KM_DEF_ENV
+#define CONFIG_KM_DEF_ENV	\
+	CONFIG_KM_DEF_ENV_BOOTPARAMS					\
+	"netdev=" __stringify(CONFIG_KM_DEF_NETDEV) "\0"		\
+	CONFIG_KM_DEF_ENV_CPU						\
+	CONFIG_KM_DEF_ENV_BOOTTARGETS					\
+	CONFIG_KM_DEF_ENV_BOOTARGS					\
+	CONFIG_KM_DEF_ENV_FLASH_BOOT					\
+	CONFIG_KM_DEF_ENV_CONSTANTS					\
+	"altbootcmd=run bootcmd\0"					\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"bootcmd=km_checkbidhwk &&  "					\
+		"setenv bootcmd \'if km_checktestboot; then; "          \
+				"setenv boot_bank ${test_bank}; else; " \
+				"setenv boot_bank ${actual_bank}; fi;"  \
+			"run ${subbootcmds}; reset\' && "		\
+		"setenv altbootcmd \'setenv boot_bank ${backup_bank}; "	\
+			"run ${subbootcmds}; reset\' && "		\
+		"saveenv && saveenv && boot\0"				\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"init=/sbin/init-overlay.sh\0"					\
+	"load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0"		\
+	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
+	""
+#endif /* CONFIG_KM_DEF_ENV */
+
+#endif /* __CONFIG_KEYMILE_H */
diff --git a/roms/u-boot/include/configs/km/km-mpc8309.h b/roms/u-boot/include/configs/km/km-mpc8309.h
new file mode 100644
index 000000000..e710c0449
--- /dev/null
+++ b/roms/u-boot/include/configs/km/km-mpc8309.h
@@ -0,0 +1,137 @@
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/* QE microcode/firmware address */
+/* between the u-boot partition and env */
+#ifndef CONFIG_SYS_QE_FW_ADDR
+#define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
+#endif
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#ifndef CONFIG_SYS_SICRL
+#define CONFIG_SYS_SICRL (0			\
+		| SICR_1_UART1_UART1RTS		\
+		| SICR_1_I2C_CKSTOP		\
+		| SICR_1_IRQ_A_IRQ		\
+		| SICR_1_IRQ_B_IRQ		\
+		| SICR_1_GPIO_A_GPIO		\
+		| SICR_1_GPIO_B_GPIO		\
+		| SICR_1_GPIO_C_GPIO		\
+		| SICR_1_GPIO_D_GPIO		\
+		| SICR_1_GPIO_E_GPIO		\
+		| SICR_1_GPIO_F_GPIO		\
+		| SICR_1_USB_A_UART2S		\
+		| SICR_1_USB_B_UART2RTS		\
+		| SICR_1_FEC1_FEC1		\
+		| SICR_1_FEC2_FEC2		\
+		)
+#endif
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH (0			\
+		| SICR_2_FEC3_FEC3		\
+		| SICR_2_HDLC1_A_HDLC1		\
+		| SICR_2_ELBC_A_LA		\
+		| SICR_2_ELBC_B_LCLK		\
+		| SICR_2_HDLC2_A_HDLC2		\
+		| SICR_2_USB_D_GPIO		\
+		| SICR_2_PCI_PCI		\
+		| SICR_2_HDLC1_B_HDLC1		\
+		| SICR_2_HDLC1_C_HDLC1		\
+		| SICR_2_HDLC2_B_GPIO		\
+		| SICR_2_HDLC2_C_HDLC2		\
+		| SICR_2_QUIESCE_B		\
+		)
+
+/* GPR_1 */
+#define CONFIG_SYS_GPR1  0x50008060
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_PZ_MAXZ | \
+	DDRCDR_NZ_MAXZ | \
+	DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_RD_NEVER | \
+					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* ethernet port connected to piggy (UEC2) */
+#define CONFIG_HAS_ETH1
+#define CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
diff --git a/roms/u-boot/include/configs/km/km-mpc832x.h b/roms/u-boot/include/configs/km/km-mpc832x.h
new file mode 100644
index 000000000..22dfb5da6
--- /dev/null
+++ b/roms/u-boot/include/configs/km/km-mpc832x.h
@@ -0,0 +1,76 @@
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_PZ_MAXZ | \
+	DDRCDR_NZ_MAXZ | \
+	DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_WR_CFG | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
diff --git a/roms/u-boot/include/configs/km/km-mpc8360.h b/roms/u-boot/include/configs/km/km-mpc8360.h
new file mode 100644
index 000000000..798b12696
--- /dev/null
+++ b/roms/u-boot/include/configs/km/km-mpc8360.h
@@ -0,0 +1,76 @@
+/* KMBEC FPGA (PRIO) */
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	64
+
+/*
+ * High Level Configuration Options
+ */
+
+/*
+ * System IO Setup
+ */
+#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
+
+/**
+ * DDR RAM settings
+ */
+#define CONFIG_SYS_DDR_SDRAM_CFG (\
+	SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+	SDRAM_CFG_SREN | \
+	SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+
+#define CONFIG_SYS_DDR_CLK_CNTL (\
+	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_DDR_INTERVAL (\
+	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_BNDS			0x0000007f
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDR_MODE		0x47860452
+#define CONFIG_SYS_DDR_MODE2		0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 (\
+	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+	(0 << TIMING_CFG0_WWT_SHIFT) | \
+	(0 << TIMING_CFG0_RRT_SHIFT) | \
+	(0 << TIMING_CFG0_WRT_SHIFT) | \
+	(0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 (\
+	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+	(5 << TIMING_CFG2_CPO_SHIFT) | \
+	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3			0x00000000
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_PAXE_BASE		0xA0000000
+#define CONFIG_SYS_PAXE_SIZE		256
diff --git a/roms/u-boot/include/configs/km/km-mpc83xx.h b/roms/u-boot/include/configs/km/km-mpc83xx.h
new file mode 100644
index 000000000..7aacd37c8
--- /dev/null
+++ b/roms/u-boot/include/configs/km/km-mpc83xx.h
@@ -0,0 +1,130 @@
+/*
+ * Internal Definitions
+ */
+#include <linux/stringify.h>
+#define BOOTFLASH_START	0xF0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE		2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Size  Device
+ * ---- ---     ------- ------  -----  ------
+ *  0   Local   GPCM    16 bit  256MB FLASH
+ *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
+ *
+ */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES	4
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	200000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+		{1, {I2C_NULL_HOP} } }
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+/* Address and size of Redundant Environment Sector	*/
+#endif /* CFG_SYS_RAMBOOT */
+
+/*
+ * Environment Configuration
+ */
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_KM_DEF_ENV						 \
+	CONFIG_KM_DEF_ARCH						 \
+	"newenv="							 \
+		"prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \
+		"era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0"	 \
+	"unlock=yes\0"							 \
+	""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
diff --git a/roms/u-boot/include/configs/km/km-powerpc.h b/roms/u-boot/include/configs/km/km-powerpc.h
new file mode 100644
index 000000000..3be926c10
--- /dev/null
+++ b/roms/u-boot/include/configs/km/km-powerpc.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_KEYMILE_POWERPC_H
+#define __CONFIG_KEYMILE_POWERPC_H
+
+/* Do boardspecific init for all boards */
+
+/* EEprom support 24C08, 24C16, 24C64 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3  /* 8 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Increase max size of compressed kernel */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000     /* 32 MB */
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"u-boot="CONFIG_HOSTNAME "/u-boot.bin\0"		\
+	"update="							\
+		"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
+		"erase " __stringify(BOOTFLASH_START) "  +${filesize} && "\
+		"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START)	\
+		"  ${filesize} && "					\
+		"protect on " __stringify(BOOTFLASH_START) "  +${filesize}\0"\
+	"set_fdthigh=true\0"						\
+	"checkfdt=true\0"						\
+	"bootm_mapsize=" __stringify(CONFIG_SYS_BOOTM_LEN) "\0"		\
+	""
+
+#endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/roms/u-boot/include/configs/km/km_arm.h b/roms/u-boot/include/configs/km/km_arm.h
new file mode 100644
index 000000000..4115906c5
--- /dev/null
+++ b/roms/u-boot/include/configs/km/km_arm.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_KM_ARM_H
+#define _CONFIG_KM_ARM_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD
+
+#define CONFIG_NAND_ECC_BCH
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Increase max size of compressed kernel */
+#define CONFIG_SYS_BOOTM_LEN		(32 << 20)
+
+#include "asm/arch/config.h"
+
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
+		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
+		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.kwb\0"		\
+	CONFIG_KM_UPDATE_UBOOT						\
+	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
+	"checkfdt="							\
+		"if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; "	\
+		"then true; else setenv cramfsloadfdt true; "		\
+		"setenv boot bootm ${load_addr_r}; "			\
+		"echo No FDT found, booting with the kernel "		\
+		"appended one; fi\0"					\
+	""
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/*
+ * Other required minimal configurations
+ */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer autoneg timeout */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+
+/*
+ * I2C related stuff
+ */
+#undef CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
+#define CONFIG_SYS_NUM_I2C_BUSES	6
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+				}
+
+#ifndef __ASSEMBLY__
+#include <asm/arch/gpio.h>
+#include <linux/delay.h>
+#include <linux/stringify.h>
+extern void __set_direction(unsigned pin, int high);
+#define KM_KIRKWOOD_SDA_PIN	8
+#define KM_KIRKWOOD_SCL_PIN	9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
+#define KM_KIRKWOOD_ENV_WP	38
+
+#define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
+#define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
+#define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
+#define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
+#endif
+
+#define I2C_DELAY	udelay(1)
+#define I2C_SOFT_DECLARATIONS
+
+#define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
+#define	CONFIG_SYS_I2C_SOFT_SPEED	100000
+
+/* EEprom support 24C128, 24C256 valid for environment eeprom */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6 /* 64 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/*
+ *  Environment variables configurations
+ */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
+#else
+#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_EEPROM_WREN
+#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
+#endif
+
+#define KM_FLASH_GPIO_PIN	16
+
+#define	CONFIG_KM_UPDATE_UBOOT						\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"
+
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=setenv addr 0x100000 && "				\
+		"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; "  \
+		"mw.b ${addr} 0 4 && "					\
+		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && "	\
+		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+#ifndef CONFIG_KM_BOARD_EXTRA_ENV
+#define CONFIG_KM_BOARD_EXTRA_ENV       ""
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_BOARD_EXTRA_ENV					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_NEW_ENV						\
+	"arch=arm\0"							\
+	""
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* address for the bootcount (taken from end of RAM) */
+#define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
+
+/* enable POST tests */
+#define CONFIG_POST	(CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_SKIP_ENV_FLAGS
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+
+#endif /* _CONFIG_KM_ARM_H */
diff --git a/roms/u-boot/include/configs/km/pg-wcom-ls102xa.h b/roms/u-boot/include/configs/km/pg-wcom-ls102xa.h
new file mode 100644
index 000000000..eb480a34a
--- /dev/null
+++ b/roms/u-boot/include/configs/km/pg-wcom-ls102xa.h
@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Hitachi Power Grids. All rights reserved.
+ */
+
+#ifndef __CONFIG_PG_WCOM_LS102XA_H
+#define __CONFIG_PG_WCOM_LS102XA_H
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+
+#define CONFIG_PRAM			((CONFIG_KM_PNVRAM + \
+					  CONFIG_KM_PHRAM + \
+					  CONFIG_KM_RESERVED_PRAM) >> 10)
+
+#define CONFIG_SYS_CLK_FREQ		66666666
+/*
+ * Take into account default implementation where DDR_FDBK_MULTI is consider as
+ * configured for DDR_PLL = 2*MEM_PLL_RAT.
+ * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT.
+ */
+#define CONFIG_DDR_CLK_FREQ		(100000000 >> 1)
+
+#define PHYS_SDRAM			0x80000000
+#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x54
+
+/* POST memory regions test */
+#define CONFIG_POST			(CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash Definitions */
+#define CONFIG_FSL_IFC
+#define CONFIG_SYS_FLASH_BASE		0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_TE | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(64 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_AVD_TGL_PGM_EN | \
+					CSOR_NOR_ADM_SHIFT(0x4) | \
+					CSOR_NOR_NOR_MODE_ASYNC_NOR | \
+					CSOR_NOR_TRHZ_20 | \
+					CSOR_NOR_BCTLD)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
+					FTIM0_NOR_TEADC(0x7) | \
+					FTIM0_NOR_TAVDS(0x0) | \
+					FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1) | \
+					FTIM1_NOR_TRAD_NOR(0x21) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x21))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
+					FTIM2_NOR_TCH(0x1) | \
+					FTIM2_NOR_TWPH(0x6) | \
+					FTIM2_NOR_TWP(0xb))
+#define CONFIG_SYS_NOR_FTIM3		0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* NAND Flash Definitions */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0x68000000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+				CSPR_PORT_SIZE_8 | \
+				CSPR_TE | \
+				CSPR_MSEL_NAND | \
+				CSPR_V)
+#define CONFIG_SYS_NAND_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN \
+					| CSOR_NAND_ECC_DEC_EN \
+					| CSOR_NAND_ECC_MODE_4 \
+					| CSOR_NAND_RAL_3 \
+					| CSOR_NAND_PGS_2K \
+					| CSOR_NAND_SPRZ_64 \
+					| CSOR_NAND_PB(64) \
+					| CSOR_NAND_TRHZ_40 \
+					| CSOR_NAND_BCTLD)
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x3) | \
+					FTIM0_NAND_TWP(0x8) | \
+					FTIM0_NAND_TWCHT(0x3) | \
+					FTIM0_NAND_TWH(0x5))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1e) | \
+					FTIM1_NAND_TWBE(0x1e) | \
+					FTIM1_NAND_TRR(0x6) | \
+					FTIM1_NAND_TRP(0x8))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x9) | \
+					FTIM2_NAND_TREH(0x5) | \
+					FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3		(FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* QRIO FPGA Definitions */
+#define CONFIG_SYS_QRIO_BASE		0x70000000
+#define CONFIG_SYS_QRIO_BASE_PHYS	CONFIG_SYS_QRIO_BASE
+
+#define CONFIG_SYS_CSPR2_EXT		(0x00)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_TE | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_AMASK2		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR2		(CSOR_GPCM_ADM_SHIFT(0x4) | \
+					CSOR_GPCM_TRHZ_20 | \
+					CSOR_GPCM_BCTLD)
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x2) | \
+					FTIM0_GPCM_TEADC(0x8) | \
+					FTIM0_GPCM_TEAHC(0x2))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x2) | \
+					FTIM1_GPCM_TRAD(0x6))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x1) | \
+					FTIM2_GPCM_TCH(0x1) | \
+					FTIM2_GPCM_TWP(0x7))
+#define CONFIG_SYS_CS2_FTIM3		0x04000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define I2C_MUX_PCA_ADDR		0x70
+#define I2C_MUX_CH_DEFAULT		0x0
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+					{1, {I2C_NULL_HOP}                 }, \
+				}
+
+/*
+ * eTSEC
+ */
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME			"ethernet@2d90000"
+#endif
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR		0x01ee0200
+#define COUNTER_FREQUENCY		8333333
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		256
+#define CONFIG_FSL_DEVICE_DISABLE
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		0x100000     /* 1Mbyte */
+#define CONFIG_SYS_QE_FW_ADDR		0x60020000
+
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_TOTAL_SIZE		0x40000
+#define ENV_DEL_ADDR		CONFIG_ENV_ADDR_REDUND  /* direct for newenv */
+
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV
+#endif
+
+#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+#endif
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"			\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize} && "					\
+		"erase " __stringify(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize} && "					\
+		"cp.b ${load_addr_r} "					\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && "	\
+		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize}\0"					\
+	"update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+		" +${filesize} && "					\
+		"erase " __stringify(CONFIG_SYS_FLASH_BASE)		\
+		" +${filesize} && "					\
+		"cp.b ${load_addr_r} "					\
+		__stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && "	\
+		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0"		\
+	"set_fdthigh=true\0"			\
+	"checkfdt=true\0"						\
+	""
+
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=protect off " __stringify(ENV_DEL_ADDR)			\
+		" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "		\
+		"erase " __stringify(ENV_DEL_ADDR)			\
+		" +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && "		\
+		"protect on " __stringify(ENV_DEL_ADDR)			\
+		" +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
+
+#define CONFIG_HW_ENV_SETTINGS						\
+	"hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,"	\
+			"can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,"	\
+			"asrc,spdif,lpuart1,ftm1\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_NEW_ENV						\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_HW_ENV_SETTINGS						\
+	"EEprom_ivm=pca9547:70:9\0"					\
+	"ethrotate=no\0"						\
+	""
+
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Increase map for Linux */
+
+#endif