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authorAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
committerAngelos Mouzakitis <a.mouzakitis@virtualopensystems.com>2023-10-10 14:33:42 +0000
commitaf1a266670d040d2f4083ff309d732d648afba2a (patch)
tree2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h
parente02cda008591317b1625707ff8e115a4841aa889 (diff)
Add submodule dependency filesHEADmaster
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h')
-rw-r--r--roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h52
1 files changed, 52 insertions, 0 deletions
diff --git a/roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h b/roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h
new file mode 100644
index 000000000..836244358
--- /dev/null
+++ b/roms/u-boot/include/dt-bindings/clock/imxrt1020-clock.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
+#define __DT_BINDINGS_CLOCK_IMXRT1020_H
+
+#define IMXRT1020_CLK_DUMMY 0
+#define IMXRT1020_CLK_CKIL 1
+#define IMXRT1020_CLK_CKIH 2
+#define IMXRT1020_CLK_OSC 3
+#define IMXRT1020_CLK_PLL2_PFD0_352M 4
+#define IMXRT1020_CLK_PLL2_PFD1_594M 5
+#define IMXRT1020_CLK_PLL2_PFD2_396M 6
+#define IMXRT1020_CLK_PLL2_PFD3_297M 7
+#define IMXRT1020_CLK_PLL3_PFD0_720M 8
+#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9
+#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10
+#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11
+#define IMXRT1020_CLK_PLL2_198M 12
+#define IMXRT1020_CLK_PLL3_120M 13
+#define IMXRT1020_CLK_PLL3_80M 14
+#define IMXRT1020_CLK_PLL3_60M 15
+#define IMXRT1020_CLK_PLL2_BYPASS 16
+#define IMXRT1020_CLK_PLL3_BYPASS 17
+#define IMXRT1020_CLK_PLL6_BYPASS 18
+#define IMXRT1020_CLK_PRE_PERIPH_SEL 19
+#define IMXRT1020_CLK_PERIPH_SEL 20
+#define IMXRT1020_CLK_SEMC_ALT_SEL 21
+#define IMXRT1020_CLK_SEMC_SEL 22
+#define IMXRT1020_CLK_USDHC1_SEL 23
+#define IMXRT1020_CLK_USDHC2_SEL 24
+#define IMXRT1020_CLK_LPUART_SEL 25
+#define IMXRT1020_CLK_ARM_PODF 26
+#define IMXRT1020_CLK_LPUART_PODF 27
+#define IMXRT1020_CLK_USDHC1_PODF 28
+#define IMXRT1020_CLK_USDHC2_PODF 29
+#define IMXRT1020_CLK_SEMC_PODF 30
+#define IMXRT1020_CLK_AHB_PODF 31
+#define IMXRT1020_CLK_USDHC1 32
+#define IMXRT1020_CLK_USDHC2 33
+#define IMXRT1020_CLK_LPUART1 34
+#define IMXRT1020_CLK_SEMC 35
+#define IMXRT1020_CLK_PLL2_SYS 36
+#define IMXRT1020_CLK_PLL3_USB_OTG 37
+#define IMXRT1020_CLK_PLL4_AUDIO 38
+#define IMXRT1020_CLK_PLL6_ENET 39
+#define IMXRT1020_CLK_END 40
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */