Add submodule dependency filesHEADmaster

Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec

42 files changed, 4716 insertions, 0 deletions

diff --git a/roms/u-boot/include/power/acpi_pmc.h b/roms/u-boot/include/power/acpi_pmc.h
new file mode 100644
index 000000000..64176d79b
--- /dev/null
+++ b/roms/u-boot/include/power/acpi_pmc.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ACPI_PMC_H
+#define __ACPI_PMC_H
+
+#ifndef __ASSEMBLY__
+
+enum {
+	GPE0_REG_MAX	= 4,
+};
+
+enum {
+	PM1_STS		= 0x00,
+	PM1_EN		= 0x02,
+	PM1_CNT		= 0x04,
+	PM1_TMR		= 0x08,
+
+	GPE0_STS	= 0x20,
+	GPE0_EN		= 0x30,
+};
+
+/**
+ * struct acpi_pmc_upriv - holds common data for the x86 PMC
+ *
+ * @pmc_bar0: Base address 0 of PMC
+ * @pmc_bar1: Base address 2 of PMC
+ * @acpi_base: Base address of ACPI block
+ * @pm1_sts: PM1 status
+ * @pm1_en: PM1 enable
+ * @pm1_cnt: PM1 control
+ * @gpe_cfg: Address of GPE_CFG register
+ * @gpe0_dwx_mask: Mask to use for each GPE0 (typically 7 or 0xf)
+ * @gpe0_dwx_shift_base: Base shift value to use for GPE0 (0 or 4)
+ * @gpe0_sts_req: GPE0 status register offset
+ * @gpe0_en_req: GPE0 enable register offset
+ * @gpe0_sts: GPE0 status values
+ * @gpe0_en: GPE0 enable values
+ * @gpe0_dw: GPE0 DW values
+ * @gpe0_count: Number of GPE0 registers
+ * @tco1_sts: TCO1 status
+ * @tco2_sts: TCO2 status
+ * @prsts: Power and reset status
+ * @gen_pmcon1: General power mgmt configuration 1
+ * @gen_pmcon2: General power mgmt configuration 2
+ * @gen_pmcon3: General power mgmt configuration 3
+ */
+struct acpi_pmc_upriv {
+	void *pmc_bar0;
+	void *pmc_bar2;
+	u32 acpi_base;
+	u16 pm1_sts;
+	u16 pm1_en;
+	u32 pm1_cnt;
+	u32 *gpe_cfg;
+	u32 gpe0_dwx_mask;
+	u32 gpe0_dwx_shift_base;
+	u32 gpe0_sts_reg;
+	u32 gpe0_en_reg;
+	u32 gpe0_sts[GPE0_REG_MAX];
+	u32 gpe0_en[GPE0_REG_MAX];
+	u32 gpe0_dw[GPE0_REG_MAX];
+	int gpe0_count;
+	u16 tco1_sts;
+	u16 tco2_sts;
+	u32 prsts;
+	u32 gen_pmcon1;
+	u32 gen_pmcon2;
+	u32 gen_pmcon3;
+};
+
+struct acpi_pmc_ops {
+	/**
+	 * init() - Set up the PMC for use
+	 *
+	 * This reads the current state of the PMC. Most of the state is read
+	 * automatically by the uclass since it is common.
+	 *
+	 * This is optional.
+	 *
+	 * @dev: PMC device to use
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*init)(struct udevice *dev);
+
+	/**
+	 * prev_sleep_state() - Get the previous sleep state (optional)
+	 *
+	 * This reads various state registers and returns the sleep state from
+	 * which the system woke. If this method is not provided, the uclass
+	 * will return a calculated value.
+	 *
+	 * This is optional.
+	 *
+	 * @dev: PMC device to use
+	 * @prev_sleep_state: Previous sleep state as calculated by the uclass.
+	 *	The method can use this as the return value or calculate its
+	 *	own.
+	 *
+	 * @return enum acpi_sleep_state indicating the previous sleep state
+	 *	(ACPI_S0, ACPI_S3 or ACPI_S5), or -ve on error
+	 */
+	int (*prev_sleep_state)(struct udevice *dev, int prev_sleep_state);
+
+	/**
+	 * disable_tco() - Disable the timer/counter
+	 *
+	 * Disables the timer/counter in the PMC
+	 *
+	 * This is optional.
+	 *
+	 * @dev: PMC device to use
+	 * @return 0
+	 */
+	int (*disable_tco)(struct udevice *dev);
+
+	/**
+	 * global_reset_set_enable() - Enable/Disable global reset
+	 *
+	 * Enable or disable global reset. If global reset is enabled, both hard
+	 * reset and soft reset will trigger global reset, where both host and
+	 * TXE are reset. This is cleared on cold boot, hard reset, soft reset
+	 * and Sx.
+	 *
+	 * This is optional.
+	 *
+	 * @dev: PMC device to use
+	 * @enable: true to enable global reset, false to disable
+	 * @return 0
+	 */
+	int (*global_reset_set_enable)(struct udevice *dev, bool enable);
+};
+
+#define acpi_pmc_get_ops(dev)	((struct acpi_pmc_ops *)(dev)->driver->ops)
+
+/**
+ * init() - Set up the PMC for use
+ *
+ * This reads the current state of the PMC. This reads in the common registers,
+ * then calls the device's init() method to read the SoC-specific registers.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int pmc_init(struct udevice *dev);
+
+/**
+ * pmc_prev_sleep_state() - Get the previous sleep state
+ *
+ * This reads various state registers and returns the sleep state from
+ * which the system woke.
+ *
+ * @return enum acpi_sleep_state indicating the previous sleep state
+ *	(ACPI_S0, ACPI_S3 or ACPI_S5), or -ve on error
+ */
+int pmc_prev_sleep_state(struct udevice *dev);
+
+/**
+ * pmc_disable_tco() - Disable the timer/counter
+ *
+ * Disables the timer/counter in the PMC
+ *
+ * @dev: PMC device to use
+ * @return 0
+ */
+int pmc_disable_tco(struct udevice *dev);
+
+/**
+ * pmc_global_reset_set_enable() - Enable/Disable global reset
+ *
+ * Enable or disable global reset. If global reset is enabled, both hard
+ * reset and soft reset will trigger global reset, where both host and
+ * TXE are reset. This is cleared on cold boot, hard reset, soft reset
+ * and Sx.
+ *
+ * @dev: PMC device to use
+ * @enable: true to enable global reset, false to disable
+ * @return 0
+ */
+int pmc_global_reset_set_enable(struct udevice *dev, bool enable);
+
+int pmc_ofdata_to_uc_plat(struct udevice *dev);
+
+int pmc_disable_tco_base(ulong tco_base);
+
+void pmc_dump_info(struct udevice *dev);
+
+/**
+ * pmc_gpe_init() - Set up general-purpose events
+ *
+ * @dev: PMC device
+ * @return 0 if OK, -ve on error
+ */
+int pmc_gpe_init(struct udevice *dev);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif
diff --git a/roms/u-boot/include/power/act8846_pmic.h b/roms/u-boot/include/power/act8846_pmic.h
new file mode 100644
index 000000000..acd0fd671
--- /dev/null
+++ b/roms/u-boot/include/power/act8846_pmic.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _PMIC_ACT8846_H_
+#define _PMIC_ACT8846_H_
+
+#include <asm/gpio.h>
+
+#define ACT8846_NUM_OF_REGS	12
+
+#define BUCK_VOL_MASK 0x3f
+#define LDO_VOL_MASK 0x3f
+
+#define BUCK_EN_MASK 0x80
+#define LDO_EN_MASK 0x80
+
+#define VOL_MIN_IDX 0x00
+#define VOL_MAX_IDX 0x3f
+
+struct  act8846_reg_table {
+	char	*name;
+	char	reg_ctl;
+	char	reg_vol;
+};
+
+struct pmic_act8846 {
+	struct pmic *pmic;
+	int node;	/*device tree node*/
+	struct gpio_desc pwr_hold;
+	struct udevice *dev;
+};
+
+#endif
diff --git a/roms/u-boot/include/power/as3722.h b/roms/u-boot/include/power/as3722.h
new file mode 100644
index 000000000..f5398123f
--- /dev/null
+++ b/roms/u-boot/include/power/as3722.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ */
+
+#ifndef __POWER_AS3722_H__
+#define __POWER_AS3722_H__
+
+struct udevice;
+
+#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_INVERT (1 << 1)
+
+#define AS3722_DEVICE_ID 0x0c
+#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
+#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
+#define AS3722_SD_CONTROL 0x4d
+#define AS3722_LDO_CONTROL0 0x4e
+#define AS3722_LDO_CONTROL1 0x4f
+#define AS3722_ASIC_ID1 0x90
+#define AS3722_ASIC_ID2 0x91
+
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_SIGNAL_OUT 0x20
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
+
+int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value);
+int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value);
+
+#endif /* __POWER_AS3722_H__ */
diff --git a/roms/u-boot/include/power/battery.h b/roms/u-boot/include/power/battery.h
new file mode 100644
index 000000000..1e3d59d76
--- /dev/null
+++ b/roms/u-boot/include/power/battery.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __POWER_BATTERY_H_
+#define __POWER_BATTERY_H_
+
+struct battery {
+	unsigned int version;
+	unsigned int state_of_chrg;
+	unsigned int time_to_empty;
+	unsigned int capacity;
+	unsigned int voltage_uV;
+
+	unsigned int state;
+};
+
+int power_bat_init(unsigned char bus);
+#endif /* __POWER_BATTERY_H_ */
diff --git a/roms/u-boot/include/power/bd71837.h b/roms/u-boot/include/power/bd71837.h
new file mode 100644
index 000000000..75e07e1de
--- /dev/null
+++ b/roms/u-boot/include/power/bd71837.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2018 ROHM Semiconductors */
+
+#ifndef BD718XX_H_
+#define BD718XX_H_
+
+#define BD718XX_REGULATOR_DRIVER "bd718x7_regulator"
+
+enum {
+	ROHM_CHIP_TYPE_BD71837 = 0,
+	ROHM_CHIP_TYPE_BD71847,
+	ROHM_CHIP_TYPE_BD70528,
+	ROHM_CHIP_TYPE_AMOUNT
+};
+
+enum {
+	BD718XX_REV			= 0x00,
+	BD718XX_SWRESET			= 0x01,
+	BD718XX_I2C_DEV			= 0x02,
+	BD718XX_PWRCTRL0		= 0x03,
+	BD718XX_PWRCTRL1		= 0x04,
+	BD718XX_BUCK1_CTRL		= 0x05,
+	BD718XX_BUCK2_CTRL		= 0x06,
+	BD71837_BUCK3_CTRL		= 0x07,
+	BD71837_BUCK4_CTRL		= 0x08,
+	BD718XX_1ST_NODVS_BUCK_CTRL	= 0x09,
+	BD718XX_2ND_NODVS_BUCK_CTRL	= 0x0a,
+	BD718XX_3RD_NODVS_BUCK_CTRL	= 0x0b,
+	BD718XX_4TH_NODVS_BUCK_CTRL	= 0x0c,
+	BD718XX_BUCK1_VOLT_RUN		= 0x0d,
+	BD718XX_BUCK1_VOLT_IDLE		= 0x0e,
+	BD718XX_BUCK1_VOLT_SUSP		= 0x0f,
+	BD718XX_BUCK2_VOLT_RUN		= 0x10,
+	BD718XX_BUCK2_VOLT_IDLE		= 0x11,
+	BD71837_BUCK3_VOLT_RUN		= 0x12,
+	BD71837_BUCK4_VOLT_RUN		= 0x13,
+	BD718XX_1ST_NODVS_BUCK_VOLT	= 0x14,
+	BD718XX_2ND_NODVS_BUCK_VOLT	= 0x15,
+	BD718XX_3RD_NODVS_BUCK_VOLT	= 0x16,
+	BD718XX_4TH_NODVS_BUCK_VOLT	= 0x17,
+	BD718XX_LDO1_VOLT		= 0x18,
+	BD718XX_LDO2_VOLT		= 0x19,
+	BD718XX_LDO3_VOLT		= 0x1a,
+	BD718XX_LDO4_VOLT		= 0x1b,
+	BD718XX_LDO5_VOLT		= 0x1c,
+	BD718XX_LDO6_VOLT		= 0x1d,
+	BD71837_LDO7_VOLT		= 0x1e,
+	BD718XX_TRANS_COND0		= 0x1f,
+	BD718XX_TRANS_COND1		= 0x20,
+	BD718XX_VRFAULTEN		= 0x21,
+	BD718XX_MVRFLTMASK0		= 0x22,
+	BD718XX_MVRFLTMASK1		= 0x23,
+	BD718XX_MVRFLTMASK2		= 0x24,
+	BD718XX_RCVCFG			= 0x25,
+	BD718XX_RCVNUM			= 0x26,
+	BD718XX_PWRONCONFIG0		= 0x27,
+	BD718XX_PWRONCONFIG1		= 0x28,
+	BD718XX_RESETSRC		= 0x29,
+	BD718XX_MIRQ			= 0x2a,
+	BD718XX_IRQ			= 0x2b,
+	BD718XX_IN_MON			= 0x2c,
+	BD718XX_POW_STATE		= 0x2d,
+	BD718XX_OUT32K			= 0x2e,
+	BD718XX_REGLOCK			= 0x2f,
+	BD718XX_MUXSW_EN		= 0x30,
+	BD718XX_REG_OTPVER		= 0xff,
+	BD718XX_MAX_REGISTER		= 0x100,
+};
+
+#define BD718XX_REGLOCK_PWRSEQ		0x1
+#define BD718XX_REGLOCK_VREG		0x10
+
+#define BD718XX_BUCK_EN			0x01
+#define BD718XX_LDO_EN			0x40
+#define BD718XX_BUCK_SEL		0x02
+#define BD718XX_LDO_SEL			0x80
+
+#define DVS_BUCK_RUN_MASK		0x3f
+#define BD718XX_1ST_NODVS_BUCK_MASK	0x07
+#define BD718XX_3RD_NODVS_BUCK_MASK	0x07
+#define BD718XX_4TH_NODVS_BUCK_MASK	0x3f
+
+#define BD71847_BUCK3_MASK		0x07
+#define BD71847_BUCK3_RANGE_MASK	0xc0
+#define BD71847_BUCK4_MASK		0x03
+#define BD71847_BUCK4_RANGE_MASK	0x40
+
+#define BD71837_BUCK5_RANGE_MASK	0x80
+#define BD71837_BUCK6_MASK		0x03
+
+#define BD718XX_LDO1_MASK		0x03
+#define BD718XX_LDO1_RANGE_MASK		0x20
+#define BD718XX_LDO2_MASK		0x20
+#define BD718XX_LDO3_MASK		0x0f
+#define BD718XX_LDO4_MASK		0x0f
+#define BD718XX_LDO6_MASK		0x0f
+
+#define BD71837_LDO5_MASK		0x0f
+#define BD71847_LDO5_MASK		0x0f
+#define BD71847_LDO5_RANGE_MASK		0x20
+#define BD71837_LDO7_MASK		0x0f
+
+#endif
diff --git a/roms/u-boot/include/power/da9063_pmic.h b/roms/u-boot/include/power/da9063_pmic.h
new file mode 100644
index 000000000..273a07ef4
--- /dev/null
+++ b/roms/u-boot/include/power/da9063_pmic.h
@@ -0,0 +1,320 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2018 Flowbird
+ *  Martin Fuzzey  <martin.fuzzey@flowbird.group>
+ */
+
+#ifndef __DA9063_PMIC_H_
+#define __DA9063_PMIC_H_
+
+/* Register definitions below taken from the kernel */
+
+/* Page selection I2C or SPI always in the beginning of any page. */
+/* Page 0 : I2C access 0x000 - 0x0FF	SPI access 0x000 - 0x07F */
+/* Page 1 :				SPI access 0x080 - 0x0FF */
+/* Page 2 : I2C access 0x100 - 0x1FF	SPI access 0x100 - 0x17F */
+/* Page 3 :				SPI access 0x180 - 0x1FF */
+#define	DA9063_REG_PAGE_CON		0x00
+
+/* System Control and Event Registers */
+#define	DA9063_REG_STATUS_A		0x01
+#define	DA9063_REG_STATUS_B		0x02
+#define	DA9063_REG_STATUS_C		0x03
+#define	DA9063_REG_STATUS_D		0x04
+#define	DA9063_REG_FAULT_LOG		0x05
+#define	DA9063_REG_EVENT_A		0x06
+#define	DA9063_REG_EVENT_B		0x07
+#define	DA9063_REG_EVENT_C		0x08
+#define	DA9063_REG_EVENT_D		0x09
+#define	DA9063_REG_IRQ_MASK_A		0x0A
+#define	DA9063_REG_IRQ_MASK_B		0x0B
+#define	DA9063_REG_IRQ_MASK_C		0x0C
+#define	DA9063_REG_IRQ_MASK_D		0x0D
+#define	DA9063_REG_CONTROL_A		0x0E
+#define	DA9063_REG_CONTROL_B		0x0F
+#define	DA9063_REG_CONTROL_C		0x10
+#define	DA9063_REG_CONTROL_D		0x11
+#define	DA9063_REG_CONTROL_E		0x12
+#define	DA9063_REG_CONTROL_F		0x13
+#define	DA9063_REG_PD_DIS		0x14
+
+/* GPIO Control Registers */
+#define	DA9063_REG_GPIO_0_1		0x15
+#define	DA9063_REG_GPIO_2_3		0x16
+#define	DA9063_REG_GPIO_4_5		0x17
+#define	DA9063_REG_GPIO_6_7		0x18
+#define	DA9063_REG_GPIO_8_9		0x19
+#define	DA9063_REG_GPIO_10_11		0x1A
+#define	DA9063_REG_GPIO_12_13		0x1B
+#define	DA9063_REG_GPIO_14_15		0x1C
+#define	DA9063_REG_GPIO_MODE0_7		0x1D
+#define	DA9063_REG_GPIO_MODE8_15	0x1E
+#define	DA9063_REG_SWITCH_CONT		0x1F
+
+/* Regulator Control Registers */
+#define	DA9063_REG_BCORE2_CONT		0x20
+#define	DA9063_REG_BCORE1_CONT		0x21
+#define	DA9063_REG_BPRO_CONT		0x22
+#define	DA9063_REG_BMEM_CONT		0x23
+#define	DA9063_REG_BIO_CONT		0x24
+#define	DA9063_REG_BPERI_CONT		0x25
+#define	DA9063_REG_LDO1_CONT		0x26
+#define	DA9063_REG_LDO2_CONT		0x27
+#define	DA9063_REG_LDO3_CONT		0x28
+#define	DA9063_REG_LDO4_CONT		0x29
+#define	DA9063_REG_LDO5_CONT		0x2A
+#define	DA9063_REG_LDO6_CONT		0x2B
+#define	DA9063_REG_LDO7_CONT		0x2C
+#define	DA9063_REG_LDO8_CONT		0x2D
+#define	DA9063_REG_LDO9_CONT		0x2E
+#define	DA9063_REG_LDO10_CONT		0x2F
+#define	DA9063_REG_LDO11_CONT		0x30
+#define	DA9063_REG_SUPPLIES		0x31
+#define	DA9063_REG_DVC_1		0x32
+#define	DA9063_REG_DVC_2		0x33
+
+/* GP-ADC Control Registers */
+#define	DA9063_REG_ADC_MAN		0x34
+#define	DA9063_REG_ADC_CONT		0x35
+#define	DA9063_REG_VSYS_MON		0x36
+#define	DA9063_REG_ADC_RES_L		0x37
+#define	DA9063_REG_ADC_RES_H		0x38
+#define	DA9063_REG_VSYS_RES		0x39
+#define	DA9063_REG_ADCIN1_RES		0x3A
+#define	DA9063_REG_ADCIN2_RES		0x3B
+#define	DA9063_REG_ADCIN3_RES		0x3C
+#define	DA9063_REG_MON_A8_RES		0x3D
+#define	DA9063_REG_MON_A9_RES		0x3E
+#define	DA9063_REG_MON_A10_RES		0x3F
+
+/* RTC Calendar and Alarm Registers */
+#define	DA9063_REG_COUNT_S		0x40
+#define	DA9063_REG_COUNT_MI		0x41
+#define	DA9063_REG_COUNT_H		0x42
+#define	DA9063_REG_COUNT_D		0x43
+#define	DA9063_REG_COUNT_MO		0x44
+#define	DA9063_REG_COUNT_Y		0x45
+
+#define	DA9063_AD_REG_ALARM_MI		0x46
+#define	DA9063_AD_REG_ALARM_H		0x47
+#define	DA9063_AD_REG_ALARM_D		0x48
+#define	DA9063_AD_REG_ALARM_MO		0x49
+#define	DA9063_AD_REG_ALARM_Y		0x4A
+#define	DA9063_AD_REG_SECOND_A		0x4B
+#define	DA9063_AD_REG_SECOND_B		0x4C
+#define	DA9063_AD_REG_SECOND_C		0x4D
+#define	DA9063_AD_REG_SECOND_D		0x4E
+
+#define	DA9063_BB_REG_ALARM_S		0x46
+#define	DA9063_BB_REG_ALARM_MI		0x47
+#define	DA9063_BB_REG_ALARM_H		0x48
+#define	DA9063_BB_REG_ALARM_D		0x49
+#define	DA9063_BB_REG_ALARM_MO		0x4A
+#define	DA9063_BB_REG_ALARM_Y		0x4B
+#define	DA9063_BB_REG_SECOND_A		0x4C
+#define	DA9063_BB_REG_SECOND_B		0x4D
+#define	DA9063_BB_REG_SECOND_C		0x4E
+#define	DA9063_BB_REG_SECOND_D		0x4F
+
+#define DA9063_REG_HOLE_1 {0x50, 0x7F}
+
+/* Sequencer Control Registers */
+#define	DA9063_REG_SEQ			0x81
+#define	DA9063_REG_SEQ_TIMER		0x82
+#define	DA9063_REG_ID_2_1		0x83
+#define	DA9063_REG_ID_4_3		0x84
+#define	DA9063_REG_ID_6_5		0x85
+#define	DA9063_REG_ID_8_7		0x86
+#define	DA9063_REG_ID_10_9		0x87
+#define	DA9063_REG_ID_12_11		0x88
+#define	DA9063_REG_ID_14_13		0x89
+#define	DA9063_REG_ID_16_15		0x8A
+#define	DA9063_REG_ID_18_17		0x8B
+#define	DA9063_REG_ID_20_19		0x8C
+#define	DA9063_REG_ID_22_21		0x8D
+#define	DA9063_REG_ID_24_23		0x8E
+#define	DA9063_REG_ID_26_25		0x8F
+#define	DA9063_REG_ID_28_27		0x90
+#define	DA9063_REG_ID_30_29		0x91
+#define	DA9063_REG_ID_32_31		0x92
+#define	DA9063_REG_SEQ_A		0x95
+#define	DA9063_REG_SEQ_B		0x96
+#define	DA9063_REG_WAIT			0x97
+#define	DA9063_REG_EN_32K		0x98
+#define	DA9063_REG_RESET		0x99
+
+/* Regulator Setting Registers */
+#define	DA9063_REG_BUCK_ILIM_A		0x9A
+#define	DA9063_REG_BUCK_ILIM_B		0x9B
+#define	DA9063_REG_BUCK_ILIM_C		0x9C
+#define	DA9063_REG_BCORE2_CFG		0x9D
+#define	DA9063_REG_BCORE1_CFG		0x9E
+#define	DA9063_REG_BPRO_CFG		0x9F
+#define	DA9063_REG_BIO_CFG		0xA0
+#define	DA9063_REG_BMEM_CFG		0xA1
+#define	DA9063_REG_BPERI_CFG		0xA2
+#define	DA9063_REG_VBCORE2_A		0xA3
+#define	DA9063_REG_VBCORE1_A		0xA4
+#define	DA9063_REG_VBPRO_A		0xA5
+#define	DA9063_REG_VBMEM_A		0xA6
+#define	DA9063_REG_VBIO_A		0xA7
+#define	DA9063_REG_VBPERI_A		0xA8
+#define	DA9063_REG_VLDO1_A		0xA9
+#define	DA9063_REG_VLDO2_A		0xAA
+#define	DA9063_REG_VLDO3_A		0xAB
+#define	DA9063_REG_VLDO4_A		0xAC
+#define	DA9063_REG_VLDO5_A		0xAD
+#define	DA9063_REG_VLDO6_A		0xAE
+#define	DA9063_REG_VLDO7_A		0xAF
+#define	DA9063_REG_VLDO8_A		0xB0
+#define	DA9063_REG_VLDO9_A		0xB1
+#define	DA9063_REG_VLDO10_A		0xB2
+#define	DA9063_REG_VLDO11_A		0xB3
+#define	DA9063_REG_VBCORE2_B		0xB4
+#define	DA9063_REG_VBCORE1_B		0xB5
+#define	DA9063_REG_VBPRO_B		0xB6
+#define	DA9063_REG_VBMEM_B		0xB7
+#define	DA9063_REG_VBIO_B		0xB8
+#define	DA9063_REG_VBPERI_B		0xB9
+#define	DA9063_REG_VLDO1_B		0xBA
+#define	DA9063_REG_VLDO2_B		0xBB
+#define	DA9063_REG_VLDO3_B		0xBC
+#define	DA9063_REG_VLDO4_B		0xBD
+#define	DA9063_REG_VLDO5_B		0xBE
+#define	DA9063_REG_VLDO6_B		0xBF
+#define	DA9063_REG_VLDO7_B		0xC0
+#define	DA9063_REG_VLDO8_B		0xC1
+#define	DA9063_REG_VLDO9_B		0xC2
+#define	DA9063_REG_VLDO10_B		0xC3
+#define	DA9063_REG_VLDO11_B		0xC4
+
+/* Backup Battery Charger Control Register */
+#define	DA9063_REG_BBAT_CONT		0xC5
+
+/* GPIO PWM (LED) */
+#define	DA9063_REG_GPO11_LED		0xC6
+#define	DA9063_REG_GPO14_LED		0xC7
+#define	DA9063_REG_GPO15_LED		0xC8
+
+/* GP-ADC Threshold Registers */
+#define	DA9063_REG_ADC_CFG		0xC9
+#define	DA9063_REG_AUTO1_HIGH		0xCA
+#define	DA9063_REG_AUTO1_LOW		0xCB
+#define	DA9063_REG_AUTO2_HIGH		0xCC
+#define	DA9063_REG_AUTO2_LOW		0xCD
+#define	DA9063_REG_AUTO3_HIGH		0xCE
+#define	DA9063_REG_AUTO3_LOW		0xCF
+
+#define DA9063_REG_HOLE_2 {0xD0, 0xFF}
+
+/* DA9063 Configuration registers */
+/* OTP */
+#define	DA9063_REG_OTP_COUNT		0x101
+#define	DA9063_REG_OTP_ADDR		0x102
+#define	DA9063_REG_OTP_DATA		0x103
+
+/* Customer Trim and Configuration */
+#define	DA9063_REG_T_OFFSET		0x104
+#define	DA9063_REG_INTERFACE		0x105
+#define	DA9063_REG_CONFIG_A		0x106
+#define	DA9063_REG_CONFIG_B		0x107
+#define	DA9063_REG_CONFIG_C		0x108
+#define	DA9063_REG_CONFIG_D		0x109
+#define	DA9063_REG_CONFIG_E		0x10A
+#define	DA9063_REG_CONFIG_F		0x10B
+#define	DA9063_REG_CONFIG_G		0x10C
+#define	DA9063_REG_CONFIG_H		0x10D
+#define	DA9063_REG_CONFIG_I		0x10E
+#define	DA9063_REG_CONFIG_J		0x10F
+#define	DA9063_REG_CONFIG_K		0x110
+#define	DA9063_REG_CONFIG_L		0x111
+
+#define	DA9063_AD_REG_MON_REG_1		0x112
+#define	DA9063_AD_REG_MON_REG_2		0x113
+#define	DA9063_AD_REG_MON_REG_3		0x114
+#define	DA9063_AD_REG_MON_REG_4		0x115
+#define	DA9063_AD_REG_MON_REG_5		0x116
+#define	DA9063_AD_REG_MON_REG_6		0x117
+#define	DA9063_AD_REG_TRIM_CLDR		0x118
+
+#define	DA9063_AD_REG_GP_ID_0		0x119
+#define	DA9063_AD_REG_GP_ID_1		0x11A
+#define	DA9063_AD_REG_GP_ID_2		0x11B
+#define	DA9063_AD_REG_GP_ID_3		0x11C
+#define	DA9063_AD_REG_GP_ID_4		0x11D
+#define	DA9063_AD_REG_GP_ID_5		0x11E
+#define	DA9063_AD_REG_GP_ID_6		0x11F
+#define	DA9063_AD_REG_GP_ID_7		0x120
+#define	DA9063_AD_REG_GP_ID_8		0x121
+#define	DA9063_AD_REG_GP_ID_9		0x122
+#define	DA9063_AD_REG_GP_ID_10		0x123
+#define	DA9063_AD_REG_GP_ID_11		0x124
+#define	DA9063_AD_REG_GP_ID_12		0x125
+#define	DA9063_AD_REG_GP_ID_13		0x126
+#define	DA9063_AD_REG_GP_ID_14		0x127
+#define	DA9063_AD_REG_GP_ID_15		0x128
+#define	DA9063_AD_REG_GP_ID_16		0x129
+#define	DA9063_AD_REG_GP_ID_17		0x12A
+#define	DA9063_AD_REG_GP_ID_18		0x12B
+#define	DA9063_AD_REG_GP_ID_19		0x12C
+
+#define	DA9063_BB_REG_CONFIG_M		0x112
+#define	DA9063_BB_REG_CONFIG_N		0x113
+
+#define	DA9063_BB_REG_MON_REG_1		0x114
+#define	DA9063_BB_REG_MON_REG_2		0x115
+#define	DA9063_BB_REG_MON_REG_3		0x116
+#define	DA9063_BB_REG_MON_REG_4		0x117
+#define	DA9063_BB_REG_MON_REG_5		0x11E
+#define	DA9063_BB_REG_MON_REG_6		0x11F
+#define	DA9063_BB_REG_TRIM_CLDR		0x120
+/* General Purpose Registers */
+#define	DA9063_BB_REG_GP_ID_0		0x121
+#define	DA9063_BB_REG_GP_ID_1		0x122
+#define	DA9063_BB_REG_GP_ID_2		0x123
+#define	DA9063_BB_REG_GP_ID_3		0x124
+#define	DA9063_BB_REG_GP_ID_4		0x125
+#define	DA9063_BB_REG_GP_ID_5		0x126
+#define	DA9063_BB_REG_GP_ID_6		0x127
+#define	DA9063_BB_REG_GP_ID_7		0x128
+#define	DA9063_BB_REG_GP_ID_8		0x129
+#define	DA9063_BB_REG_GP_ID_9		0x12A
+#define	DA9063_BB_REG_GP_ID_10		0x12B
+#define	DA9063_BB_REG_GP_ID_11		0x12C
+#define	DA9063_BB_REG_GP_ID_12		0x12D
+#define	DA9063_BB_REG_GP_ID_13		0x12E
+#define	DA9063_BB_REG_GP_ID_14		0x12F
+#define	DA9063_BB_REG_GP_ID_15		0x130
+#define	DA9063_BB_REG_GP_ID_16		0x131
+#define	DA9063_BB_REG_GP_ID_17		0x132
+#define	DA9063_BB_REG_GP_ID_18		0x133
+#define	DA9063_BB_REG_GP_ID_19		0x134
+
+/* 0x135 - 0x13f are readable, but not documented */
+#define DA9063_REG_HOLE_3 {0x140, 0x17F}
+
+/* Chip ID and variant */
+#define	DA9063_REG_CHIP_ID		0x181
+#define	DA9063_REG_CHIP_VARIANT		0x182
+#define DA9063_REG_CUSTOMER_ID		0x183
+#define DA9063_REG_CONFIG_ID		0x184
+
+#define DA9063_NUM_OF_REGS		(DA9063_REG_CONFIG_ID + 1)
+
+/* Drivers name */
+#define DA9063_LDO_DRIVER	"da9063_ldo"
+#define DA9063_BUCK_DRIVER	"da9063_buck"
+
+/* Regulator modes */
+enum {
+	DA9063_LDOMODE_SLEEP,
+	DA9063_LDOMODE_NORMAL
+};
+
+enum {
+	DA9063_BUCKMODE_SLEEP,
+	DA9063_BUCKMODE_SYNC,
+	DA9063_BUCKMODE_AUTO,
+};
+
+#endif
diff --git a/roms/u-boot/include/power/fan53555.h b/roms/u-boot/include/power/fan53555.h
new file mode 100644
index 000000000..c039f0607
--- /dev/null
+++ b/roms/u-boot/include/power/fan53555.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+#ifndef _FAN53555_H_
+#define _FAN53555_H_
+
+enum fan53555_vendor {
+	FAN53555_VENDOR_FAIRCHILD,
+	FAN53555_VENDOR_SILERGY,
+};
+
+#endif
diff --git a/roms/u-boot/include/power/fg_battery_cell_params.h b/roms/u-boot/include/power/fg_battery_cell_params.h
new file mode 100644
index 000000000..b8c895bba
--- /dev/null
+++ b/roms/u-boot/include/power/fg_battery_cell_params.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __FG_BATTERY_CELL_PARAMS_H_
+#define __FG_BATTERY_CELL_PARAMS_H_
+
+#if  defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS)
+
+/* Cell characteristics - Exynos4 TRATS development board */
+/* Shall be written to addr 0x80h */
+u16 cell_character0[16] = {
+	0xA2A0,
+	0xB6E0,
+	0xB850,
+	0xBAD0,
+	0xBB20,
+	0xBB70,
+	0xBBC0,
+	0xBC20,
+	0xBC80,
+	0xBCE0,
+	0xBD80,
+	0xBE20,
+	0xC090,
+	0xC420,
+	0xC910,
+	0xD070
+};
+
+/* Shall be written to addr 0x90h */
+u16 cell_character1[16] = {
+	0x0090,
+	0x1A50,
+	0x02F0,
+	0x2060,
+	0x2060,
+	0x2E60,
+	0x26A0,
+	0x2DB0,
+	0x2DB0,
+	0x1870,
+	0x2A20,
+	0x16F0,
+	0x08F0,
+	0x0D40,
+	0x08C0,
+	0x08C0
+};
+
+/* Shall be written to addr 0xA0h */
+u16 cell_character2[16] = {
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100
+};
+#endif
+#endif /* __FG_BATTERY_CELL_PARAMS_H_ */
diff --git a/roms/u-boot/include/power/hi6553_pmic.h b/roms/u-boot/include/power/hi6553_pmic.h
new file mode 100644
index 000000000..d0abe2075
--- /dev/null
+++ b/roms/u-boot/include/power/hi6553_pmic.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef __HI6553_PMIC_H__
+#define __HI6553_PMIC_H__
+
+/* Registers */
+enum {
+	HI6553_VERSION_REG = 0x000,
+	HI6553_ENABLE2_LDO1_8 = 0x029,
+	HI6553_DISABLE2_LDO1_8,
+	HI6553_ONOFF_STATUS2_LDO1_8,
+	HI6553_ENABLE3_LDO9_16,
+	HI6553_DISABLE3_LDO9_16,
+	HI6553_ONOFF_STATUS3_LDO9_16,
+
+	HI6553_DISABLE6_XO_CLK = 0x036,
+	HI6553_PERI_EN_MARK = 0x040,
+	HI6553_BUCK2_REG1 = 0x04a,
+	HI6553_BUCK2_REG5 = 0x04e,
+	HI6553_BUCK2_REG6,
+
+	HI6553_BUCK3_REG3 = 0x054,
+	HI6553_BUCK3_REG5 = 0x056,
+	HI6553_BUCK3_REG6,
+	HI6553_BUCK4_REG2 = 0x05b,
+	HI6553_BUCK4_REG5 = 0x05e,
+	HI6553_BUCK4_REG6,
+
+	HI6553_CLK_TOP0 = 0x063,
+	HI6553_CLK_TOP3 = 0x066,
+	HI6553_CLK_TOP4,
+	HI6553_VSET_BUCK2_ADJ = 0x06d,
+	HI6553_VSET_BUCK3_ADJ,
+	HI6553_LDO7_REG_ADJ = 0x078,
+	HI6553_LDO10_REG_ADJ = 0x07b,
+	HI6553_LDO19_REG_ADJ = 0x084,
+	HI6553_LDO20_REG_ADJ,
+	HI6553_DR_LED_CTRL = 0x098,
+	HI6553_DR_OUT_CTRL,
+	HI6553_DR3_ISET,
+	HI6553_DR3_START_DEL,
+	HI6553_DR4_ISET,
+	HI6553_DR4_START_DEL,
+	HI6553_DR345_TIM_CONF0 = 0x0a0,
+	HI6553_NP_REG_ADJ1 = 0x0be,
+	HI6553_NP_REG_CHG = 0x0c0,
+	HI6553_BUCK01_CTRL2 = 0x0d9,
+	HI6553_BUCK0_CTRL1 = 0x0dd,
+	HI6553_BUCK0_CTRL5 = 0x0e1,
+	HI6553_BUCK0_CTRL7 = 0x0e3,
+	HI6553_BUCK1_CTRL1 = 0x0e8,
+	HI6553_BUCK1_CTRL5 = 0x0ec,
+	HI6553_BUCK1_CTRL7 = 0x0ef,
+	HI6553_CLK19M2_600_586_EN = 0x0fe,
+};
+
+#define HI6553_DISABLE6_XO_CLK_BB		(1 << 0)
+#define HI6553_DISABLE6_XO_CLK_CONN		(1 << 1)
+#define HI6553_DISABLE6_XO_CLK_NFC		(1 << 2)
+#define HI6553_DISABLE6_XO_CLK_RF1		(1 << 3)
+#define HI6553_DISABLE6_XO_CLK_RF2		(1 << 4)
+
+#define HI6553_LED_START_DELAY_TIME		0x00
+#define HI6553_LED_ELEC_VALUE			0x07
+#define HI6553_LED_LIGHT_TIME			0xf0
+#define HI6553_LED_GREEN_ENABLE			(1 << 1)
+#define HI6553_LED_OUT_CTRL			0x00
+
+#define HI6553_PMU_V300				0x30
+#define HI6553_PMU_V310				0x31
+
+int power_hi6553_init(u8 *base);
+
+#endif	/* __HI6553_PMIC_H__ */
diff --git a/roms/u-boot/include/power/lp873x.h b/roms/u-boot/include/power/lp873x.h
new file mode 100644
index 000000000..e0c07115d
--- /dev/null
+++ b/roms/u-boot/include/power/lp873x.h
@@ -0,0 +1,19 @@
+#define	LP8732		0x0
+#define LP8733		0x1
+
+#define LP873X_LDO_NUM		2
+#define LP873X_BUCK_NUM		2
+
+/* Drivers name */
+#define LP873X_LDO_DRIVER	"lp873x_ldo"
+#define LP873X_BUCK_DRIVER	"lp873x_buck"
+
+#define LP873X_BUCK_VOLT_MASK		0xFF
+#define LP873X_BUCK_VOLT_MAX_HEX	0xFF
+#define LP873X_BUCK_VOLT_MAX		3360000
+#define LP873X_BUCK_MODE_MASK		0x1
+
+#define LP873X_LDO_VOLT_MASK    0x1F
+#define LP873X_LDO_VOLT_MAX_HEX 0x19
+#define LP873X_LDO_VOLT_MAX     3300000
+#define LP873X_LDO_MODE_MASK	0x1
diff --git a/roms/u-boot/include/power/lp87565.h b/roms/u-boot/include/power/lp87565.h
new file mode 100644
index 000000000..5160f5df6
--- /dev/null
+++ b/roms/u-boot/include/power/lp87565.h
@@ -0,0 +1,12 @@
+#define LP87565	0x0
+#define LP87565_Q1	0x1
+
+#define LP87565_BUCK_NUM		6
+
+/* Drivers name */
+#define LP87565_BUCK_DRIVER	"lp87565_buck"
+
+#define LP87565_BUCK_VOLT_MASK		0xFF
+#define LP87565_BUCK_VOLT_MAX_HEX	0xFF
+#define LP87565_BUCK_VOLT_MAX		3360000
+#define LP87565_BUCK_MODE_MASK		0x80
diff --git a/roms/u-boot/include/power/ltc3676_pmic.h b/roms/u-boot/include/power/ltc3676_pmic.h
new file mode 100644
index 000000000..36c79716f
--- /dev/null
+++ b/roms/u-boot/include/power/ltc3676_pmic.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014 Gateworks Corporation
+ *  Tim Harvey <tharvey@gateworks.com>
+ */
+
+#ifndef __LTC3676_PMIC_H_
+#define __LTC3676_PMIC_H_
+
+/* LTC3676 registers */
+enum {
+	LTC3676_BUCK1	= 0x01,
+	LTC3676_BUCK2	= 0x02,
+	LTC3676_BUCK3	= 0x03,
+	LTC3676_BUCK4	= 0x04,
+	LTC3676_LDOA	= 0x05,
+	LTC3676_LDOB	= 0x06,
+	LTC3676_SQD1	= 0x07,
+	LTC3676_SQD2	= 0x08,
+	LTC3676_CNTRL	= 0x09,
+	LTC3676_DVB1A	= 0x0A,
+	LTC3676_DVB1B	= 0x0B,
+	LTC3676_DVB2A	= 0x0C,
+	LTC3676_DVB2B	= 0x0D,
+	LTC3676_DVB3A	= 0x0E,
+	LTC3676_DVB3B	= 0x0F,
+	LTC3676_DVB4A	= 0x10,
+	LTC3676_DVB4B	= 0x11,
+	LTC3676_MSKIRQ	= 0x12,
+	LTC3676_MSKPG	= 0x13,
+	LTC3676_USER	= 0x14,
+	LTC3676_HRST	= 0x1E,
+	LTC3676_CLIRQ	= 0x1F,
+	LTC3676_IRQSTAT	= 0x15,
+	LTC3676_PGSTATL	= 0x16,
+	LTC3676_PGSTATR	= 0x17,
+	LTC3676_NUM_OF_REGS = 0x20,
+};
+
+/*
+ * SW Configuration
+ */
+
+#define LTC3676_DVB_MASK	0x1f
+#define LTC3676_PGOOD_MASK	(1<<5)
+#define LTC3676_REF_SELA	(0<<5)
+#define LTC3676_REF_SELB	(1<<5)
+
+int power_ltc3676_init(unsigned char bus);
+#endif
diff --git a/roms/u-boot/include/power/max17042_fg.h b/roms/u-boot/include/power/max17042_fg.h
new file mode 100644
index 000000000..ec8377d37
--- /dev/null
+++ b/roms/u-boot/include/power/max17042_fg.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX17042_FG_H_
+#define __MAX17042_FG_H_
+
+/* MAX 17042 registers */
+enum {
+	MAX17042_STATUS         = 0x00,
+	MAX17042_SOCREP         = 0x06,
+	MAX17042_VCELL          = 0x09,
+	MAX17042_CURRENT        = 0x0A,
+	MAX17042_AVG_CURRENT	= 0x0B,
+	MAX17042_SOCMIX	= 0x0D,
+	MAX17042_SOCAV		= 0x0E,
+	MAX17042_DESIGN_CAP	= 0x18,
+	MAX17042_AVG_VCELL	= 0x19,
+	MAX17042_CONFIG	= 0x1D,
+	MAX17042_VERSION	= 0x21,
+	MAX17042_LEARNCFG       = 0x28,
+	MAX17042_FILTERCFG	= 0x29,
+	MAX17042_RELAXCFG	= 0x2A,
+	MAX17042_MISCCFG	= 0x2B,
+	MAX17042_CGAIN		= 0x2E,
+	MAX17042_COFF		= 0x2F,
+	MAX17042_RCOMP0	= 0x38,
+	MAX17042_TEMPCO	= 0x39,
+	MAX17042_FSTAT		= 0x3D,
+	MAX17042_MLOCKReg1	= 0x62,
+	MAX17042_MLOCKReg2	= 0x63,
+	MAX17042_MODEL1         = 0x80,
+	MAX17042_MODEL2         = 0x90,
+	MAX17042_MODEL3         = 0xA0,
+	MAX17042_VFOCV		= 0xFB,
+	MAX17042_VFSOC		= 0xFF,
+
+	FG_NUM_OF_REGS = 0x100,
+};
+
+#define RCOMP0			0x0060
+#define TempCo			0x1015
+
+
+#define MAX17042_POR (1 << 1)
+
+#define MODEL_UNLOCK1		0x0059
+#define MODEL_UNLOCK2		0x00c4
+#define MODEL_LOCK1		0x0000
+#define MODEL_LOCK2		0x0000
+
+#define MAX17042_I2C_ADDR	(0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX17042_FG_H_ */
diff --git a/roms/u-boot/include/power/max77686_pmic.h b/roms/u-boot/include/power/max77686_pmic.h
new file mode 100644
index 000000000..82fe3509a
--- /dev/null
+++ b/roms/u-boot/include/power/max77686_pmic.h
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ */
+
+#ifndef __MAX77686_H_
+#define __MAX77686_H_
+
+#include <power/pmic.h>
+
+enum {
+	MAX77686_REG_PMIC_ID		= 0x0,
+	MAX77686_REG_PMIC_INTSRC,
+	MAX77686_REG_PMIC_INT1,
+	MAX77686_REG_PMIC_INT2,
+	MAX77686_REG_PMIC_INT1MSK,
+	MAX77686_REG_PMIC_INT2MSK,
+
+	MAX77686_REG_PMIC_STATUS1,
+	MAX77686_REG_PMIC_STATUS2,
+
+	MAX77686_REG_PMIC_PWRON,
+	MAX77686_REG_PMIC_ONOFFDELAY,
+	MAX77686_REG_PMIC_MRSTB,
+
+	MAX77686_REG_PMIC_BUCK1CRTL	= 0x10,
+	MAX77686_REG_PMIC_BUCK1OUT,
+	MAX77686_REG_PMIC_BUCK2CTRL1,
+	MAX77686_REG_PMIC_BUCK234FREQ,
+	MAX77686_REG_PMIC_BUCK2DVS1,
+	MAX77686_REG_PMIC_BUCK2DVS2,
+	MAX77686_REG_PMIC_BUCK2DVS3,
+	MAX77686_REG_PMIC_BUCK2DVS4,
+	MAX77686_REG_PMIC_BUCK2DVS5,
+	MAX77686_REG_PMIC_BUCK2DVS6,
+	MAX77686_REG_PMIC_BUCK2DVS7,
+	MAX77686_REG_PMIC_BUCK2DVS8,
+	MAX77686_REG_PMIC_BUCK3CTRL,
+	MAX77686_REG_PMIC_BUCK3DVS1	= 0x1e,
+	MAX77686_REG_PMIC_BUCK3DVS2,
+	MAX77686_REG_PMIC_BUCK3DVS3,
+	MAX77686_REG_PMIC_BUCK3DVS4,
+	MAX77686_REG_PMIC_BUCK3DVS5,
+	MAX77686_REG_PMIC_BUCK3DVS6,
+	MAX77686_REG_PMIC_BUCK3DVS7,
+	MAX77686_REG_PMIC_BUCK3DVS8,
+	MAX77686_REG_PMIC_BUCK4CTRL1,
+	MAX77686_REG_PMIC_BUCK4DVS1	= 0x28,
+	MAX77686_REG_PMIC_BUCK4DVS2,
+	MAX77686_REG_PMIC_BUCK4DVS3,
+	MAX77686_REG_PMIC_BUCK4DVS4,
+	MAX77686_REG_PMIC_BUCK4DVS5,
+	MAX77686_REG_PMIC_BUCK4DVS6,
+	MAX77686_REG_PMIC_BUCK4DVS7,
+	MAX77686_REG_PMIC_BUCK4DVS8,
+	MAX77686_REG_PMIC_BUCK5CTRL,
+	MAX77686_REG_PMIC_BUCK5OUT,
+	MAX77686_REG_PMIC_BUCK6CRTL,
+	MAX77686_REG_PMIC_BUCK6OUT,
+	MAX77686_REG_PMIC_BUCK7CRTL,
+	MAX77686_REG_PMIC_BUCK7OUT,
+	MAX77686_REG_PMIC_BUCK8CRTL,
+	MAX77686_REG_PMIC_BUCK8OUT,
+	MAX77686_REG_PMIC_BUCK9CRTL,
+	MAX77686_REG_PMIC_BUCK9OUT,
+
+	MAX77686_REG_PMIC_LDO1CTRL1	= 0x40,
+	MAX77686_REG_PMIC_LDO2CTRL1,
+	MAX77686_REG_PMIC_LDO3CTRL1,
+	MAX77686_REG_PMIC_LDO4CTRL1,
+	MAX77686_REG_PMIC_LDO5CTRL1,
+	MAX77686_REG_PMIC_LDO6CTRL1,
+	MAX77686_REG_PMIC_LDO7CTRL1,
+	MAX77686_REG_PMIC_LDO8CTRL1,
+	MAX77686_REG_PMIC_LDO9CTRL1,
+	MAX77686_REG_PMIC_LDO10CTRL1,
+	MAX77686_REG_PMIC_LDO11CTRL1,
+	MAX77686_REG_PMIC_LDO12CTRL1,
+	MAX77686_REG_PMIC_LDO13CTRL1,
+	MAX77686_REG_PMIC_LDO14CTRL1,
+	MAX77686_REG_PMIC_LDO15CTRL1,
+	MAX77686_REG_PMIC_LDO16CTRL1,
+	MAX77686_REG_PMIC_LDO17CTRL1,
+	MAX77686_REG_PMIC_LDO18CTRL1,
+	MAX77686_REG_PMIC_LDO19CTRL1,
+	MAX77686_REG_PMIC_LDO20CTRL1,
+	MAX77686_REG_PMIC_LDO21CTRL1,
+	MAX77686_REG_PMIC_LDO22CTRL1,
+	MAX77686_REG_PMIC_LDO23CTRL1,
+	MAX77686_REG_PMIC_LDO24CTRL1,
+	MAX77686_REG_PMIC_LDO25CTRL1,
+	MAX77686_REG_PMIC_LDO26CTRL1,
+	MAX77686_REG_PMIC_LDO1CTRL2,
+	MAX77686_REG_PMIC_LDO2CTRL2,
+	MAX77686_REG_PMIC_LDO3CTRL2,
+	MAX77686_REG_PMIC_LDO4CTRL2,
+	MAX77686_REG_PMIC_LDO5CTRL2,
+	MAX77686_REG_PMIC_LDO6CTRL2,
+	MAX77686_REG_PMIC_LDO7CTRL2,
+	MAX77686_REG_PMIC_LDO8CTRL2,
+	MAX77686_REG_PMIC_LDO9CTRL2,
+	MAX77686_REG_PMIC_LDO10CTRL2,
+	MAX77686_REG_PMIC_LDO11CTRL2,
+	MAX77686_REG_PMIC_LDO12CTRL2,
+	MAX77686_REG_PMIC_LDO13CTRL2,
+	MAX77686_REG_PMIC_LDO14CTRL2,
+	MAX77686_REG_PMIC_LDO15CTRL2,
+	MAX77686_REG_PMIC_LDO16CTRL2,
+	MAX77686_REG_PMIC_LDO17CTRL2,
+	MAX77686_REG_PMIC_LDO18CTRL2,
+	MAX77686_REG_PMIC_LDO19CTRL2,
+	MAX77686_REG_PMIC_LDO20CTRL2,
+	MAX77686_REG_PMIC_LDO21CTRL2,
+	MAX77686_REG_PMIC_LDO22CTRL2,
+	MAX77686_REG_PMIC_LDO23CTRL2,
+	MAX77686_REG_PMIC_LDO24CTRL2,
+	MAX77686_REG_PMIC_LDO25CTRL2,
+	MAX77686_REG_PMIC_LDO26CTRL2,
+
+	MAX77686_REG_PMIC_BBAT		= 0x7e,
+	MAX77686_REG_PMIC_32KHZ,
+
+	MAX77686_NUM_OF_REGS,
+};
+
+/* I2C device address for pmic max77686 */
+#define MAX77686_I2C_ADDR	(0x12 >> 1)
+#define MAX77686_LDO_NUM	26
+#define MAX77686_BUCK_NUM	9
+
+/* Drivers name */
+#define MAX77686_LDO_DRIVER	"max77686_ldo"
+#define MAX77686_BUCK_DRIVER	"max77686_buck"
+
+enum {
+	REG_DISABLE = 0,
+	REG_ENABLE
+};
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+enum {
+	OPMODE_OFF = 0,
+	OPMODE_LPM,
+	OPMODE_STANDBY,
+	OPMODE_STANDBY_LPM,
+	OPMODE_ON,
+};
+
+#ifdef CONFIG_POWER
+int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
+int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
+int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
+#endif
+
+#define MAX77686_LDO_VOLT_MAX_HEX	0x3f
+#define MAX77686_LDO_VOLT_MASK		0x3f
+#define MAX77686_LDO_MODE_MASK		0xc0
+#define MAX77686_LDO_MODE_OFF		(0x00 << 0x06)
+#define MAX77686_LDO_MODE_LPM		(0x01 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY	(0x01 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY_LPM	(0x02 << 0x06)
+#define MAX77686_LDO_MODE_ON		(0x03 << 0x06)
+#define MAX77686_BUCK234_VOLT_MAX_HEX	0xff
+#define MAX77686_BUCK234_VOLT_MASK	0xff
+#define MAX77686_BUCK_VOLT_MAX_HEX	0x3f
+#define MAX77686_BUCK_VOLT_MASK		0x3f
+#define MAX77686_BUCK_MODE_MASK		0x03
+#define MAX77686_BUCK_MODE_SHIFT_1	0x00
+#define MAX77686_BUCK_MODE_SHIFT_2	0x04
+#define MAX77686_BUCK_MODE_OFF		0x00
+#define MAX77686_BUCK_MODE_STANDBY	0x01
+#define MAX77686_BUCK_MODE_LPM		0x02
+#define MAX77686_BUCK_MODE_ON		0x03
+
+/* For regulator hex<->volt conversion */
+#define MAX77686_LDO_UV_MIN		800000 /* Minimum LDO uV value */
+#define MAX77686_LDO_UV_LSTEP		25000 /* uV lower value step */
+#define MAX77686_LDO_UV_HSTEP		50000 /* uV higher value step */
+#define MAX77686_BUCK_UV_LMIN		600000 /* Lower minimun BUCK value */
+#define MAX77686_BUCK_UV_HMIN		750000 /* Higher minimun BUCK value */
+#define MAX77686_BUCK_UV_LSTEP		12500  /* uV lower value step */
+#define MAX77686_BUCK_UV_HSTEP		50000  /* uV higher value step */
+
+/* Buck1 1 volt value */
+#define MAX77686_BUCK1OUT_1V	0x5
+/* Buck1 1.05 volt value */
+#define MAX77686_BUCK1OUT_1_05V    0x6
+#define MAX77686_BUCK1CTRL_EN	(3 << 0)
+/* Buck2 1.3 volt value */
+#define MAX77686_BUCK2DVS1_1_3V	0x38
+#define MAX77686_BUCK2CTRL_ON	(1 << 4)
+/* Buck3 1.0125 volt value */
+#define MAX77686_BUCK3DVS1_1_0125V	0x21
+#define MAX77686_BUCK3CTRL_ON	(1 << 4)
+/* Buck4 1.2 volt value */
+#define MAX77686_BUCK4DVS1_1_2V	0x30
+#define MAX77686_BUCK4CTRL_ON	(1 << 4)
+/* LDO2 1.5 volt value */
+#define MAX77686_LD02CTRL1_1_5V	0x1c
+/* LDO3 1.8 volt value */
+#define MAX77686_LD03CTRL1_1_8V	0x14
+/* LDO5 1.8 volt value */
+#define MAX77686_LD05CTRL1_1_8V	0x14
+/* LDO10 1.8 volt value */
+#define MAX77686_LD10CTRL1_1_8V	0x14
+/*
+ * MAX77686_REG_PMIC_32KHZ set to 32KH CP
+ * output is activated
+ */
+#define MAX77686_32KHCP_EN	(1 << 1)
+/*
+ * MAX77686_REG_PMIC_BBAT set to
+ * Back up batery charger on and
+ * limit voltage setting to 3.5v
+ */
+#define MAX77686_BBCHOSTEN	(1 << 0)
+#define MAX77686_BBCVS_3_5V	(3 << 3)
+#endif /* __MAX77686_PMIC_H_ */
diff --git a/roms/u-boot/include/power/max77693_fg.h b/roms/u-boot/include/power/max77693_fg.h
new file mode 100644
index 000000000..c2ae62231
--- /dev/null
+++ b/roms/u-boot/include/power/max77693_fg.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#ifndef __MAX77693_FG_H_
+#define __MAX77693_FG_H_
+
+/* MAX 77693 registers */
+enum {
+	MAX77693_STATUS		= 0x00,
+	MAX77693_SOCREP		= 0x06,
+	MAX77693_VCELL		= 0x09,
+	MAX77693_CURRENT	= 0x0A,
+	MAX77693_AVG_CURRENT	= 0x0B,
+	MAX77693_SOCMIX		= 0x0D,
+	MAX77693_SOCAV		= 0x0E,
+	MAX77693_DESIGN_CAP	= 0x18,
+	MAX77693_AVG_VCELL	= 0x19,
+	MAX77693_CONFIG		= 0x1D,
+	MAX77693_VERSION	= 0x21,
+	MAX77693_LEARNCFG	= 0x28,
+	MAX77693_FILTERCFG	= 0x29,
+	MAX77693_RELAXCFG	= 0x2A,
+	MAX77693_MISCCFG	= 0x2B,
+	MAX77693_CGAIN		= 0x2E,
+	MAX77693_COFF		= 0x2F,
+	MAX77693_RCOMP0		= 0x38,
+	MAX77693_TEMPCO		= 0x39,
+	MAX77693_FSTAT		= 0x3D,
+	MAX77693_VFOCV		= 0xEE,
+	MAX77693_VFSOC		= 0xFF,
+
+	FG_NUM_OF_REGS		= 0x100,
+};
+
+#define MAX77693_POR (1 << 1)
+
+#define MODEL_UNLOCK1		0x0059
+#define MODEL_UNLOCK2		0x00c4
+#define MODEL_LOCK1		0x0000
+#define MODEL_LOCK2		0x0000
+
+#define MAX77693_FUEL_I2C_ADDR	(0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX77693_FG_H_ */
diff --git a/roms/u-boot/include/power/max77693_muic.h b/roms/u-boot/include/power/max77693_muic.h
new file mode 100644
index 000000000..c9afab218
--- /dev/null
+++ b/roms/u-boot/include/power/max77693_muic.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#ifndef __MAX77693_MUIC_H_
+#define __MAX77693_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/*
+ * MUIC REGISTER
+ */
+
+#define MAX77693_MUIC_PREFIX	"max77693-muic:"
+
+/* MAX77693_MUIC_STATUS1 */
+#define MAX77693_MUIC_ADC_MASK	0x1F
+
+/* MAX77693_MUIC_STATUS2 */
+#define MAX77693_MUIC_CHG_NO		0x00
+#define MAX77693_MUIC_CHG_USB		0x01
+#define MAX77693_MUIC_CHG_USB_D		0x02
+#define MAX77693_MUIC_CHG_TA		0x03
+#define MAX77693_MUIC_CHG_TA_500	0x04
+#define MAX77693_MUIC_CHG_TA_1A		0x05
+#define MAX77693_MUIC_CHG_MASK		0x07
+
+/* MAX77693_MUIC_CONTROL1 */
+#define MAX77693_MUIC_CTRL1_DN1DP2	((0x1 << 3) | 0x1)
+#define MAX77693_MUIC_CTRL1_UT1UR2	((0x3 << 3) | 0x3)
+#define MAX77693_MUIC_CTRL1_ADN1ADP2	((0x4 << 3) | 0x4)
+#define MAX77693_MUIC_CTRL1_AUT1AUR2	((0x5 << 3) | 0x5)
+#define MAX77693_MUIC_CTRL1_MASK	0xC0
+
+#define MUIC_PATH_USB	0
+#define MUIC_PATH_UART	1
+
+#define MUIC_PATH_CP	0
+#define MUIC_PATH_AP	1
+
+enum muic_path {
+	MUIC_PATH_USB_CP,
+	MUIC_PATH_USB_AP,
+	MUIC_PATH_UART_CP,
+	MUIC_PATH_UART_AP,
+};
+
+/* MAX 777693 MUIC registers */
+enum {
+	MAX77693_MUIC_ID	= 0x00,
+	MAX77693_MUIC_INT1	= 0x01,
+	MAX77693_MUIC_INT2	= 0x02,
+	MAX77693_MUIC_INT3	= 0x03,
+	MAX77693_MUIC_STATUS1	= 0x04,
+	MAX77693_MUIC_STATUS2	= 0x05,
+	MAX77693_MUIC_STATUS3	= 0x06,
+	MAX77693_MUIC_INTMASK1	= 0x07,
+	MAX77693_MUIC_INTMASK2	= 0x08,
+	MAX77693_MUIC_INTMASK3	= 0x09,
+	MAX77693_MUIC_CDETCTRL	= 0x0A,
+	MAX77693_MUIC_CONTROL1	= 0x0C,
+	MAX77693_MUIC_CONTROL2	= 0x0D,
+	MAX77693_MUIC_CONTROL3	= 0x0E,
+
+	MUIC_NUM_OF_REGS	= 0x0F,
+};
+
+#define MAX77693_MUIC_I2C_ADDR	(0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX77693_MUIC_H_ */
diff --git a/roms/u-boot/include/power/max77693_pmic.h b/roms/u-boot/include/power/max77693_pmic.h
new file mode 100644
index 000000000..9e0e05c56
--- /dev/null
+++ b/roms/u-boot/include/power/max77693_pmic.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#ifndef __MAX77693_PMIC_H_
+#define __MAX77693_PMIC_H_
+
+#include <power/power_chrg.h>
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 2000
+
+#define MAX77693_CHG_PREFIX	"max77693-chg:"
+
+/* Registers */
+
+#define MAX77693_CHG_BASE	0xB0
+#define MAX77693_CHG_INT_OK	0xB2
+#define MAX77693_CHG_CNFG_00	0xB7
+#define MAX77693_CHG_CNFG_02	0xB9
+#define MAX77693_CHG_CNFG_06	0xBD
+#define MAX77693_SAFEOUT	0xC6
+
+#define PMIC_NUM_OF_REGS	0xC7
+
+#define MAX77693_CHG_DETBAT	(0x1 << 7)	/* MAX77693_CHG_INT_OK */
+#define MAX77693_CHG_MODE_ON	0x05		/* MAX77693_CHG_CNFG_00 */
+#define MAX77693_CHG_CC		0x3F		/* MAX77693_CHG_CNFG_02	*/
+#define MAX77693_CHG_LOCK	(0x0 << 2)	/* MAX77693_CHG_CNFG_06	*/
+#define MAX77693_CHG_UNLOCK	(0x3 << 2)	/* MAX77693_CHG_CNFG_06	*/
+
+#define MAX77693_ENSAFEOUT1	(1 << 6)
+#define MAX77693_ENSAFEOUT2	(1 << 7)
+
+#define MAX77693_PMIC_I2C_ADDR	(0xCC >> 1)
+
+int pmic_init_max77693(unsigned char bus);
+#endif /* __MAX77693_PMIC_H_ */
diff --git a/roms/u-boot/include/power/max8997_muic.h b/roms/u-boot/include/power/max8997_muic.h
new file mode 100644
index 000000000..e4ceab6f7
--- /dev/null
+++ b/roms/u-boot/include/power/max8997_muic.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX8997_MUIC_H_
+#define __MAX8997_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/* MAX8997_MUIC_STATUS2 */
+#define MAX8997_MUIC_CHG_NO	0x00
+#define MAX8997_MUIC_CHG_USB	0x01
+#define MAX8997_MUIC_CHG_USB_D	0x02
+#define MAX8997_MUIC_CHG_TA	0x03
+#define MAX8997_MUIC_CHG_TA_500 0x04
+#define MAX8997_MUIC_CHG_TA_1A	0x05
+#define MAX8997_MUIC_CHG_MASK	0x07
+
+/* MAX 8997 MUIC registers */
+enum {
+	MAX8997_MUIC_ID         = 0x00,
+	MAX8997_MUIC_INT1	= 0x01,
+	MAX8997_MUIC_INT2	= 0x02,
+	MAX8997_MUIC_INT3	= 0x03,
+	MAX8997_MUIC_STATUS1	= 0x04,
+	MAX8997_MUIC_STATUS2	= 0x05,
+	MAX8997_MUIC_STATUS3	= 0x06,
+	MAX8997_MUIC_INTMASK1	= 0x07,
+	MAX8997_MUIC_INTMASK2	= 0x08,
+	MAX8997_MUIC_INTMASK3	= 0x09,
+	MAX8997_MUIC_CDETCTRL	= 0x0A,
+	MAX8997_MUIC_CONTROL1	= 0x0C,
+	MAX8997_MUIC_CONTROL2	= 0x0D,
+	MAX8997_MUIC_CONTROL3	= 0x0E,
+
+	MUIC_NUM_OF_REGS = 0x0F,
+};
+
+#define MAX8997_MUIC_I2C_ADDR	(0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX8997_MUIC_H_ */
diff --git a/roms/u-boot/include/power/max8997_pmic.h b/roms/u-boot/include/power/max8997_pmic.h
new file mode 100644
index 000000000..956eebb96
--- /dev/null
+++ b/roms/u-boot/include/power/max8997_pmic.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX8997_PMIC_H_
+#define __MAX8997_PMIC_H_
+
+/* MAX 8997 registers */
+enum {
+	MAX8997_REG_PMIC_ID0	= 0x00,
+	MAX8997_REG_PMIC_ID1	= 0x01,
+	MAX8997_REG_INTSRC	= 0x02,
+	MAX8997_REG_INT1	= 0x03,
+	MAX8997_REG_INT2	= 0x04,
+	MAX8997_REG_INT3	= 0x05,
+	MAX8997_REG_INT4	= 0x06,
+
+	MAX8997_REG_INT1MSK	= 0x08,
+	MAX8997_REG_INT2MSK	= 0x09,
+	MAX8997_REG_INT3MSK	= 0x0a,
+	MAX8997_REG_INT4MSK	= 0x0b,
+
+	MAX8997_REG_STATUS1	= 0x0d,
+	MAX8997_REG_STATUS2	= 0x0e,
+	MAX8997_REG_STATUS3	= 0x0f,
+	MAX8997_REG_STATUS4	= 0x10,
+
+	MAX8997_REG_MAINCON1	= 0x13,
+	MAX8997_REG_MAINCON2	= 0x14,
+	MAX8997_REG_BUCKRAMP	= 0x15,
+
+	MAX8997_REG_BUCK1CTRL	= 0x18,
+	MAX8997_REG_BUCK1DVS1	= 0x19,
+	MAX8997_REG_BUCK1DVS2	= 0x1a,
+	MAX8997_REG_BUCK1DVS3	= 0x1b,
+	MAX8997_REG_BUCK1DVS4	= 0x1c,
+	MAX8997_REG_BUCK1DVS5	= 0x1d,
+	MAX8997_REG_BUCK1DVS6	= 0x1e,
+	MAX8997_REG_BUCK1DVS7	= 0x1f,
+	MAX8997_REG_BUCK1DVS8	= 0x20,
+	MAX8997_REG_BUCK2CTRL	= 0x21,
+	MAX8997_REG_BUCK2DVS1	= 0x22,
+	MAX8997_REG_BUCK2DVS2	= 0x23,
+	MAX8997_REG_BUCK2DVS3	= 0x24,
+	MAX8997_REG_BUCK2DVS4	= 0x25,
+	MAX8997_REG_BUCK2DVS5	= 0x26,
+	MAX8997_REG_BUCK2DVS6	= 0x27,
+	MAX8997_REG_BUCK2DVS7	= 0x28,
+	MAX8997_REG_BUCK2DVS8	= 0x29,
+	MAX8997_REG_BUCK3CTRL	= 0x2a,
+	MAX8997_REG_BUCK3DVS	= 0x2b,
+	MAX8997_REG_BUCK4CTRL	= 0x2c,
+	MAX8997_REG_BUCK4DVS	= 0x2d,
+	MAX8997_REG_BUCK5CTRL	= 0x2e,
+	MAX8997_REG_BUCK5DVS1	= 0x2f,
+	MAX8997_REG_BUCK5DVS2	= 0x30,
+	MAX8997_REG_BUCK5DVS3	= 0x31,
+	MAX8997_REG_BUCK5DVS4	= 0x32,
+	MAX8997_REG_BUCK5DVS5	= 0x33,
+	MAX8997_REG_BUCK5DVS6	= 0x34,
+	MAX8997_REG_BUCK5DVS7	= 0x35,
+	MAX8997_REG_BUCK5DVS8	= 0x36,
+	MAX8997_REG_BUCK6CTRL	= 0x37,
+	MAX8997_REG_BUCK6BPSKIPCTRL	= 0x38,
+	MAX8997_REG_BUCK7CTRL	= 0x39,
+	MAX8997_REG_BUCK7DVS	= 0x3a,
+	MAX8997_REG_LDO1CTRL	= 0x3b,
+	MAX8997_REG_LDO2CTRL	= 0x3c,
+	MAX8997_REG_LDO3CTRL	= 0x3d,
+	MAX8997_REG_LDO4CTRL	= 0x3e,
+	MAX8997_REG_LDO5CTRL	= 0x3f,
+	MAX8997_REG_LDO6CTRL	= 0x40,
+	MAX8997_REG_LDO7CTRL	= 0x41,
+	MAX8997_REG_LDO8CTRL	= 0x42,
+	MAX8997_REG_LDO9CTRL	= 0x43,
+	MAX8997_REG_LDO10CTRL	= 0x44,
+	MAX8997_REG_LDO11CTRL	= 0x45,
+	MAX8997_REG_LDO12CTRL	= 0x46,
+	MAX8997_REG_LDO13CTRL	= 0x47,
+	MAX8997_REG_LDO14CTRL	= 0x48,
+	MAX8997_REG_LDO15CTRL	= 0x49,
+	MAX8997_REG_LDO16CTRL	= 0x4a,
+	MAX8997_REG_LDO17CTRL	= 0x4b,
+	MAX8997_REG_LDO18CTRL	= 0x4c,
+	MAX8997_REG_LDO21CTRL	= 0x4d,
+
+	MAX8997_REG_MBCCTRL1	= 0x50,
+	MAX8997_REG_MBCCTRL2	= 0x51,
+	MAX8997_REG_MBCCTRL3	= 0x52,
+	MAX8997_REG_MBCCTRL4	= 0x53,
+	MAX8997_REG_MBCCTRL5	= 0x54,
+	MAX8997_REG_MBCCTRL6	= 0x55,
+	MAX8997_REG_OTPCGHCVS	= 0x56,
+
+	MAX8997_REG_SAFEOUTCTRL = 0x5a,
+
+	MAX8997_REG_LBCNFG1	= 0x5e,
+	MAX8997_REG_LBCNFG2	= 0x5f,
+	MAX8997_REG_BBCCTRL	= 0x60,
+
+	MAX8997_REG_FLASH1_CUR	= 0x63, /* 0x63 ~ 0x6e for FLASH */
+	MAX8997_REG_FLASH2_CUR	= 0x64,
+	MAX8997_REG_MOVIE_CUR	= 0x65,
+	MAX8997_REG_GSMB_CUR	= 0x66,
+	MAX8997_REG_BOOST_CNTL	= 0x67,
+	MAX8997_REG_LEN_CNTL	= 0x68,
+	MAX8997_REG_FLASH_CNTL	= 0x69,
+	MAX8997_REG_WDT_CNTL	= 0x6a,
+	MAX8997_REG_MAXFLASH1	= 0x6b,
+	MAX8997_REG_MAXFLASH2	= 0x6c,
+	MAX8997_REG_FLASHSTATUS	= 0x6d,
+	MAX8997_REG_FLASHSTATUSMASK	= 0x6e,
+
+	MAX8997_REG_GPIOCNTL1	= 0x70,
+	MAX8997_REG_GPIOCNTL2	= 0x71,
+	MAX8997_REG_GPIOCNTL3	= 0x72,
+	MAX8997_REG_GPIOCNTL4	= 0x73,
+	MAX8997_REG_GPIOCNTL5	= 0x74,
+	MAX8997_REG_GPIOCNTL6	= 0x75,
+	MAX8997_REG_GPIOCNTL7	= 0x76,
+	MAX8997_REG_GPIOCNTL8	= 0x77,
+	MAX8997_REG_GPIOCNTL9	= 0x78,
+	MAX8997_REG_GPIOCNTL10	= 0x79,
+	MAX8997_REG_GPIOCNTL11	= 0x7a,
+	MAX8997_REG_GPIOCNTL12	= 0x7b,
+
+	MAX8997_REG_LDO1CONFIG	= 0x80,
+	MAX8997_REG_LDO2CONFIG	= 0x81,
+	MAX8997_REG_LDO3CONFIG	= 0x82,
+	MAX8997_REG_LDO4CONFIG	= 0x83,
+	MAX8997_REG_LDO5CONFIG	= 0x84,
+	MAX8997_REG_LDO6CONFIG	= 0x85,
+	MAX8997_REG_LDO7CONFIG	= 0x86,
+	MAX8997_REG_LDO8CONFIG	= 0x87,
+	MAX8997_REG_LDO9CONFIG	= 0x88,
+	MAX8997_REG_LDO10CONFIG	= 0x89,
+	MAX8997_REG_LDO11CONFIG	= 0x8a,
+	MAX8997_REG_LDO12CONFIG	= 0x8b,
+	MAX8997_REG_LDO13CONFIG	= 0x8c,
+	MAX8997_REG_LDO14CONFIG	= 0x8d,
+	MAX8997_REG_LDO15CONFIG	= 0x8e,
+	MAX8997_REG_LDO16CONFIG	= 0x8f,
+	MAX8997_REG_LDO17CONFIG	= 0x90,
+	MAX8997_REG_LDO18CONFIG	= 0x91,
+	MAX8997_REG_LDO21CONFIG	= 0x92,
+
+	MAX8997_REG_DVSOKTIMER1	= 0x97,
+	MAX8997_REG_DVSOKTIMER2	= 0x98,
+	MAX8997_REG_DVSOKTIMER4	= 0x99,
+	MAX8997_REG_DVSOKTIMER5	= 0x9a,
+
+	PMIC_NUM_OF_REGS = 0x9b,
+};
+
+#define ACTDISSAFEO1 (1 << 4)
+#define ACTDISSAFEO2 (1 << 5)
+#define ENSAFEOUT1 (1 << 6)
+#define ENSAFEOUT2 (1 << 7)
+
+#define ENBUCK (1 << 0)
+#define ACTIVE_DISCHARGE (1 << 3)
+#define GNSLCT (1 << 2)
+#define LDO_ADE (1 << 1)
+#define SAFEOUT_4_85V 0x00
+#define SAFEOUT_4_90V 0x01
+#define SAFEOUT_4_95V 0x02
+#define SAFEOUT_3_30V 0x03
+
+/* Charger */
+#define DETBAT                  (1 << 2)
+#define MBCICHFCSET             (1 << 4)
+#define MBCHOSTEN               (1 << 6)
+#define VCHGR_FC                (1 << 7)
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 950
+#define CHARGER_CURRENT_RESOLUTION 50
+
+#define MAX8997_I2C_ADDR        (0xCC >> 1)
+#define MAX8997_RTC_ADDR	(0x0C >> 1)
+#define MAX8997_MUIC_ADDR	(0x4A >> 1)
+#define MAX8997_FG_ADDR	(0x6C >> 1)
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON = 1,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+#define MAX8997_LDO_MAX_VAL 0x3F
+unsigned char max8997_reg_ldo(int uV);
+#endif /* __MAX8997_PMIC_H_ */
diff --git a/roms/u-boot/include/power/max8998_pmic.h b/roms/u-boot/include/power/max8998_pmic.h
new file mode 100644
index 000000000..b1a87d66a
--- /dev/null
+++ b/roms/u-boot/include/power/max8998_pmic.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX8998_PMIC_H_
+#define __MAX8998_PMIC_H_
+
+/* MAX 8998 registers */
+enum {
+	MAX8998_REG_IRQ1,
+	MAX8998_REG_IRQ2,
+	MAX8998_REG_IRQ3,
+	MAX8998_REG_IRQ4,
+	MAX8998_REG_IRQM1,
+	MAX8998_REG_IRQM2,
+	MAX8998_REG_IRQM3,
+	MAX8998_REG_IRQM4,
+	MAX8998_REG_STATUS1,
+	MAX8998_REG_STATUS2,
+	MAX8998_REG_STATUSM1,
+	MAX8998_REG_STATUSM2,
+	MAX8998_REG_CHGR1,
+	MAX8998_REG_CHGR2,
+	MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
+	MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
+	MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
+	MAX8998_REG_ONOFF1,
+	MAX8998_REG_ONOFF2,
+	MAX8998_REG_ONOFF3,
+	MAX8998_REG_ONOFF4,
+	MAX8998_REG_BUCK1_VOLTAGE1,
+	MAX8998_REG_BUCK1_VOLTAGE2,
+	MAX8998_REG_BUCK1_VOLTAGE3,
+	MAX8998_REG_BUCK1_VOLTAGE4,
+	MAX8998_REG_BUCK2_VOLTAGE1,
+	MAX8998_REG_BUCK2_VOLTAGE2,
+	MAX8998_REG_BUCK3,
+	MAX8998_REG_BUCK4,
+	MAX8998_REG_LDO2_LDO3,
+	MAX8998_REG_LDO4,
+	MAX8998_REG_LDO5,
+	MAX8998_REG_LDO6,
+	MAX8998_REG_LDO7,
+	MAX8998_REG_LDO8_LDO9,
+	MAX8998_REG_LDO10_LDO11,
+	MAX8998_REG_LDO12,
+	MAX8998_REG_LDO13,
+	MAX8998_REG_LDO14,
+	MAX8998_REG_LDO15,
+	MAX8998_REG_LDO16,
+	MAX8998_REG_LDO17,
+	MAX8998_REG_BKCHR,
+	MAX8998_REG_LBCNFG1,
+	MAX8998_REG_LBCNFG2,
+	PMIC_NUM_OF_REGS,
+};
+
+#define MAX8998_LDO3		(1 << 2)
+#define MAX8998_LDO4		(1 << 1)
+#define MAX8998_LDO7		(1 << 6)
+#define MAX8998_LDO8		(1 << 5)
+#define MAX8998_LDO17		(1 << 4)
+#define MAX8998_SAFEOUT1	(1 << 4)
+
+#define MAX8998_I2C_ADDR        (0xCC >> 1)
+
+enum { LDO_OFF, LDO_ON };
+
+#endif /* __MAX8998_PMIC_H_ */
diff --git a/roms/u-boot/include/power/mc34vr500_pmic.h b/roms/u-boot/include/power/mc34vr500_pmic.h
new file mode 100644
index 000000000..d2edda689
--- /dev/null
+++ b/roms/u-boot/include/power/mc34vr500_pmic.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+ */
+
+#ifndef __MC34VR500_H_
+#define __MC34VR500_H_
+
+#include <power/pmic.h>
+
+#define MC34VR500_I2C_ADDR	0x08
+
+/* Drivers name */
+#define MC34VR500_REGULATOR_DRIVER	"mc34vr500_regulator"
+
+/* Register map */
+enum {
+	MC34VR500_DEVICEID		= 0x00,
+
+	MC34VR500_SILICONREVID		= 0x03,
+	MC34VR500_FABID,
+	MC34VR500_INTSTAT0,
+	MC34VR500_INTMASK0,
+	MC34VR500_INTSENSE0,
+	MC34VR500_INTSTAT1,
+	MC34VR500_INTMASK1,
+	MC34VR500_INTSENSE1,
+
+	MC34VR500_INTSTAT4		= 0x11,
+	MC34VR500_INTMASK4,
+	MC34VR500_INTSENSE4,
+
+	MC34VR500_PWRCTL		= 0x1B,
+
+	MC34VR500_SW1VOLT		= 0x2E,
+	MC34VR500_SW1STBY,
+	MC34VR500_SW1OFF,
+	MC34VR500_SW1MODE,
+	MC34VR500_SW1CONF,
+	MC34VR500_SW2VOLT,
+	MC34VR500_SW2STBY,
+	MC34VR500_SW2OFF,
+	MC34VR500_SW2MODE,
+	MC34VR500_SW2CONF,
+
+	MC34VR500_SW3VOLT		= 0x3C,
+	MC34VR500_SW3STBY,
+	MC34VR500_SW3OFF,
+	MC34VR500_SW3MODE,
+	MC34VR500_SW3CONF,
+
+	MC34VR500_SW4VOLT		= 0x4A,
+	MC34VR500_SW4STBY,
+	MC34VR500_SW4OFF,
+	MC34VR500_SW4MODE,
+	MC34VR500_SW4CONF,
+
+	MC34VR500_REFOUTCRTRL		= 0x6A,
+
+	MC34VR500_LDO1CTL		= 0x6D,
+	MC34VR500_LDO2CTL,
+	MC34VR500_LDO3CTL,
+	MC34VR500_LDO4CTL,
+	MC34VR500_LDO5CTL,
+
+	MC34VR500_PAGE_REGISTER		= 0x7F,
+
+	/* Internal RAM */
+	MC34VR500_SW1_VOLT		= 0xA8,
+	MC34VR500_SW1_SEQ,
+	MC34VR500_SW1_CONFIG,
+
+	MC34VR500_SW2_VOLT		= 0xAC,
+	MC34VR500_SW2_SEQ,
+	MC34VR500_SW2_CONFIG,
+
+	MC34VR500_SW3_VOLT		= 0xB0,
+	MC34VR500_SW3_SEQ,
+	MC34VR500_SW3_CONFIG,
+
+	MC34VR500_SW4_VOLT		= 0xB8,
+	MC34VR500_SW4_SEQ,
+	MC34VR500_SW4_CONFIG,
+
+	MC34VR500_REFOUT_SEQ		= 0xC4,
+
+	MC34VR500_LDO1_VOLT		= 0xCC,
+	MC34VR500_LDO1_SEQ,
+
+	MC34VR500_LDO2_VOLT		= 0xD0,
+	MC34VR500_LDO2_SEQ,
+
+	MC34VR500_LDO3_VOLT		= 0xD4,
+	MC34VR500_LDO3_SEQ,
+
+	MC34VR500_LDO4_VOLT		= 0xD8,
+	MC34VR500_LDO4_SEQ,
+
+	MC34VR500_LDO5_VOLT		= 0xDC,
+	MC34VR500_LDO5_SEQ,
+
+	MC34VR500_PU_CONFIG1		= 0xE0,
+
+	MC34VR500_TBB_POR		= 0xE4,
+
+	MC34VR500_PWRGD_EN		= 0xE8,
+
+	MC34VR500_NUM_OF_REGS,
+};
+
+/* Registor offset based on SWxVOLT register */
+#define MC34VR500_VOLT_OFFSET	0
+#define MC34VR500_STBY_OFFSET	1
+#define MC34VR500_OFF_OFFSET	2
+#define MC34VR500_MODE_OFFSET	3
+#define MC34VR500_CONF_OFFSET	4
+
+#define SW_MODE_MASK	0xf
+#define SW_MODE_SHIFT	0
+
+#define LDO_VOL_MASK	0xf
+#define LDO_EN		(1 << 4)
+#define LDO_MODE_SHIFT	4
+#define LDO_MODE_MASK	(1 << 4)
+#define LDO_MODE_OFF	0
+#define LDO_MODE_ON	1
+
+#define REFOUTEN	(1 << 4)
+
+/*
+ * Regulator Mode Control
+ *
+ * OFF: The regulator is switched off and the output voltage is discharged.
+ * PFM: In this mode, the regulator is always in PFM mode, which is useful
+ *      at light loads for optimized efficiency.
+ * PWM: In this mode, the regulator is always in PWM mode operation
+ *	regardless of load conditions.
+ * APS: In this mode, the regulator moves automatically between pulse
+ *	skipping mode and PWM mode depending on load conditions.
+ *
+ * SWxMODE[3:0]
+ * Normal Mode  |  Standby Mode	|      value
+ *   OFF		OFF		0x0
+ *   PWM		OFF		0x1
+ *   PFM		OFF		0x3
+ *   APS		OFF		0x4
+ *   PWM		PWM		0x5
+ *   PWM		APS		0x6
+ *   APS		APS		0x8
+ *   APS		PFM		0xc
+ *   PWM		PFM		0xd
+ */
+#define OFF_OFF		0x0
+#define PWM_OFF		0x1
+#define PFM_OFF		0x3
+#define APS_OFF		0x4
+#define PWM_PWM		0x5
+#define PWM_APS		0x6
+#define APS_APS		0x8
+#define APS_PFM		0xc
+#define PWM_PFM		0xd
+
+enum swx {
+	SW1 = 0,
+	SW2,
+	SW3,
+	SW4,
+};
+
+int mc34vr500_get_sw_volt(uint8_t sw);
+int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt);
+int power_mc34vr500_init(unsigned char bus);
+#endif /* __MC34VR500_PMIC_H_ */
diff --git a/roms/u-boot/include/power/mp5416.h b/roms/u-boot/include/power/mp5416.h
new file mode 100644
index 000000000..dc096fed3
--- /dev/null
+++ b/roms/u-boot/include/power/mp5416.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2020 Gateworks Corporation */
+
+#ifndef MP5416_H_
+#define MP5416_H_
+
+#define MP6416_REGULATOR_DRIVER "mp5416_regulator"
+
+enum {
+	MP5416_CTL0		= 0x00,
+	MP5416_CTL1		= 0x01,
+	MP5416_CTL2		= 0x02,
+	MP5416_ILIMIT		= 0x03,
+	MP5416_VSET_SW1		= 0x04,
+	MP5416_VSET_SW2		= 0x05,
+	MP5416_VSET_SW3		= 0x06,
+	MP5416_VSET_SW4		= 0x07,
+	MP5416_VSET_LDO2	= 0x08,
+	MP5416_VSET_LDO3	= 0x09,
+	MP5416_VSET_LDO4	= 0x0a,
+	MP5416_VSET_LDO5	= 0x0b,
+	MP5416_STATUS1		= 0x0d,
+	MP5416_STATUS2		= 0x0e,
+	MP5416_STATUS3		= 0x0f,
+	MP5416_ID2		= 0x11,
+	MP5416_NUM_OF_REGS	= 0x12,
+};
+
+#define MP5416_VSET_EN          BIT(7)
+#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
+#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
+#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500)
+#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000)
+#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500)
+#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000)
+
+#endif
diff --git a/roms/u-boot/include/power/palmas.h b/roms/u-boot/include/power/palmas.h
new file mode 100644
index 000000000..df5f15c5b
--- /dev/null
+++ b/roms/u-boot/include/power/palmas.h
@@ -0,0 +1,26 @@
+#define	PALMAS		0x0
+#define TPS659038	0x1
+#define TPS65917	0x2
+
+/* I2C device address for pmic palmas */
+#define PALMAS_I2C_ADDR	(0x12 >> 1)
+#define PALMAS_LDO_NUM		11
+#define PALMAS_SMPS_NUM	8
+
+/* Drivers name */
+#define PALMAS_LDO_DRIVER     "palmas_ldo"
+#define PALMAS_SMPS_DRIVER    "palmas_smps"
+
+#define PALMAS_SMPS_VOLT_MASK		0x7F
+#define PALMAS_SMPS_RANGE_MASK		0x80
+#define PALMAS_SMPS_VOLT_MAX_HEX	0x7F
+#define PALMAS_SMPS_VOLT_MAX		3300000
+#define PALMAS_SMPS_MODE_MASK		0x3
+#define	PALMAS_SMPS_STATUS_MASK		0x30
+
+#define PALMAS_LDO_VOLT_MASK    0x3F
+#define PALMAS_LDO_VOLT_MAX_HEX 0x3F
+#define PALMAS_LDO_VOLT_MAX     3300000
+#define PALMAS_LDO_MODE_MASK	0x1
+#define PALMAS_LDO_STATUS_MASK	0x10
+#define PALMAS_LDO_BYPASS_EN	0x40
diff --git a/roms/u-boot/include/power/pca9450.h b/roms/u-boot/include/power/pca9450.h
new file mode 100644
index 000000000..27703bb1f
--- /dev/null
+++ b/roms/u-boot/include/power/pca9450.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef PCA9450_H_
+#define PCA9450_H_
+
+#define PCA9450_REGULATOR_DRIVER "pca9450_regulator"
+
+enum {
+	PCA9450_REG_DEV_ID      = 0x00,
+	PCA9450_INT1            = 0x01,
+	PCA9450_INT1_MSK        = 0x02,
+	PCA9450_STATUS1         = 0x03,
+	PCA9450_STATUS2         = 0x04,
+	PCA9450_PWRON_STAT      = 0x05,
+	PCA9450_SW_RST          = 0x06,
+	PCA9450_PWR_CTRL        = 0x07,
+	PCA9450_RESET_CTRL      = 0x08,
+	PCA9450_CONFIG1         = 0x09,
+	PCA9450_CONFIG2         = 0x0A,
+	PCA9450_BUCK123_DVS     = 0x0C,
+	PCA9450_BUCK1OUT_LIMIT  = 0x0D,
+	PCA9450_BUCK2OUT_LIMIT  = 0x0E,
+	PCA9450_BUCK3OUT_LIMIT  = 0x0F,
+	PCA9450_BUCK1CTRL       = 0x10,
+	PCA9450_BUCK1OUT_DVS0   = 0x11,
+	PCA9450_BUCK1OUT_DVS1   = 0x12,
+	PCA9450_BUCK2CTRL       = 0x13,
+	PCA9450_BUCK2OUT_DVS0   = 0x14,
+	PCA9450_BUCK2OUT_DVS1   = 0x15,
+	PCA9450_BUCK3CTRL       = 0x16,
+	PCA9450_BUCK3OUT_DVS0   = 0x17,
+	PCA9450_BUCK3OUT_DVS1   = 0x18,
+	PCA9450_BUCK4CTRL       = 0x19,
+	PCA9450_BUCK4OUT        = 0x1A,
+	PCA9450_BUCK5CTRL       = 0x1B,
+	PCA9450_BUCK5OUT        = 0x1C,
+	PCA9450_BUCK6CTRL       = 0x1D,
+	PCA9450_BUCK6OUT        = 0x1E,
+	PCA9450_LDO_AD_CTRL     = 0x20,
+	PCA9450_LDO1CTRL        = 0x21,
+	PCA9450_LDO2CTRL        = 0x22,
+	PCA9450_LDO3CTRL        = 0x23,
+	PCA9450_LDO4CTRL        = 0x24,
+	PCA9450_LDO5CTRL_L      = 0x25,
+	PCA9450_LDO5CTRL_H      = 0x26,
+	PCA9450_LOADSW_CTRL     = 0x2A,
+	PCA9450_VRFLT1_STS      = 0x2B,
+	PCA9450_VRFLT2_STS      = 0x2C,
+	PCA9450_VRFLT1_MASK     = 0x2D,
+	PCA9450_VRFLT2_MASK     = 0x2E,
+	PCA9450_REG_NUM,
+};
+
+int power_pca9450_init(unsigned char bus, unsigned char addr);
+
+#endif
diff --git a/roms/u-boot/include/power/pfuze100_pmic.h b/roms/u-boot/include/power/pfuze100_pmic.h
new file mode 100644
index 000000000..f4383ed77
--- /dev/null
+++ b/roms/u-boot/include/power/pfuze100_pmic.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014 Gateworks Corporation
+ *  Tim Harvey <tharvey@gateworks.com>
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* Device ID */
+enum {PFUZE100 = 0x10, PFUZE200 = 0x11, PFUZE3000 = 0x30};
+
+#define PFUZE100_REGULATOR_DRIVER	"pfuze100_regulator"
+
+/* PFUZE100 registers */
+enum {
+	PFUZE100_DEVICEID	= 0x00,
+	PFUZE100_REVID		= 0x03,
+	PFUZE100_FABID		= 0x04,
+
+	PFUZE100_SW1ABVOL	= 0x20,
+	PFUZE100_SW1ABSTBY	= 0x21,
+	PFUZE100_SW1ABOFF	= 0x22,
+	PFUZE100_SW1ABMODE	= 0x23,
+	PFUZE100_SW1ABCONF	= 0x24,
+	PFUZE100_SW1CVOL	= 0x2e,
+	PFUZE100_SW1CSTBY	= 0x2f,
+	PFUZE100_SW1COFF	= 0x30,
+	PFUZE100_SW1CMODE	= 0x31,
+	PFUZE100_SW1CCONF	= 0x32,
+	PFUZE100_SW2VOL		= 0x35,
+	PFUZE100_SW2STBY	= 0x36,
+	PFUZE100_SW2OFF		= 0x37,
+	PFUZE100_SW2MODE	= 0x38,
+	PFUZE100_SW2CONF	= 0x39,
+	PFUZE100_SW3AVOL	= 0x3c,
+	PFUZE100_SW3ASTBY	= 0x3D,
+	PFUZE100_SW3AOFF	= 0x3E,
+	PFUZE100_SW3AMODE	= 0x3F,
+	PFUZE100_SW3ACONF	= 0x40,
+	PFUZE100_SW3BVOL	= 0x43,
+	PFUZE100_SW3BSTBY	= 0x44,
+	PFUZE100_SW3BOFF	= 0x45,
+	PFUZE100_SW3BMODE	= 0x46,
+	PFUZE100_SW3BCONF	= 0x47,
+	PFUZE100_SW4VOL		= 0x4a,
+	PFUZE100_SW4STBY	= 0x4b,
+	PFUZE100_SW4OFF		= 0x4c,
+	PFUZE100_SW4MODE	= 0x4d,
+	PFUZE100_SW4CONF	= 0x4e,
+	PFUZE100_SWBSTCON1	= 0x66,
+	PFUZE100_VREFDDRCON	= 0x6a,
+	PFUZE100_VSNVSVOL	= 0x6b,
+	PFUZE100_VGEN1VOL	= 0x6c,
+	PFUZE100_VGEN2VOL	= 0x6d,
+	PFUZE100_VGEN3VOL	= 0x6e,
+	PFUZE100_VGEN4VOL	= 0x6f,
+	PFUZE100_VGEN5VOL	= 0x70,
+	PFUZE100_VGEN6VOL	= 0x71,
+
+	PFUZE100_NUM_OF_REGS	= 0x7f,
+};
+
+/* Registor offset based on VOLT register */
+#define PFUZE100_VOL_OFFSET	0
+#define PFUZE100_STBY_OFFSET	1
+#define PFUZE100_OFF_OFFSET	2
+#define PFUZE100_MODE_OFFSET	3
+#define PFUZE100_CONF_OFFSET	4
+
+/*
+ * Buck Regulators
+ */
+
+#define PFUZE100_SW1ABC_SETP(x)	((x - 3000) / 250)
+
+/* SW1A/B/C Output Voltage Configuration */
+#define SW1x_0_300V 0
+#define SW1x_0_325V 1
+#define SW1x_0_350V 2
+#define SW1x_0_375V 3
+#define SW1x_0_400V 4
+#define SW1x_0_425V 5
+#define SW1x_0_450V 6
+#define SW1x_0_475V 7
+#define SW1x_0_500V 8
+#define SW1x_0_525V 9
+#define SW1x_0_550V 10
+#define SW1x_0_575V 11
+#define SW1x_0_600V 12
+#define SW1x_0_625V 13
+#define SW1x_0_650V 14
+#define SW1x_0_675V 15
+#define SW1x_0_700V 16
+#define SW1x_0_725V 17
+#define SW1x_0_750V 18
+#define SW1x_0_775V 19
+#define SW1x_0_800V 20
+#define SW1x_0_825V 21
+#define SW1x_0_850V 22
+#define SW1x_0_875V 23
+#define SW1x_0_900V 24
+#define SW1x_0_925V 25
+#define SW1x_0_950V 26
+#define SW1x_0_975V 27
+#define SW1x_1_000V 28
+#define SW1x_1_025V 29
+#define SW1x_1_050V 30
+#define SW1x_1_075V 31
+#define SW1x_1_100V 32
+#define SW1x_1_125V 33
+#define SW1x_1_150V 34
+#define SW1x_1_175V 35
+#define SW1x_1_200V 36
+#define SW1x_1_225V 37
+#define SW1x_1_250V 38
+#define SW1x_1_275V 39
+#define SW1x_1_300V 40
+#define SW1x_1_325V 41
+#define SW1x_1_350V 42
+#define SW1x_1_375V 43
+#define SW1x_1_400V 44
+#define SW1x_1_425V 45
+#define SW1x_1_450V 46
+#define SW1x_1_475V 47
+#define SW1x_1_500V 48
+#define SW1x_1_525V 49
+#define SW1x_1_550V 50
+#define SW1x_1_575V 51
+#define SW1x_1_600V 52
+#define SW1x_1_625V 53
+#define SW1x_1_650V 54
+#define SW1x_1_675V 55
+#define SW1x_1_700V 56
+#define SW1x_1_725V 57
+#define SW1x_1_750V 58
+#define SW1x_1_775V 59
+#define SW1x_1_800V 60
+#define SW1x_1_825V 61
+#define SW1x_1_850V 62
+#define SW1x_1_875V 63
+
+#define SW1x_NORMAL_MASK  0x3f
+#define SW1x_STBY_MASK    0x3f
+#define SW1x_OFF_MASK     0x3f
+
+#define SW_MODE_MASK	0xf
+#define SW_MODE_SHIFT	0
+
+#define SW1xCONF_DVSSPEED_MASK 0xc0
+#define SW1xCONF_DVSSPEED_2US  0x00
+#define SW1xCONF_DVSSPEED_4US  0x40
+#define SW1xCONF_DVSSPEED_8US  0x80
+#define SW1xCONF_DVSSPEED_16US 0xc0
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V	0
+#define LDOA_0_85V	1
+#define LDOA_0_90V	2
+#define LDOA_0_95V	3
+#define LDOA_1_00V	4
+#define LDOA_1_05V	5
+#define LDOA_1_10V	6
+#define LDOA_1_15V	7
+#define LDOA_1_20V	8
+#define LDOA_1_25V	9
+#define LDOA_1_30V	10
+#define LDOA_1_35V	11
+#define LDOA_1_40V	12
+#define LDOA_1_45V	13
+#define LDOA_1_50V	14
+#define LDOA_1_55V	15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V	0
+#define LDOB_1_90V	1
+#define LDOB_2_00V	2
+#define LDOB_2_10V	3
+#define LDOB_2_20V	4
+#define LDOB_2_30V	5
+#define LDOB_2_40V	6
+#define LDOB_2_50V	7
+#define LDOB_2_60V	8
+#define LDOB_2_70V	9
+#define LDOB_2_80V	10
+#define LDOB_2_90V	11
+#define LDOB_3_00V	12
+#define LDOB_3_10V	13
+#define LDOB_3_20V	14
+#define LDOB_3_30V	15
+
+#define LDO_VOL_MASK	0xf
+#define LDO_EN		(1 << 4)
+#define LDO_MODE_SHIFT	4
+#define LDO_MODE_MASK	(1 << 4)
+#define LDO_MODE_OFF	0
+#define LDO_MODE_ON	1
+
+#define VREFDDRCON_EN	(1 << 4)
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V	0
+#define SWBST_5_05V	1
+#define SWBST_5_10V	2
+#define SWBST_5_15V	3
+
+#define SWBST_VOL_MASK	0x3
+#define SWBST_MODE_MASK	0xC
+#define SWBST_MODE_SHIFT 0x2
+#define SWBST_MODE_OFF	0
+#define SWBST_MODE_PFM	1
+#define SWBST_MODE_AUTO	2
+#define SWBST_MODE_APS	3
+
+/*
+ * Regulator Mode Control
+ *
+ * OFF: The regulator is switched off and the output voltage is discharged.
+ * PFM: In this mode, the regulator is always in PFM mode, which is useful
+ *      at light loads for optimized efficiency.
+ * PWM: In this mode, the regulator is always in PWM mode operation
+ *	regardless of load conditions.
+ * APS: In this mode, the regulator moves automatically between pulse
+ *	skipping mode and PWM mode depending on load conditions.
+ *
+ * SWxMODE[3:0]
+ * Normal Mode  |  Standby Mode	|      value
+ *   OFF		OFF		0x0
+ *   PWM		OFF		0x1
+ *   PFM		OFF		0x3
+ *   APS		OFF		0x4
+ *   PWM		PWM		0x5
+ *   PWM		APS		0x6
+ *   APS		APS		0x8
+ *   APS		PFM		0xc
+ *   PWM		PFM		0xd
+ */
+#define OFF_OFF		0x0
+#define PWM_OFF		0x1
+#define PFM_OFF		0x3
+#define APS_OFF		0x4
+#define PWM_PWM		0x5
+#define PWM_APS		0x6
+#define APS_APS		0x8
+#define APS_PFM		0xc
+#define PWM_PFM		0xd
+
+#define SWITCH_SIZE	0x7
+
+int power_pfuze100_init(unsigned char bus);
+#endif
diff --git a/roms/u-boot/include/power/pfuze3000_pmic.h b/roms/u-boot/include/power/pfuze3000_pmic.h
new file mode 100644
index 000000000..b836d67fb
--- /dev/null
+++ b/roms/u-boot/include/power/pfuze3000_pmic.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc
+ *  Peng Fan <Peng.Fan@freescale.com>
+ */
+#ifndef __PFUZE3000_PMIC_H_
+#define __PFUZE3000_PMIC_H_
+
+/* PFUZE3000 registers */
+enum {
+	PFUZE3000_DEVICEID	= 0x00,
+
+	PFUZE3000_REVID		= 0x03,
+	PFUZE3000_FABID		= 0x04,
+	PFUZE3000_INTSTAT0	= 0x05,
+	PFUZE3000_INTMASK0	= 0x06,
+	PFUZE3000_INTSENSE0	= 0x07,
+	PFUZE3000_INTSTAT1	= 0x08,
+	PFUZE3000_INTMASK1	= 0x09,
+	PFUZE3000_INTSENSE1	= 0x0A,
+
+	PFUZE3000_INTSTAT3	= 0x0E,
+	PFUZE3000_INTMASK3	= 0x0F,
+	PFUZE3000_INTSENSE3	= 0x10,
+	PFUZE3000_INTSTAT4	= 0x11,
+	PFUZE3000_INTMASK4	= 0x12,
+	PFUZE3000_INTSENSE4	= 0x13,
+
+	PFUZE3000_COINCTL	= 0x1A,
+	PFUZE3000_PWRCTL	= 0x1B,
+	PFUZE3000_MEMA		= 0x1C,
+	PFUZE3000_MEMB		= 0x1D,
+	PFUZE3000_MEMC		= 0x1E,
+	PFUZE3000_MEMD		= 0x1F,
+
+	PFUZE3000_SW1AVOLT	= 0x20,
+	PFUZE3000_SW1ASTBY	= 0x21,
+	PFUZE3000_SW1AOFF	= 0x22,
+	PFUZE3000_SW1AMODE	= 0x23,
+	PFUZE3000_SW1ACONF	= 0x24,
+
+	PFUZE3000_SW1BVOLT	= 0x2E,
+	PFUZE3000_SW1BSTBY	= 0x2F,
+	PFUZE3000_SW1BOFF	= 0x30,
+	PFUZE3000_SW1BMODE	= 0x31,
+	PFUZE3000_SW1BCONF	= 0x32,
+
+	PFUZE3000_SW2VOLT	= 0x35,
+	PFUZE3000_SW2STBY	= 0x36,
+	PFUZE3000_SW2OFF	= 0x37,
+	PFUZE3000_SW2MODE	= 0x38,
+	PFUZE3000_SW2CONF	= 0x39,
+
+	PFUZE3000_SW3VOLT	= 0x3C,
+	PFUZE3000_SW3STBY	= 0x3D,
+	PFUZE3000_SW3OFF	= 0x3E,
+	PFUZE3000_SW3MODE	= 0x3F,
+	PFUZE3000_SW3CONF	= 0x40,
+
+	PFUZE3000_SWBSTCTL	= 0x66,
+
+	PFUZE3000_LDOGCTL	= 0x69,
+	PFUZE3000_VREFDDRCTL	= 0x6A,
+	PFUZE3000_VSNVSCTL	= 0x6B,
+	PFUZE3000_VLDO1CTL	= 0x6C,
+	PFUZE3000_VLDO2CTL	= 0x6D,
+	PFUZE3000_VCC_SDCTL	= 0x6E,
+	PFUZE3000_V33CTL	= 0x6F,
+	PFUZE3000_VLDO3CTL	= 0x70,
+	PFUZE3000_VLD4CTL	= 0x71,
+
+	PFUZE3000_NUM_OF_REGS	= 0x100,
+};
+
+int power_pfuze3000_init(unsigned char bus);
+
+/* Voltage Configuration */
+#define PFUZE3000_SW1AB_SETP(x)    ((x - 7000) / 250)
+#define PFUZE3000_SW3_SETP(x)      ((x - 9000) / 500)
+#define PFUZE3000_VLDO_SETP(x)     ((x - 8000) / 500)
+
+#endif
diff --git a/roms/u-boot/include/power/pmic.h b/roms/u-boot/include/power/pmic.h
new file mode 100644
index 000000000..be9de6b4d
--- /dev/null
+++ b/roms/u-boot/include/power/pmic.h
@@ -0,0 +1,330 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014-2015 Samsung Electronics
+ *  Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ *  Copyright (C) 2011-2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __CORE_PMIC_H_
+#define __CORE_PMIC_H_
+
+#include <dm/ofnode.h>
+#include <i2c.h>
+#include <linux/list.h>
+#include <power/power_chrg.h>
+
+enum { PMIC_I2C, PMIC_SPI, PMIC_NONE};
+
+#ifdef CONFIG_POWER
+enum { I2C_PMIC, I2C_NUM, };
+enum { PMIC_READ, PMIC_WRITE, };
+enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, };
+
+enum {
+	PMIC_CHARGER_DISABLE,
+	PMIC_CHARGER_ENABLE,
+};
+
+struct p_i2c {
+	unsigned char addr;
+	unsigned char *buf;
+	unsigned char tx_num;
+};
+
+struct p_spi {
+	unsigned int cs;
+	unsigned int mode;
+	unsigned int bitlen;
+	unsigned int clk;
+	unsigned int flags;
+	u32 (*prepare_tx)(u32 reg, u32 *val, u32 write);
+};
+
+struct pmic;
+struct power_fg {
+	int (*fg_battery_check) (struct pmic *p, struct pmic *bat);
+	int (*fg_battery_update) (struct pmic *p, struct pmic *bat);
+};
+
+struct power_chrg {
+	int (*chrg_type) (struct pmic *p);
+	int (*chrg_bat_present) (struct pmic *p);
+	int (*chrg_state) (struct pmic *p, int state, int current);
+};
+
+struct power_battery {
+	struct battery *bat;
+	int (*battery_init) (struct pmic *bat, struct pmic *p1,
+			     struct pmic *p2, struct pmic *p3);
+	int (*battery_charge) (struct pmic *bat);
+	/* Keep info about power devices involved with battery operation */
+	struct pmic *chrg, *fg, *muic;
+};
+
+struct pmic {
+	const char *name;
+	unsigned char bus;
+	unsigned char interface;
+	unsigned char sensor_byte_order;
+	unsigned int number_of_regs;
+	union hw {
+		struct p_i2c i2c;
+		struct p_spi spi;
+	} hw;
+
+	void (*low_power_mode) (void);
+	struct power_battery *pbat;
+	struct power_chrg *chrg;
+	struct power_fg *fg;
+
+	struct pmic *parent;
+	struct list_head list;
+};
+#endif /* CONFIG_POWER */
+
+#ifdef CONFIG_DM_PMIC
+/**
+ * U-Boot PMIC Framework
+ * =====================
+ *
+ * UCLASS_PMIC - This is designed to provide an I/O interface for PMIC devices.
+ *
+ * For the multi-function PMIC devices, this can be used as parent I/O device
+ * for each IC's interface. Then, each child uses its parent for read/write.
+ *
+ * The driver model tree could look like this:
+ *
+ *_ root device
+ * |_ BUS 0 device (e.g. I2C0)                 - UCLASS_I2C/SPI/...
+ * | |_ PMIC device (READ/WRITE ops)           - UCLASS_PMIC
+ * |   |_ REGULATOR device (ldo/buck/... ops)  - UCLASS_REGULATOR
+ * |   |_ CHARGER device (charger ops)         - UCLASS_CHARGER (in the future)
+ * |   |_ MUIC device (microUSB connector ops) - UCLASS_MUIC    (in the future)
+ * |   |_ ...
+ * |
+ * |_ BUS 1 device (e.g. I2C1)                 - UCLASS_I2C/SPI/...
+ *   |_ PMIC device (READ/WRITE ops)           - UCLASS_PMIC
+ *     |_ RTC device (rtc ops)                 - UCLASS_RTC     (in the future)
+ *
+ * We can find two PMIC cases in boards design:
+ * - single I/O interface
+ * - multiple I/O interfaces
+ * We bind a single PMIC device for each interface, to provide an I/O for
+ * its child devices. And each child usually implements a different function,
+ * controlled by the same interface.
+ *
+ * The binding should be done automatically. If device tree nodes/subnodes are
+ * proper defined, then:
+ *
+ * |_ the ROOT driver will bind the device for I2C/SPI node:
+ *   |_ the I2C/SPI driver should bind a device for pmic node:
+ *     |_ the PMIC driver should bind devices for its childs:
+ *       |_ regulator (child)
+ *       |_ charger   (child)
+ *       |_ other     (child)
+ *
+ * The same for other device nodes, for multi-interface PMIC.
+ *
+ * Note:
+ * Each PMIC interface driver should use a different compatible string.
+ *
+ * If a PMIC child device driver needs access the PMIC-specific registers,
+ * it need know only the register address and the access can be done through
+ * the parent pmic driver. Like in the example:
+ *
+ *_ root driver
+ * |_ dev: bus I2C0                                         - UCLASS_I2C
+ * | |_ dev: my_pmic (read/write)              (is parent)  - UCLASS_PMIC
+ * |   |_ dev: my_regulator (set value/etc..)  (is child)   - UCLASS_REGULATOR
+ *
+ * To ensure such device relationship, the pmic device driver should also bind
+ * all its child devices, like in the example below. It can be done by calling
+ * the 'pmic_bind_children()' - please refer to the function description, which
+ * can be found in this header file. This function, should be called inside the
+ * driver's bind() method.
+ *
+ * For the example driver, please refer the MAX77686 driver:
+ * - 'drivers/power/pmic/max77686.c'
+ */
+
+/**
+ * struct dm_pmic_ops - PMIC device I/O interface
+ *
+ * Should be implemented by UCLASS_PMIC device drivers. The standard
+ * device operations provides the I/O interface for it's childs.
+ *
+ * @reg_count: device's register count
+ * @read:      read 'len' bytes at "reg" and store it into the 'buffer'
+ * @write:     write 'len' bytes from the 'buffer' to the register at 'reg' address
+ */
+struct dm_pmic_ops {
+	int (*reg_count)(struct udevice *dev);
+	int (*read)(struct udevice *dev, uint reg, uint8_t *buffer, int len);
+	int (*write)(struct udevice *dev, uint reg, const uint8_t *buffer,
+		     int len);
+};
+
+/**
+ * enum pmic_op_type - used for various pmic devices operation calls,
+ * for reduce a number of lines with the same code for read/write or get/set.
+ *
+ * @PMIC_OP_GET - get operation
+ * @PMIC_OP_SET - set operation
+*/
+enum pmic_op_type {
+	PMIC_OP_GET,
+	PMIC_OP_SET,
+};
+
+/**
+ * struct pmic_child_info - basic device's child info for bind child nodes with
+ * the driver by the node name prefix and driver name. This is a helper struct
+ * for function: pmic_bind_children().
+ *
+ * @prefix - child node name prefix (or its name if is unique or single)
+ * @driver - driver name for the sub-node with prefix
+ */
+struct pmic_child_info {
+	const char *prefix;
+	const char *driver;
+};
+
+/* drivers/power/pmic-uclass.c */
+
+/**
+ * pmic_bind_children() - bind drivers for given parent pmic, using child info
+ * found in 'child_info' array.
+ *
+ * @pmic       - pmic device - the parent of found child's
+ * @child_info - N-childs info array
+ * @return a positive number of childs, or 0 if no child found (error)
+ *
+ * Note: For N-childs the child_info array should have N+1 entries and the last
+ * entry prefix should be NULL - the same as for drivers compatible.
+ *
+ * For example, a single prefix info (N=1):
+ * static const struct pmic_child_info bind_info[] = {
+ *     { .prefix = "ldo", .driver = "ldo_driver" },
+ *     { },
+ * };
+ *
+ * This function is useful for regulator sub-nodes:
+ * my_regulator@0xa {
+ *     reg = <0xa>;
+ *     (pmic - bind automatically by compatible)
+ *     compatible = "my_pmic";
+ *     ...
+ *     (pmic's childs - bind by pmic_bind_children())
+ *     (nodes prefix: "ldo", driver: "my_regulator_ldo")
+ *     ldo1 { ... };
+ *     ldo2 { ... };
+ *
+ *     (nodes prefix: "buck", driver: "my_regulator_buck")
+ *     buck1 { ... };
+ *     buck2 { ... };
+ * };
+ */
+int pmic_bind_children(struct udevice *pmic, ofnode parent,
+		       const struct pmic_child_info *child_info);
+
+/**
+ * pmic_get: get the pmic device using its name
+ *
+ * @name - device name
+ * @devp - returned pointer to the pmic device
+ * @return 0 on success or negative value of errno.
+ *
+ * The returned devp device can be used with pmic_read/write calls
+ */
+int pmic_get(const char *name, struct udevice **devp);
+
+/**
+ * pmic_reg_count: get the pmic register count
+ *
+ * The required pmic device can be obtained by 'pmic_get()'
+ *
+ * @dev - pointer to the UCLASS_PMIC device
+ * @return register count value on success or negative value of errno.
+ */
+int pmic_reg_count(struct udevice *dev);
+
+/**
+ * pmic_read/write: read/write to the UCLASS_PMIC device
+ *
+ * The required pmic device can be obtained by 'pmic_get()'
+ *
+ * @pmic   - pointer to the UCLASS_PMIC device
+ * @reg    - device register offset
+ * @buffer - pointer to read/write buffer
+ * @len    - byte count for read/write
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_read(struct udevice *dev, uint reg, uint8_t *buffer, int len);
+int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len);
+
+/**
+ * pmic_reg_read() - read a PMIC register value
+ *
+ * @dev:	PMIC device to read
+ * @reg:	Register to read
+ * @return value read on success or negative value of errno.
+ */
+int pmic_reg_read(struct udevice *dev, uint reg);
+
+/**
+ * pmic_reg_write() - write a PMIC register value
+ *
+ * @dev:	PMIC device to write
+ * @reg:	Register to write
+ * @value:	Value to write
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_reg_write(struct udevice *dev, uint reg, uint value);
+
+/**
+ * pmic_clrsetbits() - clear and set bits in a PMIC register
+ *
+ * This reads a register, optionally clears some bits, optionally sets some
+ * bits, then writes the register.
+ *
+ * @dev:	PMIC device to update
+ * @reg:	Register to update
+ * @clr:	Bit mask to clear (set those bits that you want cleared)
+ * @set:	Bit mask to set (set those bits that you want set)
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
+
+/*
+ * This structure holds the private data for PMIC uclass
+ * For now we store information about the number of bytes
+ * being sent at once to the device.
+ */
+struct uc_pmic_priv {
+	uint trans_len;
+};
+
+#endif /* CONFIG_DM_PMIC */
+
+#ifdef CONFIG_POWER
+int pmic_init(unsigned char bus);
+int power_init_board(void);
+int pmic_dialog_init(unsigned char bus);
+int check_reg(struct pmic *p, u32 reg);
+struct pmic *pmic_alloc(void);
+struct pmic *pmic_get(const char *s);
+int pmic_probe(struct pmic *p);
+int pmic_reg_read(struct pmic *p, u32 reg, u32 *val);
+int pmic_reg_write(struct pmic *p, u32 reg, u32 val);
+int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on);
+#endif
+
+#define pmic_i2c_addr (p->hw.i2c.addr)
+#define pmic_i2c_tx_num (p->hw.i2c.tx_num)
+
+#define pmic_spi_bitlen (p->hw.spi.bitlen)
+#define pmic_spi_flags (p->hw.spi.flags)
+
+#endif /* __CORE_PMIC_H_ */
diff --git a/roms/u-boot/include/power/power_chrg.h b/roms/u-boot/include/power/power_chrg.h
new file mode 100644
index 000000000..db19953fb
--- /dev/null
+++ b/roms/u-boot/include/power/power_chrg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __POWER_CHARGER_H_
+#define __POWER_CHARGER_H_
+
+/* Type of available chargers */
+enum {
+	CHARGER_NO = 0,
+	CHARGER_TA,
+	CHARGER_USB,
+	CHARGER_TA_500,
+	CHARGER_UNKNOWN,
+};
+
+enum {
+	UNKNOWN,
+	EXT_SOURCE,
+	CHARGE,
+	NORMAL,
+};
+
+#endif /* __POWER_CHARGER_H_ */
diff --git a/roms/u-boot/include/power/regulator.h b/roms/u-boot/include/power/regulator.h
new file mode 100644
index 000000000..fad87c99e
--- /dev/null
+++ b/roms/u-boot/include/power/regulator.h
@@ -0,0 +1,667 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014-2015 Samsung Electronics
+ *  Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#ifndef _INCLUDE_REGULATOR_H_
+#define _INCLUDE_REGULATOR_H_
+
+struct udevice;
+
+/**
+ * U-Boot Voltage/Current Regulator
+ * ================================
+ *
+ * The regulator API is based on a driver model, with the device tree support.
+ * And this header describes the functions and data types for the uclass id:
+ * 'UCLASS_REGULATOR' and the regulator driver API.
+ *
+ * The regulator uclass - is based on uclass platform data which is allocated,
+ * automatically for each regulator device on bind and 'dev->uclass_plat'
+ * points to it. The data type is: 'struct dm_regulator_uclass_plat'.
+ * The uclass file: 'drivers/power/regulator/regulator-uclass.c'
+ *
+ * The regulator device - is based on driver's model 'struct udevice'.
+ * The API can use regulator name in two meanings:
+ * - devname  - the regulator device's name: 'dev->name'
+ * - platname - the device's plat's name. So in the code it looks like:
+ *              'uc_pdata = dev->uclass_plat'; 'name = uc_pdata->name'.
+ *
+ * The regulator device driver - provide an implementation of uclass operations
+ * pointed by 'dev->driver->ops' as a struct of type 'struct dm_regulator_ops'.
+ *
+ * To proper bind the regulator device, the device tree node should provide
+ * regulator constraints, like in the example below:
+ *
+ * ldo1 {
+ *      regulator-name = "VDD_MMC_1.8V";     (must be unique for proper bind)
+ *      regulator-min-microvolt = <1000000>; (optional)
+ *      regulator-max-microvolt = <1000000>; (optional)
+ *      regulator-min-microamp = <1000>;     (optional)
+ *      regulator-max-microamp = <1000>;     (optional)
+ *      regulator-always-on;                 (optional)
+ *      regulator-boot-on;                   (optional)
+ * };
+ *
+ * Note: For the proper operation, at least name constraint is needed, since
+ * it can be used when calling regulator_get_by_platname(). And the mandatory
+ * rule for this name is, that it must be globally unique for the single dts.
+ * If regulator-name property is not provided, node name will be chosen.
+ *
+ * Regulator bind:
+ * For each regulator device, the device_bind() should be called with passed
+ * device tree offset. This is required for this uclass's '.post_bind' method,
+ * which does the scan on the device node, for the 'regulator-name' constraint.
+ * If the parent is not a PMIC device, and the child is not bind by function:
+ * 'pmic_bind_childs()', then it's recommended to bind the device by call to
+ * dm_scan_fdt_dev() - this is usually done automatically for bus devices,
+ * as a post bind method.
+ *
+ * Regulator get:
+ * Having the device's name constraint, we can call regulator_by_platname(),
+ * to find the required regulator. Before return, the regulator is probed,
+ * and the rest of its constraints are put into the device's uclass platform
+ * data, by the uclass regulator '.pre_probe' method.
+ *
+ * For more info about PMIC bind, please refer to file: 'include/power/pmic.h'
+ *
+ * Note:
+ * Please do not use the device_bind_by_name() function, since it pass '-1' as
+ * device node offset - and the bind will fail on uclass .post_bind method,
+ * because of missing 'regulator-name' constraint.
+ *
+ *
+ * Fixed Voltage/Current Regulator
+ * ===============================
+ *
+ * When fixed voltage regulator is needed, then enable the config:
+ * - CONFIG_DM_REGULATOR_FIXED
+ *
+ * The driver file: 'drivers/power/regulator/fixed.c', provides basic support
+ * for control the GPIO, and return the device tree constraint values.
+ *
+ * To bind the fixed voltage regulator device, we usually use a 'simple-bus'
+ * node as a parent. And 'regulator-fixed' for the driver compatible. This is
+ * the same as in the kernel. The example node of fixed regulator:
+ *
+ * simple-bus {
+ *     compatible = "simple-bus";
+ *     #address-cells = <1>;
+ *     #size-cells = <0>;
+ *
+ *     blue_led {
+ *         compatible = "regulator-fixed";
+ *         regulator-name = "VDD_LED_3.3V";
+ *         regulator-min-microvolt = <3300000>;
+ *         regulator-max-microvolt = <3300000>;
+ *         gpio = <&gpc1 0 GPIO_ACTIVE_LOW>;
+ *     };
+ * };
+ *
+ * The fixed regulator devices also provide regulator uclass platform data. And
+ * devices bound from such node, can use the regulator drivers API.
+*/
+
+/* enum regulator_type - used for regulator_*() variant calls */
+enum regulator_type {
+	REGULATOR_TYPE_LDO = 0,
+	REGULATOR_TYPE_BUCK,
+	REGULATOR_TYPE_DVS,
+	REGULATOR_TYPE_FIXED,
+	REGULATOR_TYPE_GPIO,
+	REGULATOR_TYPE_OTHER,
+};
+
+/**
+ * struct dm_regulator_mode - this structure holds an information about
+ * each regulator operation mode. Probably in most cases - an array.
+ * This will be probably a driver-static data, since it is device-specific.
+ *
+ * @id             - a driver-specific mode id
+ * @register_value - a driver-specific value for its mode id
+ * @name           - the name of mode - used for regulator command
+ * Note:
+ * The field 'id', should be always a positive number, since the negative values
+ * are reserved for the errno numbers when returns the mode id.
+ */
+struct dm_regulator_mode {
+	int id; /* Set only as >= 0 (negative value is reserved for errno) */
+	int register_value;
+	const char *name;
+};
+
+enum regulator_flag {
+	REGULATOR_FLAG_AUTOSET_UV	= 1 << 0,
+	REGULATOR_FLAG_AUTOSET_UA	= 1 << 1,
+};
+
+/**
+ * struct dm_regulator_uclass_plat - pointed by dev->uclass_plat, and
+ * allocated on each regulator bind. This structure holds an information
+ * about each regulator's constraints and supported operation modes.
+ * There is no "step" voltage value - so driver should take care of this.
+ *
+ * @type       - one of 'enum regulator_type'
+ * @mode       - pointer to the regulator mode (array if more than one)
+ * @mode_count - number of '.mode' entries
+ * @min_uV*    - minimum voltage (micro Volts)
+ * @max_uV*    - maximum voltage (micro Volts)
+ * @min_uA*    - minimum amperage (micro Amps)
+ * @max_uA*    - maximum amperage (micro Amps)
+ * @always_on* - bool type, true or false
+ * @boot_on*   - bool type, true or false
+ * @force_off* - bool type, true or false
+ * TODO(sjg@chromium.org): Consider putting the above two into @flags
+ * @ramp_delay - Time to settle down after voltage change (unit: uV/us)
+ * @flags:     - flags value (see REGULATOR_FLAG_...)
+ * @name**     - fdt regulator name - should be taken from the device tree
+ * ctrl_reg:   - Control register offset used to enable/disable regulator
+ * volt_reg:   - register offset for writing voltage vsel values
+ *
+ * Note:
+ * *  - set automatically on device probe by the uclass's '.pre_probe' method.
+ * ** - set automatically on device bind by the uclass's '.post_bind' method.
+ * The constraints: type, mode, mode_count, can be set by device driver, e.g.
+ * by the driver '.probe' method.
+ */
+struct dm_regulator_uclass_plat {
+	enum regulator_type type;
+	struct dm_regulator_mode *mode;
+	int mode_count;
+	int min_uV;
+	int max_uV;
+	int init_uV;
+	int min_uA;
+	int max_uA;
+	unsigned int ramp_delay;
+	bool always_on;
+	bool boot_on;
+	bool force_off;
+	const char *name;
+	int flags;
+	u8 ctrl_reg;
+	u8 volt_reg;
+	bool suspend_on;
+	u32 suspend_uV;
+};
+
+/* Regulator device operations */
+struct dm_regulator_ops {
+	/**
+	 * The regulator output value function calls operates on a micro Volts.
+	 *
+	 * get/set_value - get/set output value of the given output number
+	 * @dev          - regulator device
+	 * Sets:
+	 * @uV           - set the output value [micro Volts]
+	 * @return output value [uV] on success or negative errno if fail.
+	 */
+	int (*get_value)(struct udevice *dev);
+	int (*set_value)(struct udevice *dev, int uV);
+
+	/**
+	 * The regulator suspend output value function calls operates
+	 * on a micro Volts.
+	 *
+	 * get/set_suspen_value - get/set suspend mode output value
+	 * @dev          - regulator device
+	 * Sets:
+	 * @uV           - set the suspend output value [micro Volts]
+	 * @return output value [uV] on success or negative errno if fail.
+	 */
+	int (*set_suspend_value)(struct udevice *dev, int uV);
+	int (*get_suspend_value)(struct udevice *dev);
+
+	/**
+	 * The regulator output current function calls operates on a micro Amps.
+	 *
+	 * get/set_current - get/set output current of the given output number
+	 * @dev            - regulator device
+	 * Sets:
+	 * @uA           - set the output current [micro Amps]
+	 * @return output value [uA] on success or negative errno if fail.
+	 */
+	int (*get_current)(struct udevice *dev);
+	int (*set_current)(struct udevice *dev, int uA);
+
+	/**
+	 * The most basic feature of the regulator output is its enable state.
+	 *
+	 * get/set_enable - get/set enable state of the given output number
+	 * @dev           - regulator device
+	 * Sets:
+	 * @enable         - set true - enable or false - disable
+	 * @return true/false for get or -errno if fail; 0 / -errno for set.
+	 */
+	int (*get_enable)(struct udevice *dev);
+	int (*set_enable)(struct udevice *dev, bool enable);
+
+	/**
+	 * The most basic feature of the regulator output is its enable state
+	 * in suspend mode.
+	 *
+	 * get/set_suspend_enable - get/set enable state of the suspend output
+	 * @dev           - regulator device
+	 * Sets:
+	 * @enable         - set true - enable or false - disable
+	 * @return true/false for get or -errno if fail; 0 / -errno for set.
+	 */
+	int (*set_suspend_enable)(struct udevice *dev, bool enable);
+	int (*get_suspend_enable)(struct udevice *dev);
+
+	/**
+	 * The 'get/set_mode()' function calls should operate on a driver-
+	 * specific mode id definitions, which should be found in:
+	 * field 'id' of struct dm_regulator_mode.
+	 *
+	 * get/set_mode - get/set operation mode of the given output number
+	 * @dev         - regulator device
+	 * Sets
+	 * @mode_id     - set output mode id (struct dm_regulator_mode->id)
+	 * @return id/0 for get/set on success or negative errno if fail.
+	 * Note:
+	 * The field 'id' of struct type 'dm_regulator_mode', should be always
+	 * a positive number, since the negative is reserved for the error.
+	 */
+	int (*get_mode)(struct udevice *dev);
+	int (*set_mode)(struct udevice *dev, int mode_id);
+};
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+/**
+ * regulator_mode: returns a pointer to the array of regulator mode info
+ *
+ * @dev        - pointer to the regulator device
+ * @modep      - pointer to the returned mode info array
+ * @return     - count of modep entries on success or negative errno if fail.
+ */
+int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep);
+
+/**
+ * regulator_get_value: get microvoltage voltage value of a given regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive output value [uV] on success or negative errno if fail.
+ */
+int regulator_get_value(struct udevice *dev);
+
+/**
+ * regulator_set_value: set the microvoltage value of a given regulator.
+ *
+ * @dev    - pointer to the regulator device
+ * @uV     - the output value to set [micro Volts]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_value(struct udevice *dev, int uV);
+
+/**
+ * regulator_set_suspend_value: set the suspend microvoltage value of a given regulator.
+ *
+ * @dev    - pointer to the regulator device
+ * @uV     - the output suspend value to set [micro Volts]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_suspend_value(struct udevice *dev, int uV);
+
+/**
+ * regulator_get_suspend_value: get the suspend microvoltage value of a given regulator.
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive output value [uV] on success or negative errno if fail.
+ */
+int regulator_get_suspend_value(struct udevice *dev);
+
+/**
+ * regulator_set_value_force: set the microvoltage value of a given regulator
+ *			      without any min-,max condition check
+ *
+ * @dev    - pointer to the regulator device
+ * @uV     - the output value to set [micro Volts]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_value_force(struct udevice *dev, int uV);
+
+/**
+ * regulator_get_current: get microampere value of a given regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive output current [uA] on success or negative errno if fail.
+ */
+int regulator_get_current(struct udevice *dev);
+
+/**
+ * regulator_set_current: set the microampere value of a given regulator.
+ *
+ * @dev    - pointer to the regulator device
+ * @uA     - set the output current [micro Amps]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_current(struct udevice *dev, int uA);
+
+/**
+ * regulator_get_enable: get regulator device enable state.
+ *
+ * @dev    - pointer to the regulator device
+ * @return - true/false of enable state or -errno val if fails
+ */
+int regulator_get_enable(struct udevice *dev);
+
+/**
+ * regulator_set_enable: set regulator enable state
+ *
+ * @dev    - pointer to the regulator device
+ * @enable - set true or false
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_enable(struct udevice *dev, bool enable);
+
+/**
+ * regulator_set_enable_if_allowed: set regulator enable state if allowed by
+ *					regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @enable - set true or false
+ * @return - 0 on success or if enabling is not supported
+ *	     -errno val if fails.
+ */
+int regulator_set_enable_if_allowed(struct udevice *dev, bool enable);
+
+/**
+ * regulator_set_suspend_enable: set regulator suspend enable state
+ *
+ * @dev    - pointer to the regulator device
+ * @enable - set true or false
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_suspend_enable(struct udevice *dev, bool enable);
+
+/**
+ * regulator_get_suspend_enable: get regulator suspend enable state
+ *
+ * @dev    - pointer to the regulator device
+ * @return - true/false of enable state or -errno val if fails
+ */
+int regulator_get_suspend_enable(struct udevice *dev);
+
+/**
+ * regulator_get_mode: get active operation mode id of a given regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive mode 'id' number on success or -errno val if fails
+ * Note:
+ * The device can provide an array of operating modes, which is type of struct
+ * dm_regulator_mode. Each mode has it's own 'id', which should be unique inside
+ * that array. By calling this function, the driver should return an active mode
+ * id of the given regulator device.
+ */
+int regulator_get_mode(struct udevice *dev);
+
+/**
+ * regulator_set_mode: set the given regulator's, active mode id
+ *
+ * @dev     - pointer to the regulator device
+ * @mode_id - mode id to set ('id' field of struct type dm_regulator_mode)
+ * @return  - 0 on success or -errno value if fails
+ * Note:
+ * The device can provide an array of operating modes, which is type of struct
+ * dm_regulator_mode. Each mode has it's own 'id', which should be unique inside
+ * that array. By calling this function, the driver should set the active mode
+ * of a given regulator to given by "mode_id" argument.
+ */
+int regulator_set_mode(struct udevice *dev, int mode_id);
+
+/**
+ * regulators_enable_boot_on() - enable regulators needed for boot
+ *
+ * This enables all regulators which are marked to be on at boot time. This
+ * only works for regulators which don't have a range for voltage/current,
+ * since in that case it is not possible to know which value to use.
+ *
+ * This effectively calls regulator_autoset() for every regulator.
+ */
+int regulators_enable_boot_on(bool verbose);
+
+/**
+ * regulators_enable_boot_off() - disable regulators needed for boot
+ *
+ * This disables all regulators which are marked to be off at boot time.
+ *
+ * This effectively calls regulator_unset() for every regulator.
+ */
+int regulators_enable_boot_off(bool verbose);
+
+/**
+ * regulator_autoset: setup the voltage/current on a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_plat):
+ *
+ * - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
+ *   or if both are unset, then the function returns
+ * - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
+ * - Current limit - will set - if '.min_uA' and '.max_uA' values are equal
+ *
+ * The function returns on the first-encountered error.
+ *
+ * @platname - expected string for dm_regulator_uclass_plat .name field
+ * @devp     - returned pointer to the regulator device - if non-NULL passed
+ * @return: 0 on success or negative value of errno.
+ */
+int regulator_autoset(struct udevice *dev);
+
+/**
+ * regulator_unset: turn off a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_platdata):
+ *
+ * - Disable - will set - if  'force_off' is set to true,
+ *
+ * The function returns on the first-encountered error.
+ */
+int regulator_unset(struct udevice *dev);
+
+/**
+ * regulator_autoset_by_name: setup the regulator given by its uclass's
+ * platform data name field. The setup depends on constraints found in device's
+ * uclass's platform data (struct dm_regulator_uclass_plat):
+ * - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
+ *   or if both are unset, then the function returns
+ * - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
+ * - Current limit - will set - if '.min_uA' and '.max_uA' values are equal
+ *
+ * The function returns on first encountered error.
+ *
+ * @platname - expected string for dm_regulator_uclass_plat .name field
+ * @devp     - returned pointer to the regulator device - if non-NULL passed
+ * @return: 0 on success or negative value of errno.
+ *
+ * The returned 'regulator' device can be used with:
+ * - regulator_get/set_*
+ */
+int regulator_autoset_by_name(const char *platname, struct udevice **devp);
+
+/**
+ * regulator_list_autoset: setup the regulators given by list of their uclass's
+ * platform data name field. The setup depends on constraints found in device's
+ * uclass's platform data. The function loops with calls to:
+ * regulator_autoset_by_name() for each name from the list.
+ *
+ * @list_platname - an array of expected strings for .name field of each
+ *                  regulator's uclass plat
+ * @list_devp     - an array of returned pointers to the successfully setup
+ *                  regulator devices if non-NULL passed
+ * @verbose       - (true/false) print each regulator setup info, or be quiet
+ * @return 0 on successfully setup of all list entries, otherwise first error.
+ *
+ * The returned 'regulator' devices can be used with:
+ * - regulator_get/set_*
+ *
+ * Note: The list must ends with NULL entry, like in the "platname" list below:
+ * char *my_regulators[] = {
+ *     "VCC_3.3V",
+ *     "VCC_1.8V",
+ *     NULL,
+ * };
+ */
+int regulator_list_autoset(const char *list_platname[],
+			   struct udevice *list_devp[],
+			   bool verbose);
+
+/**
+ * regulator_get_by_devname: returns the pointer to the pmic regulator device.
+ * Search by name, found in regulator device's name.
+ *
+ * @devname - expected string for 'dev->name' of regulator device
+ * @devp    - returned pointer to the regulator device
+ * @return 0 on success or negative value of errno.
+ *
+ * The returned 'regulator' device is probed and can be used with:
+ * - regulator_get/set_*
+ */
+int regulator_get_by_devname(const char *devname, struct udevice **devp);
+
+/**
+ * regulator_get_by_platname: returns the pointer to the pmic regulator device.
+ * Search by name, found in regulator uclass plat.
+ *
+ * @platname - expected string for uc_pdata->name of regulator uclass plat
+ * @devp     - returns pointer to the regulator device or NULL on error
+ * @return 0 on success or negative value of errno.
+ *
+ * The returned 'regulator' device is probed and can be used with:
+ * - regulator_get/set_*
+ */
+int regulator_get_by_platname(const char *platname, struct udevice **devp);
+
+/**
+ * device_get_supply_regulator: returns the pointer to the supply regulator.
+ * Search by phandle, found in device's node.
+ *
+ * Note: Please pay attention to proper order of device bind sequence.
+ * The regulator device searched by the phandle, must be binded before
+ * this function call.
+ *
+ * @dev         - device with supply phandle
+ * @supply_name - phandle name of regulator
+ * @devp        - returned pointer to the supply device
+ * @return 0 on success or negative value of errno.
+ */
+int device_get_supply_regulator(struct udevice *dev, const char *supply_name,
+				struct udevice **devp);
+#else
+static inline int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_value(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_value(struct udevice *dev, int uV)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_suspend_value(struct udevice *dev, int uV)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_suspend_value(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_value_force(struct udevice *dev, int uV)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_current(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_current(struct udevice *dev, int uA)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_enable(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_enable(struct udevice *dev, bool enable)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_enable_if_allowed(struct udevice *dev, bool enable)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_suspend_enable(struct udevice *dev, bool enable)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_suspend_enable(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_mode(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_set_mode(struct udevice *dev, int mode_id)
+{
+	return -ENOSYS;
+}
+
+static inline int regulators_enable_boot_on(bool verbose)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_autoset(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_autoset_by_name(const char *platname, struct udevice **devp)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_list_autoset(const char *list_platname[], struct udevice *list_devp[],
+					 bool verbose)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_by_devname(const char *devname, struct udevice **devp)
+{
+	return -ENOSYS;
+}
+
+static inline int regulator_get_by_platname(const char *platname, struct udevice **devp)
+{
+	return -ENOSYS;
+}
+
+static inline int device_get_supply_regulator(struct udevice *dev, const char *supply_name,
+					       struct udevice **devp)
+{
+	return -ENOSYS;
+}
+#endif
+
+#endif /* _INCLUDE_REGULATOR_H_ */
diff --git a/roms/u-boot/include/power/rk8xx_pmic.h b/roms/u-boot/include/power/rk8xx_pmic.h
new file mode 100644
index 000000000..8ff0af35c
--- /dev/null
+++ b/roms/u-boot/include/power/rk8xx_pmic.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _PMIC_RK8XX_H_
+#define _PMIC_RK8XX_H_
+
+enum {
+	REG_SECONDS			= 0x00,
+	REG_MINUTES,
+	REG_HOURS,
+	REG_DAYS,
+	REG_MONTHS,
+	REG_YEARS,
+	REG_WEEKS,
+	REG_ALARM_SECONDS,
+	REG_ALARM_MINUTES,
+	REG_ALARM_HOURS,
+	REG_ALARM_DAYS,
+	REG_ALARM_MONTHS,
+	REG_ALARM_YEARS,
+
+	REG_RTC_CTRL			= 0x10,
+	REG_RTC_STATUS,
+	REG_RTC_INT,
+	REG_RTC_COMP_LSB,
+	REG_RTC_COMP_MSB,
+
+	ID_MSB				= 0x17,
+	ID_LSB,
+
+	REG_CLK32OUT			= 0x20,
+	REG_VB_MON,
+	REG_THERMAL,
+	REG_DCDC_EN,
+	REG_LDO_EN,
+	REG_SLEEP_SET_OFF1,
+	REG_SLEEP_SET_OFF2,
+	REG_DCDC_UV_STS,
+	REG_DCDC_UV_ACT,
+	REG_LDO_UV_STS,
+	REG_LDO_UV_ACT,
+	REG_DCDC_PG,
+	REG_LDO_PG,
+	REG_VOUT_MON_TDB,
+	REG_BUCK1_CONFIG,
+	REG_BUCK1_ON_VSEL,
+	REG_BUCK1_SLP_VSEL,
+	REG_BUCK1_DVS_VSEL,
+	REG_BUCK2_CONFIG,
+	REG_BUCK2_ON_VSEL,
+	REG_BUCK2_SLP_VSEL,
+	REG_BUCK2_DVS_VSEL,
+	REG_BUCK3_CONFIG,
+	REG_BUCK4_CONFIG,
+	REG_BUCK4_ON_VSEL,
+	REG_BUCK4_SLP_VSEL,
+	REG_BOOST_CONFIG_REG,
+	REG_LDO1_ON_VSEL,
+	REG_LDO1_SLP_VSEL,
+	REG_LDO2_ON_VSEL,
+	REG_LDO2_SLP_VSEL,
+	REG_LDO3_ON_VSEL,
+	REG_LDO3_SLP_VSEL,
+	REG_LDO4_ON_VSEL,
+	REG_LDO4_SLP_VSEL,
+	REG_LDO5_ON_VSEL,
+	REG_LDO5_SLP_VSEL,
+	REG_LDO6_ON_VSEL,
+	REG_LDO6_SLP_VSEL,
+	REG_LDO7_ON_VSEL,
+	REG_LDO7_SLP_VSEL,
+	REG_LDO8_ON_VSEL,
+	REG_LDO8_SLP_VSEL,
+	REG_DEVCTRL,
+	REG_INT_STS1,
+	REG_INT_STS_MSK1,
+	REG_INT_STS2,
+	REG_INT_STS_MSK2,
+	REG_IO_POL,
+	REG_OTP_VDD_EN,
+	REG_H5V_EN,
+	REG_SLEEP_SET_OFF,
+	REG_BOOST_LDO9_ON_VSEL,
+	REG_BOOST_LDO9_SLP_VSEL,
+	REG_BOOST_CTRL,
+
+	/* Not sure what this does */
+	REG_DCDC_ILMAX			= 0x90,
+	REG_CHRG_COMP			= 0x9a,
+	REG_SUP_STS			= 0xa0,
+	REG_USB_CTRL,
+	REG1_CHRG_CTRL,
+	REG2_CHRG_CTRL,
+	REG3_CHRG_CTRL,
+	REG_BAT_CTRL,
+	REG_BAT_HTS_TS1,
+	REG_BAT_LTS_TS1,
+	REG_BAT_HTS_TS2,
+	REG_BAT_LTS_TS2,
+	REG_TS_CTRL,
+	REG_ADC_CTRL,
+	REG_ON_SOURCE,
+	REG_OFF_SOURCE,
+	REG_GGCON,
+	REG_GGSTS,
+	REG_FRAME_SMP_INTERV,
+	REG_AUTO_SLP_CUR_THR,
+	REG3_GASCNT_CAL,
+	REG2_GASCNT_CAL,
+	REG1_GASCNT_CAL,
+	REG0_GASCNT_CAL,
+	REG3_GASCNT,
+	REG2_GASCNT,
+	REG1_GASCNT,
+	REG0_GASCNT,
+	REGH_BAT_CUR_AVG,
+	REGL_BAT_CUR_AVG,
+	REGH_TS1_ADC,
+	REGL_TS1_ADC,
+	REGH_TS2_ADC,
+	REGL_TS2_ADC,
+	REGH_BAT_OCV,
+	REGL_BAT_OCV,
+	REGH_BAT_VOL,
+	REGL_BAT_VOL,
+	REGH_RELAX_ENTRY_THRES,
+	REGL_RELAX_ENTRY_THRES,
+	REGH_RELAX_EXIT_THRES,
+	REGL_RELAX_EXIT_THRES,
+	REGH_RELAX_VOL1,
+	REGL_RELAX_VOL1,
+	REGH_RELAX_VOL2,
+	REGL_RELAX_VOL2,
+	REGH_BAT_CUR_R_CALC,
+	REGL_BAT_CUR_R_CALC,
+	REGH_BAT_VOL_R_CALC,
+	REGL_BAT_VOL_R_CALC,
+	REGH_CAL_OFFSET,
+	REGL_CAL_OFFSET,
+	REG_NON_ACT_TIMER_CNT,
+	REGH_VCALIB0,
+	REGL_VCALIB0,
+	REGH_VCALIB1,
+	REGL_VCALIB1,
+	REGH_IOFFSET,
+	REGL_IOFFSET,
+	REG_SOC,
+	REG3_REMAIN_CAP,
+	REG2_REMAIN_CAP,
+	REG1_REMAIN_CAP,
+	REG0_REMAIN_CAP,
+	REG_UPDAT_LEVE,
+	REG3_NEW_FCC,
+	REG2_NEW_FCC,
+	REG1_NEW_FCC,
+	REG0_NEW_FCC,
+	REG_NON_ACT_TIMER_CNT_SAVE,
+	REG_OCV_VOL_VALID,
+	REG_REBOOT_CNT,
+	REG_POFFSET,
+	REG_MISC_MARK,
+	REG_HALT_CNT,
+	REGH_CALC_REST,
+	REGL_CALC_REST,
+	SAVE_DATA19,
+	RK808_NUM_OF_REGS,
+};
+
+enum {
+	RK817_REG_SYS_CFG3 = 0xf4,
+};
+
+enum {
+	RK816_REG_DCDC_EN1 = 0x23,
+	RK816_REG_DCDC_EN2,
+	RK816_REG_DCDC_SLP_EN,
+	RK816_REG_LDO_SLP_EN,
+	RK816_REG_LDO_EN1 = 0x27,
+	RK816_REG_LDO_EN2,
+};
+
+enum {
+	RK805_ID = 0x8050,
+	RK808_ID = 0x0000,
+	RK809_ID = 0x8090,
+	RK816_ID = 0x8160,
+	RK817_ID = 0x8170,
+	RK818_ID = 0x8180,
+};
+
+enum {
+	RK817_POWER_EN0 = 0xb1,
+	RK817_POWER_EN1,
+	RK817_POWER_EN2,
+	RK817_POWER_EN3,
+};
+
+#define RK817_POWER_EN_SAVE0	0x99
+#define RK817_POWER_EN_SAVE1	0xa4
+
+#define RK817_ID_MSB	0xed
+#define RK817_ID_LSB	0xee
+#define RK8XX_ID_MSK	0xfff0
+
+#define RK817_PMIC_SYS_CFG3	0xf4
+#define RK817_GPIO_INT_CFG	0xfe
+
+#define RK8XX_ON_SOURCE		0xae
+#define RK8XX_OFF_SOURCE	0xaf
+#define RK817_BUCK4_CMIN	0xc6
+#define RK817_ON_SOURCE		0xf5
+#define RK817_OFF_SOURCE	0xf6
+
+struct reg_data {
+	u8 reg;
+	u8 val;
+	u8 mask;
+};
+struct rk8xx_reg_table {
+	char *name;
+	u8 reg_ctl;
+	u8 reg_vol;
+};
+
+struct rk8xx_priv {
+	int variant;
+};
+
+int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
+int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
+int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
+
+#endif
diff --git a/roms/u-boot/include/power/rn5t567_pmic.h b/roms/u-boot/include/power/rn5t567_pmic.h
new file mode 100644
index 000000000..93bc7cba5
--- /dev/null
+++ b/roms/u-boot/include/power/rn5t567_pmic.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Toradex AG
+ * Stefan Agner <stefan.agner@toradex.com>
+ */
+#ifndef __RN5T567_PMIC_H_
+#define __RN5T567_PMIC_H_
+
+/* RN5T567 registers */
+enum {
+	RN5T567_LSIVER		= 0x00,
+	RN5T567_OTPVER		= 0x01,
+	RN5T567_IODAC		= 0x02,
+	RN5T567_VINDAC		= 0x03,
+	RN5T567_OUT32KEN	= 0x05,
+
+	RN5T567_CPUCNT		= 0x06,
+
+	RN5T567_PSWR		= 0x07,
+	RN5T567_PONHIS		= 0x09,
+	RN5T567_POFFHIS		= 0x0A,
+	RN5T567_WATCHDOG	= 0x0B,
+	RN5T567_WATCHDOGCNT	= 0x0C,
+	RN5T567_PWRFUNC		= 0x0D,
+	RN5T567_SLPCNT		= 0x0E,
+	RN5T567_REPCNT		= 0x0F,
+	RN5T567_PWRONTIMSET	= 0x10,
+	RN5T567_NOETIMSETCNT	= 0x11,
+	RN5T567_PWRIREN		= 0x12,
+	RN5T567_PWRIRQ		= 0x13,
+	RN5T567_PWRMON		= 0x14,
+	RN5T567_PWRIRSEL	= 0x15,
+
+	RN5T567_DC1_SLOT	= 0x16,
+	RN5T567_DC2_SLOT	= 0x17,
+	RN5T567_DC3_SLOT	= 0x18,
+	RN5T567_DC4_SLOT	= 0x19,
+
+	RN5T567_LDO1_SLOT	= 0x1B,
+	RN5T567_LDO2_SLOT	= 0x1C,
+	RN5T567_LDO3_SLOT	= 0x1D,
+	RN5T567_LDO4_SLOT	= 0x1E,
+	RN5T567_LDO5_SLOT	= 0x1F,
+
+	RN5T567_PSO0_SLOT	= 0x25,
+	RN5T567_PSO1_SLOT	= 0x26,
+	RN5T567_PSO2_SLOT	= 0x27,
+	RN5T567_PSO3_SLOT	= 0x28,
+
+	RN5T567_LDORTC1_SLOT	= 0x2A,
+
+	RN5T567_DC1CTL		= 0x2C,
+	RN5T567_DC1CTL2		= 0x2D,
+	RN5T567_DC2CTL		= 0x2E,
+	RN5T567_DC2CTL2		= 0x2F,
+	RN5T567_DC3CTL		= 0x30,
+	RN5T567_DC3CTL2		= 0x31,
+	RN5T567_DC4CTL		= 0x32,
+	RN5T567_DC4CTL2		= 0x33,
+
+	RN5T567_DC1DAC		= 0x36,
+	RN5T567_DC2DAC		= 0x37,
+	RN5T567_DC3DAC		= 0x38,
+	RN5T567_DC4DAC		= 0x39,
+
+	RN5T567_DC1DAC_SLP	= 0x3B,
+	RN5T567_DC2DAC_SLP	= 0x3C,
+	RN5T567_DC3DAC_SLP	= 0x3D,
+	RN5T567_DC4DAC_SLP	= 0x3E,
+
+	RN5T567_DCIREN		= 0x40,
+	RN5T567_DCIRQ		= 0x41,
+	RN5T567_DCIRMON		= 0x42,
+
+	RN5T567_LDOEN1		= 0x44,
+	RN5T567_LDOEN2		= 0x45,
+	RN5T567_LDODIS1		= 0x46,
+
+	RN5T567_LDO1DAC		= 0x4C,
+	RN5T567_LDO2DAC		= 0x4D,
+	RN5T567_LDO3DAC		= 0x4E,
+	RN5T567_LDO4DAC		= 0x4F,
+	RN5T567_LDO5DAC		= 0x50,
+
+	RN5T567_LDORTC1DAC	= 0x56,
+	RN5T567_LDORTC2DAC	= 0x57,
+
+	RN5T567_LDO1DAC_SLP	= 0x58,
+	RN5T567_LDO2DAC_SLP	= 0x59,
+	RN5T567_LDO3DAC_SLP	= 0x5A,
+	RN5T567_LDO4DAC_SLP	= 0x5B,
+	RN5T567_LDO5DAC_SLP	= 0x5C,
+
+	RN5T567_IOSEL		= 0x90,
+	RN5T567_IOOUT		= 0x91,
+	RN5T567_GPEDGE1		= 0x92,
+	RN5T567_EN_GPIR		= 0x94,
+	RN5T567_IR_GPR		= 0x95,
+	RN5T567_IR_GPF		= 0x96,
+	RN5T567_MON_IOIN	= 0x97,
+	RN5T567_GPLED_FUNC	= 0x98,
+	RN5T567_INTPOL		= 0x9C,
+	RN5T567_INTEN		= 0x9D,
+	RN5T567_INTMON		= 0x9E,
+
+	RN5T567_PREVINDAC	= 0xB0,
+	RN5T567_OVTEMP		= 0xBC,
+
+	RN5T567_NUM_OF_REGS	= 0xBF,
+};
+
+#endif
diff --git a/roms/u-boot/include/power/s2mps11.h b/roms/u-boot/include/power/s2mps11.h
new file mode 100644
index 000000000..22b38fff7
--- /dev/null
+++ b/roms/u-boot/include/power/s2mps11.h
@@ -0,0 +1,164 @@
+#ifndef __S2MPS11__H__
+#define __S2MPS11__H__
+
+enum s2mps11_reg {
+	S2MPS11_REG_ID = 0,
+	S2MPS11_REG_INT1,
+	S2MPS11_REG_INT2,
+	S2MPS11_REG_INT3,
+	S2MPS11_REG_INT1M,
+	S2MPS11_REG_INT2M,
+	S2MPS11_REG_INT3M,
+	S2MPS11_REG_STATUS1,
+	S2MPS11_REG_STATUS2,
+	S2MPS11_REG_OFFSRC,
+	S2MPS11_REG_PWRONSRC,
+	S2MPS11_REG_RTC_CTRL,
+	S2MPS11_REG_CTRL1,
+	S2MPS11_REG_ETC_TEST,
+	S2MPS11_REG_RSVD3,
+	S2MPS11_REG_BU_CHG,
+	S2MPS11_REG_RAMP,
+	S2MPS11_REG_RAMP_BUCK,
+	S2MPS11_REG_LDO1_8,
+	S2MPS11_REG_LDO9_16,
+	S2MPS11_REG_LDO17_24,
+	S2MPS11_REG_LDO25_32,
+	S2MPS11_REG_LDO33_38,
+	S2MPS11_REG_LDO1_8_OVC,
+	S2MPS11_REG_LDO9_16_OVC,
+	S2MPS11_REG_LDO17_24_OVC,
+	S2MPS11_REG_LDO25_32_OVC,
+	S2MPS11_REG_LDO33_38_OVC,
+	S2MPS11_REG_RESERVED1,
+	S2MPS11_REG_RESERVED2,
+	S2MPS11_REG_RESERVED3,
+	S2MPS11_REG_RESERVED4,
+	S2MPS11_REG_RESERVED5,
+	S2MPS11_REG_RESERVED6,
+	S2MPS11_REG_RESERVED7,
+	S2MPS11_REG_RESERVED8,
+	S2MPS11_REG_WDRSTEN_CTRL,
+	S2MPS11_REG_B1CTRL1,
+	S2MPS11_REG_B1CTRL2,
+	S2MPS11_REG_B2CTRL1,
+	S2MPS11_REG_B2CTRL2,
+	S2MPS11_REG_B3CTRL1,
+	S2MPS11_REG_B3CTRL2,
+	S2MPS11_REG_B4CTRL1,
+	S2MPS11_REG_B4CTRL2,
+	S2MPS11_REG_B5CTRL1,
+	S2MPS11_REG_BUCK5_SW,
+	S2MPS11_REG_B5CTRL2,
+	S2MPS11_REG_B5CTRL3,
+	S2MPS11_REG_B5CTRL4,
+	S2MPS11_REG_B5CTRL5,
+	S2MPS11_REG_B6CTRL1,
+	S2MPS11_REG_B6CTRL2,
+	S2MPS11_REG_B7CTRL1,
+	S2MPS11_REG_B7CTRL2,
+	S2MPS11_REG_B8CTRL1,
+	S2MPS11_REG_B8CTRL2,
+	S2MPS11_REG_B9CTRL1,
+	S2MPS11_REG_B9CTRL2,
+	S2MPS11_REG_B10CTRL1,
+	S2MPS11_REG_B10CTRL2,
+	S2MPS11_REG_L1CTRL,
+	S2MPS11_REG_L2CTRL,
+	S2MPS11_REG_L3CTRL,
+	S2MPS11_REG_L4CTRL,
+	S2MPS11_REG_L5CTRL,
+	S2MPS11_REG_L6CTRL,
+	S2MPS11_REG_L7CTRL,
+	S2MPS11_REG_L8CTRL,
+	S2MPS11_REG_L9CTRL,
+	S2MPS11_REG_L10CTRL,
+	S2MPS11_REG_L11CTRL,
+	S2MPS11_REG_L12CTRL,
+	S2MPS11_REG_L13CTRL,
+	S2MPS11_REG_L14CTRL,
+	S2MPS11_REG_L15CTRL,
+	S2MPS11_REG_L16CTRL,
+	S2MPS11_REG_L17CTRL,
+	S2MPS11_REG_L18CTRL,
+	S2MPS11_REG_L19CTRL,
+	S2MPS11_REG_L20CTRL,
+	S2MPS11_REG_L21CTRL,
+	S2MPS11_REG_L22CTRL,
+	S2MPS11_REG_L23CTRL,
+	S2MPS11_REG_L24CTRL,
+	S2MPS11_REG_L25CTRL,
+	S2MPS11_REG_L26CTRL,
+	S2MPS11_REG_L27CTRL,
+	S2MPS11_REG_L28CTRL,
+	S2MPS11_REG_L29CTRL,
+	S2MPS11_REG_L30CTRL,
+	S2MPS11_REG_L31CTRL,
+	S2MPS11_REG_L32CTRL,
+	S2MPS11_REG_L33CTRL,
+	S2MPS11_REG_L34CTRL,
+	S2MPS11_REG_L35CTRL,
+	S2MPS11_REG_L36CTRL,
+	S2MPS11_REG_L37CTRL,
+	S2MPS11_REG_L38CTRL,
+	S2MPS11_REG_COUNT,
+};
+
+#define S2MPS11_LDO26_ENABLE	0xec
+
+#define S2MPS11_LDO_NUM		26
+#define S2MPS11_BUCK_NUM	10
+
+/* Driver name */
+#define S2MPS11_BUCK_DRIVER	"s2mps11_buck"
+#define S2MPS11_OF_BUCK_PREFIX	"BUCK"
+#define S2MPS11_LDO_DRIVER	"s2mps11_ldo"
+#define S2MPS11_OF_LDO_PREFIX	"LDO"
+
+/* BUCK */
+#define S2MPS11_BUCK_VOLT_MASK	0xff
+#define S2MPS11_BUCK9_VOLT_MASK	0x1f
+
+#define S2MPS11_BUCK_LSTEP	6250
+#define S2MPS11_BUCK_HSTEP	12500
+#define S2MPS11_BUCK9_STEP	25000
+
+#define S2MPS11_BUCK_UV_MIN	600000
+#define S2MPS11_BUCK_UV_HMIN	750000
+#define S2MPS11_BUCK9_UV_MIN	1400000
+
+#define S2MPS11_BUCK_VOLT_MAX_HEX	0xA0
+#define S2MPS11_BUCK5_VOLT_MAX_HEX	0xDF
+#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX	0xDC
+#define S2MPS11_BUCK9_VOLT_MAX_HEX	0x5F
+
+#define S2MPS11_BUCK_MODE_SHIFT		6
+#define S2MPS11_BUCK_MODE_MASK		(0x3)
+#define S2MPS11_BUCK_MODE_OFF		(0x0 << 6)
+#define S2MPS11_BUCK_MODE_STANDBY	(0x1 << 6)
+#define S2MPS11_BUCK_MODE_ON		(0x3 << 6)
+
+/* LDO */
+#define S2MPS11_LDO_VOLT_MASK		0x3F
+#define S2MPS11_LDO_VOLT_MAX_HEX	0x3F
+
+#define S2MPS11_LDO_STEP	25000
+#define S2MPS11_LDO_UV_MIN	800000
+
+#define S2MPS11_LDO_MODE_MASK		0x3
+#define S2MPS11_LDO_MODE_SHIFT		6
+
+#define S2MPS11_LDO_MODE_OFF		(0x0 << 6)
+#define S2MPS11_LDO_MODE_STANDBY	(0x1 << 6)
+#define S2MPS11_LDO_MODE_STANDBY_LPM	(0x2 << 6)
+#define S2MPS11_LDO_MODE_ON		(0x3 << 6)
+
+enum {
+	OP_OFF = 0,
+	OP_LPM,
+	OP_STANDBY,
+	OP_STANDBY_LPM,
+	OP_ON,
+};
+
+#endif
diff --git a/roms/u-boot/include/power/s5m8767.h b/roms/u-boot/include/power/s5m8767.h
new file mode 100644
index 000000000..f75ed5d92
--- /dev/null
+++ b/roms/u-boot/include/power/s5m8767.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __S5M8767_H_
+#define __S5M8767_H_
+
+enum s5m8767_regnum {
+	S5M8767_BUCK1 = 0,
+	S5M8767_BUCK2,
+	S5M8767_BUCK3,
+	S5M8767_BUCK4,
+	S5M8767_BUCK5,
+	S5M8767_BUCK6,
+	S5M8767_BUCK7,
+	S5M8767_BUCK8,
+	S5M8767_BUCK9,
+	S5M8767_LDO1,
+	S5M8767_LDO2,
+	S5M8767_LDO3,
+	S5M8767_LDO4,
+	S5M8767_LDO5,
+	S5M8767_LDO6,
+	S5M8767_LDO7,
+	S5M8767_LDO8,
+	S5M8767_LDO9,
+	S5M8767_LDO10,
+	S5M8767_LDO11,
+	S5M8767_LDO12,
+	S5M8767_LDO13,
+	S5M8767_LDO14,
+	S5M8767_LDO15,
+	S5M8767_LDO16,
+	S5M8767_LDO17,
+	S5M8767_LDO18,
+	S5M8767_LDO19,
+	S5M8767_LDO20,
+	S5M8767_LDO21,
+	S5M8767_LDO22,
+	S5M8767_LDO23,
+	S5M8767_LDO24,
+	S5M8767_LDO25,
+	S5M8767_LDO26,
+	S5M8767_LDO27,
+	S5M8767_LDO28,
+	S5M8767_EN32KHZ_CP,
+
+	S5M8767_NUM_OF_REGS,
+};
+
+struct sec_voltage_desc {
+	int max;
+	int min;
+	int step;
+};
+
+/**
+ * struct s5m8767_para - s5m8767 register parameters
+ * @param vol_addr	i2c address of the given buck/ldo register
+ * @param vol_bitpos	bit position to be set or clear within register
+ * @param vol_bitmask	bit mask value
+ * @param reg_enaddr	control register address, which enable the given
+ *			given buck/ldo.
+ * @param reg_enbiton	value to be written to buck/ldo to make it ON
+ * @param vol		Voltage information
+ */
+struct s5m8767_para {
+	enum s5m8767_regnum regnum;
+	u8	vol_addr;
+	u8	vol_bitpos;
+	u8	vol_bitmask;
+	u8	reg_enaddr;
+	u8	reg_enbiton;
+	const struct sec_voltage_desc *vol;
+};
+
+/* Drivers name */
+#define S5M8767_LDO_DRIVER	"s5m8767_ldo"
+#define S5M8767_BUCK_DRIVER	"s5m8767_buck"
+
+int s5m8767_enable_32khz_cp(struct udevice *dev);
+
+#endif /* __S5M8767_PMIC_H_ */
diff --git a/roms/u-boot/include/power/sandbox_pmic.h b/roms/u-boot/include/power/sandbox_pmic.h
new file mode 100644
index 000000000..1dbd15b52
--- /dev/null
+++ b/roms/u-boot/include/power/sandbox_pmic.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <p.marczak@samsung.com>
+ */
+
+#ifndef _SANDBOX_PMIC_H_
+#define  _SANDBOX_PMIC_H_
+
+#define SANDBOX_LDO_DRIVER		"sandbox_ldo"
+#define SANDBOX_OF_LDO_PREFIX		"ldo"
+#define SANDBOX_BUCK_DRIVER		"sandbox_buck"
+#define SANDBOX_OF_BUCK_PREFIX		"buck"
+
+#define SANDBOX_BUCK_COUNT	3
+#define SANDBOX_LDO_COUNT	2
+/*
+ * Sandbox PMIC registers:
+ * We have only 12 significant registers, but we alloc 16 for padding.
+ */
+enum {
+	SANDBOX_PMIC_REG_BUCK1_UV = 0,
+	SANDBOX_PMIC_REG_BUCK1_UA,
+	SANDBOX_PMIC_REG_BUCK1_OM,
+
+	SANDBOX_PMIC_REG_BUCK2_UV,
+	SANDBOX_PMIC_REG_BUCK2_UA,
+	SANDBOX_PMIC_REG_BUCK2_OM,
+
+	SANDBOX_PMIC_REG_LDO_OFFSET,
+	SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET,
+	SANDBOX_PMIC_REG_LDO1_UA,
+	SANDBOX_PMIC_REG_LDO1_OM,
+
+	SANDBOX_PMIC_REG_LDO2_UV,
+	SANDBOX_PMIC_REG_LDO2_UA,
+	SANDBOX_PMIC_REG_LDO2_OM,
+
+	SANDBOX_PMIC_REG_COUNT = 16,
+};
+
+/* Register offset for output: micro Volts, micro Amps, Operation Mode */
+enum {
+	OUT_REG_UV = 0,
+	OUT_REG_UA,
+	OUT_REG_OM,
+	OUT_REG_COUNT,
+};
+
+/* Buck operation modes */
+enum {
+	BUCK_OM_OFF = 0,
+	BUCK_OM_ON,
+	BUCK_OM_PWM,
+	BUCK_OM_COUNT,
+};
+
+/* Ldo operation modes */
+enum {
+	LDO_OM_OFF = 0,
+	LDO_OM_ON,
+	LDO_OM_SLEEP,
+	LDO_OM_STANDBY,
+	LDO_OM_COUNT,
+};
+
+/* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
+#define OUT_BUCK1_UV_MIN	800000
+#define OUT_BUCK1_UV_MAX	2400000
+#define OUT_BUCK1_UV_STEP	25000
+
+/* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */
+#define OUT_BUCK1_UA_MIN	150000
+#define OUT_BUCK1_UA_MAX	250000
+#define OUT_BUCK1_UA_STEP	25000
+
+/* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
+#define OUT_BUCK2_UV_MIN	750000
+#define OUT_BUCK2_UV_MAX	3950000
+#define OUT_BUCK2_UV_STEP	50000
+
+/* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
+#define OUT_LDO1_UV_MIN		800000
+#define OUT_LDO1_UV_MAX		2400000
+#define OUT_LDO1_UV_STEP	25000
+
+/* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */
+#define OUT_LDO1_UA_MIN		100000
+#define OUT_LDO1_UA_MAX		200000
+#define OUT_LDO1_UA_STEP	50000
+
+/* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
+#define OUT_LDO2_UV_MIN		750000
+#define OUT_LDO2_UV_MAX		3950000
+#define OUT_LDO2_UV_STEP	50000
+
+/* register <-> value conversion */
+#define REG2VAL(min, step, reg)		((min) + ((step) * (reg)))
+#define VAL2REG(min, step, val)		(((val) - (min)) / (step))
+
+/* Operation mode id -> register value conversion */
+#define OM2REG(x)			(x)
+
+/* Test data for: test/dm/power.c */
+
+/* BUCK names */
+#define SANDBOX_BUCK1_DEVNAME	"buck1"
+#define SANDBOX_BUCK1_PLATNAME	"SUPPLY_1.2V"
+#define SANDBOX_BUCK2_DEVNAME	"buck2"
+#define SANDBOX_BUCK2_PLATNAME	"SUPPLY_3.3V"
+/* BUCK3: for testing fallback regulator prefix matching during bind */
+#define SANDBOX_BUCK3_DEVNAME	"no_match_by_nodename"
+#define SANDBOX_BUCK3_PLATNAME	"buck_SUPPLY_1.5V"
+/* LDO names */
+#define SANDBOX_LDO1_DEVNAME	"ldo1"
+#define SANDBOX_LDO1_PLATNAME	"VDD_EMMC_1.8V"
+#define SANDBOX_LDO2_DEVNAME	"ldo2"
+#define SANDBOX_LDO2_PLATNAME	"VDD_LCD_3.3V"
+
+/*
+ * Expected regulators setup after call of:
+ * - regulator_autoset_by_name()
+ * - regulator_list_autoset()
+ */
+
+/* BUCK1: for testing regulator_autoset_by_name() */
+#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV	1200000
+#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA	200000
+#define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE	true
+
+/* BUCK2: for testing sandbox ADC's supply */
+#define SANDBOX_BUCK2_INITIAL_EXPECTED_UV	3000000
+#define SANDBOX_BUCK2_SET_UV			3300000
+
+/* LDO1/2 for testing regulator_list_autoset() */
+#define SANDBOX_LDO1_AUTOSET_EXPECTED_UV	1800000
+#define SANDBOX_LDO1_AUTOSET_EXPECTED_UA	100000
+#define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE	true
+
+#define SANDBOX_LDO2_AUTOSET_EXPECTED_UV	3000000
+#define SANDBOX_LDO2_AUTOSET_EXPECTED_UA	-ENOSYS
+#define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE	false
+
+#endif
diff --git a/roms/u-boot/include/power/stpmic1.h b/roms/u-boot/include/power/stpmic1.h
new file mode 100644
index 000000000..d3567df32
--- /dev/null
+++ b/roms/u-boot/include/power/stpmic1.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __PMIC_STPMIC1_H_
+#define __PMIC_STPMIC1_H_
+
+#include <linux/bitops.h>
+#define STPMIC1_MAIN_CR			0x10
+#define STPMIC1_BUCKS_MRST_CR		0x18
+#define STPMIC1_LDOS_MRST_CR		0x1a
+#define STPMIC1_BUCKX_MAIN_CR(buck)	(0x20 + (buck))
+#define STPMIC1_REFDDR_MAIN_CR		0x24
+#define STPMIC1_LDOX_MAIN_CR(ldo)	(0x25 + (ldo))
+#define STPMIC1_BST_SW_CR		0x40
+#define STPMIC1_NVM_SR			0xb8
+#define STPMIC1_NVM_CR			0xb9
+
+/* Main PMIC Control Register (MAIN_CR) */
+#define STPMIC1_SWOFF			BIT(0)
+#define STPMIC1_RREQ_EN			BIT(1)
+
+/* BUCKS_MRST_CR */
+#define STPMIC1_MRST_BUCK(buck)		BIT(buck)
+#define STPMIC1_MRST_BUCK_DEBUG		(STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
+					 STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
+
+/* LDOS_MRST_CR */
+#define STPMIC1_MRST_LDO(ldo)		BIT(ldo)
+#define STPMIC1_MRST_LDO_DEBUG		0
+
+/* BUCKx_MAIN_CR (x=1...4) */
+#define STPMIC1_BUCK_ENA		BIT(0)
+#define STPMIC1_BUCK_PREG_MODE		BIT(1)
+#define STPMIC1_BUCK_VOUT_MASK		GENMASK(7, 2)
+#define STPMIC1_BUCK_VOUT_SHIFT		2
+#define STPMIC1_BUCK_VOUT(sel)		(sel << STPMIC1_BUCK_VOUT_SHIFT)
+
+#define STPMIC1_BUCK2_1200000V		STPMIC1_BUCK_VOUT(24)
+#define STPMIC1_BUCK2_1250000V		STPMIC1_BUCK_VOUT(26)
+#define STPMIC1_BUCK2_1350000V		STPMIC1_BUCK_VOUT(30)
+
+#define STPMIC1_BUCK3_1800000V		STPMIC1_BUCK_VOUT(39)
+
+/* REFDDR_MAIN_CR */
+#define STPMIC1_VREF_ENA		BIT(0)
+
+/* LDOX_MAIN_CR */
+#define STPMIC1_LDO_ENA			BIT(0)
+#define STPMIC1_LDO12356_VOUT_MASK	GENMASK(6, 2)
+#define STPMIC1_LDO12356_VOUT_SHIFT	2
+#define STPMIC1_LDO_VOUT(sel)		(sel << STPMIC1_LDO12356_VOUT_SHIFT)
+
+#define STPMIC1_LDO3_MODE		BIT(7)
+#define STPMIC1_LDO3_DDR_SEL		31
+#define STPMIC1_LDO3_1800000		STPMIC1_LDO_VOUT(9)
+
+#define STPMIC1_LDO4_UV			3300000
+
+/* BST_SW_CR */
+#define STPMIC1_BST_ON			BIT(0)
+#define STPMIC1_VBUSOTG_ON		BIT(1)
+#define STPMIC1_SWOUT_ON		BIT(2)
+#define STPMIC1_PWR_SW_ON		(STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
+
+/* NVM_SR */
+#define STPMIC1_NVM_BUSY		BIT(0)
+
+/* NVM_CR */
+#define STPMIC1_NVM_CMD_PROGRAM		1
+#define STPMIC1_NVM_CMD_READ		2
+
+/* Timeout */
+#define STPMIC1_DEFAULT_START_UP_DELAY_MS	1
+#define STPMIC1_DEFAULT_STOP_DELAY_MS		5
+#define STPMIC1_USB_BOOST_START_UP_DELAY_MS	10
+
+enum {
+	STPMIC1_BUCK1,
+	STPMIC1_BUCK2,
+	STPMIC1_BUCK3,
+	STPMIC1_BUCK4,
+	STPMIC1_MAX_BUCK,
+};
+
+enum {
+	STPMIC1_PREG_MODE_HP,
+	STPMIC1_PREG_MODE_LP,
+};
+
+enum {
+	STPMIC1_LDO1,
+	STPMIC1_LDO2,
+	STPMIC1_LDO3,
+	STPMIC1_LDO4,
+	STPMIC1_LDO5,
+	STPMIC1_LDO6,
+	STPMIC1_MAX_LDO,
+};
+
+enum {
+	STPMIC1_LDO_MODE_NORMAL,
+	STPMIC1_LDO_MODE_BYPASS,
+	STPMIC1_LDO_MODE_SINK_SOURCE,
+};
+
+enum {
+	STPMIC1_PWR_SW1,
+	STPMIC1_PWR_SW2,
+	STPMIC1_MAX_PWR_SW,
+};
+#endif
diff --git a/roms/u-boot/include/power/tps62362.h b/roms/u-boot/include/power/tps62362.h
new file mode 100644
index 000000000..f0fc53846
--- /dev/null
+++ b/roms/u-boot/include/power/tps62362.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Felipe Balbi <balbi@ti.com>
+ */
+
+#ifndef __POWER_TPS62362_H__
+#define __POWER_TPS62362_H__
+
+/* I2C chip address */
+#define TPS62362_I2C_ADDR			0x60
+
+/* Registers */
+#define TPS62362_SET0				0x00
+#define TPS62362_SET1				0x01
+#define TPS62362_SET2				0x02
+#define TPS62362_SET3				0x03
+#define TPS62362_NUM_REGS			4
+
+#define TPS62362_DCDC_VOLT_SEL_0950MV		0x12
+#define TPS62362_DCDC_VOLT_SEL_1100MV		0x21
+#define TPS62362_DCDC_VOLT_SEL_1200MV		0x2b
+#define TPS62362_DCDC_VOLT_SEL_1260MV		0x31
+#define TPS62362_DCDC_VOLT_SEL_1330MV		0x38
+
+int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel);
+int power_tps62362_init(unsigned char bus);
+#endif	/* __POWER_TPS62362_H__ */
diff --git a/roms/u-boot/include/power/tps65090.h b/roms/u-boot/include/power/tps65090.h
new file mode 100644
index 000000000..2716968a8
--- /dev/null
+++ b/roms/u-boot/include/power/tps65090.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __TPS65090_PMIC_H_
+#define __TPS65090_PMIC_H_
+
+/* I2C device address for TPS65090 PMU */
+#define TPS65090_I2C_ADDR	0x48
+
+/* TPS65090 register addresses */
+enum {
+	REG_IRQ1 = 0,
+	REG_CG_CTRL0 = 4,
+	REG_CG_STATUS1 = 0xa,
+	REG_FET_BASE = 0xe,	/* Not a real register, FETs count from here */
+	REG_FET1_CTRL,
+	REG_FET2_CTRL,
+	REG_FET3_CTRL,
+	REG_FET4_CTRL,
+	REG_FET5_CTRL,
+	REG_FET6_CTRL,
+	REG_FET7_CTRL,
+	TPS65090_NUM_REGS,
+};
+
+enum {
+	IRQ1_VBATG = 1 << 3,
+	CG_CTRL0_ENC_MASK	= 0x01,
+
+	MAX_FET_NUM	= 7,
+	MAX_CTRL_READ_TRIES = 5,
+
+	/* TPS65090 FET_CTRL register values */
+	FET_CTRL_TOFET		= 1 << 7,  /* Timeout, startup, overload */
+	FET_CTRL_PGFET		= 1 << 4,  /* Power good for FET status */
+	FET_CTRL_WAIT		= 3 << 2,  /* Overcurrent timeout max */
+	FET_CTRL_ADENFET	= 1 << 1,  /* Enable output auto discharge */
+	FET_CTRL_ENFET		= 1 << 0,  /* Enable FET */
+};
+
+enum {
+	/* Status register fields */
+	TPS65090_ST1_OTC	= 1 << 0,
+	TPS65090_ST1_OCC	= 1 << 1,
+	TPS65090_ST1_STATE_SHIFT = 4,
+	TPS65090_ST1_STATE_MASK	= 0xf << TPS65090_ST1_STATE_SHIFT,
+};
+
+/* Drivers name */
+#define TPS65090_FET_DRIVER	"tps65090_fet"
+
+#endif /* __TPS65090_PMIC_H_ */
diff --git a/roms/u-boot/include/power/tps65217.h b/roms/u-boot/include/power/tps65217.h
new file mode 100644
index 000000000..669a94a6c
--- /dev/null
+++ b/roms/u-boot/include/power/tps65217.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ */
+
+#ifndef __POWER_TPS65217_H__
+#define __POWER_TPS65217_H__
+
+/* I2C chip address */
+#define TPS65217_CHIP_PM			0x24
+
+/* Registers */
+enum {
+	TPS65217_CHIPID				= 0x00,
+	TPS65217_POWER_PATH,
+	TPS65217_INTERRUPT,
+	TPS65217_CHGCONFIG0,
+	TPS65217_CHGCONFIG1,
+	TPS65217_CHGCONFIG2,
+	TPS65217_CHGCONFIG3,
+	TPS65217_WLEDCTRL1,
+	TPS65217_WLEDCTRL2,
+	TPS65217_MUXCTRL,
+	TPS65217_STATUS,
+	TPS65217_PASSWORD,
+	TPS65217_PGOOD,
+	TPS65217_DEFPG,
+	TPS65217_DEFDCDC1,
+	TPS65217_DEFDCDC2,
+	TPS65217_DEFDCDC3,
+	TPS65217_DEFSLEW,
+	TPS65217_DEFLDO1,
+	TPS65217_DEFLDO2,
+	TPS65217_DEFLS1,
+	TPS65217_DEFLS2,
+	TPS65217_ENABLE,
+	TPS65217_RESERVED0, /* no 0x17 register available */
+	TPS65217_DEFUVLO,
+	TPS65217_SEQ1,
+	TPS65217_SEQ2,
+	TPS65217_SEQ3,
+	TPS65217_SEQ4,
+	TPS65217_SEQ5,
+	TPS65217_SEQ6,
+	TPS65217_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65217_PROT_LEVEL_NONE		0x00
+#define TPS65217_PROT_LEVEL_1			0x01
+#define TPS65217_PROT_LEVEL_2			0x02
+
+#define TPS65217_PASSWORD_LOCK_FOR_WRITE	0x00
+#define TPS65217_PASSWORD_UNLOCK		0x7D
+
+#define TPS65217_DCDC_GO			0x80
+
+#define TPS65217_MASK_ALL_BITS			0xFF
+
+#define TPS65217_USB_INPUT_CUR_LIMIT_MASK	0x03
+#define TPS65217_USB_INPUT_CUR_LIMIT_100MA	0x00
+#define TPS65217_USB_INPUT_CUR_LIMIT_500MA	0x01
+#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
+#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
+
+#define TPS65217_DCDC_VOLT_SEL_950MV		0x02
+#define TPS65217_DCDC_VOLT_SEL_1100MV		0x08
+#define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
+#define TPS65217_DCDC_VOLT_SEL_1200MV		0x0c
+#define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
+#define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
+
+#define TPS65217_LDO_MASK			0x1F
+#define TPS65217_LDO_VOLTAGE_OUT_1_8		0x06
+#define TPS65217_LDO_VOLTAGE_OUT_3_3		0x1F
+
+#define TPS65217_PWR_OFF			0x80
+#define TPS65217_PWR_SRC_USB_BITMASK		0x4
+#define TPS65217_PWR_SRC_AC_BITMASK		0x8
+
+int power_tps65217_init(unsigned char bus);
+
+int tps65217_reg_read(uchar src_reg, uchar *src_val);
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+		       uchar mask);
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+#endif	/* __POWER_TPS65217_H__ */
diff --git a/roms/u-boot/include/power/tps65218.h b/roms/u-boot/include/power/tps65218.h
new file mode 100644
index 000000000..bb66c3f3a
--- /dev/null
+++ b/roms/u-boot/include/power/tps65218.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef __POWER_TPS65218_H__
+#define __POWER_TPS65218_H__
+
+#include <linux/bitops.h>
+
+/* I2C chip address */
+#define TPS65218_CHIP_PM			0x24
+
+/* Registers */
+enum {
+	TPS65218_CHIPID				= 0x00,
+	TPS65218_INT1,
+	TPS65218_INT2,
+	TPS65218_INT_MASK1,
+	TPS65218_INT_MASK2,
+	TPS65218_STATUS,
+	TPS65218_CONTROL,
+	TPS65218_FLAG,
+	TPS65218_PASSWORD			= 0x10,
+	TPS65218_ENABLE1,
+	TPS65218_ENABLE2,
+	TPS65218_CONFIG1,
+	TPS65218_CONFIG2,
+	TPS65218_CONFIG3,
+	TPS65218_DCDC1,
+	TPS65218_DCDC2,
+	TPS65218_DCDC3,
+	TPS65218_DCDC4,
+	TPS65218_SLEW,
+	TPS65218_LDO1,
+	TPS65218_SEQ1				= 0x20,
+	TPS65218_SEQ2,
+	TPS65218_SEQ3,
+	TPS65218_SEQ4,
+	TPS65218_SEQ5,
+	TPS65218_SEQ6,
+	TPS65218_SEQ7,
+	TPS65218_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65218_PROT_LEVEL_NONE		0x00
+#define TPS65218_PROT_LEVEL_1			0x01
+#define TPS65218_PROT_LEVEL_2			0x02
+
+#define TPS65218_PASSWORD_LOCK_FOR_WRITE	0x00
+#define TPS65218_PASSWORD_UNLOCK		0x7D
+
+#define TPS65218_DCDC_GO			0x80
+
+#define TPS65218_MASK_ALL_BITS			0xFF
+
+#define TPS65218_DCDC_VSEL_MASK			0x3F
+
+#define TPS65218_DCDC_VOLT_SEL_0950MV		0x0a
+#define TPS65218_DCDC_VOLT_SEL_1100MV		0x19
+#define TPS65218_DCDC_VOLT_SEL_1200MV		0x23
+#define TPS65218_DCDC_VOLT_SEL_1260MV		0x29
+#define TPS65218_DCDC_VOLT_SEL_1330MV		0x30
+#define TPS65218_DCDC3_VOLT_SEL_1350MV		0x12
+#define TPS65218_DCDC3_VOLT_SEL_1200MV		0xC
+
+#define TPS65218_CC_STAT	(BIT(0) | BIT(1))
+#define TPS65218_STATE		(BIT(2) | BIT(3))
+#define TPS65218_PB_STATE	BIT(4)
+#define TPS65218_AC_STATE	BIT(5)
+#define TPS65218_EE		BIT(6)
+#define TPS65218_FSEAL		BIT(7)
+
+int tps65218_reg_read(uchar dest_reg, uchar *dest_val);
+int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+		       uchar mask);
+int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+int tps65218_toggle_fseal(void);
+int tps65218_lock_fseal(void);
+int power_tps65218_init(unsigned char bus);
+#endif	/* __POWER_TPS65218_H__ */
diff --git a/roms/u-boot/include/power/tps65910.h b/roms/u-boot/include/power/tps65910.h
new file mode 100644
index 000000000..21b2a21ee
--- /dev/null
+++ b/roms/u-boot/include/power/tps65910.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU     0
+#define CORE    1
+
+#define TPS65910_SR_I2C_ADDR				0x12
+#define TPS65910_CTRL_I2C_ADDR				0x2D
+
+/* PMIC Register offsets */
+enum {
+	TPS65910_VDD1_REG				= 0x21,
+	TPS65910_VDD1_OP_REG				= 0x22,
+	TPS65910_VDD2_REG				= 0x24,
+	TPS65910_VDD2_OP_REG				= 0x25,
+	TPS65910_DEVCTRL_REG				= 0x3F,
+};
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK				(0x3 << 6)
+#define TPS65910_ILMAX_MASK				(0x1 << 5)
+#define TPS65910_TSTEP_MASK				(0x7 << 2)
+#define TPS65910_ST_MASK				(0x3)
+
+#define TPS65910_REG_VGAIN_SEL_X1			(0x0 << 6)
+#define TPS65910_REG_VGAIN_SEL_X1_0			(0x1 << 6)
+#define TPS65910_REG_VGAIN_SEL_X3			(0x2 << 6)
+#define TPS65910_REG_VGAIN_SEL_X4			(0x3 << 6)
+
+#define TPS65910_REG_ILMAX_1_0_A			(0x0 << 5)
+#define TPS65910_REG_ILMAX_1_5_A			(0x1 << 5)
+
+#define TPS65910_REG_TSTEP_				(0x0 << 2)
+#define TPS65910_REG_TSTEP_12_5				(0x1 << 2)
+#define TPS65910_REG_TSTEP_9_4				(0x2 << 2)
+#define TPS65910_REG_TSTEP_7_5				(0x3 << 2)
+#define TPS65910_REG_TSTEP_6_25				(0x4 << 2)
+#define TPS65910_REG_TSTEP_4_7				(0x5 << 2)
+#define TPS65910_REG_TSTEP_3_12				(0x6 << 2)
+#define TPS65910_REG_TSTEP_2_5				(0x7 << 2)
+
+#define TPS65910_REG_ST_OFF				(0x0)
+#define TPS65910_REG_ST_ON_HI_POW			(0x1)
+#define TPS65910_REG_ST_OFF_1				(0x2)
+#define TPS65910_REG_ST_ON_LOW_POW			(0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define TPS65910_OP_REG_SEL				(0x7F)
+
+#define TPS65910_OP_REG_CMD_MASK			(0x1 << 7)
+#define TPS65910_OP_REG_CMD_OP				(0x0 << 7)
+#define TPS65910_OP_REG_CMD_SR				(0x1 << 7)
+
+#define TPS65910_OP_REG_SEL_MASK			(0x7F)
+#define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_0			(0x2B)	/* 1.1000 V */
+#define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
+#define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
+#define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
+#define TPS65910_OP_REG_SEL_1_3_2_5			(0x3D)	/* 1.3250 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK		(0x1 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
+
+int power_tps65910_init(unsigned char bus);
+int tps65910_set_i2c_control(void);
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
+#endif	/* __POWER_TPS65910_H__ */
diff --git a/roms/u-boot/include/power/tps65910_pmic.h b/roms/u-boot/include/power/tps65910_pmic.h
new file mode 100644
index 000000000..66214786d
--- /dev/null
+++ b/roms/u-boot/include/power/tps65910_pmic.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ */
+
+#ifndef __TPS65910_PMIC_H_
+#define __TPS65910_PMIC_H_
+
+#define TPS65910_I2C_SEL_MASK		(0x1 << 4)
+#define TPS65910_VDD_SR_MASK		(0x1 << 7)
+#define TPS65910_GAIN_SEL_MASK		(0x3 << 6)
+#define TPS65910_VDD_SEL_MASK		0x7f
+#define TPS65910_VDD_SEL_MIN		3
+#define TPS65910_VDD_SEL_MAX		75
+#define TPS65910_SEL_MASK		(0x3 << 2)
+#define TPS65910_SUPPLY_STATE_MASK	0x3
+#define TPS65910_SUPPLY_STATE_OFF	0x0
+#define TPS65910_SUPPLY_STATE_ON	0x1
+
+/* i2c registers */
+enum {
+	TPS65910_REG_RTC_SEC			= 0x00,
+	TPS65910_REG_RTC_MIN,
+	TPS65910_REG_RTC_HOUR,
+	TPS65910_REG_RTC_DAY,
+	TPS65910_REG_RTC_MONTH,
+	TPS65910_REG_RTC_YEAR,
+	TPS65910_REG_RTC_WEEK,
+	TPS65910_REG_RTC_ALARM_SEC		= 0x08,
+	TPS65910_REG_RTC_ALARM_MIN,
+	TPS65910_REG_RTC_ALARM_HOUR,
+	TPS65910_REG_RTC_ALARM_DAY,
+	TPS65910_REG_RTC_ALARM_MONTH,
+	TPS65910_REG_RTC_ALARM_YEAR,
+	TPS65910_REG_RTC_CTRL			= 0x10,
+	TPS65910_REG_RTC_STAT,
+	TPS65910_REG_RTC_INT,
+	TPS65910_REG_RTC_COMP_LSB,
+	TPS65910_REG_RTC_COMP_MSB,
+	TPS65910_REG_RTC_RESISTOR_PRG,
+	TPS65910_REG_RTC_RESET_STAT,
+	TPS65910_REG_BACKUP1,
+	TPS65910_REG_BACKUP2,
+	TPS65910_REG_BACKUP3,
+	TPS65910_REG_BACKUP4,
+	TPS65910_REG_BACKUP5,
+	TPS65910_REG_PUADEN,
+	TPS65910_REG_REF,
+	TPS65910_REG_VRTC,
+	TPS65910_REG_VIO			= 0x20,
+	TPS65910_REG_VDD1,
+	TPS65910_REG_VDD1_VAL,
+	TPS65910_REG_VDD1_VAL_SR,
+	TPS65910_REG_VDD2,
+	TPS65910_REG_VDD2_VAL,
+	TPS65910_REG_VDD2_VAL_SR,
+	TPS65910_REG_VDD3,
+	TPS65910_REG_VDIG1			= 0x30,
+	TPS65910_REG_VDIG2,
+	TPS65910_REG_VAUX1,
+	TPS65910_REG_VAUX2,
+	TPS65910_REG_VAUX33,
+	TPS65910_REG_VMMC,
+	TPS65910_REG_VPLL,
+	TPS65910_REG_VDAC,
+	TPS65910_REG_THERM,
+	TPS65910_REG_BATTERY_BACKUP_CHARGE,
+	TPS65910_REG_DCDC_CTRL			= 0x3e,
+	TPS65910_REG_DEVICE_CTRL,
+	TPS65910_REG_DEVICE_CTRL2,
+	TPS65910_REG_SLEEP_KEEP_LDO_ON,
+	TPS65910_REG_SLEEP_KEEP_RES_ON,
+	TPS65910_REG_SLEEP_SET_LDO_OFF,
+	TPS65910_REG_SLEEP_SET_RES_OFF,
+	TPS65910_REG_EN1_LDO_ASS,
+	TPS65910_REG_EM1_SMPS_ASS,
+	TPS65910_REG_EN2_LDO_ASS,
+	TPS65910_REG_EM2_SMPS_ASS,
+	TPS65910_REG_INT_STAT			= 0x50,
+	TPS65910_REG_INT_MASK,
+	TPS65910_REG_INT_STAT2,
+	TPS65910_REG_INT_MASK2,
+	TPS65910_REG_GPIO			= 0x60,
+	TPS65910_REG_JTAGREVNUM			= 0x80,
+	TPS65910_NUM_REGS
+};
+
+/* chip supplies */
+enum {
+	TPS65910_SUPPLY_VCCIO	= 0x00,
+	TPS65910_SUPPLY_VCC1,
+	TPS65910_SUPPLY_VCC2,
+	TPS65910_SUPPLY_VCC3,
+	TPS65910_SUPPLY_VCC4,
+	TPS65910_SUPPLY_VCC5,
+	TPS65910_SUPPLY_VCC6,
+	TPS65910_SUPPLY_VCC7,
+	TPS65910_NUM_SUPPLIES
+};
+
+/* regulator unit numbers */
+enum {
+	TPS65910_UNIT_VRTC = 0x00,
+	TPS65910_UNIT_VIO,
+	TPS65910_UNIT_VDD1,
+	TPS65910_UNIT_VDD2,
+	TPS65910_UNIT_VDD3,
+	TPS65910_UNIT_VDIG1,
+	TPS65910_UNIT_VDIG2,
+	TPS65910_UNIT_VPLL,
+	TPS65910_UNIT_VDAC,
+	TPS65910_UNIT_VAUX1,
+	TPS65910_UNIT_VAUX2,
+	TPS65910_UNIT_VAUX33,
+	TPS65910_UNIT_VMMC,
+};
+
+/* platform data */
+struct tps65910_regulator_pdata {
+	u32 supply;	/* regulator supply voltage in uV */
+	uint unit;	/* unit-address according to DT */
+};
+
+/* driver names */
+#define TPS65910_BUCK_DRIVER	"tps65910_buck"
+#define TPS65910_BOOST_DRIVER	"tps65910_boost"
+#define TPS65910_LDO_DRIVER	"tps65910_ldo"
+
+#endif /* __TPS65910_PMIC_H_ */
diff --git a/roms/u-boot/include/power/tps65941.h b/roms/u-boot/include/power/tps65941.h
new file mode 100644
index 000000000..2d48b31ae
--- /dev/null
+++ b/roms/u-boot/include/power/tps65941.h
@@ -0,0 +1,26 @@
+#define	TPS659411		0x0
+#define TPS659412		0x1
+#define TPS659413		0x2
+#define TPS659414		0x3
+
+/* I2C device address for pmic tps65941 */
+#define TPS65941_I2C_ADDR	(0x12 >> 1)
+#define TPS65941_LDO_NUM		4
+#define TPS65941_BUCK_NUM		5
+
+/* Drivers name */
+#define TPS65941_LDO_DRIVER		"tps65941_ldo"
+#define TPS65941_BUCK_DRIVER		"tps65941_buck"
+
+#define TPS65941_BUCK_VOLT_MASK		0xFF
+#define TPS65941_BUCK_VOLT_MAX_HEX	0xFF
+#define TPS65941_BUCK_VOLT_MAX		3340000
+#define TPS65941_BUCK_MODE_MASK		0x1
+
+#define TPS65941_LDO_VOLT_MASK		0x3E
+#define TPS65941_LDO_VOLT_MAX_HEX	0x3A
+#define TPS65941_LDO_VOLT_MIN_HEX	0x4
+#define TPS65941_LDO_VOLT_MAX		3300000
+#define TPS65941_LDO_MODE_MASK		0x1
+#define TPS65941_LDO_BYPASS_EN		0x80
+#define TP65941_BUCK_CONF_SLEW_MASK	0x7