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author | 2023-10-10 14:33:42 +0000 | |
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committer | 2023-10-10 14:33:42 +0000 | |
commit | af1a266670d040d2f4083ff309d732d648afba2a (patch) | |
tree | 2fc46203448ddcc6f81546d379abfaeb323575e9 /roms/u-boot/include/zynqmppl.h | |
parent | e02cda008591317b1625707ff8e115a4841aa889 (diff) |
Change-Id: Iaf8d18082d3991dec7c0ebbea540f092188eb4ec
Diffstat (limited to 'roms/u-boot/include/zynqmppl.h')
-rw-r--r-- | roms/u-boot/include/zynqmppl.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/roms/u-boot/include/zynqmppl.h b/roms/u-boot/include/zynqmppl.h new file mode 100644 index 000000000..35cfe17d4 --- /dev/null +++ b/roms/u-boot/include/zynqmppl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2015 Xilinx, Inc, + * Michal Simek <michal.simek@xilinx.com> + */ + +#ifndef _ZYNQMPPL_H_ +#define _ZYNQMPPL_H_ + +#include <xilinx.h> +#include <linux/bitops.h> + +#define ZYNQMP_FPGA_OP_INIT (1 << 0) +#define ZYNQMP_FPGA_OP_LOAD (1 << 1) +#define ZYNQMP_FPGA_OP_DONE (1 << 2) + +#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2) +#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3) + +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ + ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) + +extern struct xilinx_fpga_op zynqmp_op; + +#define XILINX_ZYNQMP_DESC \ +{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } + +#endif /* _ZYNQMPPL_H_ */ |