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diff --git a/capstone/suite/synctools/tablegen/AArch64/AArch64RegisterBanks.td b/capstone/suite/synctools/tablegen/AArch64/AArch64RegisterBanks.td
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+++ b/capstone/suite/synctools/tablegen/AArch64/AArch64RegisterBanks.td
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+//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+/// General Purpose Registers: W, X.
+def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
+
+/// Floating Point/Vector Registers: B, H, S, D, Q.
+def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
+
+/// Conditional register: NZCV.
+def CCRegBank : RegisterBank<"CC", [CCR]>;