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Diffstat (limited to 'capstone/suite/synctools/tablegen/X86/X86InstrSGX.td')
| -rw-r--r-- | capstone/suite/synctools/tablegen/X86/X86InstrSGX.td | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/capstone/suite/synctools/tablegen/X86/X86InstrSGX.td b/capstone/suite/synctools/tablegen/X86/X86InstrSGX.td new file mode 100644 index 000000000..488cc4438 --- /dev/null +++ b/capstone/suite/synctools/tablegen/X86/X86InstrSGX.td @@ -0,0 +1,30 @@ +//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel SGX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// SGX instructions + +let SchedRW = [WriteSystem], Predicates = [HasSGX] in { +// ENCLS - Execute an Enclave System Function of Specified Leaf Number +def ENCLS : I<0x01, MRM_CF, (outs), (ins), + "encls", []>, TB; + +// ENCLU - Execute an Enclave User Function of Specified Leaf Number +def ENCLU : I<0x01, MRM_D7, (outs), (ins), + "enclu", []>, TB; + +// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number +def ENCLV : I<0x01, MRM_C0, (outs), (ins), + "enclv", []>, TB; +} // SchedRW |