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path: root/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c
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Diffstat (limited to 'roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c')
-rw-r--r--roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c
new file mode 100644
index 000000000..08f219c10
--- /dev/null
+++ b/roms/edk2/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c
@@ -0,0 +1,36 @@
+/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+
+VOID
+EFIAPI
+ArmGicV2EnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ /*
+ * Enable the CPU interface in Non-Secure world
+ * Note: The ICCICR register is banked when Security extensions are implemented
+ */
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
+}
+
+VOID
+EFIAPI
+ArmGicV2DisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ // Disable Gic Interface
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
+}