diff options
Diffstat (limited to 'roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei')
10 files changed, 5405 insertions, 0 deletions
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/DmaMem.c b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/DmaMem.c new file mode 100644 index 000000000..2d8bfa1b0 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/DmaMem.c @@ -0,0 +1,242 @@ +/** @file
+ The DMA memory help function.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "EmmcBlockIoPei.h"
+
+EDKII_IOMMU_PPI *mIoMmu;
+
+/**
+ Provides the controller-specific addresses required to access system memory from a
+ DMA bus master.
+
+ @param Operation Indicates if the bus master is going to read or write to system memory.
+ @param HostAddress The system memory address to map to the PCI controller.
+ @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
+ that were mapped.
+ @param DeviceAddress The resulting map address for the bus master PCI controller to use to
+ access the hosts HostAddress.
+ @param Mapping A resulting value to pass to Unmap().
+
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
+
+**/
+EFI_STATUS
+IoMmuMap (
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Attribute;
+
+ if (mIoMmu != NULL) {
+ Status = mIoMmu->Map (
+ mIoMmu,
+ Operation,
+ HostAddress,
+ NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ switch (Operation) {
+ case EdkiiIoMmuOperationBusMasterRead:
+ case EdkiiIoMmuOperationBusMasterRead64:
+ Attribute = EDKII_IOMMU_ACCESS_READ;
+ break;
+ case EdkiiIoMmuOperationBusMasterWrite:
+ case EdkiiIoMmuOperationBusMasterWrite64:
+ Attribute = EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ case EdkiiIoMmuOperationBusMasterCommonBuffer:
+ case EdkiiIoMmuOperationBusMasterCommonBuffer64:
+ Attribute = EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE;
+ break;
+ default:
+ ASSERT(FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+ Status = mIoMmu->SetAttribute (
+ mIoMmu,
+ *Mapping,
+ Attribute
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ } else {
+ *DeviceAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress;
+ *Mapping = NULL;
+ Status = EFI_SUCCESS;
+ }
+ return Status;
+}
+
+/**
+ Completes the Map() operation and releases any corresponding resources.
+
+ @param Mapping The mapping value returned from Map().
+
+ @retval EFI_SUCCESS The range was unmapped.
+ @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
+**/
+EFI_STATUS
+IoMmuUnmap (
+ IN VOID *Mapping
+ )
+{
+ EFI_STATUS Status;
+
+ if (mIoMmu != NULL) {
+ Status = mIoMmu->SetAttribute (mIoMmu, Mapping, 0);
+ Status = mIoMmu->Unmap (mIoMmu, Mapping);
+ } else {
+ Status = EFI_SUCCESS;
+ }
+ return Status;
+}
+
+/**
+ Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
+ OperationBusMasterCommonBuffer64 mapping.
+
+ @param Pages The number of pages to allocate.
+ @param HostAddress A pointer to store the base system memory address of the
+ allocated range.
+ @param DeviceAddress The resulting map address for the bus master PCI controller to use to
+ access the hosts HostAddress.
+ @param Mapping A resulting value to pass to Unmap().
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
+ MEMORY_WRITE_COMBINE and MEMORY_CACHED.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+IoMmuAllocateBuffer (
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumberOfBytes;
+ EFI_PHYSICAL_ADDRESS HostPhyAddress;
+
+ *HostAddress = NULL;
+ *DeviceAddress = 0;
+
+ if (mIoMmu != NULL) {
+ Status = mIoMmu->AllocateBuffer (
+ mIoMmu,
+ EfiBootServicesData,
+ Pages,
+ HostAddress,
+ 0
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ NumberOfBytes = EFI_PAGES_TO_SIZE(Pages);
+ Status = mIoMmu->Map (
+ mIoMmu,
+ EdkiiIoMmuOperationBusMasterCommonBuffer,
+ *HostAddress,
+ &NumberOfBytes,
+ DeviceAddress,
+ Mapping
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ Status = mIoMmu->SetAttribute (
+ mIoMmu,
+ *Mapping,
+ EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ } else {
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesData,
+ Pages,
+ &HostPhyAddress
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ *HostAddress = (VOID *)(UINTN)HostPhyAddress;
+ *DeviceAddress = HostPhyAddress;
+ *Mapping = NULL;
+ }
+ return Status;
+}
+
+/**
+ Frees memory that was allocated with AllocateBuffer().
+
+ @param Pages The number of pages to free.
+ @param HostAddress The base system memory address of the allocated range.
+ @param Mapping The mapping value returned from Map().
+
+ @retval EFI_SUCCESS The requested memory pages were freed.
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+ was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+IoMmuFreeBuffer (
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
+ )
+{
+ EFI_STATUS Status;
+
+ if (mIoMmu != NULL) {
+ Status = mIoMmu->SetAttribute (mIoMmu, Mapping, 0);
+ Status = mIoMmu->Unmap (mIoMmu, Mapping);
+ Status = mIoMmu->FreeBuffer (mIoMmu, Pages, HostAddress);
+ } else {
+ Status = EFI_SUCCESS;
+ }
+ return Status;
+}
+
+/**
+ Initialize IOMMU.
+**/
+VOID
+IoMmuInit (
+ VOID
+ )
+{
+ PeiServicesLocatePpi (
+ &gEdkiiIoMmuPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&mIoMmu
+ );
+}
+
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.c b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.c new file mode 100644 index 000000000..267db4a89 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.c @@ -0,0 +1,843 @@ +/** @file
+
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "EmmcBlockIoPei.h"
+
+//
+// Template for EMMC HC Slot Data.
+//
+EMMC_PEIM_HC_SLOT gEmmcHcSlotTemplate = {
+ EMMC_PEIM_SLOT_SIG, // Signature
+ { // Media
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ },
+ {
+ MSG_EMMC_DP,
+ FALSE,
+ TRUE,
+ FALSE,
+ 0x200,
+ 0
+ }
+ },
+ 0, // MediaNum
+ { // PartitionType
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown,
+ EmmcPartitionUnknown
+ },
+ 0, // EmmcHcBase
+ { // Capability
+ 0,
+ },
+ { // Csd
+ 0,
+ },
+ { // ExtCsd
+ {0},
+ },
+ TRUE, // SectorAddressing
+ NULL // Private
+};
+
+//
+// Template for EMMC HC Private Data.
+//
+EMMC_PEIM_HC_PRIVATE_DATA gEmmcHcPrivateTemplate = {
+ EMMC_PEIM_SIG, // Signature
+ NULL, // Pool
+ { // BlkIoPpi
+ EmmcBlockIoPeimGetDeviceNo,
+ EmmcBlockIoPeimGetMediaInfo,
+ EmmcBlockIoPeimReadBlocks
+ },
+ { // BlkIo2Ppi
+ EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION,
+ EmmcBlockIoPeimGetDeviceNo2,
+ EmmcBlockIoPeimGetMediaInfo2,
+ EmmcBlockIoPeimReadBlocks2
+ },
+ { // BlkIoPpiList
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiPeiVirtualBlockIoPpiGuid,
+ NULL
+ },
+ { // BlkIo2PpiList
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiVirtualBlockIo2PpiGuid,
+ NULL
+ },
+ { // EndOfPeiNotifyList
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ EmmcBlockIoPeimEndOfPei
+ },
+ { // Slot
+ {
+ 0,
+ },
+ {
+ 0,
+ },
+ {
+ 0,
+ },
+ {
+ 0,
+ },
+ {
+ 0,
+ },
+ {
+ 0,
+ }
+ },
+ 0, // SlotNum
+ 0 // TotalBlkIoDevices
+};
+/**
+ Gets the count of block I/O devices that one specific block driver detects.
+
+ This function is used for getting the count of block I/O devices that one
+ specific block driver detects. To the PEI ATAPI driver, it returns the number
+ of all the detected ATAPI devices it detects during the enumeration process.
+ To the PEI legacy floppy driver, it returns the number of all the legacy
+ devices it finds during its enumeration process. If no device is detected,
+ then the function will return zero.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI
+ instance.
+ @param[out] NumberBlockDevices The number of block I/O devices discovered.
+
+ @retval EFI_SUCCESS The operation performed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetDeviceNo (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ )
+{
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS (This);
+ *NumberBlockDevices = Private->TotalBlkIoDevices;
+ return EFI_SUCCESS;
+}
+
+/**
+ Gets a block device's media information.
+
+ This function will provide the caller with the specified block device's media
+ information. If the media changes, calling this function will update the media
+ information accordingly.
+
+ @param[in] PeiServices General-purpose services that are available to every
+ PEIM
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, the PPIs that
+ want to talk to a single device must specify the
+ device index that was assigned during the enumeration
+ process. This index is a number from one to
+ NumberBlockDevices.
+ @param[out] MediaInfo The media information of the specified block media.
+ The caller is responsible for the ownership of this
+ data structure.
+
+ @par Note:
+ The MediaInfo structure describes an enumeration of possible block device
+ types. This enumeration exists because no device paths are actually passed
+ across interfaces that describe the type or class of hardware that is publishing
+ the block I/O interface. This enumeration will allow for policy decisions
+ in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+ LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+ by a given device type, they should be reported in ascending order; this
+ order also applies to nested partitions, such as legacy MBR, where the
+ outermost partitions would have precedence in the reporting order. The
+ same logic applies to systems such as IDE that have precedence relationships
+ like "Master/Slave" or "Primary/Secondary". The master device should be
+ reported first, the slave second.
+
+ @retval EFI_SUCCESS Media information about the specified block device
+ was obtained successfully.
+ @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetMediaInfo (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
+ )
+{
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+ UINT8 SlotNum;
+ UINT8 MediaNum;
+ UINT8 Location;
+ BOOLEAN Found;
+
+ Found = FALSE;
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS (This);
+
+ if ((DeviceIndex == 0) || (DeviceIndex > Private->TotalBlkIoDevices)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Location = 0;
+ MediaNum = 0;
+ for (SlotNum = 0; SlotNum < Private->SlotNum; SlotNum++) {
+ for (MediaNum = 0; MediaNum < Private->Slot[SlotNum].MediaNum; MediaNum++) {
+ Location ++;
+ if (Location == DeviceIndex) {
+ Found = TRUE;
+ break;
+ }
+ }
+ if (Found) {
+ break;
+ }
+ }
+
+ MediaInfo->DeviceType = EMMC;
+ MediaInfo->MediaPresent = TRUE;
+ MediaInfo->LastBlock = (UINTN)Private->Slot[SlotNum].Media[MediaNum].LastBlock;
+ MediaInfo->BlockSize = Private->Slot[SlotNum].Media[MediaNum].BlockSize;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads the requested number of blocks from the specified block device.
+
+ The function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to read from
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the read operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimReadBlocks (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT32 BlockSize;
+ UINTN NumberOfBlocks;
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+ UINT8 SlotNum;
+ UINT8 MediaNum;
+ UINT8 Location;
+ UINT8 PartitionConfig;
+ UINTN Remaining;
+ UINT32 MaxBlock;
+ BOOLEAN Found;
+
+ Status = EFI_SUCCESS;
+ Found = FALSE;
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS (This);
+
+ //
+ // Check parameters
+ //
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (BufferSize == 0) {
+ return EFI_SUCCESS;
+ }
+
+ if ((DeviceIndex == 0) || (DeviceIndex > Private->TotalBlkIoDevices)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Location = 0;
+ MediaNum = 0;
+ for (SlotNum = 0; SlotNum < Private->SlotNum; SlotNum++) {
+ for (MediaNum = 0; MediaNum < Private->Slot[SlotNum].MediaNum; MediaNum++) {
+ Location ++;
+ if (Location == DeviceIndex) {
+ Found = TRUE;
+ break;
+ }
+ }
+ if (Found) {
+ break;
+ }
+ }
+
+ BlockSize = Private->Slot[SlotNum].Media[MediaNum].BlockSize;
+ if (BufferSize % BlockSize != 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ if (StartLBA > Private->Slot[SlotNum].Media[MediaNum].LastBlock) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NumberOfBlocks = BufferSize / BlockSize;
+
+ //
+ // Check if needs to switch partition access.
+ //
+ PartitionConfig = Private->Slot[SlotNum].ExtCsd.PartitionConfig;
+ if ((PartitionConfig & 0x7) != Private->Slot[SlotNum].PartitionType[MediaNum]) {
+ PartitionConfig &= (UINT8)~0x7;
+ PartitionConfig |= Private->Slot[SlotNum].PartitionType[MediaNum];
+ Status = EmmcPeimSwitch (
+ &Private->Slot[SlotNum],
+ 0x3,
+ OFFSET_OF (EMMC_EXT_CSD, PartitionConfig),
+ PartitionConfig,
+ 0x0
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ Private->Slot[SlotNum].ExtCsd.PartitionConfig = PartitionConfig;
+ }
+ //
+ // Start to execute data transfer. The max block number in single cmd is 65535 blocks.
+ //
+ Remaining = NumberOfBlocks;
+ MaxBlock = 0xFFFF;
+
+ while (Remaining > 0) {
+ if (Remaining <= MaxBlock) {
+ NumberOfBlocks = Remaining;
+ } else {
+ NumberOfBlocks = MaxBlock;
+ }
+
+ Status = EmmcPeimSetBlkCount (&Private->Slot[SlotNum], (UINT16)NumberOfBlocks);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ BufferSize = NumberOfBlocks * BlockSize;
+ Status = EmmcPeimRwMultiBlocks (&Private->Slot[SlotNum], StartLBA, BlockSize, Buffer, BufferSize, TRUE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ StartLBA += NumberOfBlocks;
+ Buffer = (UINT8*)Buffer + BufferSize;
+ Remaining -= NumberOfBlocks;
+ }
+ return Status;
+}
+
+/**
+ Gets the count of block I/O devices that one specific block driver detects.
+
+ This function is used for getting the count of block I/O devices that one
+ specific block driver detects. To the PEI ATAPI driver, it returns the number
+ of all the detected ATAPI devices it detects during the enumeration process.
+ To the PEI legacy floppy driver, it returns the number of all the legacy
+ devices it finds during its enumeration process. If no device is detected,
+ then the function will return zero.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI
+ instance.
+ @param[out] NumberBlockDevices The number of block I/O devices discovered.
+
+ @retval EFI_SUCCESS The operation performed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetDeviceNo2 (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ )
+{
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS2 (This);
+ *NumberBlockDevices = Private->TotalBlkIoDevices;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Gets a block device's media information.
+
+ This function will provide the caller with the specified block device's media
+ information. If the media changes, calling this function will update the media
+ information accordingly.
+
+ @param[in] PeiServices General-purpose services that are available to every
+ PEIM
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, the PPIs that
+ want to talk to a single device must specify the
+ device index that was assigned during the enumeration
+ process. This index is a number from one to
+ NumberBlockDevices.
+ @param[out] MediaInfo The media information of the specified block media.
+ The caller is responsible for the ownership of this
+ data structure.
+
+ @par Note:
+ The MediaInfo structure describes an enumeration of possible block device
+ types. This enumeration exists because no device paths are actually passed
+ across interfaces that describe the type or class of hardware that is publishing
+ the block I/O interface. This enumeration will allow for policy decisions
+ in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+ LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+ by a given device type, they should be reported in ascending order; this
+ order also applies to nested partitions, such as legacy MBR, where the
+ outermost partitions would have precedence in the reporting order. The
+ same logic applies to systems such as IDE that have precedence relationships
+ like "Master/Slave" or "Primary/Secondary". The master device should be
+ reported first, the slave second.
+
+ @retval EFI_SUCCESS Media information about the specified block device
+ was obtained successfully.
+ @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetMediaInfo2 (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
+ )
+{
+ EFI_STATUS Status;
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+ EFI_PEI_BLOCK_IO_MEDIA Media;
+ UINT8 SlotNum;
+ UINT8 MediaNum;
+ UINT8 Location;
+ BOOLEAN Found;
+
+ Found = FALSE;
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS2 (This);
+
+ Status = EmmcBlockIoPeimGetMediaInfo (
+ PeiServices,
+ &Private->BlkIoPpi,
+ DeviceIndex,
+ &Media
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Location = 0;
+ MediaNum = 0;
+ for (SlotNum = 0; SlotNum < Private->SlotNum; SlotNum++) {
+ for (MediaNum = 0; MediaNum < Private->Slot[SlotNum].MediaNum; MediaNum++) {
+ Location ++;
+ if (Location == DeviceIndex) {
+ Found = TRUE;
+ break;
+ }
+ }
+ if (Found) {
+ break;
+ }
+ }
+
+ CopyMem (MediaInfo, &(Private->Slot[SlotNum].Media[MediaNum]), sizeof (EFI_PEI_BLOCK_IO2_MEDIA));
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads the requested number of blocks from the specified block device.
+
+ The function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to read from
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the read operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimReadBlocks2 (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+
+ Status = EFI_SUCCESS;
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS2 (This);
+
+ Status = EmmcBlockIoPeimReadBlocks (
+ PeiServices,
+ &Private->BlkIoPpi,
+ DeviceIndex,
+ StartLBA,
+ BufferSize,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ One notified function to cleanup the allocated DMA buffers at the end of PEI.
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDescriptor Pointer to the descriptor for the Notification
+ event that caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimEndOfPei (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+
+ Private = GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY (NotifyDescriptor);
+
+ if ((Private->Pool != NULL) && (Private->Pool->Head != NULL)) {
+ EmmcPeimFreeMemPool (Private->Pool);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The user code starts with this function.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS The driver is successfully initialized.
+ @retval Others Can't initialize the driver.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeEmmcBlockIoPeim (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+ EDKII_SD_MMC_HOST_CONTROLLER_PPI *SdMmcHcPpi;
+ UINT32 Index;
+ UINT32 PartitionIndex;
+ UINTN *MmioBase;
+ UINT8 BarNum;
+ UINT8 SlotNum;
+ UINT8 MediaNum;
+ UINT8 Controller;
+ UINT64 Capacity;
+ EMMC_EXT_CSD *ExtCsd;
+ EMMC_HC_SLOT_CAP Capability;
+ EMMC_PEIM_HC_SLOT *Slot;
+ UINT32 SecCount;
+ UINT32 GpSizeMult;
+
+ //
+ // Shadow this PEIM to run from memory
+ //
+ if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // locate Emmc host controller PPI
+ //
+ Status = PeiServicesLocatePpi (
+ &gEdkiiPeiSdMmcHostControllerPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SdMmcHcPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ IoMmuInit ();
+
+ Controller = 0;
+ MmioBase = NULL;
+ while (TRUE) {
+ Status = SdMmcHcPpi->GetSdMmcHcMmioBar (SdMmcHcPpi, Controller, &MmioBase, &BarNum);
+ //
+ // When status is error, meant no controller is found
+ //
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ if (BarNum == 0) {
+ Controller++;
+ continue;
+ }
+
+ Private = AllocateCopyPool (sizeof (EMMC_PEIM_HC_PRIVATE_DATA), &gEmmcHcPrivateTemplate);
+ if (Private == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ break;
+ }
+ Private->BlkIoPpiList.Ppi = (VOID*)&Private->BlkIoPpi;
+ Private->BlkIo2PpiList.Ppi = (VOID*)&Private->BlkIo2Ppi;
+ //
+ // Initialize the memory pool which will be used in all transactions.
+ //
+ Status = EmmcPeimInitMemPool (Private);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_OUT_OF_RESOURCES;
+ break;
+ }
+
+ for (Index = 0; Index < BarNum; Index++) {
+ Status = EmmcPeimHcGetCapability (MmioBase[Index], &Capability);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ if (Capability.SlotType != 0x1) {
+ DEBUG ((EFI_D_INFO, "The slot at 0x%x is not embedded slot type\n", MmioBase[Index]));
+ Status = EFI_UNSUPPORTED;
+ continue;
+ }
+
+ Status = EmmcPeimHcReset (MmioBase[Index]);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ Status = EmmcPeimHcCardDetect (MmioBase[Index]);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ Status = EmmcPeimHcInitHost (MmioBase[Index]);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+
+ SlotNum = Private->SlotNum;
+ Slot = &Private->Slot[SlotNum];
+ CopyMem (Slot, &gEmmcHcSlotTemplate, sizeof (EMMC_PEIM_HC_SLOT));
+ Slot->Private = Private;
+ Slot->EmmcHcBase = MmioBase[Index];
+ CopyMem (&Slot->Capability, &Capability, sizeof (Capability));
+
+ Status = EmmcPeimIdentification (Slot);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+
+ ExtCsd = &Slot->ExtCsd;
+ if (ExtCsd->ExtCsdRev < 5) {
+ DEBUG ((EFI_D_ERROR, "The EMMC device version is too low, we don't support!!!\n"));
+ Status = EFI_UNSUPPORTED;
+ continue;
+ }
+ if ((ExtCsd->PartitioningSupport & BIT0) != BIT0) {
+ DEBUG ((EFI_D_ERROR, "The EMMC device doesn't support Partition Feature!!!\n"));
+ Status = EFI_UNSUPPORTED;
+ continue;
+ }
+
+ for (PartitionIndex = 0; PartitionIndex < EMMC_PEIM_MAX_PARTITIONS; PartitionIndex++) {
+ switch (PartitionIndex) {
+ case EmmcPartitionUserData:
+ SecCount = *(UINT32*)&ExtCsd->SecCount;
+ Capacity = MultU64x32 ((UINT64)SecCount, 0x200);
+ break;
+ case EmmcPartitionBoot1:
+ case EmmcPartitionBoot2:
+ Capacity = ExtCsd->BootSizeMult * SIZE_128KB;
+ break;
+ case EmmcPartitionRPMB:
+ Capacity = ExtCsd->RpmbSizeMult * SIZE_128KB;
+ break;
+ case EmmcPartitionGP1:
+ GpSizeMult = (ExtCsd->GpSizeMult[0] | (ExtCsd->GpSizeMult[1] << 8) | (ExtCsd->GpSizeMult[2] << 16));
+ Capacity = MultU64x32 (MultU64x32 (MultU64x32 ((UINT64)GpSizeMult, ExtCsd->HcWpGrpSize), ExtCsd->HcEraseGrpSize), SIZE_512KB);
+ break;
+ case EmmcPartitionGP2:
+ GpSizeMult = (ExtCsd->GpSizeMult[3] | (ExtCsd->GpSizeMult[4] << 8) | (ExtCsd->GpSizeMult[5] << 16));
+ Capacity = MultU64x32 (MultU64x32 (MultU64x32 ((UINT64)GpSizeMult, ExtCsd->HcWpGrpSize), ExtCsd->HcEraseGrpSize), SIZE_512KB);
+ break;
+ case EmmcPartitionGP3:
+ GpSizeMult = (ExtCsd->GpSizeMult[6] | (ExtCsd->GpSizeMult[7] << 8) | (ExtCsd->GpSizeMult[8] << 16));
+ Capacity = MultU64x32 (MultU64x32 (MultU64x32 ((UINT64)GpSizeMult, ExtCsd->HcWpGrpSize), ExtCsd->HcEraseGrpSize), SIZE_512KB);
+ break;
+ case EmmcPartitionGP4:
+ GpSizeMult = (ExtCsd->GpSizeMult[9] | (ExtCsd->GpSizeMult[10] << 8) | (ExtCsd->GpSizeMult[11] << 16));
+ Capacity = MultU64x32 (MultU64x32 (MultU64x32 ((UINT64)GpSizeMult, ExtCsd->HcWpGrpSize), ExtCsd->HcEraseGrpSize), SIZE_512KB);
+ break;
+ default:
+ ASSERT (FALSE);
+ continue;
+ }
+
+ MediaNum = Slot->MediaNum;
+ if (Capacity != 0) {
+ Slot->Media[MediaNum].LastBlock = DivU64x32 (Capacity, Slot->Media[MediaNum].BlockSize) - 1;
+ Slot->PartitionType[MediaNum] = PartitionIndex;
+ Private->TotalBlkIoDevices++;
+ Slot->MediaNum++;
+ }
+ }
+ Private->SlotNum++;
+ }
+ Controller++;
+
+ if (!EFI_ERROR (Status)) {
+ PeiServicesInstallPpi (&Private->BlkIoPpiList);
+ PeiServicesNotifyPpi (&Private->EndOfPeiNotifyList);
+ } else {
+ if (Private->Pool->Head != NULL) {
+ EmmcPeimFreeMemPool (Private->Pool);
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.h b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.h new file mode 100644 index 000000000..774274e48 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.h @@ -0,0 +1,514 @@ +/** @file
+
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _EMMC_BLOCK_IO_PEI_H_
+#define _EMMC_BLOCK_IO_PEI_H_
+
+#include <PiPei.h>
+
+#include <Ppi/SdMmcHostController.h>
+#include <Ppi/BlockIo.h>
+#include <Ppi/BlockIo2.h>
+#include <Ppi/IoMmu.h>
+#include <Ppi/EndOfPeiPhase.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <IndustryStandard/Emmc.h>
+
+typedef struct _EMMC_PEIM_HC_PRIVATE_DATA EMMC_PEIM_HC_PRIVATE_DATA;
+typedef struct _EMMC_PEIM_HC_SLOT EMMC_PEIM_HC_SLOT;
+typedef struct _EMMC_TRB EMMC_TRB;
+
+#include "EmmcHci.h"
+#include "EmmcHcMem.h"
+
+#define EMMC_PEIM_SIG SIGNATURE_32 ('E', 'M', 'C', 'P')
+#define EMMC_PEIM_SLOT_SIG SIGNATURE_32 ('E', 'M', 'C', 'S')
+
+#define EMMC_PEIM_MAX_SLOTS 6
+#define EMMC_PEIM_MAX_PARTITIONS 8
+
+struct _EMMC_PEIM_HC_SLOT {
+ UINT32 Signature;
+ EFI_PEI_BLOCK_IO2_MEDIA Media[EMMC_PEIM_MAX_PARTITIONS];
+ UINT8 MediaNum;
+ EMMC_PARTITION_TYPE PartitionType[EMMC_PEIM_MAX_PARTITIONS];
+
+ UINTN EmmcHcBase;
+ EMMC_HC_SLOT_CAP Capability;
+ EMMC_CSD Csd;
+ EMMC_EXT_CSD ExtCsd;
+ BOOLEAN SectorAddressing;
+ EMMC_PEIM_HC_PRIVATE_DATA *Private;
+};
+
+struct _EMMC_PEIM_HC_PRIVATE_DATA {
+ UINT32 Signature;
+ EMMC_PEIM_MEM_POOL *Pool;
+ EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
+ EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
+ EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
+ EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
+
+ //
+ // EndOfPei callback is used to do the cleanups before exit of PEI phase.
+ //
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
+
+ EMMC_PEIM_HC_SLOT Slot[EMMC_PEIM_MAX_SLOTS];
+ UINT8 SlotNum;
+ UINT8 TotalBlkIoDevices;
+};
+
+#define EMMC_TIMEOUT MultU64x32((UINT64)(3), 1000000)
+#define GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS(a) CR (a, EMMC_PEIM_HC_PRIVATE_DATA, BlkIoPpi, EMMC_PEIM_SIG)
+#define GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS2(a) CR (a, EMMC_PEIM_HC_PRIVATE_DATA, BlkIo2Ppi, EMMC_PEIM_SIG)
+#define GET_EMMC_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) CR (a, EMMC_PEIM_HC_PRIVATE_DATA, EndOfPeiNotifyList, EMMC_PEIM_SIG)
+
+struct _EMMC_TRB {
+ EMMC_PEIM_HC_SLOT *Slot;
+ UINT16 BlockSize;
+
+ EMMC_COMMAND_PACKET *Packet;
+ VOID *Data;
+ UINT32 DataLen;
+ BOOLEAN Read;
+ EFI_PHYSICAL_ADDRESS DataPhy;
+ VOID *DataMap;
+ EMMC_HC_TRANSFER_MODE Mode;
+
+ UINT64 Timeout;
+
+ EMMC_HC_ADMA_DESC_LINE *AdmaDesc;
+ UINTN AdmaDescSize;
+};
+
+/**
+ Gets the count of block I/O devices that one specific block driver detects.
+
+ This function is used for getting the count of block I/O devices that one
+ specific block driver detects. To the PEI ATAPI driver, it returns the number
+ of all the detected ATAPI devices it detects during the enumeration process.
+ To the PEI legacy floppy driver, it returns the number of all the legacy
+ devices it finds during its enumeration process. If no device is detected,
+ then the function will return zero.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI
+ instance.
+ @param[out] NumberBlockDevices The number of block I/O devices discovered.
+
+ @retval EFI_SUCCESS The operation performed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetDeviceNo (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ );
+
+/**
+ Gets a block device's media information.
+
+ This function will provide the caller with the specified block device's media
+ information. If the media changes, calling this function will update the media
+ information accordingly.
+
+ @param[in] PeiServices General-purpose services that are available to every
+ PEIM
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, the PPIs that
+ want to talk to a single device must specify the
+ device index that was assigned during the enumeration
+ process. This index is a number from one to
+ NumberBlockDevices.
+ @param[out] MediaInfo The media information of the specified block media.
+ The caller is responsible for the ownership of this
+ data structure.
+
+ @par Note:
+ The MediaInfo structure describes an enumeration of possible block device
+ types. This enumeration exists because no device paths are actually passed
+ across interfaces that describe the type or class of hardware that is publishing
+ the block I/O interface. This enumeration will allow for policy decisions
+ in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+ LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+ by a given device type, they should be reported in ascending order; this
+ order also applies to nested partitions, such as legacy MBR, where the
+ outermost partitions would have precedence in the reporting order. The
+ same logic applies to systems such as IDE that have precedence relationships
+ like "Master/Slave" or "Primary/Secondary". The master device should be
+ reported first, the slave second.
+
+ @retval EFI_SUCCESS Media information about the specified block device
+ was obtained successfully.
+ @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetMediaInfo (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
+ );
+
+/**
+ Reads the requested number of blocks from the specified block device.
+
+ The function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to read from
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the read operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimReadBlocks (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Gets the count of block I/O devices that one specific block driver detects.
+
+ This function is used for getting the count of block I/O devices that one
+ specific block driver detects. To the PEI ATAPI driver, it returns the number
+ of all the detected ATAPI devices it detects during the enumeration process.
+ To the PEI legacy floppy driver, it returns the number of all the legacy
+ devices it finds during its enumeration process. If no device is detected,
+ then the function will return zero.
+
+ @param[in] PeiServices General-purpose services that are available
+ to every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI
+ instance.
+ @param[out] NumberBlockDevices The number of block I/O devices discovered.
+
+ @retval EFI_SUCCESS The operation performed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetDeviceNo2 (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ OUT UINTN *NumberBlockDevices
+ );
+
+/**
+ Gets a block device's media information.
+
+ This function will provide the caller with the specified block device's media
+ information. If the media changes, calling this function will update the media
+ information accordingly.
+
+ @param[in] PeiServices General-purpose services that are available to every
+ PEIM
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, the PPIs that
+ want to talk to a single device must specify the
+ device index that was assigned during the enumeration
+ process. This index is a number from one to
+ NumberBlockDevices.
+ @param[out] MediaInfo The media information of the specified block media.
+ The caller is responsible for the ownership of this
+ data structure.
+
+ @par Note:
+ The MediaInfo structure describes an enumeration of possible block device
+ types. This enumeration exists because no device paths are actually passed
+ across interfaces that describe the type or class of hardware that is publishing
+ the block I/O interface. This enumeration will allow for policy decisions
+ in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+ LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+ by a given device type, they should be reported in ascending order; this
+ order also applies to nested partitions, such as legacy MBR, where the
+ outermost partitions would have precedence in the reporting order. The
+ same logic applies to systems such as IDE that have precedence relationships
+ like "Master/Slave" or "Primary/Secondary". The master device should be
+ reported first, the slave second.
+
+ @retval EFI_SUCCESS Media information about the specified block device
+ was obtained successfully.
+ @retval EFI_DEVICE_ERROR Cannot get the media information due to a hardware
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimGetMediaInfo2 (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ OUT EFI_PEI_BLOCK_IO2_MEDIA *MediaInfo
+ );
+
+/**
+ Reads the requested number of blocks from the specified block device.
+
+ The function reads the requested number of blocks from the device. All the
+ blocks are read, or an error is returned. If there is no media in the device,
+ the function returns EFI_NO_MEDIA.
+
+ @param[in] PeiServices General-purpose services that are available to
+ every PEIM.
+ @param[in] This Indicates the EFI_PEI_RECOVERY_BLOCK_IO2_PPI instance.
+ @param[in] DeviceIndex Specifies the block device to which the function wants
+ to talk. Because the driver that implements Block I/O
+ PPIs will manage multiple block devices, PPIs that
+ want to talk to a single device must specify the device
+ index that was assigned during the enumeration process.
+ This index is a number from one to NumberBlockDevices.
+ @param[in] StartLBA The starting logical block address (LBA) to read from
+ on the device
+ @param[in] BufferSize The size of the Buffer in bytes. This number must be
+ a multiple of the intrinsic block size of the device.
+ @param[out] Buffer A pointer to the destination buffer for the data.
+ The caller is responsible for the ownership of the
+ buffer.
+
+ @retval EFI_SUCCESS The data was read correctly from the device.
+ @retval EFI_DEVICE_ERROR The device reported an error while attempting
+ to perform the read operation.
+ @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not
+ valid, or the buffer is not properly aligned.
+ @retval EFI_NO_MEDIA There is no media in the device.
+ @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of
+ the intrinsic block size of the device.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimReadBlocks2 (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_BLOCK_IO2_PPI *This,
+ IN UINTN DeviceIndex,
+ IN EFI_PEI_LBA StartLBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer
+ );
+
+/**
+ Initialize the memory management pool for the host controller.
+
+ @param Private The Emmc Peim driver private data.
+
+ @retval EFI_SUCCESS The memory pool is initialized.
+ @retval Others Fail to init the memory pool.
+
+**/
+EFI_STATUS
+EmmcPeimInitMemPool (
+ IN EMMC_PEIM_HC_PRIVATE_DATA *Private
+ );
+
+/**
+ Release the memory management pool.
+
+ @param Pool The memory pool to free.
+
+ @retval EFI_DEVICE_ERROR Fail to free the memory pool.
+ @retval EFI_SUCCESS The memory pool is freed.
+
+**/
+EFI_STATUS
+EmmcPeimFreeMemPool (
+ IN EMMC_PEIM_MEM_POOL *Pool
+ );
+
+/**
+ Allocate some memory from the host controller's memory pool
+ which can be used to communicate with host controller.
+
+ @param Pool The host controller's memory pool.
+ @param Size Size of the memory to allocate.
+
+ @return The allocated memory or NULL.
+
+**/
+VOID *
+EmmcPeimAllocateMem (
+ IN EMMC_PEIM_MEM_POOL *Pool,
+ IN UINTN Size
+ );
+
+/**
+ Free the allocated memory back to the memory pool.
+
+ @param Pool The memory pool of the host controller.
+ @param Mem The memory to free.
+ @param Size The size of the memory to free.
+
+**/
+VOID
+EmmcPeimFreeMem (
+ IN EMMC_PEIM_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
+ );
+
+/**
+ Initialize IOMMU.
+**/
+VOID
+IoMmuInit (
+ VOID
+ );
+
+/**
+ Provides the controller-specific addresses required to access system memory from a
+ DMA bus master.
+
+ @param Operation Indicates if the bus master is going to read or write to system memory.
+ @param HostAddress The system memory address to map to the PCI controller.
+ @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
+ that were mapped.
+ @param DeviceAddress The resulting map address for the bus master PCI controller to use to
+ access the hosts HostAddress.
+ @param Mapping A resulting value to pass to Unmap().
+
+ @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
+ @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
+
+**/
+EFI_STATUS
+IoMmuMap (
+ IN EDKII_IOMMU_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+/**
+ Completes the Map() operation and releases any corresponding resources.
+
+ @param Mapping The mapping value returned from Map().
+
+ @retval EFI_SUCCESS The range was unmapped.
+ @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
+ @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
+**/
+EFI_STATUS
+IoMmuUnmap (
+ IN VOID *Mapping
+ );
+
+/**
+ Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
+ OperationBusMasterCommonBuffer64 mapping.
+
+ @param Pages The number of pages to allocate.
+ @param HostAddress A pointer to store the base system memory address of the
+ allocated range.
+ @param DeviceAddress The resulting map address for the bus master PCI controller to use to
+ access the hosts HostAddress.
+ @param Mapping A resulting value to pass to Unmap().
+
+ @retval EFI_SUCCESS The requested memory pages were allocated.
+ @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
+ MEMORY_WRITE_COMBINE and MEMORY_CACHED.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+ @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
+
+**/
+EFI_STATUS
+IoMmuAllocateBuffer (
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+/**
+ Frees memory that was allocated with AllocateBuffer().
+
+ @param Pages The number of pages to free.
+ @param HostAddress The base system memory address of the allocated range.
+ @param Mapping The mapping value returned from Map().
+
+ @retval EFI_SUCCESS The requested memory pages were freed.
+ @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
+ was not allocated with AllocateBuffer().
+
+**/
+EFI_STATUS
+IoMmuFreeBuffer (
+ IN UINTN Pages,
+ IN VOID *HostAddress,
+ IN VOID *Mapping
+ );
+
+/**
+ One notified function to cleanup the allocated DMA buffers at the end of PEI.
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDescriptor Pointer to the descriptor for the Notification
+ event that caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcBlockIoPeimEndOfPei (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+#endif
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.inf b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.inf new file mode 100644 index 000000000..8ab632eb3 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.inf @@ -0,0 +1,60 @@ +## @file
+# Description file for the Embedded MMC (eMMC) Peim driver.
+#
+# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = EmmcBlockIoPei
+ MODULE_UNI_FILE = EmmcBlockIoPei.uni
+ FILE_GUID = 7F06A90F-AE0D-4887-82C0-FEC7F4F68B29
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeEmmcBlockIoPeim
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[Sources]
+ EmmcBlockIoPei.c
+ EmmcBlockIoPei.h
+ EmmcHci.c
+ EmmcHci.h
+ EmmcHcMem.c
+ EmmcHcMem.h
+ DmaMem.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ IoLib
+ TimerLib
+ BaseMemoryLib
+ PeimEntryPoint
+ PeiServicesLib
+ DebugLib
+
+[Ppis]
+ gEfiPeiVirtualBlockIoPpiGuid ## PRODUCES
+ gEfiPeiVirtualBlockIo2PpiGuid ## PRODUCES
+ gEdkiiPeiSdMmcHostControllerPpiGuid ## CONSUMES
+ gEdkiiIoMmuPpiGuid ## CONSUMES
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid AND gEdkiiPeiSdMmcHostControllerPpiGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ EmmcBlockIoPeiExtra.uni
+
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.uni b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.uni new file mode 100644 index 000000000..8c4c79c1a --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPei.uni @@ -0,0 +1,14 @@ +// /** @file
+// The EmmcBlockIoPei driver is used to support recovery from EMMC device.
+//
+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Support recovery from EMMC devices"
+
+#string STR_MODULE_DESCRIPTION #language en-US "The EmmcBlockIoPei driver is used to support recovery from EMMC device."
+
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPeiExtra.uni b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPeiExtra.uni new file mode 100644 index 000000000..feeb1b34f --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcBlockIoPeiExtra.uni @@ -0,0 +1,14 @@ +// /** @file
+// EmmcBlockIoPei Localized Strings and Content
+//
+// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"EMMC BlockIo Peim for Recovery"
+
+
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHcMem.c b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHcMem.c new file mode 100644 index 000000000..19a0afcb6 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHcMem.c @@ -0,0 +1,429 @@ +/** @file
+
+Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "EmmcBlockIoPei.h"
+
+/**
+ Allocate a block of memory to be used by the buffer pool.
+
+ @param Pages How many pages to allocate.
+
+ @return The allocated memory block or NULL if failed.
+
+**/
+EMMC_PEIM_MEM_BLOCK *
+EmmcPeimAllocMemBlock (
+ IN UINTN Pages
+ )
+{
+ EMMC_PEIM_MEM_BLOCK *Block;
+ VOID *BufHost;
+ VOID *Mapping;
+ EFI_PHYSICAL_ADDRESS MappedAddr;
+ EFI_STATUS Status;
+ VOID *TempPtr;
+
+ TempPtr = NULL;
+ Block = NULL;
+
+ Status = PeiServicesAllocatePool (sizeof(EMMC_PEIM_MEM_BLOCK), &TempPtr);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ ZeroMem ((VOID*)(UINTN)TempPtr, sizeof(EMMC_PEIM_MEM_BLOCK));
+
+ //
+ // each bit in the bit array represents EMMC_PEIM_MEM_UNIT
+ // bytes of memory in the memory block.
+ //
+ ASSERT (EMMC_PEIM_MEM_UNIT * 8 <= EFI_PAGE_SIZE);
+
+ Block = (EMMC_PEIM_MEM_BLOCK*)(UINTN)TempPtr;
+ Block->BufLen = EFI_PAGES_TO_SIZE (Pages);
+ Block->BitsLen = Block->BufLen / (EMMC_PEIM_MEM_UNIT * 8);
+
+ Status = PeiServicesAllocatePool (Block->BitsLen, &TempPtr);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ ZeroMem ((VOID*)(UINTN)TempPtr, Block->BitsLen);
+
+ Block->Bits = (UINT8*)(UINTN)TempPtr;
+
+ Status = IoMmuAllocateBuffer (
+ Pages,
+ &BufHost,
+ &MappedAddr,
+ &Mapping
+ );
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ ZeroMem ((VOID*)(UINTN)BufHost, EFI_PAGES_TO_SIZE (Pages));
+
+ Block->BufHost = (UINT8 *) (UINTN) BufHost;
+ Block->Buf = (UINT8 *) (UINTN) MappedAddr;
+ Block->Mapping = Mapping;
+ Block->Next = NULL;
+
+ return Block;
+}
+
+/**
+ Free the memory block from the memory pool.
+
+ @param Pool The memory pool to free the block from.
+ @param Block The memory block to free.
+
+**/
+VOID
+EmmcPeimFreeMemBlock (
+ IN EMMC_PEIM_MEM_POOL *Pool,
+ IN EMMC_PEIM_MEM_BLOCK *Block
+ )
+{
+ ASSERT ((Pool != NULL) && (Block != NULL));
+
+ IoMmuFreeBuffer (EFI_SIZE_TO_PAGES (Block->BufLen), Block->BufHost, Block->Mapping);
+}
+
+/**
+ Alloc some memory from the block.
+
+ @param Block The memory block to allocate memory from.
+ @param Units Number of memory units to allocate.
+
+ @return The pointer to the allocated memory. If couldn't allocate the needed memory,
+ the return value is NULL.
+
+**/
+VOID *
+EmmcPeimAllocMemFromBlock (
+ IN EMMC_PEIM_MEM_BLOCK *Block,
+ IN UINTN Units
+ )
+{
+ UINTN Byte;
+ UINT8 Bit;
+ UINTN StartByte;
+ UINT8 StartBit;
+ UINTN Available;
+ UINTN Count;
+
+ ASSERT ((Block != 0) && (Units != 0));
+
+ StartByte = 0;
+ StartBit = 0;
+ Available = 0;
+
+ for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) {
+ //
+ // If current bit is zero, the corresponding memory unit is
+ // available, otherwise we need to restart our searching.
+ // Available counts the consecutive number of zero bit.
+ //
+ if (!EMMC_PEIM_MEM_BIT_IS_SET (Block->Bits[Byte], Bit)) {
+ Available++;
+
+ if (Available >= Units) {
+ break;
+ }
+
+ EMMC_PEIM_NEXT_BIT (Byte, Bit);
+
+ } else {
+ EMMC_PEIM_NEXT_BIT (Byte, Bit);
+
+ Available = 0;
+ StartByte = Byte;
+ StartBit = Bit;
+ }
+ }
+
+ if (Available < Units) {
+ return NULL;
+ }
+
+ //
+ // Mark the memory as allocated
+ //
+ Byte = StartByte;
+ Bit = StartBit;
+
+ for (Count = 0; Count < Units; Count++) {
+ ASSERT (!EMMC_PEIM_MEM_BIT_IS_SET (Block->Bits[Byte], Bit));
+
+ Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | (UINT8) EMMC_PEIM_MEM_BIT (Bit));
+ EMMC_PEIM_NEXT_BIT (Byte, Bit);
+ }
+
+ return Block->Buf + (StartByte * 8 + StartBit) * EMMC_PEIM_MEM_UNIT;
+}
+
+/**
+ Insert the memory block to the pool's list of the blocks.
+
+ @param Head The head of the memory pool's block list.
+ @param Block The memory block to insert.
+
+**/
+VOID
+EmmcPeimInsertMemBlockToPool (
+ IN EMMC_PEIM_MEM_BLOCK *Head,
+ IN EMMC_PEIM_MEM_BLOCK *Block
+ )
+{
+ ASSERT ((Head != NULL) && (Block != NULL));
+ Block->Next = Head->Next;
+ Head->Next = Block;
+}
+
+/**
+ Is the memory block empty?
+
+ @param Block The memory block to check.
+
+ @retval TRUE The memory block is empty.
+ @retval FALSE The memory block isn't empty.
+
+**/
+BOOLEAN
+EmmcPeimIsMemBlockEmpty (
+ IN EMMC_PEIM_MEM_BLOCK *Block
+ )
+{
+ UINTN Index;
+
+
+ for (Index = 0; Index < Block->BitsLen; Index++) {
+ if (Block->Bits[Index] != 0) {
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+
+
+/**
+ Initialize the memory management pool for the host controller.
+
+ @param Private The Emmc Peim driver private data.
+
+ @retval EFI_SUCCESS The memory pool is initialized.
+ @retval Others Fail to init the memory pool.
+
+**/
+EFI_STATUS
+EmmcPeimInitMemPool (
+ IN EMMC_PEIM_HC_PRIVATE_DATA *Private
+ )
+{
+ EMMC_PEIM_MEM_POOL *Pool;
+ EFI_STATUS Status;
+ VOID *TempPtr;
+
+ TempPtr = NULL;
+ Pool = NULL;
+
+ Status = PeiServicesAllocatePool (sizeof (EMMC_PEIM_MEM_POOL), &TempPtr);
+ if (EFI_ERROR (Status)) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem ((VOID*)(UINTN)TempPtr, sizeof (EMMC_PEIM_MEM_POOL));
+
+ Pool = (EMMC_PEIM_MEM_POOL *)((UINTN)TempPtr);
+
+ Pool->Head = EmmcPeimAllocMemBlock (EMMC_PEIM_MEM_DEFAULT_PAGES);
+
+ if (Pool->Head == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Private->Pool = Pool;
+ return EFI_SUCCESS;
+}
+
+/**
+ Release the memory management pool.
+
+ @param Pool The memory pool to free.
+
+ @retval EFI_DEVICE_ERROR Fail to free the memory pool.
+ @retval EFI_SUCCESS The memory pool is freed.
+
+**/
+EFI_STATUS
+EmmcPeimFreeMemPool (
+ IN EMMC_PEIM_MEM_POOL *Pool
+ )
+{
+ EMMC_PEIM_MEM_BLOCK *Block;
+
+ ASSERT (Pool->Head != NULL);
+
+ //
+ // Unlink all the memory blocks from the pool, then free them.
+ //
+ for (Block = Pool->Head->Next; Block != NULL; Block = Pool->Head->Next) {
+ EmmcPeimFreeMemBlock (Pool, Block);
+ }
+
+ EmmcPeimFreeMemBlock (Pool, Pool->Head);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Allocate some memory from the host controller's memory pool
+ which can be used to communicate with host controller.
+
+ @param Pool The host controller's memory pool.
+ @param Size Size of the memory to allocate.
+
+ @return The allocated memory or NULL.
+
+**/
+VOID *
+EmmcPeimAllocateMem (
+ IN EMMC_PEIM_MEM_POOL *Pool,
+ IN UINTN Size
+ )
+{
+ EMMC_PEIM_MEM_BLOCK *Head;
+ EMMC_PEIM_MEM_BLOCK *Block;
+ EMMC_PEIM_MEM_BLOCK *NewBlock;
+ VOID *Mem;
+ UINTN AllocSize;
+ UINTN Pages;
+
+ Mem = NULL;
+ AllocSize = EMMC_PEIM_MEM_ROUND (Size);
+ Head = Pool->Head;
+ ASSERT (Head != NULL);
+
+ //
+ // First check whether current memory blocks can satisfy the allocation.
+ //
+ for (Block = Head; Block != NULL; Block = Block->Next) {
+ Mem = EmmcPeimAllocMemFromBlock (Block, AllocSize / EMMC_PEIM_MEM_UNIT);
+
+ if (Mem != NULL) {
+ ZeroMem (Mem, Size);
+ break;
+ }
+ }
+
+ if (Mem != NULL) {
+ return Mem;
+ }
+
+ //
+ // Create a new memory block if there is not enough memory
+ // in the pool. If the allocation size is larger than the
+ // default page number, just allocate a large enough memory
+ // block. Otherwise allocate default pages.
+ //
+ if (AllocSize > EFI_PAGES_TO_SIZE (EMMC_PEIM_MEM_DEFAULT_PAGES)) {
+ Pages = EFI_SIZE_TO_PAGES (AllocSize) + 1;
+ } else {
+ Pages = EMMC_PEIM_MEM_DEFAULT_PAGES;
+ }
+
+ NewBlock = EmmcPeimAllocMemBlock (Pages);
+ if (NewBlock == NULL) {
+ return NULL;
+ }
+
+ //
+ // Add the new memory block to the pool, then allocate memory from it
+ //
+ EmmcPeimInsertMemBlockToPool (Head, NewBlock);
+ Mem = EmmcPeimAllocMemFromBlock (NewBlock, AllocSize / EMMC_PEIM_MEM_UNIT);
+
+ if (Mem != NULL) {
+ ZeroMem (Mem, Size);
+ }
+
+ return Mem;
+}
+
+/**
+ Free the allocated memory back to the memory pool.
+
+ @param Pool The memory pool of the host controller.
+ @param Mem The memory to free.
+ @param Size The size of the memory to free.
+
+**/
+VOID
+EmmcPeimFreeMem (
+ IN EMMC_PEIM_MEM_POOL *Pool,
+ IN VOID *Mem,
+ IN UINTN Size
+ )
+{
+ EMMC_PEIM_MEM_BLOCK *Head;
+ EMMC_PEIM_MEM_BLOCK *Block;
+ UINT8 *ToFree;
+ UINTN AllocSize;
+ UINTN Byte;
+ UINTN Bit;
+ UINTN Count;
+
+ Head = Pool->Head;
+ AllocSize = EMMC_PEIM_MEM_ROUND (Size);
+ ToFree = (UINT8 *) Mem;
+
+ for (Block = Head; Block != NULL; Block = Block->Next) {
+ //
+ // scan the memory block list for the memory block that
+ // completely contains the memory to free.
+ //
+ if ((Block->Buf <= ToFree) && ((ToFree + AllocSize) <= (Block->Buf + Block->BufLen))) {
+ //
+ // compute the start byte and bit in the bit array
+ //
+ Byte = ((ToFree - Block->Buf) / EMMC_PEIM_MEM_UNIT) / 8;
+ Bit = ((ToFree - Block->Buf) / EMMC_PEIM_MEM_UNIT) % 8;
+
+ //
+ // reset associated bits in bit array
+ //
+ for (Count = 0; Count < (AllocSize / EMMC_PEIM_MEM_UNIT); Count++) {
+ ASSERT (EMMC_PEIM_MEM_BIT_IS_SET (Block->Bits[Byte], Bit));
+
+ Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ EMMC_PEIM_MEM_BIT (Bit));
+ EMMC_PEIM_NEXT_BIT (Byte, Bit);
+ }
+
+ break;
+ }
+ }
+
+ //
+ // If Block == NULL, it means that the current memory isn't
+ // in the host controller's pool. This is critical because
+ // the caller has passed in a wrong memory point
+ //
+ ASSERT (Block != NULL);
+
+ //
+ // Release the current memory block if it is empty and not the head
+ //
+ if ((Block != Head) && EmmcPeimIsMemBlockEmpty (Block)) {
+ EmmcPeimFreeMemBlock (Pool, Block);
+ }
+
+ return ;
+}
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHcMem.h b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHcMem.h new file mode 100644 index 000000000..255ad345d --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHcMem.h @@ -0,0 +1,56 @@ +/** @file
+
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _EMMC_PEIM_MEM_H_
+#define _EMMC_PEIM_MEM_H_
+
+#define EMMC_PEIM_MEM_BIT(a) ((UINTN)(1 << (a)))
+
+#define EMMC_PEIM_MEM_BIT_IS_SET(Data, Bit) \
+ ((BOOLEAN)(((Data) & EMMC_PEIM_MEM_BIT(Bit)) == EMMC_PEIM_MEM_BIT(Bit)))
+
+typedef struct _EMMC_PEIM_MEM_BLOCK EMMC_PEIM_MEM_BLOCK;
+
+struct _EMMC_PEIM_MEM_BLOCK {
+ UINT8 *Bits; // Bit array to record which unit is allocated
+ UINTN BitsLen;
+ UINT8 *Buf;
+ UINT8 *BufHost;
+ UINTN BufLen; // Memory size in bytes
+ VOID *Mapping;
+ EMMC_PEIM_MEM_BLOCK *Next;
+};
+
+typedef struct _EMMC_PEIM_MEM_POOL {
+ EMMC_PEIM_MEM_BLOCK *Head;
+} EMMC_PEIM_MEM_POOL;
+
+//
+// Memory allocation unit, note that the value must meet EMMC spec alignment requirement.
+//
+#define EMMC_PEIM_MEM_UNIT 128
+
+#define EMMC_PEIM_MEM_UNIT_MASK (EMMC_PEIM_MEM_UNIT - 1)
+#define EMMC_PEIM_MEM_DEFAULT_PAGES 16
+
+#define EMMC_PEIM_MEM_ROUND(Len) (((Len) + EMMC_PEIM_MEM_UNIT_MASK) & (~EMMC_PEIM_MEM_UNIT_MASK))
+
+//
+// Advance the byte and bit to the next bit, adjust byte accordingly.
+//
+#define EMMC_PEIM_NEXT_BIT(Byte, Bit) \
+ do { \
+ (Bit)++; \
+ if ((Bit) > 7) { \
+ (Byte)++; \
+ (Bit) = 0; \
+ } \
+ } while (0)
+
+#endif
+
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHci.c b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHci.c new file mode 100644 index 000000000..287a10266 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHci.c @@ -0,0 +1,2894 @@ +/** @file
+
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "EmmcBlockIoPei.h"
+
+/**
+ Read/Write specified EMMC host controller mmio register.
+
+ @param[in] Address The address of the mmio register to be read/written.
+ @param[in] Read A boolean to indicate it's read or write operation.
+ @param[in] Count The width of the mmio register in bytes.
+ Must be 1, 2 , 4 or 8 bytes.
+ @param[in, out] Data For read operations, the destination buffer to store
+ the results. For write operations, the source buffer
+ to write data from. The caller is responsible for
+ having ownership of the data buffer and ensuring its
+ size not less than Count bytes.
+
+ @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.
+ @retval EFI_SUCCESS The read/write operation succeeds.
+ @retval Others The read/write operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcPeimHcRwMmio (
+ IN UINTN Address,
+ IN BOOLEAN Read,
+ IN UINT8 Count,
+ IN OUT VOID *Data
+ )
+{
+ if ((Address == 0) || (Data == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (Count) {
+ case 1:
+ if (Read) {
+ *(UINT8*)Data = MmioRead8 (Address);
+ } else {
+ MmioWrite8 (Address, *(UINT8*)Data);
+ }
+ break;
+ case 2:
+ if (Read) {
+ *(UINT16*)Data = MmioRead16 (Address);
+ } else {
+ MmioWrite16 (Address, *(UINT16*)Data);
+ }
+ break;
+ case 4:
+ if (Read) {
+ *(UINT32*)Data = MmioRead32 (Address);
+ } else {
+ MmioWrite32 (Address, *(UINT32*)Data);
+ }
+ break;
+ case 8:
+ if (Read) {
+ *(UINT64*)Data = MmioRead64 (Address);
+ } else {
+ MmioWrite64 (Address, *(UINT64*)Data);
+ }
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Do OR operation with the value of the specified EMMC host controller mmio register.
+
+ @param[in] Address The address of the mmio register to be read/written.
+ @param[in] Count The width of the mmio register in bytes.
+ Must be 1, 2 , 4 or 8 bytes.
+ @param[in] OrData The pointer to the data used to do OR operation.
+ The caller is responsible for having ownership of
+ the data buffer and ensuring its size not less than
+ Count bytes.
+
+ @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.
+ @retval EFI_SUCCESS The OR operation succeeds.
+ @retval Others The OR operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcPeimHcOrMmio (
+ IN UINTN Address,
+ IN UINT8 Count,
+ IN VOID *OrData
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Data;
+ UINT64 Or;
+
+ Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (Count == 1) {
+ Or = *(UINT8*) OrData;
+ } else if (Count == 2) {
+ Or = *(UINT16*) OrData;
+ } else if (Count == 4) {
+ Or = *(UINT32*) OrData;
+ } else if (Count == 8) {
+ Or = *(UINT64*) OrData;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Data |= Or;
+ Status = EmmcPeimHcRwMmio (Address, FALSE, Count, &Data);
+
+ return Status;
+}
+
+/**
+ Do AND operation with the value of the specified EMMC host controller mmio register.
+
+ @param[in] Address The address of the mmio register to be read/written.
+ @param[in] Count The width of the mmio register in bytes.
+ Must be 1, 2 , 4 or 8 bytes.
+ @param[in] AndData The pointer to the data used to do AND operation.
+ The caller is responsible for having ownership of
+ the data buffer and ensuring its size not less than
+ Count bytes.
+
+ @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.
+ @retval EFI_SUCCESS The AND operation succeeds.
+ @retval Others The AND operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcPeimHcAndMmio (
+ IN UINTN Address,
+ IN UINT8 Count,
+ IN VOID *AndData
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Data;
+ UINT64 And;
+
+ Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (Count == 1) {
+ And = *(UINT8*) AndData;
+ } else if (Count == 2) {
+ And = *(UINT16*) AndData;
+ } else if (Count == 4) {
+ And = *(UINT32*) AndData;
+ } else if (Count == 8) {
+ And = *(UINT64*) AndData;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Data &= And;
+ Status = EmmcPeimHcRwMmio (Address, FALSE, Count, &Data);
+
+ return Status;
+}
+
+/**
+ Wait for the value of the specified MMIO register set to the test value.
+
+ @param[in] Address The address of the mmio register to be checked.
+ @param[in] Count The width of the mmio register in bytes.
+ Must be 1, 2, 4 or 8 bytes.
+ @param[in] MaskValue The mask value of memory.
+ @param[in] TestValue The test value of memory.
+
+ @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
+ @retval EFI_SUCCESS The MMIO register has expected value.
+ @retval Others The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcPeimHcCheckMmioSet (
+ IN UINTN Address,
+ IN UINT8 Count,
+ IN UINT64 MaskValue,
+ IN UINT64 TestValue
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Value;
+
+ //
+ // Access PCI MMIO space to see if the value is the tested one.
+ //
+ Value = 0;
+ Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Value);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Value &= MaskValue;
+
+ if (Value == TestValue) {
+ return EFI_SUCCESS;
+ }
+
+ return EFI_NOT_READY;
+}
+
+/**
+ Wait for the value of the specified MMIO register set to the test value.
+
+ @param[in] Address The address of the mmio register to wait.
+ @param[in] Count The width of the mmio register in bytes.
+ Must be 1, 2, 4 or 8 bytes.
+ @param[in] MaskValue The mask value of memory.
+ @param[in] TestValue The test value of memory.
+ @param[in] Timeout The time out value for wait memory set, uses 1
+ microsecond as a unit.
+
+ @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
+ range.
+ @retval EFI_SUCCESS The MMIO register has expected value.
+ @retval Others The MMIO operation fails.
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcPeimHcWaitMmioSet (
+ IN UINTN Address,
+ IN UINT8 Count,
+ IN UINT64 MaskValue,
+ IN UINT64 TestValue,
+ IN UINT64 Timeout
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN InfiniteWait;
+
+ if (Timeout == 0) {
+ InfiniteWait = TRUE;
+ } else {
+ InfiniteWait = FALSE;
+ }
+
+ while (InfiniteWait || (Timeout > 0)) {
+ Status = EmmcPeimHcCheckMmioSet (
+ Address,
+ Count,
+ MaskValue,
+ TestValue
+ );
+ if (Status != EFI_NOT_READY) {
+ return Status;
+ }
+
+ //
+ // Stall for 1 microsecond.
+ //
+ MicroSecondDelay (1);
+
+ Timeout--;
+ }
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Software reset the specified EMMC host controller and enable all interrupts.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The software reset executes successfully.
+ @retval Others The software reset fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcReset (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ UINT8 SwReset;
+
+ SwReset = 0xFF;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimHcReset: write full 1 fails: %r\n", Status));
+ return Status;
+ }
+
+ Status = EmmcPeimHcWaitMmioSet (
+ Bar + EMMC_HC_SW_RST,
+ sizeof (SwReset),
+ 0xFF,
+ 0x00,
+ EMMC_TIMEOUT
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO, "EmmcPeimHcReset: reset done with %r\n", Status));
+ return Status;
+ }
+ //
+ // Enable all interrupt after reset all.
+ //
+ Status = EmmcPeimHcEnableInterrupt (Bar);
+
+ return Status;
+}
+
+/**
+ Set all interrupt status bits in Normal and Error Interrupt Status Enable
+ register.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The operation executes successfully.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcEnableInterrupt (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ UINT16 IntStatus;
+
+ //
+ // Enable all bits in Error Interrupt Status Enable Register
+ //
+ IntStatus = 0xFFFF;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Enable all bits in Normal Interrupt Status Enable Register
+ //
+ IntStatus = 0xFFFF;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
+
+ return Status;
+}
+
+/**
+ Get the capability data from the specified slot.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[out] Capability The buffer to store the capability data.
+
+ @retval EFI_SUCCESS The operation executes successfully.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcGetCapability (
+ IN UINTN Bar,
+ OUT EMMC_HC_SLOT_CAP *Capability
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Cap;
+
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ CopyMem (Capability, &Cap, sizeof (Cap));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Detect whether there is a EMMC card attached at the specified EMMC host controller
+ slot.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS There is a EMMC card attached.
+ @retval EFI_NO_MEDIA There is not a EMMC card attached.
+ @retval Others The detection fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcCardDetect (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Data;
+ UINT32 PresentState;
+
+ //
+ // Check Normal Interrupt Status Register
+ //
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Data & (BIT6 | BIT7)) != 0) {
+ //
+ // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
+ //
+ Data &= BIT6 | BIT7;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ //
+ // Check Present State Register to see if there is a card presented.
+ //
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((PresentState & BIT16) != 0) {
+ return EFI_SUCCESS;
+ } else {
+ return EFI_NO_MEDIA;
+ }
+}
+
+/**
+ Stop EMMC card clock.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS Succeed to stop EMMC clock.
+ @retval Others Fail to stop EMMC clock.
+
+**/
+EFI_STATUS
+EmmcPeimHcStopClock (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ UINT32 PresentState;
+ UINT16 ClockCtrl;
+
+ //
+ // Ensure no SD transactions are occurring on the SD Bus by
+ // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
+ // in the Present State register to be 0.
+ //
+ Status = EmmcPeimHcWaitMmioSet (
+ Bar + EMMC_HC_PRESENT_STATE,
+ sizeof (PresentState),
+ BIT0 | BIT1,
+ 0,
+ EMMC_TIMEOUT
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Set SD Clock Enable in the Clock Control register to 0
+ //
+ ClockCtrl = (UINT16)~BIT2;
+ Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+
+ return Status;
+}
+
+/**
+ EMMC card clock supply.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
+
+ @retval EFI_SUCCESS The clock is supplied successfully.
+ @retval Others The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcClockSupply (
+ IN UINTN Bar,
+ IN UINT64 ClockFreq
+ )
+{
+ EFI_STATUS Status;
+ EMMC_HC_SLOT_CAP Capability;
+ UINT32 BaseClkFreq;
+ UINT32 SettingFreq;
+ UINT32 Divisor;
+ UINT32 Remainder;
+ UINT16 ControllerVer;
+ UINT16 ClockCtrl;
+
+ //
+ // Calculate a divisor for SD clock frequency
+ //
+ Status = EmmcPeimHcGetCapability (Bar, &Capability);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ ASSERT (Capability.BaseClkFreq != 0);
+
+ BaseClkFreq = Capability.BaseClkFreq;
+
+ if (ClockFreq == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (ClockFreq > (BaseClkFreq * 1000)) {
+ ClockFreq = BaseClkFreq * 1000;
+ }
+
+ //
+ // Calculate the divisor of base frequency.
+ //
+ Divisor = 0;
+ SettingFreq = BaseClkFreq * 1000;
+ while (ClockFreq < SettingFreq) {
+ Divisor++;
+
+ SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
+ Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
+ if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
+ break;
+ }
+ if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
+ SettingFreq ++;
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
+
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
+ //
+ if ((ControllerVer & 0xFF) == 2) {
+ ASSERT (Divisor <= 0x3FF);
+ ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
+ } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
+ //
+ // Only the most significant bit can be used as divisor.
+ //
+ if (((Divisor - 1) & Divisor) != 0) {
+ Divisor = 1 << (HighBitSet32 (Divisor) + 1);
+ }
+ ASSERT (Divisor <= 0x80);
+ ClockCtrl = (Divisor & 0xFF) << 8;
+ } else {
+ DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Stop bus clock at first
+ //
+ Status = EmmcPeimHcStopClock (Bar);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Supply clock frequency with specified divisor
+ //
+ ClockCtrl |= BIT0;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
+ return Status;
+ }
+
+ //
+ // Wait Internal Clock Stable in the Clock Control register to be 1
+ //
+ Status = EmmcPeimHcWaitMmioSet (
+ Bar + EMMC_HC_CLOCK_CTRL,
+ sizeof (ClockCtrl),
+ BIT1,
+ BIT1,
+ EMMC_TIMEOUT
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Set SD Clock Enable in the Clock Control register to 1
+ //
+ ClockCtrl = BIT2;
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+
+ return Status;
+}
+
+/**
+ EMMC bus power control.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] PowerCtrl The value setting to the power control register.
+
+ @retval TRUE There is a EMMC card attached.
+ @retval FALSE There is no a EMMC card attached.
+
+**/
+EFI_STATUS
+EmmcPeimHcPowerControl (
+ IN UINTN Bar,
+ IN UINT8 PowerCtrl
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Clr SD Bus Power
+ //
+ PowerCtrl &= (UINT8)~BIT0;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
+ //
+ PowerCtrl |= BIT0;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
+
+ return Status;
+}
+
+/**
+ Set the EMMC bus width.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] BusWidth The bus width used by the EMMC device, it must be 1, 4 or 8.
+
+ @retval EFI_SUCCESS The bus width is set successfully.
+ @retval Others The bus width isn't set successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcSetBusWidth (
+ IN UINTN Bar,
+ IN UINT16 BusWidth
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HostCtrl1;
+
+ if (BusWidth == 1) {
+ HostCtrl1 = (UINT8)~(BIT5 | BIT1);
+ Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ } else if (BusWidth == 4) {
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ HostCtrl1 |= BIT1;
+ HostCtrl1 &= (UINT8)~BIT5;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
+ } else if (BusWidth == 8) {
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ HostCtrl1 &= (UINT8)~BIT1;
+ HostCtrl1 |= BIT5;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return Status;
+}
+
+/**
+ Supply EMMC card with lowest clock frequency at initialization.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The clock is supplied successfully.
+ @retval Others The clock isn't supplied successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcInitClockFreq (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ EMMC_HC_SLOT_CAP Capability;
+ UINT32 InitFreq;
+
+ //
+ // Calculate a divisor for SD clock frequency
+ //
+ Status = EmmcPeimHcGetCapability (Bar, &Capability);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (Capability.BaseClkFreq == 0) {
+ //
+ // Don't support get Base Clock Frequency information via another method
+ //
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Supply 400KHz clock frequency at initialization phase.
+ //
+ InitFreq = 400;
+ Status = EmmcPeimHcClockSupply (Bar, InitFreq);
+ return Status;
+}
+
+/**
+ Supply EMMC card with maximum voltage at initialization.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The voltage is supplied successfully.
+ @retval Others The voltage isn't supplied successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcInitPowerVoltage (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ EMMC_HC_SLOT_CAP Capability;
+ UINT8 MaxVoltage;
+ UINT8 HostCtrl2;
+
+ //
+ // Get the support voltage of the Host Controller
+ //
+ Status = EmmcPeimHcGetCapability (Bar, &Capability);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Calculate supported maximum voltage according to SD Bus Voltage Select
+ //
+ if (Capability.Voltage33 != 0) {
+ //
+ // Support 3.3V
+ //
+ MaxVoltage = 0x0E;
+ } else if (Capability.Voltage30 != 0) {
+ //
+ // Support 3.0V
+ //
+ MaxVoltage = 0x0C;
+ } else if (Capability.Voltage18 != 0) {
+ //
+ // Support 1.8V
+ //
+ MaxVoltage = 0x0A;
+ HostCtrl2 = BIT3;
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ MicroSecondDelay (5000);
+ } else {
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
+ //
+ Status = EmmcPeimHcPowerControl (Bar, MaxVoltage);
+
+ return Status;
+}
+
+/**
+ Initialize the Timeout Control register with most conservative value at initialization.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The timeout control register is configured successfully.
+ @retval Others The timeout control register isn't configured successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcInitTimeoutCtrl (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Timeout;
+
+ Timeout = 0x0E;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
+
+ return Status;
+}
+
+/**
+ Initial EMMC host controller with lowest clock frequency, max power and max timeout value
+ at initialization.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The host controller is initialized successfully.
+ @retval Others The host controller isn't initialized successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcInitHost (
+ IN UINTN Bar
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EmmcPeimHcInitClockFreq (Bar);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EmmcPeimHcInitPowerVoltage (Bar);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EmmcPeimHcInitTimeoutCtrl (Bar);
+ return Status;
+}
+
+/**
+ Turn on/off LED.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] On The boolean to turn on/off LED.
+
+ @retval EFI_SUCCESS The LED is turned on/off successfully.
+ @retval Others The LED isn't turned on/off successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcLedOnOff (
+ IN UINTN Bar,
+ IN BOOLEAN On
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HostCtrl1;
+
+ if (On) {
+ HostCtrl1 = BIT0;
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ } else {
+ HostCtrl1 = (UINT8)~BIT0;
+ Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ }
+
+ return Status;
+}
+
+/**
+ Build ADMA descriptor table for transfer.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
+
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+ @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
+ @retval Others The ADMA descriptor table isn't created successfully.
+
+**/
+EFI_STATUS
+BuildAdmaDescTable (
+ IN EMMC_TRB *Trb
+ )
+{
+ EFI_PHYSICAL_ADDRESS Data;
+ UINT64 DataLen;
+ UINT64 Entries;
+ UINT32 Index;
+ UINT64 Remaining;
+ UINT32 Address;
+
+ Data = Trb->DataPhy;
+ DataLen = Trb->DataLen;
+ //
+ // Only support 32bit ADMA Descriptor Table
+ //
+ if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
+ // for 32-bit address descriptor table.
+ //
+ if ((Data & (BIT0 | BIT1)) != 0) {
+ DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
+ }
+
+ Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
+
+ Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (EMMC_HC_ADMA_DESC_LINE));
+ Trb->AdmaDesc = EmmcPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);
+ if (Trb->AdmaDesc == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Remaining = DataLen;
+ Address = (UINT32)Data;
+ for (Index = 0; Index < Entries; Index++) {
+ if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
+ Trb->AdmaDesc[Index].Valid = 1;
+ Trb->AdmaDesc[Index].Act = 2;
+ Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
+ Trb->AdmaDesc[Index].Address = Address;
+ break;
+ } else {
+ Trb->AdmaDesc[Index].Valid = 1;
+ Trb->AdmaDesc[Index].Act = 2;
+ Trb->AdmaDesc[Index].Length = 0;
+ Trb->AdmaDesc[Index].Address = Address;
+ }
+
+ Remaining -= ADMA_MAX_DATA_PER_LINE;
+ Address += ADMA_MAX_DATA_PER_LINE;
+ }
+
+ //
+ // Set the last descriptor line as end of descriptor table
+ //
+ Trb->AdmaDesc[Index].End = 1;
+ return EFI_SUCCESS;
+}
+
+/**
+ Create a new TRB for the EMMC cmd request.
+
+ @param[in] Slot The slot number of the EMMC card to send the command to.
+ @param[in] Packet A pointer to the SD command data structure.
+
+ @return Created Trb or NULL.
+
+**/
+EMMC_TRB *
+EmmcPeimCreateTrb (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN EMMC_COMMAND_PACKET *Packet
+ )
+{
+ EMMC_TRB *Trb;
+ EFI_STATUS Status;
+ EMMC_HC_SLOT_CAP Capability;
+ EDKII_IOMMU_OPERATION MapOp;
+ UINTN MapLength;
+
+ //
+ // Calculate a divisor for SD clock frequency
+ //
+ Status = EmmcPeimHcGetCapability (Slot->EmmcHcBase, &Capability);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ Trb = AllocateZeroPool (sizeof (EMMC_TRB));
+ if (Trb == NULL) {
+ return NULL;
+ }
+
+ Trb->Slot = Slot;
+ Trb->BlockSize = 0x200;
+ Trb->Packet = Packet;
+ Trb->Timeout = Packet->Timeout;
+
+ if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
+ Trb->Data = Packet->InDataBuffer;
+ Trb->DataLen = Packet->InTransferLength;
+ Trb->Read = TRUE;
+ } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
+ Trb->Data = Packet->OutDataBuffer;
+ Trb->DataLen = Packet->OutTransferLength;
+ Trb->Read = FALSE;
+ } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
+ Trb->Data = NULL;
+ Trb->DataLen = 0;
+ } else {
+ goto Error;
+ }
+
+ if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
+ Trb->BlockSize = (UINT16)Trb->DataLen;
+ }
+
+ if (Packet->EmmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK) {
+ Trb->Mode = EmmcPioMode;
+ } else {
+ if (Trb->Read) {
+ MapOp = EdkiiIoMmuOperationBusMasterWrite;
+ } else {
+ MapOp = EdkiiIoMmuOperationBusMasterRead;
+ }
+
+ if (Trb->DataLen != 0) {
+ MapLength = Trb->DataLen;
+ Status = IoMmuMap (MapOp, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);
+
+ if (EFI_ERROR (Status) || (MapLength != Trb->DataLen)) {
+ DEBUG ((DEBUG_ERROR, "EmmcPeimCreateTrb: Fail to map data buffer.\n"));
+ goto Error;
+ }
+ }
+
+ if (Trb->DataLen == 0) {
+ Trb->Mode = EmmcNoData;
+ } else if (Capability.Adma2 != 0) {
+ Trb->Mode = EmmcAdmaMode;
+ Status = BuildAdmaDescTable (Trb);
+ if (EFI_ERROR (Status)) {
+ goto Error;
+ }
+ } else if (Capability.Sdma != 0) {
+ Trb->Mode = EmmcSdmaMode;
+ } else {
+ Trb->Mode = EmmcPioMode;
+ }
+ }
+ return Trb;
+
+Error:
+ EmmcPeimFreeTrb (Trb);
+ return NULL;
+}
+
+/**
+ Free the resource used by the TRB.
+
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+**/
+VOID
+EmmcPeimFreeTrb (
+ IN EMMC_TRB *Trb
+ )
+{
+ if ((Trb != NULL) && (Trb->DataMap != NULL)) {
+ IoMmuUnmap (Trb->DataMap);
+ }
+
+ if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
+ EmmcPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);
+ }
+
+ if (Trb != NULL) {
+ FreePool (Trb);
+ }
+ return;
+}
+
+/**
+ Check if the env is ready for execute specified TRB.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+ @retval EFI_SUCCESS The env is ready for TRB execution.
+ @retval EFI_NOT_READY The env is not ready for TRB execution.
+ @retval Others Some erros happen.
+
+**/
+EFI_STATUS
+EmmcPeimCheckTrbEnv (
+ IN UINTN Bar,
+ IN EMMC_TRB *Trb
+ )
+{
+ EFI_STATUS Status;
+ EMMC_COMMAND_PACKET *Packet;
+ UINT32 PresentState;
+
+ Packet = Trb->Packet;
+
+ if ((Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) ||
+ (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR1b) ||
+ (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR5b)) {
+ //
+ // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
+ // the Present State register to be 0
+ //
+ PresentState = BIT0 | BIT1;
+ } else {
+ //
+ // Wait Command Inhibit (CMD) in the Present State register
+ // to be 0
+ //
+ PresentState = BIT0;
+ }
+
+ Status = EmmcPeimHcCheckMmioSet (
+ Bar + EMMC_HC_PRESENT_STATE,
+ sizeof (PresentState),
+ PresentState,
+ 0
+ );
+
+ return Status;
+}
+
+/**
+ Wait for the env to be ready for execute specified TRB.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+ @retval EFI_SUCCESS The env is ready for TRB execution.
+ @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
+ @retval Others Some erros happen.
+
+**/
+EFI_STATUS
+EmmcPeimWaitTrbEnv (
+ IN UINTN Bar,
+ IN EMMC_TRB *Trb
+ )
+{
+ EFI_STATUS Status;
+ EMMC_COMMAND_PACKET *Packet;
+ UINT64 Timeout;
+ BOOLEAN InfiniteWait;
+
+ //
+ // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
+ //
+ Packet = Trb->Packet;
+ Timeout = Packet->Timeout;
+ if (Timeout == 0) {
+ InfiniteWait = TRUE;
+ } else {
+ InfiniteWait = FALSE;
+ }
+
+ while (InfiniteWait || (Timeout > 0)) {
+ //
+ // Check Trb execution result by reading Normal Interrupt Status register.
+ //
+ Status = EmmcPeimCheckTrbEnv (Bar, Trb);
+ if (Status != EFI_NOT_READY) {
+ return Status;
+ }
+ //
+ // Stall for 1 microsecond.
+ //
+ MicroSecondDelay (1);
+
+ Timeout--;
+ }
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Execute the specified TRB.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+ @retval EFI_SUCCESS The TRB is sent to host controller successfully.
+ @retval Others Some erros happen when sending this request to the host controller.
+
+**/
+EFI_STATUS
+EmmcPeimExecTrb (
+ IN UINTN Bar,
+ IN EMMC_TRB *Trb
+ )
+{
+ EFI_STATUS Status;
+ EMMC_COMMAND_PACKET *Packet;
+ UINT16 Cmd;
+ UINT16 IntStatus;
+ UINT32 Argument;
+ UINT16 BlkCount;
+ UINT16 BlkSize;
+ UINT16 TransMode;
+ UINT8 HostCtrl1;
+ UINT32 SdmaAddr;
+ UINT64 AdmaAddr;
+
+ Packet = Trb->Packet;
+ //
+ // Clear all bits in Error Interrupt Status Register
+ //
+ IntStatus = 0xFFFF;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Clear all bits in Normal Interrupt Status Register
+ //
+ IntStatus = 0xFFFF;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set Host Control 1 register DMA Select field
+ //
+ if (Trb->Mode == EmmcAdmaMode) {
+ HostCtrl1 = BIT4;
+ Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ EmmcPeimHcLedOnOff (Bar, TRUE);
+
+ if (Trb->Mode == EmmcSdmaMode) {
+ if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ } else if (Trb->Mode == EmmcAdmaMode) {
+ AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ BlkSize = Trb->BlockSize;
+ if (Trb->Mode == EmmcSdmaMode) {
+ //
+ // Set SDMA boundary to be 512K bytes.
+ //
+ BlkSize |= 0x7000;
+ }
+
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ BlkCount = 0;
+ if (Trb->Mode != EmmcNoData) {
+ //
+ // Calculate Block Count.
+ //
+ BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
+ }
+
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Argument = Packet->EmmcCmdBlk->CommandArgument;
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ TransMode = 0;
+ if (Trb->Mode != EmmcNoData) {
+ if (Trb->Mode != EmmcPioMode) {
+ TransMode |= BIT0;
+ }
+ if (Trb->Read) {
+ TransMode |= BIT4;
+ }
+ if (BlkCount > 1) {
+ TransMode |= BIT5 | BIT1;
+ }
+ }
+
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Cmd = (UINT16)LShiftU64(Packet->EmmcCmdBlk->CommandIndex, 8);
+ if (Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) {
+ Cmd |= BIT5;
+ }
+ //
+ // Convert ResponseType to value
+ //
+ if (Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeBc) {
+ switch (Packet->EmmcCmdBlk->ResponseType) {
+ case EmmcResponceTypeR1:
+ case EmmcResponceTypeR5:
+ case EmmcResponceTypeR6:
+ case EmmcResponceTypeR7:
+ Cmd |= (BIT1 | BIT3 | BIT4);
+ break;
+ case EmmcResponceTypeR2:
+ Cmd |= (BIT0 | BIT3);
+ break;
+ case EmmcResponceTypeR3:
+ case EmmcResponceTypeR4:
+ Cmd |= BIT1;
+ break;
+ case EmmcResponceTypeR1b:
+ case EmmcResponceTypeR5b:
+ Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
+ break;
+ default:
+ ASSERT (FALSE);
+ break;
+ }
+ }
+ //
+ // Execute cmd
+ //
+ Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
+ return Status;
+}
+
+/**
+ Check the TRB execution result.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+ @retval EFI_SUCCESS The TRB is executed successfully.
+ @retval EFI_NOT_READY The TRB is not completed for execution.
+ @retval Others Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+EmmcPeimCheckTrbResult (
+ IN UINTN Bar,
+ IN EMMC_TRB *Trb
+ )
+{
+ EFI_STATUS Status;
+ EMMC_COMMAND_PACKET *Packet;
+ UINT16 IntStatus;
+ UINT32 Response[4];
+ UINT32 SdmaAddr;
+ UINT8 Index;
+ UINT8 SwReset;
+ UINT32 PioLength;
+
+ SwReset = 0;
+ Packet = Trb->Packet;
+ //
+ // Check Trb execution result by reading Normal Interrupt Status register.
+ //
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_NOR_INT_STS,
+ TRUE,
+ sizeof (IntStatus),
+ &IntStatus
+ );
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+ //
+ // Check Transfer Complete bit is set or not.
+ //
+ if ((IntStatus & BIT1) == BIT1) {
+ if ((IntStatus & BIT15) == BIT15) {
+ //
+ // Read Error Interrupt Status register to check if the error is
+ // Data Timeout Error.
+ // If yes, treat it as success as Transfer Complete has higher
+ // priority than Data Timeout Error.
+ //
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_ERR_INT_STS,
+ TRUE,
+ sizeof (IntStatus),
+ &IntStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ if ((IntStatus & BIT4) == BIT4) {
+ Status = EFI_SUCCESS;
+ } else {
+ Status = EFI_DEVICE_ERROR;
+ }
+ }
+ }
+
+ goto Done;
+ }
+ //
+ // Check if there is a error happened during cmd execution.
+ // If yes, then do error recovery procedure to follow SD Host Controller
+ // Simplified Spec 3.0 section 3.10.1.
+ //
+ if ((IntStatus & BIT15) == BIT15) {
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_ERR_INT_STS,
+ TRUE,
+ sizeof (IntStatus),
+ &IntStatus
+ );
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+
+ if ((IntStatus & 0x0F) != 0) {
+ SwReset |= BIT1;
+ }
+ if ((IntStatus & 0xF0) != 0) {
+ SwReset |= BIT2;
+ }
+
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_SW_RST,
+ FALSE,
+ sizeof (SwReset),
+ &SwReset
+ );
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+ Status = EmmcPeimHcWaitMmioSet (
+ Bar + EMMC_HC_SW_RST,
+ sizeof (SwReset),
+ 0xFF,
+ 0,
+ EMMC_TIMEOUT
+ );
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+
+ Status = EFI_DEVICE_ERROR;
+ goto Done;
+ }
+ //
+ // Check if DMA interrupt is signalled for the SDMA transfer.
+ //
+ if ((Trb->Mode == EmmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
+ //
+ // Clear DMA interrupt bit.
+ //
+ IntStatus = BIT3;
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_NOR_INT_STS,
+ FALSE,
+ sizeof (IntStatus),
+ &IntStatus
+ );
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+ //
+ // Update SDMA Address register.
+ //
+ SdmaAddr = EMMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, EMMC_SDMA_BOUNDARY);
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_SDMA_ADDR,
+ FALSE,
+ sizeof (UINT32),
+ &SdmaAddr
+ );
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+ Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
+ }
+
+ if ((Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeAdtc) &&
+ (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR1b) &&
+ (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR5b)) {
+ if ((IntStatus & BIT0) == BIT0) {
+ Status = EFI_SUCCESS;
+ goto Done;
+ }
+ }
+
+ if (Packet->EmmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK) {
+ //
+ // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
+ // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
+ // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
+ //
+ if ((IntStatus & BIT5) == BIT5) {
+ //
+ // Clear Buffer Read Ready interrupt at first.
+ //
+ IntStatus = BIT5;
+ EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
+ //
+ // Read data out from Buffer Port register
+ //
+ for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
+ EmmcPeimHcRwMmio (Bar + EMMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
+ }
+ Status = EFI_SUCCESS;
+ goto Done;
+ }
+ }
+
+ Status = EFI_NOT_READY;
+Done:
+ //
+ // Get response data when the cmd is executed successfully.
+ //
+ if (!EFI_ERROR (Status)) {
+ if (Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeBc) {
+ for (Index = 0; Index < 4; Index++) {
+ Status = EmmcPeimHcRwMmio (
+ Bar + EMMC_HC_RESPONSE + Index * 4,
+ TRUE,
+ sizeof (UINT32),
+ &Response[Index]
+ );
+ if (EFI_ERROR (Status)) {
+ EmmcPeimHcLedOnOff (Bar, FALSE);
+ return Status;
+ }
+ }
+ CopyMem (Packet->EmmcStatusBlk, Response, sizeof (Response));
+ }
+ }
+
+ if (Status != EFI_NOT_READY) {
+ EmmcPeimHcLedOnOff (Bar, FALSE);
+ }
+
+ return Status;
+}
+
+/**
+ Wait for the TRB execution result.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+ @retval EFI_SUCCESS The TRB is executed successfully.
+ @retval Others Some erros happen when executing this request.
+
+**/
+EFI_STATUS
+EmmcPeimWaitTrbResult (
+ IN UINTN Bar,
+ IN EMMC_TRB *Trb
+ )
+{
+ EFI_STATUS Status;
+ EMMC_COMMAND_PACKET *Packet;
+ UINT64 Timeout;
+ BOOLEAN InfiniteWait;
+
+ Packet = Trb->Packet;
+ //
+ // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
+ //
+ Timeout = Packet->Timeout;
+ if (Timeout == 0) {
+ InfiniteWait = TRUE;
+ } else {
+ InfiniteWait = FALSE;
+ }
+
+ while (InfiniteWait || (Timeout > 0)) {
+ //
+ // Check Trb execution result by reading Normal Interrupt Status register.
+ //
+ Status = EmmcPeimCheckTrbResult (Bar, Trb);
+ if (Status != EFI_NOT_READY) {
+ return Status;
+ }
+ //
+ // Stall for 1 microsecond.
+ //
+ MicroSecondDelay (1);
+
+ Timeout--;
+ }
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Sends EMMC command to an EMMC card that is attached to the EMMC controller.
+
+ If Packet is successfully sent to the EMMC card, then EFI_SUCCESS is returned.
+
+ If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
+
+ If Slot is not in a valid range for the EMMC controller, then EFI_INVALID_PARAMETER
+ is returned.
+
+ If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
+ EFI_INVALID_PARAMETER is returned.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in,out] Packet A pointer to the EMMC command data structure.
+
+ @retval EFI_SUCCESS The EMMC Command Packet was sent by the host.
+ @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD
+ command Packet.
+ @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
+ @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
+ OutDataBuffer are NULL.
+ @retval EFI_NO_MEDIA SD Device not present in the Slot.
+ @retval EFI_UNSUPPORTED The command described by the EMMC Command Packet is not
+ supported by the host controller.
+ @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the
+ limit supported by EMMC card ( i.e. if the number of bytes
+ exceed the Last LBA).
+
+**/
+EFI_STATUS
+EFIAPI
+EmmcPeimExecCmd (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN OUT EMMC_COMMAND_PACKET *Packet
+ )
+{
+ EFI_STATUS Status;
+ EMMC_TRB *Trb;
+
+ if (Packet == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Packet->EmmcCmdBlk == NULL) || (Packet->EmmcStatusBlk == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Trb = EmmcPeimCreateTrb (Slot, Packet);
+ if (Trb == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = EmmcPeimWaitTrbEnv (Slot->EmmcHcBase, Trb);
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+
+ Status = EmmcPeimExecTrb (Slot->EmmcHcBase, Trb);
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+
+ Status = EmmcPeimWaitTrbResult (Slot->EmmcHcBase, Trb);
+ if (EFI_ERROR (Status)) {
+ goto Done;
+ }
+
+Done:
+ EmmcPeimFreeTrb (Trb);
+
+ return Status;
+}
+
+/**
+ Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to
+ make it go to Idle State.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+
+ @retval EFI_SUCCESS The EMMC device is reset correctly.
+ @retval Others The device reset fails.
+
+**/
+EFI_STATUS
+EmmcPeimReset (
+ IN EMMC_PEIM_HC_SLOT *Slot
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeBc;
+ EmmcCmdBlk.ResponseType = 0;
+ EmmcCmdBlk.CommandArgument = 0;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command SEND_OP_COND to the EMMC device to get the data of the OCR register.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in, out] Argument On input, the argument of SEND_OP_COND is to send to the device.
+ On output, the argument is the value of OCR register.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimGetOcr (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN OUT UINT32 *Argument
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR3;
+ EmmcCmdBlk.CommandArgument = *Argument;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+ if (!EFI_ERROR (Status)) {
+ //
+ // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+ //
+ *Argument = EmmcStatusBlk.Resp0;
+ }
+
+ return Status;
+}
+
+/**
+ Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send the
+ data of their CID registers.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimGetAllCid (
+ IN EMMC_PEIM_HC_SLOT *Slot
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;
+ EmmcCmdBlk.CommandArgument = 0;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device
+ Address (RCA).
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSetRca (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ EmmcCmdBlk.CommandArgument = Rca << 16;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command SEND_CSD to the EMMC device to get the data of the CSD register.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address of selected device.
+ @param[out] Csd The buffer to store the content of the CSD register.
+ Note the caller should ignore the lowest byte of this
+ buffer as the content of this byte is meaningless even
+ if the operation succeeds.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimGetCsd (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ OUT EMMC_CSD *Csd
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_CSD;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;
+ EmmcCmdBlk.CommandArgument = Rca << 16;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+ if (!EFI_ERROR (Status)) {
+ //
+ // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+ //
+ CopyMem (((UINT8*)Csd) + 1, &EmmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);
+ }
+
+ return Status;
+}
+
+/**
+ Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address of selected device.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSelect (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ EmmcCmdBlk.CommandArgument = Rca << 16;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD register.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[out] ExtCsd The buffer to store the content of the EXT_CSD register.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimGetExtCsd (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ OUT EMMC_EXT_CSD *ExtCsd
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ EmmcCmdBlk.CommandArgument = 0x00000000;
+
+ Packet.InDataBuffer = ExtCsd;
+ Packet.InTransferLength = sizeof (EMMC_EXT_CSD);
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+ return Status;
+}
+
+/**
+ Send command SWITCH to the EMMC device to switch the mode of operation of the
+ selected Device or modifies the EXT_CSD registers.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Access The access mode of SWITCH command.
+ @param[in] Index The offset of the field to be access.
+ @param[in] Value The value to be set to the specified field of EXT_CSD register.
+ @param[in] CmdSet The value of CmdSet field of EXT_CSD register.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitch (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT8 Access,
+ IN UINT8 Index,
+ IN UINT8 Value,
+ IN UINT8 CmdSet
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SWITCH;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1b;
+ EmmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command SEND_STATUS to the addressed EMMC device to get its status register.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address of addressed device.
+ @param[out] DevStatus The returned device status.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSendStatus (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ OUT UINT32 *DevStatus
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ EmmcCmdBlk.CommandArgument = Rca << 16;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+ if (!EFI_ERROR (Status)) {
+ *DevStatus = EmmcStatusBlk.Resp0;
+ }
+
+ return Status;
+}
+
+/**
+ Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of
+ blocks for the following block read/write cmd.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] BlockCount The number of the logical block to access.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSetBlkCount (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT16 BlockCount
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SET_BLOCK_COUNT;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ EmmcCmdBlk.CommandArgument = BlockCount;
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device
+ to read/write the specified number of blocks.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Lba The logical block address of starting access.
+ @param[in] BlockSize The block size of specified EMMC device partition.
+ @param[in] Buffer The pointer to the transfer buffer.
+ @param[in] BufferSize The size of transfer buffer.
+ @param[in] IsRead Boolean to show the operation direction.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimRwMultiBlocks (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN EFI_LBA Lba,
+ IN UINT32 BlockSize,
+ IN VOID *Buffer,
+ IN UINTN BufferSize,
+ IN BOOLEAN IsRead
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ //
+ // Calculate timeout value through the below formula.
+ // Timeout = (transfer size) / (2MB/s).
+ // Taking 2MB/s as divisor is because it's nearest to the eMMC lowest
+ // transfer speed (2.4MB/s).
+ // Refer to eMMC 5.0 spec section 6.9.1 for details.
+ //
+ Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
+
+ if (IsRead) {
+ Packet.InDataBuffer = Buffer;
+ Packet.InTransferLength = (UINT32)BufferSize;
+
+ EmmcCmdBlk.CommandIndex = EMMC_READ_MULTIPLE_BLOCK;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ } else {
+ Packet.OutDataBuffer = Buffer;
+ Packet.OutTransferLength = (UINT32)BufferSize;
+
+ EmmcCmdBlk.CommandIndex = EMMC_WRITE_MULTIPLE_BLOCK;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ }
+
+ if (Slot->SectorAddressing) {
+ EmmcCmdBlk.CommandArgument = (UINT32)Lba;
+ } else {
+ EmmcCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
+ }
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling point
+ detection.
+
+ It may be sent up to 40 times until the host finishes the tuning procedure.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] BusWidth The bus width to work.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSendTuningBlk (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT8 BusWidth
+ )
+{
+ EMMC_COMMAND_BLOCK EmmcCmdBlk;
+ EMMC_STATUS_BLOCK EmmcStatusBlk;
+ EMMC_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+ UINT8 TuningBlock[128];
+
+ ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));
+ ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.EmmcCmdBlk = &EmmcCmdBlk;
+ Packet.EmmcStatusBlk = &EmmcStatusBlk;
+ Packet.Timeout = EMMC_TIMEOUT;
+
+ EmmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;
+ EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;
+ EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;
+ EmmcCmdBlk.CommandArgument = 0;
+
+ Packet.InDataBuffer = TuningBlock;
+ if (BusWidth == 8) {
+ Packet.InTransferLength = sizeof (TuningBlock);
+ } else {
+ Packet.InTransferLength = 64;
+ }
+
+ Status = EmmcPeimExecCmd (Slot, &Packet);
+
+ return Status;
+}
+
+/**
+ Tuning the clock to get HS200 optimal sampling point.
+
+ Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
+ tuning procedure.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+ Simplified Spec 3.0 section Figure 2-29 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] BusWidth The bus width to work.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimTuningClkForHs200 (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT8 BusWidth
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HostCtrl2;
+ UINT8 Retry;
+
+ //
+ // Notify the host that the sampling clock tuning procedure starts.
+ //
+ HostCtrl2 = BIT6;
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
+ //
+ Retry = 0;
+ do {
+ Status = EmmcPeimSendTuningBlk (Slot, BusWidth);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EmmcPeimHcRwMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
+ break;
+ }
+
+ if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
+ return EFI_SUCCESS;
+ }
+ } while (++Retry < 40);
+
+ DEBUG ((EFI_D_ERROR, "EmmcPeimTuningClkForHs200: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));
+ //
+ // Abort the tuning procedure and reset the tuning circuit.
+ //
+ HostCtrl2 = (UINT8)~(BIT6 | BIT7);
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ Switch the bus width to specified width.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9 and SD Host Controller
+ Simplified Spec 3.0 section Figure 3-7 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+ @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise
+ use single data rate data simpling method.
+ @param[in] BusWidth The bus width to be set, it could be 4 or 8.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitchBusWidth (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ IN BOOLEAN IsDdr,
+ IN UINT8 BusWidth
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Access;
+ UINT8 Index;
+ UINT8 Value;
+ UINT8 CmdSet;
+ UINT32 DevStatus;
+
+ //
+ // Write Byte, the Value field is written into the byte pointed by Index.
+ //
+ Access = 0x03;
+ Index = OFFSET_OF (EMMC_EXT_CSD, BusWidth);
+ if (BusWidth == 4) {
+ Value = 1;
+ } else if (BusWidth == 8) {
+ Value = 2;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (IsDdr) {
+ Value += 4;
+ }
+
+ CmdSet = 0;
+ Status = EmmcPeimSwitch (Slot, Access, Index, Value, CmdSet);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EmmcPeimSendStatus (Slot, Rca, &DevStatus);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Check the switch operation is really successful or not.
+ //
+ if ((DevStatus & BIT7) != 0) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EmmcPeimHcSetBusWidth (Slot->EmmcHcBase, BusWidth);
+
+ return Status;
+}
+
+/**
+ Switch the clock frequency to the specified value.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller
+ Simplified Spec 3.0 section Figure 3-3 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+ @param[in] HsTiming The value to be written to HS_TIMING field of EXT_CSD register.
+ @param[in] ClockFreq The max clock frequency to be set, the unit is MHz.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitchClockFreq (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ IN UINT8 HsTiming,
+ IN UINT32 ClockFreq
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Access;
+ UINT8 Index;
+ UINT8 Value;
+ UINT8 CmdSet;
+ UINT32 DevStatus;
+
+ //
+ // Write Byte, the Value field is written into the byte pointed by Index.
+ //
+ Access = 0x03;
+ Index = OFFSET_OF (EMMC_EXT_CSD, HsTiming);
+ Value = HsTiming;
+ CmdSet = 0;
+
+ Status = EmmcPeimSwitch (Slot, Access, Index, Value, CmdSet);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EmmcPeimSendStatus (Slot, Rca, &DevStatus);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Check the switch operation is really successful or not.
+ //
+ if ((DevStatus & BIT7) != 0) {
+ return EFI_DEVICE_ERROR;
+ }
+ //
+ // Convert the clock freq unit from MHz to KHz.
+ //
+ Status = EmmcPeimHcClockSupply (Slot->EmmcHcBase, ClockFreq * 1000);
+
+ return Status;
+}
+
+/**
+ Switch to the High Speed timing according to request.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+ Simplified Spec 3.0 section Figure 2-29 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+ @param[in] ClockFreq The max clock frequency to be set.
+ @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise
+ use single data rate data simpling method.
+ @param[in] BusWidth The bus width to be set, it could be 4 or 8.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitchToHighSpeed (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ IN UINT32 ClockFreq,
+ IN BOOLEAN IsDdr,
+ IN UINT8 BusWidth
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HsTiming;
+ UINT8 HostCtrl1;
+ UINT8 HostCtrl2;
+
+ Status = EmmcPeimSwitchBusWidth (Slot, Rca, IsDdr, BusWidth);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set to High Speed timing
+ //
+ HostCtrl1 = BIT2;
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ HostCtrl2 = (UINT8)~0x7;
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if (IsDdr) {
+ HostCtrl2 = BIT2;
+ } else if (ClockFreq == 52) {
+ HostCtrl2 = BIT0;
+ } else {
+ HostCtrl2 = 0;
+ }
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ HsTiming = 1;
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);
+
+ return Status;
+}
+
+/**
+ Switch to the HS200 timing according to request.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+ Simplified Spec 3.0 section Figure 2-29 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+ @param[in] ClockFreq The max clock frequency to be set.
+ @param[in] BusWidth The bus width to be set, it could be 4 or 8.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitchToHS200 (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ IN UINT32 ClockFreq,
+ IN UINT8 BusWidth
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HsTiming;
+ UINT8 HostCtrl2;
+ UINT16 ClockCtrl;
+
+ if ((BusWidth != 4) && (BusWidth != 8)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EmmcPeimSwitchBusWidth (Slot, Rca, FALSE, BusWidth);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set to HS200/SDR104 timing
+ //
+ //
+ // Stop bus clock at first
+ //
+ Status = EmmcPeimHcStopClock (Slot->EmmcHcBase);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ HostCtrl2 = (UINT8)~0x7;
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ HostCtrl2 = BIT0 | BIT1;
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
+ //
+ Status = EmmcPeimHcWaitMmioSet (
+ Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL,
+ sizeof (ClockCtrl),
+ BIT1,
+ BIT1,
+ EMMC_TIMEOUT
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set SD Clock Enable in the Clock Control register to 1
+ //
+ ClockCtrl = BIT2;
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
+
+ HsTiming = 2;
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = EmmcPeimTuningClkForHs200 (Slot, BusWidth);
+
+ return Status;
+}
+
+/**
+ Switch to the HS400 timing according to request.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+ Simplified Spec 3.0 section Figure 2-29 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+ @param[in] ClockFreq The max clock frequency to be set.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitchToHS400 (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca,
+ IN UINT32 ClockFreq
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HsTiming;
+ UINT8 HostCtrl2;
+
+ Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, 8);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set to High Speed timing and set the clock frequency to a value less than 52MHz.
+ //
+ HsTiming = 1;
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, 52);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // HS400 mode must use 8 data lines.
+ //
+ Status = EmmcPeimSwitchBusWidth (Slot, Rca, TRUE, 8);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Set to HS400 timing
+ //
+ HostCtrl2 = (UINT8)~0x7;
+ Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ HostCtrl2 = BIT0 | BIT2;
+ Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ HsTiming = 3;
+ Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);
+
+ return Status;
+}
+
+/**
+ Switch the high speed timing according to request.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller
+ Simplified Spec 3.0 section Figure 2-29 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Rca The relative device address to be assigned.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSetBusMode (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT32 Rca
+ )
+{
+ EFI_STATUS Status;
+ EMMC_HC_SLOT_CAP Capability;
+ UINT8 HsTiming;
+ BOOLEAN IsDdr;
+ UINT32 ClockFreq;
+ UINT8 BusWidth;
+
+ Status = EmmcPeimGetCsd (Slot, Rca, &Slot->Csd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetCsd fails with %r\n", Status));
+ return Status;
+ }
+
+ if ((Slot->Csd.CSizeLow | Slot->Csd.CSizeHigh << 2) == 0xFFF) {
+ Slot->SectorAddressing = TRUE;
+ } else {
+ Slot->SectorAddressing = FALSE;
+ }
+
+ Status = EmmcPeimSelect (Slot, Rca);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimSelect fails with %r\n", Status));
+ return Status;
+ }
+
+ Status = EmmcPeimHcGetCapability (Slot->EmmcHcBase, &Capability);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimHcGetCapability fails with %r\n", Status));
+ return Status;
+ }
+
+ ASSERT (Capability.BaseClkFreq != 0);
+ //
+ // Check if the Host Controller support 8bits bus width.
+ //
+ if (Capability.BusWidth8 != 0) {
+ BusWidth = 8;
+ } else {
+ BusWidth = 4;
+ }
+ //
+ // Get Device_Type from EXT_CSD register.
+ //
+ Status = EmmcPeimGetExtCsd (Slot, &Slot->ExtCsd);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetExtCsd fails with %r\n", Status));
+ return Status;
+ }
+ //
+ // Calculate supported bus speed/bus width/clock frequency.
+ //
+ HsTiming = 0;
+ IsDdr = FALSE;
+ ClockFreq = 0;
+ if (((Slot->ExtCsd.DeviceType & (BIT4 | BIT5)) != 0) && (Capability.Sdr104 != 0)) {
+ HsTiming = 2;
+ IsDdr = FALSE;
+ ClockFreq = 200;
+ } else if (((Slot->ExtCsd.DeviceType & (BIT2 | BIT3)) != 0) && (Capability.Ddr50 != 0)) {
+ HsTiming = 1;
+ IsDdr = TRUE;
+ ClockFreq = 52;
+ } else if (((Slot->ExtCsd.DeviceType & BIT1) != 0) && (Capability.HighSpeed != 0)) {
+ HsTiming = 1;
+ IsDdr = FALSE;
+ ClockFreq = 52;
+ } else if (((Slot->ExtCsd.DeviceType & BIT0) != 0) && (Capability.HighSpeed != 0)) {
+ HsTiming = 1;
+ IsDdr = FALSE;
+ ClockFreq = 26;
+ }
+ //
+ // Check if both of the device and the host controller support HS400 DDR mode.
+ //
+ if (((Slot->ExtCsd.DeviceType & (BIT6 | BIT7)) != 0) && (Capability.Hs400 != 0)) {
+ //
+ // The host controller supports 8bits bus.
+ //
+ ASSERT (BusWidth == 8);
+ HsTiming = 3;
+ IsDdr = TRUE;
+ ClockFreq = 200;
+ }
+
+ if ((ClockFreq == 0) || (HsTiming == 0)) {
+ //
+ // Continue using default setting.
+ //
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((EFI_D_INFO, "HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));
+
+ if (HsTiming == 3) {
+ //
+ // Execute HS400 timing switch procedure
+ //
+ Status = EmmcPeimSwitchToHS400 (Slot, Rca, ClockFreq);
+ } else if (HsTiming == 2) {
+ //
+ // Execute HS200 timing switch procedure
+ //
+ Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, BusWidth);
+ } else {
+ //
+ // Execute High Speed timing switch procedure
+ //
+ Status = EmmcPeimSwitchToHighSpeed (Slot, Rca, ClockFreq, IsDdr, BusWidth);
+ }
+
+ return Status;
+}
+
+/**
+ Execute EMMC device identification procedure.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+
+ @retval EFI_SUCCESS There is a EMMC card.
+ @retval Others There is not a EMMC card.
+
+**/
+EFI_STATUS
+EmmcPeimIdentification (
+ IN EMMC_PEIM_HC_SLOT *Slot
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Ocr;
+ UINT32 Rca;
+ UINTN Retry;
+
+ Status = EmmcPeimReset (Slot);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimReset fails with %r\n", Status));
+ return Status;
+ }
+
+ Ocr = 0;
+ Retry = 0;
+ do {
+ Status = EmmcPeimGetOcr (Slot, &Ocr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetOcr fails with %r\n", Status));
+ return Status;
+ }
+
+ if (Retry++ == 100) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetOcr fails too many times\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ MicroSecondDelay (10 * 1000);
+ } while ((Ocr & BIT31) == 0);
+
+ Status = EmmcPeimGetAllCid (Slot);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetAllCid fails with %r\n", Status));
+ return Status;
+ }
+ //
+ // Don't support multiple devices on the slot, that is
+ // shared bus slot feature.
+ //
+ Rca = 1;
+ Status = EmmcPeimSetRca (Slot, Rca);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimSetRca fails with %r\n", Status));
+ return Status;
+ }
+ //
+ // Enter Data Tranfer Mode.
+ //
+ DEBUG ((EFI_D_INFO, "Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));
+
+ Status = EmmcPeimSetBusMode (Slot, Rca);
+
+ return Status;
+}
+
diff --git a/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHci.h b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHci.h new file mode 100644 index 000000000..4e3e51d14 --- /dev/null +++ b/roms/edk2/MdeModulePkg/Bus/Sd/EmmcBlockIoPei/EmmcHci.h @@ -0,0 +1,339 @@ +/** @file
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _EMMC_HCI_H_
+#define _EMMC_HCI_H_
+
+//
+// EMMC Host Controller MMIO Register Offset
+//
+#define EMMC_HC_SDMA_ADDR 0x00
+#define EMMC_HC_ARG2 0x00
+#define EMMC_HC_BLK_SIZE 0x04
+#define EMMC_HC_BLK_COUNT 0x06
+#define EMMC_HC_ARG1 0x08
+#define EMMC_HC_TRANS_MOD 0x0C
+#define EMMC_HC_COMMAND 0x0E
+#define EMMC_HC_RESPONSE 0x10
+#define EMMC_HC_BUF_DAT_PORT 0x20
+#define EMMC_HC_PRESENT_STATE 0x24
+#define EMMC_HC_HOST_CTRL1 0x28
+#define EMMC_HC_POWER_CTRL 0x29
+#define EMMC_HC_BLK_GAP_CTRL 0x2A
+#define EMMC_HC_WAKEUP_CTRL 0x2B
+#define EMMC_HC_CLOCK_CTRL 0x2C
+#define EMMC_HC_TIMEOUT_CTRL 0x2E
+#define EMMC_HC_SW_RST 0x2F
+#define EMMC_HC_NOR_INT_STS 0x30
+#define EMMC_HC_ERR_INT_STS 0x32
+#define EMMC_HC_NOR_INT_STS_EN 0x34
+#define EMMC_HC_ERR_INT_STS_EN 0x36
+#define EMMC_HC_NOR_INT_SIG_EN 0x38
+#define EMMC_HC_ERR_INT_SIG_EN 0x3A
+#define EMMC_HC_AUTO_CMD_ERR_STS 0x3C
+#define EMMC_HC_HOST_CTRL2 0x3E
+#define EMMC_HC_CAP 0x40
+#define EMMC_HC_MAX_CURRENT_CAP 0x48
+#define EMMC_HC_FORCE_EVT_AUTO_CMD 0x50
+#define EMMC_HC_FORCE_EVT_ERR_INT 0x52
+#define EMMC_HC_ADMA_ERR_STS 0x54
+#define EMMC_HC_ADMA_SYS_ADDR 0x58
+#define EMMC_HC_PRESET_VAL 0x60
+#define EMMC_HC_SHARED_BUS_CTRL 0xE0
+#define EMMC_HC_SLOT_INT_STS 0xFC
+#define EMMC_HC_CTRL_VER 0xFE
+
+//
+// The transfer modes supported by SD Host Controller
+// Simplified Spec 3.0 Table 1-2
+//
+typedef enum {
+ EmmcNoData,
+ EmmcPioMode,
+ EmmcSdmaMode,
+ EmmcAdmaMode
+} EMMC_HC_TRANSFER_MODE;
+
+//
+// The maximum data length of each descriptor line
+//
+#define ADMA_MAX_DATA_PER_LINE 0x10000
+#define EMMC_SDMA_BOUNDARY 512 * 1024
+#define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))
+
+typedef enum {
+ EmmcCommandTypeBc, // Broadcast commands, no response
+ EmmcCommandTypeBcr, // Broadcast commands with response
+ EmmcCommandTypeAc, // Addressed(point-to-point) commands
+ EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands
+} EMMC_COMMAND_TYPE;
+
+typedef enum {
+ EmmcResponceTypeR1,
+ EmmcResponceTypeR1b,
+ EmmcResponceTypeR2,
+ EmmcResponceTypeR3,
+ EmmcResponceTypeR4,
+ EmmcResponceTypeR5,
+ EmmcResponceTypeR5b,
+ EmmcResponceTypeR6,
+ EmmcResponceTypeR7
+} EMMC_RESPONSE_TYPE;
+
+typedef struct _EMMC_COMMAND_BLOCK {
+ UINT16 CommandIndex;
+ UINT32 CommandArgument;
+ UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values
+ UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values
+} EMMC_COMMAND_BLOCK;
+
+typedef struct _EMMC_STATUS_BLOCK {
+ UINT32 Resp0;
+ UINT32 Resp1;
+ UINT32 Resp2;
+ UINT32 Resp3;
+} EMMC_STATUS_BLOCK;
+
+typedef struct _EMMC_COMMAND_PACKET {
+ UINT64 Timeout;
+ EMMC_COMMAND_BLOCK *EmmcCmdBlk;
+ EMMC_STATUS_BLOCK *EmmcStatusBlk;
+ VOID *InDataBuffer;
+ VOID *OutDataBuffer;
+ UINT32 InTransferLength;
+ UINT32 OutTransferLength;
+} EMMC_COMMAND_PACKET;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Valid:1;
+ UINT32 End:1;
+ UINT32 Int:1;
+ UINT32 Reserved:1;
+ UINT32 Act:2;
+ UINT32 Reserved1:10;
+ UINT32 Length:16;
+ UINT32 Address;
+} EMMC_HC_ADMA_DESC_LINE;
+
+typedef struct {
+ UINT32 TimeoutFreq:6; // bit 0:5
+ UINT32 Reserved:1; // bit 6
+ UINT32 TimeoutUnit:1; // bit 7
+ UINT32 BaseClkFreq:8; // bit 8:15
+ UINT32 MaxBlkLen:2; // bit 16:17
+ UINT32 BusWidth8:1; // bit 18
+ UINT32 Adma2:1; // bit 19
+ UINT32 Reserved2:1; // bit 20
+ UINT32 HighSpeed:1; // bit 21
+ UINT32 Sdma:1; // bit 22
+ UINT32 SuspRes:1; // bit 23
+ UINT32 Voltage33:1; // bit 24
+ UINT32 Voltage30:1; // bit 25
+ UINT32 Voltage18:1; // bit 26
+ UINT32 Reserved3:1; // bit 27
+ UINT32 SysBus64:1; // bit 28
+ UINT32 AsyncInt:1; // bit 29
+ UINT32 SlotType:2; // bit 30:31
+ UINT32 Sdr50:1; // bit 32
+ UINT32 Sdr104:1; // bit 33
+ UINT32 Ddr50:1; // bit 34
+ UINT32 Reserved4:1; // bit 35
+ UINT32 DriverTypeA:1; // bit 36
+ UINT32 DriverTypeC:1; // bit 37
+ UINT32 DriverTypeD:1; // bit 38
+ UINT32 DriverType4:1; // bit 39
+ UINT32 TimerCount:4; // bit 40:43
+ UINT32 Reserved5:1; // bit 44
+ UINT32 TuningSDR50:1; // bit 45
+ UINT32 RetuningMod:2; // bit 46:47
+ UINT32 ClkMultiplier:8; // bit 48:55
+ UINT32 Reserved6:7; // bit 56:62
+ UINT32 Hs400:1; // bit 63
+} EMMC_HC_SLOT_CAP;
+
+#pragma pack()
+
+/**
+ Software reset the specified EMMC host controller and enable all interrupts.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The software reset executes successfully.
+ @retval Others The software reset fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcReset (
+ IN UINTN Bar
+ );
+
+/**
+ Set all interrupt status bits in Normal and Error Interrupt Status Enable
+ register.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The operation executes successfully.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcEnableInterrupt (
+ IN UINTN Bar
+ );
+
+/**
+ Get the capability data from the specified slot.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+ @param[out] Capability The buffer to store the capability data.
+
+ @retval EFI_SUCCESS The operation executes successfully.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcGetCapability (
+ IN UINTN Bar,
+ OUT EMMC_HC_SLOT_CAP *Capability
+ );
+
+/**
+ Detect whether there is a EMMC card attached at the specified EMMC host controller
+ slot.
+
+ Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS There is a EMMC card attached.
+ @retval EFI_NO_MEDIA There is not a EMMC card attached.
+ @retval Others The detection fails.
+
+**/
+EFI_STATUS
+EmmcPeimHcCardDetect (
+ IN UINTN Bar
+ );
+
+/**
+ Initial EMMC host controller with lowest clock frequency, max power and max timeout value
+ at initialization.
+
+ @param[in] Bar The mmio base address of the slot to be accessed.
+
+ @retval EFI_SUCCESS The host controller is initialized successfully.
+ @retval Others The host controller isn't initialized successfully.
+
+**/
+EFI_STATUS
+EmmcPeimHcInitHost (
+ IN UINTN Bar
+ );
+
+/**
+ Send command SWITCH to the EMMC device to switch the mode of operation of the
+ selected Device or modifies the EXT_CSD registers.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Access The access mode of SWITCH command.
+ @param[in] Index The offset of the field to be access.
+ @param[in] Value The value to be set to the specified field of EXT_CSD register.
+ @param[in] CmdSet The value of CmdSet field of EXT_CSD register.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSwitch (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT8 Access,
+ IN UINT8 Index,
+ IN UINT8 Value,
+ IN UINT8 CmdSet
+ );
+
+/**
+ Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of
+ blocks for the following block read/write cmd.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] BlockCount The number of the logical block to access.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimSetBlkCount (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN UINT16 BlockCount
+ );
+
+/**
+ Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device
+ to read/write the specified number of blocks.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+ @param[in] Lba The logical block address of starting access.
+ @param[in] BlockSize The block size of specified EMMC device partition.
+ @param[in] Buffer The pointer to the transfer buffer.
+ @param[in] BufferSize The size of transfer buffer.
+ @param[in] IsRead Boolean to show the operation direction.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+EmmcPeimRwMultiBlocks (
+ IN EMMC_PEIM_HC_SLOT *Slot,
+ IN EFI_LBA Lba,
+ IN UINT32 BlockSize,
+ IN VOID *Buffer,
+ IN UINTN BufferSize,
+ IN BOOLEAN IsRead
+ );
+
+/**
+ Execute EMMC device identification procedure.
+
+ Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.
+
+ @param[in] Slot The slot number of the Emmc card to send the command to.
+
+ @retval EFI_SUCCESS There is a EMMC card.
+ @retval Others There is not a EMMC card.
+
+**/
+EFI_STATUS
+EmmcPeimIdentification (
+ IN EMMC_PEIM_HC_SLOT *Slot
+ );
+
+/**
+ Free the resource used by the TRB.
+
+ @param[in] Trb The pointer to the EMMC_TRB instance.
+
+**/
+VOID
+EmmcPeimFreeTrb (
+ IN EMMC_TRB *Trb
+ );
+
+#endif
+
|