4 files changed, 132 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
new file mode 100644
index 000000000..82a723226
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.S
@@ -0,0 +1,32 @@
+#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+#  VOID
+#  )#
+#
+ASM_PFX(CpuFlushTlb):
+  tlbi  vmalle1                 // Invalidate Inst TLB and Data TLB
+  dsb   sy
+  isb
+  ret
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm
new file mode 100644
index 000000000..a72c9aef1
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm
@@ -0,0 +1,33 @@
+;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT CpuFlushTlb
+  AREA BaseCpuLib_LowLevel, CODE, READONLY
+
+;/**
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+;  VOID
+;  );
+;
+CpuFlushTlb
+  tlbi  vmalle1                 // Invalidate Inst TLB and Data TLB
+  dsb   sy
+  isb
+  ret
+
+  END
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
new file mode 100644
index 000000000..410a27156
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.S
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# CpuSleep() for AArch64
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+#  Places the CPU in a sleep state until an interrupt is received.
+#
+#  Places the CPU in a sleep state until an interrupt is received. If interrupts
+#  are disabled prior to calling this function, then the CPU will be placed in a
+#  sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+#  VOID
+#  );
+#
+
+ASM_PFX(CpuSleep):
+    wfi
+    ret
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm
new file mode 100644
index 000000000..c6e4d7e65
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; CpuSleep() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT CpuSleep
+  AREA BaseCpuLib_LowLevel, CODE, READONLY
+
+;/**
+;  Places the CPU in a sleep state until an interrupt is received.
+;
+;  Places the CPU in a sleep state until an interrupt is received. If interrupts
+;  are disabled prior to calling this function, then the CPU will be placed in a
+;  sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+;  VOID
+;  );
+;
+
+CpuSleep
+  wfi
+  ret
+
+  END