4 files changed, 136 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
new file mode 100644
index 000000000..3bafce6f3
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S
@@ -0,0 +1,30 @@
+#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+#  VOID
+#  )#
+#
+ASM_PFX(CpuFlushTlb):
+    mov r0,#0
+    mcr p15,0,r0,c8,c5,0        // Invalidate all the unlocked entried in TLB
+    bx  LR
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
new file mode 100644
index 000000000..1f77fc7d5
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm
@@ -0,0 +1,31 @@
+;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT CpuFlushTlb
+  AREA cpu_flush_tlb, CODE, READONLY
+
+;/**
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;  Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+;  VOID
+;  );
+;
+CpuFlushTlb
+    MOV r0,#0
+    MCR p15,0,r0,c8,c5,0        ;Invalidate all the unlocked entried in TLB
+    BX LR
+
+  END
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
new file mode 100644
index 000000000..e2b734900
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#
+# CpuSleep() for ARMv7
+#
+# ARMv6 versions was:
+#    MOV r0,#0
+#    MCR p15,0,r0,c7,c0,4   ;Wait for Interrupt instruction
+#
+# But this is a no-op on ARMv7
+#
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+#  Places the CPU in a sleep state until an interrupt is received.
+#
+#  Places the CPU in a sleep state until an interrupt is received. If interrupts
+#  are disabled prior to calling this function, then the CPU will be placed in a
+#  sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+#  VOID
+#  );
+#
+ASM_PFX(CpuSleep):
+    wfi
+    bx  lr
diff --git a/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
new file mode 100644
index 000000000..ae32705a6
--- /dev/null
+++ b/roms/edk2/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm
@@ -0,0 +1,38 @@
+;------------------------------------------------------------------------------
+;
+; CpuSleep() for ARMv7
+;
+; ARMv6 versions was:
+;    MOV r0,#0
+;    MCR p15,0,r0,c7,c0,4   ;Wait for Interrupt instruction
+;
+; But this is a no-op on ARMv7
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2011, Apple Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT CpuSleep
+  AREA cpu_sleep, CODE, READONLY
+
+;/**
+;  Places the CPU in a sleep state until an interrupt is received.
+;
+;  Places the CPU in a sleep state until an interrupt is received. If interrupts
+;  are disabled prior to calling this function, then the CPU will be placed in a
+;  sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+;  VOID
+;  );
+;
+CpuSleep
+    WFI
+    BX LR
+
+  END