diff options
Diffstat (limited to 'roms/edk2/MdePkg/Library/BaseLib/X64')
90 files changed, 5379 insertions, 0 deletions
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c new file mode 100644 index 000000000..c626ef8ec --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.c @@ -0,0 +1,33 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+void __debugbreak (VOID);
+
+#pragma intrinsic(__debugbreak)
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __debugbreak ();
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.nasm new file mode 100644 index 000000000..5bdbe3290 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuBreakpoint.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuBreakpoint.Asm
+;
+; Abstract:
+;
+; CpuBreakpoint function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuBreakpoint (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuBreakpoint)
+ASM_PFX(CpuBreakpoint):
+ int 3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuId.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuId.nasm new file mode 100644 index 000000000..bb83017c8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuId.nasm @@ -0,0 +1,58 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuId.Asm
+;
+; Abstract:
+;
+; AsmCpuid function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmCpuid (
+; IN UINT32 RegisterInEax,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; )
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmCpuid)
+ASM_PFX(AsmCpuid):
+ push rbx
+ mov eax, ecx
+ push rax ; save Index on stack
+ push rdx
+ cpuid
+ test r9, r9
+ jz .0
+ mov [r9], ecx
+.0:
+ pop rcx
+ jrcxz .1
+ mov [rcx], eax
+.1:
+ mov rcx, r8
+ jrcxz .2
+ mov [rcx], ebx
+.2:
+ mov rcx, [rsp + 0x38]
+ jrcxz .3
+ mov [rcx], edx
+.3:
+ pop rax ; restore Index to rax as return value
+ pop rbx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuIdEx.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuIdEx.nasm new file mode 100644 index 000000000..fd5caa328 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuIdEx.nasm @@ -0,0 +1,60 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuIdEx.Asm
+;
+; Abstract:
+;
+; AsmCpuidEx function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; AsmCpuidEx (
+; IN UINT32 RegisterInEax,
+; IN UINT32 RegisterInEcx,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; )
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmCpuidEx)
+ASM_PFX(AsmCpuidEx):
+ push rbx
+ mov eax, ecx
+ mov ecx, edx
+ push rax ; save Index on stack
+ cpuid
+ mov r10, [rsp + 0x38]
+ test r10, r10
+ jz .0
+ mov [r10], ecx
+.0:
+ mov rcx, r8
+ jrcxz .1
+ mov [rcx], eax
+.1:
+ mov rcx, r9
+ jrcxz .2
+ mov [rcx], ebx
+.2:
+ mov rcx, [rsp + 0x40]
+ jrcxz .3
+ mov [rcx], edx
+.3:
+ pop rax ; restore Index to rax as return value
+ pop rbx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/CpuPause.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuPause.nasm new file mode 100644 index 000000000..ca3519741 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/CpuPause.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; CpuPause.Asm
+;
+; Abstract:
+;
+; CpuPause function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; CpuPause (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(CpuPause)
+ASM_PFX(CpuPause):
+ pause
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/DisableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableCache.nasm new file mode 100644 index 000000000..93f5f7539 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableCache.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisableCache.Asm
+;
+; Abstract:
+;
+; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a
+; WBINVD instruction.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmDisableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmDisableCache)
+ASM_PFX(AsmDisableCache):
+ mov rax, cr0
+ bts rax, 30
+ btr rax, 29
+ mov cr0, rax
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/DisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableInterrupts.nasm new file mode 100644 index 000000000..43c7e5d02 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/DisableInterrupts.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisableInterrupts.Asm
+;
+; Abstract:
+;
+; DisableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; DisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(DisableInterrupts)
+ASM_PFX(DisableInterrupts):
+ cli
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm new file mode 100644 index 000000000..c76ed1a76 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/DisablePaging64.nasm @@ -0,0 +1,78 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; DisablePaging64.Asm
+;
+; Abstract:
+;
+; AsmDisablePaging64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86DisablePaging64 (
+; IN UINT16 Cs,
+; IN UINT32 EntryPoint,
+; IN UINT32 Context1, OPTIONAL
+; IN UINT32 Context2, OPTIONAL
+; IN UINT32 NewStack
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86DisablePaging64)
+ASM_PFX(InternalX86DisablePaging64):
+ cli
+ lea rsi, [.0] ; rsi <- The start address of transition code
+ mov edi, [rsp + 0x28] ; rdi <- New stack
+ lea rax, [mTransitionEnd] ; rax <- end of transition code
+ sub rax, rsi ; rax <- The size of transition piece code
+ add rax, 4 ; Round RAX up to the next 4 byte boundary
+ and al, 0xfc
+ sub rdi, rax ; rdi <- Use stack to hold transition code
+ mov r10d, edi ; r10 <- The start address of transicition code below 4G
+ push rcx ; save rcx to stack
+ mov rcx, rax ; rcx <- The size of transition piece code
+ rep movsb ; copy transition code to top of new stack which must be below 4GB
+ pop rcx ; restore rcx
+
+ mov esi, r8d
+ mov edi, r9d
+ mov eax, r10d ; eax <- start of the transition code on the stack
+ sub eax, 4 ; eax <- One slot below transition code on the stack
+ push rcx ; push Cs to stack
+ push r10 ; push address of tansition code on stack
+ DB 0x48 ; prefix to composite "retq" with next "retf"
+ retf ; Use far return to load CS register from stack
+
+; Start of transition code
+.0:
+ mov esp, eax ; set up new stack
+ mov rax, cr0
+ btr eax, 31 ; Clear CR0.PG
+ mov cr0, rax ; disable paging and caches
+
+ mov ebx, edx ; save EntryPoint to rbx, for rdmsr will overwrite rdx
+ mov ecx, 0xc0000080
+ rdmsr
+ and ah, ~ 1 ; clear LME
+ wrmsr
+ mov rax, cr4
+ and al, ~ (1 << 5) ; clear PAE
+ mov cr4, rax
+ push rdi ; push Context2
+ push rsi ; push Context1
+ call rbx ; transfer control to EntryPoint
+ hlt ; no one should get here
+
+mTransitionEnd:
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/EnableCache.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableCache.nasm new file mode 100644 index 000000000..b6fae3cbf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableCache.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableCache.Asm
+;
+; Abstract:
+;
+; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear
+; the NW bit of CR0 to 0
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmEnableCache (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmEnableCache)
+ASM_PFX(AsmEnableCache):
+ wbinvd
+ mov rax, cr0
+ btr rax, 29
+ btr rax, 30
+ mov cr0, rax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.nasm new file mode 100644 index 000000000..3c7e9e78d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableDisableInterrupts.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableDisableInterrupts.Asm
+;
+; Abstract:
+;
+; EnableDisableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; EnableDisableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(EnableDisableInterrupts)
+ASM_PFX(EnableDisableInterrupts):
+ sti
+ cli
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/EnableInterrupts.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableInterrupts.nasm new file mode 100644 index 000000000..6057afd62 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/EnableInterrupts.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; EnableInterrupts.Asm
+;
+; Abstract:
+;
+; EnableInterrupts function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; EnableInterrupts (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(EnableInterrupts)
+ASM_PFX(EnableInterrupts):
+ sti
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/FlushCacheLine.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/FlushCacheLine.nasm new file mode 100644 index 000000000..1effabe0d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/FlushCacheLine.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FlushCacheLine.Asm
+;
+; Abstract:
+;
+; AsmFlushCacheLine function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID *
+; EFIAPI
+; AsmFlushCacheLine (
+; IN VOID *LinearAddress
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmFlushCacheLine)
+ASM_PFX(AsmFlushCacheLine):
+ clflush [rcx]
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/FxRestore.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/FxRestore.nasm new file mode 100644 index 000000000..261981edf --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/FxRestore.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FxRestore.Asm
+;
+; Abstract:
+;
+; AsmFxRestore function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86FxRestore (
+; IN CONST IA32_FX_BUFFER *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86FxRestore)
+ASM_PFX(InternalX86FxRestore):
+ fxrstor [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/FxSave.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/FxSave.nasm new file mode 100644 index 000000000..fafe24d62 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/FxSave.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; FxSave.Asm
+;
+; Abstract:
+;
+; AsmFxSave function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86FxSave (
+; OUT IA32_FX_BUFFER *Buffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86FxSave)
+ASM_PFX(InternalX86FxSave):
+ fxsave [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/GccInline.c b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInline.c new file mode 100644 index 000000000..40a208f19 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInline.c @@ -0,0 +1,562 @@ +/** @file
+ GCC inline implementation of BaseLib processor specific functions.
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+
+
+
+/**
+ Used to serialize load and store operations.
+
+ All loads and stores that proceed calls to this function are guaranteed to be
+ globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+ VOID
+ )
+{
+ // This is a little bit of overkill and it is more about the compiler that it is
+ // actually processor synchronization. This is like the _ReadWriteBarrier
+ // Microsoft specific intrinsic
+ __asm__ __volatile__ ("":::"memory");
+}
+
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("pause");
+}
+
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("int $3");
+}
+
+
+/**
+ Reads the current value of the EFLAGS register.
+
+ Reads and returns the current value of the EFLAGS register. This function is
+ only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a
+ 64-bit value on X64.
+
+ @return EFLAGS on IA-32 or RFLAGS on X64.
+
+**/
+UINTN
+EFIAPI
+AsmReadEflags (
+ VOID
+ )
+{
+ UINTN Eflags;
+
+ __asm__ __volatile__ (
+ "pushfq \n\t"
+ "pop %0 "
+ : "=r" (Eflags) // %0
+ );
+
+ return Eflags;
+}
+
+/**
+ Save the current floating point/SSE/SSE2 context to a buffer.
+
+ Saves the current floating point/SSE/SSE2 state to the buffer specified by
+ Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
+ available on IA-32 and X64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxSave (
+ OUT IA32_FX_BUFFER *Buffer
+ )
+{
+ __asm__ __volatile__ (
+ "fxsave %0"
+ :
+ : "m" (*Buffer) // %0
+ );
+}
+
+
+/**
+ Restores the current floating point/SSE/SSE2 context from a buffer.
+
+ Restores the current floating point/SSE/SSE2 state from the buffer specified
+ by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
+ only available on IA-32 and X64.
+
+ @param Buffer The pointer to a buffer to save the floating point/SSE/SSE2 context.
+
+**/
+VOID
+EFIAPI
+InternalX86FxRestore (
+ IN CONST IA32_FX_BUFFER *Buffer
+ )
+{
+ __asm__ __volatile__ (
+ "fxrstor %0"
+ :
+ : "m" (*Buffer) // %0
+ );
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #0 (MM0).
+
+ Reads and returns the current value of MM0. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM0.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm0 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm0, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #1 (MM1).
+
+ Reads and returns the current value of MM1. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM1.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm1 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm1, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #2 (MM2).
+
+ Reads and returns the current value of MM2. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM2.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm2 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm2, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #3 (MM3).
+
+ Reads and returns the current value of MM3. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM3.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm3 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm3, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #4 (MM4).
+
+ Reads and returns the current value of MM4. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM4.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm4 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm4, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #5 (MM5).
+
+ Reads and returns the current value of MM5. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM5.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm5 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm5, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #6 (MM6).
+
+ Reads and returns the current value of MM6. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM6.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm6 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm6, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of 64-bit MMX Register #7 (MM7).
+
+ Reads and returns the current value of MM7. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of MM7.
+
+**/
+UINT64
+EFIAPI
+AsmReadMm7 (
+ VOID
+ )
+{
+ UINT64 Data;
+
+ __asm__ __volatile__ (
+ "movd %%mm7, %0 \n\t"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #0 (MM0).
+
+ Writes the current value of MM0. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM0.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm0 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm0" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #1 (MM1).
+
+ Writes the current value of MM1. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM1.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm1 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm1" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #2 (MM2).
+
+ Writes the current value of MM2. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM2.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm2 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm2" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #3 (MM3).
+
+ Writes the current value of MM3. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM3.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm3 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm3" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #4 (MM4).
+
+ Writes the current value of MM4. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM4.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm4 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm4" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #5 (MM5).
+
+ Writes the current value of MM5. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM5.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm5 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm5" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #6 (MM6).
+
+ Writes the current value of MM6. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM6.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm6 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm6" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Writes the current value of 64-bit MMX Register #7 (MM7).
+
+ Writes the current value of MM7. This function is only available on IA32 and
+ X64.
+
+ @param Value The 64-bit value to write to MM7.
+
+**/
+VOID
+EFIAPI
+AsmWriteMm7 (
+ IN UINT64 Value
+ )
+{
+ __asm__ __volatile__ (
+ "movd %0, %%mm7" // %0
+ :
+ : "m" (Value)
+ );
+}
+
+
+/**
+ Reads the current value of Time Stamp Counter (TSC).
+
+ Reads and returns the current value of TSC. This function is only available
+ on IA-32 and X64.
+
+ @return The current value of TSC
+
+**/
+UINT64
+EFIAPI
+AsmReadTsc (
+ VOID
+ )
+{
+ UINT32 LowData;
+ UINT32 HiData;
+
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=a" (LowData),
+ "=d" (HiData)
+ );
+
+ return (((UINT64)HiData) << 32) | LowData;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/GccInlinePriv.c b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInlinePriv.c new file mode 100644 index 000000000..98be19b3c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/GccInlinePriv.c @@ -0,0 +1,1234 @@ +/** @file
+ GCC inline implementation of BaseLib processor specific functions that use
+ privlidged instructions.
+
+ Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+/**
+ Enables CPU interrupts.
+
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("sti"::: "memory");
+}
+
+
+/**
+ Disables CPU interrupts.
+
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("cli"::: "memory");
+}
+
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and X64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ UINT32 LowData;
+ UINT32 HighData;
+
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=a" (LowData), // %0
+ "=d" (HighData) // %1
+ : "c" (Index) // %2
+ );
+
+ return (((UINT64)HighData) << 32) | LowData;
+}
+
+/**
+ Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
+ value.
+
+ Writes the 64-bit value specified by Value to the MSR specified by Index. The
+ 64-bit value written to the MSR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and X64.
+
+ @param Index The 32-bit MSR index to write.
+ @param Value The 64-bit value to write to the MSR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ UINT32 LowData;
+ UINT32 HighData;
+
+ LowData = (UINT32)(Value);
+ HighData = (UINT32)(Value >> 32);
+
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (Index),
+ "a" (LowData),
+ "d" (HighData)
+ );
+
+ return Value;
+}
+
+/**
+ Reads the current value of the Control Register 0 (CR0).
+
+ Reads and returns the current value of CR0. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 0 (CR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr0 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr0,%0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of the Control Register 2 (CR2).
+
+ Reads and returns the current value of CR2. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 2 (CR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr2 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr2, %0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+/**
+ Reads the current value of the Control Register 3 (CR3).
+
+ Reads and returns the current value of CR3. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 3 (CR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr3 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr3, %0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of the Control Register 4 (CR4).
+
+ Reads and returns the current value of CR4. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of the Control Register 4 (CR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadCr4 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%cr4, %0"
+ : "=r" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes a value to Control Register 0 (CR0).
+
+ Writes and returns a new value to CR0. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr0 The value to write to CR0.
+
+ @return The value written to CR0.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr0 (
+ UINTN Cr0
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr0"
+ :
+ : "r" (Cr0)
+ );
+ return Cr0;
+}
+
+
+/**
+ Writes a value to Control Register 2 (CR2).
+
+ Writes and returns a new value to CR2. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr2 The value to write to CR2.
+
+ @return The value written to CR2.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr2 (
+ UINTN Cr2
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr2"
+ :
+ : "r" (Cr2)
+ );
+ return Cr2;
+}
+
+
+/**
+ Writes a value to Control Register 3 (CR3).
+
+ Writes and returns a new value to CR3. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr3 The value to write to CR3.
+
+ @return The value written to CR3.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr3 (
+ UINTN Cr3
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr3"
+ :
+ : "r" (Cr3)
+ );
+ return Cr3;
+}
+
+
+/**
+ Writes a value to Control Register 4 (CR4).
+
+ Writes and returns a new value to CR4. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Cr4 The value to write to CR4.
+
+ @return The value written to CR4.
+
+**/
+UINTN
+EFIAPI
+AsmWriteCr4 (
+ UINTN Cr4
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr4"
+ :
+ : "r" (Cr4)
+ );
+ return Cr4;
+}
+
+
+/**
+ Reads the current value of Debug Register 0 (DR0).
+
+ Reads and returns the current value of DR0. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr0 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr0, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 1 (DR1).
+
+ Reads and returns the current value of DR1. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr1 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr1, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 2 (DR2).
+
+ Reads and returns the current value of DR2. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr2 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr2, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 3 (DR3).
+
+ Reads and returns the current value of DR3. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr3 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr3, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 4 (DR4).
+
+ Reads and returns the current value of DR4. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr4 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr4, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 5 (DR5).
+
+ Reads and returns the current value of DR5. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr5 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr5, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 6 (DR6).
+
+ Reads and returns the current value of DR6. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr6 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr6, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Debug Register 7 (DR7).
+
+ Reads and returns the current value of DR7. This function is only available
+ on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on
+ X64.
+
+ @return The value of Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmReadDr7 (
+ VOID
+ )
+{
+ UINTN Data;
+
+ __asm__ __volatile__ (
+ "mov %%dr7, %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes a value to Debug Register 0 (DR0).
+
+ Writes and returns a new value to DR0. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr0 The value to write to Dr0.
+
+ @return The value written to Debug Register 0 (DR0).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr0 (
+ UINTN Dr0
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr0"
+ :
+ : "r" (Dr0)
+ );
+ return Dr0;
+}
+
+
+/**
+ Writes a value to Debug Register 1 (DR1).
+
+ Writes and returns a new value to DR1. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr1 The value to write to Dr1.
+
+ @return The value written to Debug Register 1 (DR1).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr1 (
+ UINTN Dr1
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr1"
+ :
+ : "r" (Dr1)
+ );
+ return Dr1;
+}
+
+
+/**
+ Writes a value to Debug Register 2 (DR2).
+
+ Writes and returns a new value to DR2. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr2 The value to write to Dr2.
+
+ @return The value written to Debug Register 2 (DR2).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr2 (
+ UINTN Dr2
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr2"
+ :
+ : "r" (Dr2)
+ );
+ return Dr2;
+}
+
+
+/**
+ Writes a value to Debug Register 3 (DR3).
+
+ Writes and returns a new value to DR3. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr3 The value to write to Dr3.
+
+ @return The value written to Debug Register 3 (DR3).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr3 (
+ UINTN Dr3
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr3"
+ :
+ : "r" (Dr3)
+ );
+ return Dr3;
+}
+
+
+/**
+ Writes a value to Debug Register 4 (DR4).
+
+ Writes and returns a new value to DR4. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr4 The value to write to Dr4.
+
+ @return The value written to Debug Register 4 (DR4).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr4 (
+ UINTN Dr4
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr4"
+ :
+ : "r" (Dr4)
+ );
+ return Dr4;
+}
+
+
+/**
+ Writes a value to Debug Register 5 (DR5).
+
+ Writes and returns a new value to DR5. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr5 The value to write to Dr5.
+
+ @return The value written to Debug Register 5 (DR5).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr5 (
+ UINTN Dr5
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr5"
+ :
+ : "r" (Dr5)
+ );
+ return Dr5;
+}
+
+
+/**
+ Writes a value to Debug Register 6 (DR6).
+
+ Writes and returns a new value to DR6. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr6 The value to write to Dr6.
+
+ @return The value written to Debug Register 6 (DR6).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr6 (
+ UINTN Dr6
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr6"
+ :
+ : "r" (Dr6)
+ );
+ return Dr6;
+}
+
+
+/**
+ Writes a value to Debug Register 7 (DR7).
+
+ Writes and returns a new value to DR7. This function is only available on
+ IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64.
+
+ @param Dr7 The value to write to Dr7.
+
+ @return The value written to Debug Register 7 (DR7).
+
+**/
+UINTN
+EFIAPI
+AsmWriteDr7 (
+ UINTN Dr7
+ )
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr7"
+ :
+ : "r" (Dr7)
+ );
+ return Dr7;
+}
+
+
+/**
+ Reads the current value of Code Segment Register (CS).
+
+ Reads and returns the current value of CS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of CS.
+
+**/
+UINT16
+EFIAPI
+AsmReadCs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%cs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Data Segment Register (DS).
+
+ Reads and returns the current value of DS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of DS.
+
+**/
+UINT16
+EFIAPI
+AsmReadDs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%ds, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Extra Segment Register (ES).
+
+ Reads and returns the current value of ES. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of ES.
+
+**/
+UINT16
+EFIAPI
+AsmReadEs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%es, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of FS Data Segment Register (FS).
+
+ Reads and returns the current value of FS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of FS.
+
+**/
+UINT16
+EFIAPI
+AsmReadFs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%fs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of GS Data Segment Register (GS).
+
+ Reads and returns the current value of GS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of GS.
+
+**/
+UINT16
+EFIAPI
+AsmReadGs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%gs, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Stack Segment Register (SS).
+
+ Reads and returns the current value of SS. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of SS.
+
+**/
+UINT16
+EFIAPI
+AsmReadSs (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "mov %%ds, %0"
+ :"=a" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current value of Task Register (TR).
+
+ Reads and returns the current value of TR. This function is only available on
+ IA-32 and X64.
+
+ @return The current value of TR.
+
+**/
+UINT16
+EFIAPI
+AsmReadTr (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "str %0"
+ : "=r" (Data)
+ );
+
+ return Data;
+}
+
+
+/**
+ Reads the current Global Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current GDTR descriptor and returns it in Gdtr. This
+ function is only available on IA-32 and X64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadGdtr (
+ OUT IA32_DESCRIPTOR *Gdtr
+ )
+{
+ __asm__ __volatile__ (
+ "sgdt %0"
+ : "=m" (*Gdtr)
+ );
+}
+
+
+/**
+ Writes the current Global Descriptor Table Register (GDTR) descriptor.
+
+ Writes and the current GDTR descriptor specified by Gdtr. This function is
+ only available on IA-32 and X64.
+
+ @param Gdtr The pointer to a GDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteGdtr (
+ IN CONST IA32_DESCRIPTOR *Gdtr
+ )
+{
+ __asm__ __volatile__ (
+ "lgdt %0"
+ :
+ : "m" (*Gdtr)
+ );
+
+}
+
+
+/**
+ Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Reads and returns the current IDTR descriptor and returns it in Idtr. This
+ function is only available on IA-32 and X64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86ReadIdtr (
+ OUT IA32_DESCRIPTOR *Idtr
+ )
+{
+ __asm__ __volatile__ (
+ "sidt %0"
+ : "=m" (*Idtr)
+ );
+}
+
+
+/**
+ Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.
+
+ Writes the current IDTR descriptor and returns it in Idtr. This function is
+ only available on IA-32 and X64.
+
+ @param Idtr The pointer to a IDTR descriptor.
+
+**/
+VOID
+EFIAPI
+InternalX86WriteIdtr (
+ IN CONST IA32_DESCRIPTOR *Idtr
+ )
+{
+ __asm__ __volatile__ (
+ "lidt %0"
+ :
+ : "m" (*Idtr)
+ );
+}
+
+
+/**
+ Reads the current Local Descriptor Table Register(LDTR) selector.
+
+ Reads and returns the current 16-bit LDTR descriptor value. This function is
+ only available on IA-32 and X64.
+
+ @return The current selector of LDT.
+
+**/
+UINT16
+EFIAPI
+AsmReadLdtr (
+ VOID
+ )
+{
+ UINT16 Data;
+
+ __asm__ __volatile__ (
+ "sldt %0"
+ : "=g" (Data) // %0
+ );
+
+ return Data;
+}
+
+
+/**
+ Writes the current Local Descriptor Table Register (GDTR) selector.
+
+ Writes and the current LDTR descriptor specified by Ldtr. This function is
+ only available on IA-32 and X64.
+
+ @param Ldtr 16-bit LDTR selector value.
+
+**/
+VOID
+EFIAPI
+AsmWriteLdtr (
+ IN UINT16 Ldtr
+ )
+{
+ __asm__ __volatile__ (
+ "lldtw %0"
+ :
+ : "g" (Ldtr) // %0
+ );
+}
+
+/**
+ Reads the current value of a Performance Counter (PMC).
+
+ Reads and returns the current value of performance counter specified by
+ Index. This function is only available on IA-32 and X64.
+
+ @param Index The 32-bit Performance Counter index to read.
+
+ @return The value of the PMC specified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadPmc (
+ IN UINT32 Index
+ )
+{
+ UINT32 LowData;
+ UINT32 HiData;
+
+ __asm__ __volatile__ (
+ "rdpmc"
+ : "=a" (LowData),
+ "=d" (HiData)
+ : "c" (Index)
+ );
+
+ return (((UINT64)HiData) << 32) | LowData;
+}
+
+/**
+ Sets up a monitor buffer that is used by AsmMwait().
+
+ Executes a MONITOR instruction with the register state specified by Eax, Ecx
+ and Edx. Returns Eax. This function is only available on IA-32 and X64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+ @param Edx The value to load into EDX or RDX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMonitor (
+ IN UINTN Eax,
+ IN UINTN Ecx,
+ IN UINTN Edx
+ )
+{
+ __asm__ __volatile__ (
+ "monitor"
+ :
+ : "a" (Eax),
+ "c" (Ecx),
+ "d" (Edx)
+ );
+
+ return Eax;
+}
+
+/**
+ Executes an MWAIT instruction.
+
+ Executes an MWAIT instruction with the register state specified by Eax and
+ Ecx. Returns Eax. This function is only available on IA-32 and X64.
+
+ @param Eax The value to load into EAX or RAX before executing the MONITOR
+ instruction.
+ @param Ecx The value to load into ECX or RCX before executing the MONITOR
+ instruction.
+
+ @return Eax
+
+**/
+UINTN
+EFIAPI
+AsmMwait (
+ IN UINTN Eax,
+ IN UINTN Ecx
+ )
+{
+ __asm__ __volatile__ (
+ "mwait"
+ :
+ : "a" (Eax),
+ "c" (Ecx)
+ );
+
+ return Eax;
+}
+
+/**
+ Executes a WBINVD instruction.
+
+ Executes a WBINVD instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmWbinvd (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("wbinvd":::"memory");
+}
+
+/**
+ Executes a INVD instruction.
+
+ Executes a INVD instruction. This function is only available on IA-32 and
+ X64.
+
+**/
+VOID
+EFIAPI
+AsmInvd (
+ VOID
+ )
+{
+ __asm__ __volatile__ ("invd":::"memory");
+
+}
+
+
+/**
+ Flushes a cache line from all the instruction and data caches within the
+ coherency domain of the CPU.
+
+ Flushed the cache line specified by LinearAddress, and returns LinearAddress.
+ This function is only available on IA-32 and X64.
+
+ @param LinearAddress The address of the cache line to flush. If the CPU is
+ in a physical addressing mode, then LinearAddress is a
+ physical address. If the CPU is in a virtual
+ addressing mode, then LinearAddress is a virtual
+ address.
+
+ @return LinearAddress
+**/
+VOID *
+EFIAPI
+AsmFlushCacheLine (
+ IN VOID *LinearAddress
+ )
+{
+ __asm__ __volatile__ (
+ "clflush (%0)"
+ :
+ : "r" (LinearAddress)
+ : "memory"
+ );
+
+ return LinearAddress;
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Invd.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Invd.nasm new file mode 100644 index 000000000..5580f64c5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Invd.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Invd.Asm
+;
+; Abstract:
+;
+; AsmInvd function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmInvd (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmInvd)
+ASM_PFX(AsmInvd):
+ invd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Lfence.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Lfence.nasm new file mode 100644 index 000000000..25fd0746a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Lfence.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Lfence.nasm
+;
+; Abstract:
+;
+; Performs a serializing operation on all load-from-memory instructions that
+; were issued prior to the call of this function.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmLfence (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmLfence)
+ASM_PFX(AsmLfence):
+ lfence
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/LongJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/LongJump.nasm new file mode 100644 index 000000000..59f709216 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/LongJump.nasm @@ -0,0 +1,77 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; LongJump.Asm
+;
+; Abstract:
+;
+; Implementation of _LongJump() on x64.
+;
+;------------------------------------------------------------------------------
+
+%include "Nasm.inc"
+
+ DEFAULT REL
+ SECTION .text
+
+extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalLongJump (
+; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalLongJump)
+ASM_PFX(InternalLongJump):
+
+ mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))]
+ test eax, eax
+ jz CetDone
+ mov rax, cr4
+ bt eax, 23 ; check if CET is enabled
+ jnc CetDone
+
+ push rdx ; save rdx
+
+ mov rdx, [rcx + 0xF8] ; rdx = target SSP
+ READSSP_RAX
+ sub rdx, rax ; rdx = delta
+ mov rax, rdx ; rax = delta
+
+ shr rax, 3 ; rax = delta/sizeof(UINT64)
+ INCSSP_RAX
+
+ pop rdx ; restore rdx
+CetDone:
+
+ mov rbx, [rcx]
+ mov rsp, [rcx + 8]
+ mov rbp, [rcx + 0x10]
+ mov rdi, [rcx + 0x18]
+ mov rsi, [rcx + 0x20]
+ mov r12, [rcx + 0x28]
+ mov r13, [rcx + 0x30]
+ mov r14, [rcx + 0x38]
+ mov r15, [rcx + 0x40]
+ ; load non-volatile fp registers
+ ldmxcsr [rcx + 0x50]
+ movdqu xmm6, [rcx + 0x58]
+ movdqu xmm7, [rcx + 0x68]
+ movdqu xmm8, [rcx + 0x78]
+ movdqu xmm9, [rcx + 0x88]
+ movdqu xmm10, [rcx + 0x98]
+ movdqu xmm11, [rcx + 0xA8]
+ movdqu xmm12, [rcx + 0xB8]
+ movdqu xmm13, [rcx + 0xC8]
+ movdqu xmm14, [rcx + 0xD8]
+ movdqu xmm15, [rcx + 0xE8]
+ mov rax, rdx ; set return value
+ jmp qword [rcx + 0x48]
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Monitor.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Monitor.nasm new file mode 100644 index 000000000..e1ccb83a8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Monitor.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Monitor.Asm
+;
+; Abstract:
+;
+; AsmMonitor function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmMonitor (
+; IN UINTN Eax,
+; IN UINTN Ecx,
+; IN UINTN Edx
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmMonitor)
+ASM_PFX(AsmMonitor):
+ mov eax, ecx
+ mov ecx, edx
+ mov edx, r8d
+ DB 0xf, 1, 0xc8 ; monitor
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Mwait.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Mwait.nasm new file mode 100644 index 000000000..83fc89549 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Mwait.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Mwait.Asm
+;
+; Abstract:
+;
+; AsmMwait function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmMwait (
+; IN UINTN Eax,
+; IN UINTN Ecx
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmMwait)
+ASM_PFX(AsmMwait):
+ mov eax, ecx
+ mov ecx, edx
+ DB 0xf, 1, 0xc9 ; mwait
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Non-existing.c b/roms/edk2/MdePkg/Library/BaseLib/X64/Non-existing.c new file mode 100644 index 000000000..e00cb7eb5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Non-existing.c @@ -0,0 +1,147 @@ +/** @file
+ Non-existing BaseLib functions on x64
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Enables the 32-bit paging mode on the CPU.
+
+ Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode. This function is
+ only available on IA-32. After the 32-bit paging mode is enabled, control is
+ transferred to the function specified by EntryPoint using the new stack
+ specified by NewStack and passing in the parameters specified by Context1 and
+ Context2. Context1 and Context2 are optional and may be NULL. The function
+ EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit protected mode with flat descriptors. This
+ means all descriptors must have a base of 0 and a limit of 4GB.
+ 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
+ descriptors.
+ 4) CR3 must point to valid page tables that will be used once the transition
+ is complete, and those page tables must guarantee that the pages for this
+ function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is enabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is enabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is enabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+InternalX86EnablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ //
+ // This function cannot work on x64 platform
+ //
+ ASSERT (FALSE);
+}
+
+/**
+ Disables the 32-bit paging mode on the CPU.
+
+ Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
+ mode. This function assumes the current execution mode is 32-paged protected
+ mode. This function is only available on IA-32. After the 32-bit paging mode
+ is disabled, control is transferred to the function specified by EntryPoint
+ using the new stack specified by NewStack and passing in the parameters
+ specified by Context1 and Context2. Context1 and Context2 are optional and
+ may be NULL. The function EntryPoint must never return.
+
+ There are a number of constraints that must be followed before calling this
+ function:
+ 1) Interrupts must be disabled.
+ 2) The caller must be in 32-bit paged mode.
+ 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
+ 4) CR3 must point to valid page tables that guarantee that the pages for
+ this function and the stack are identity mapped.
+
+ @param EntryPoint A pointer to function to call with the new stack after
+ paging is disabled.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function as the first parameter after paging is disabled.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function as the second parameter after paging is
+ disabled.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function after paging is disabled.
+
+**/
+VOID
+EFIAPI
+InternalX86DisablePaging32 (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack
+ )
+{
+ //
+ // This function cannot work on x64 platform
+ //
+ ASSERT (FALSE);
+}
+
+
+/**
+ Enables the 64-bit paging mode on the CPU.
+
+ Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
+ must be properly initialized prior to calling this service. This function
+ assumes the current execution mode is 32-bit protected mode with flat
+ descriptors. This function is only available on IA-32. After the 64-bit
+ paging mode is enabled, control is transferred to the function specified by
+ EntryPoint using the new stack specified by NewStack and passing in the
+ parameters specified by Context1 and Context2. Context1 and Context2 are
+ optional and may be 0. The function EntryPoint must never return.
+
+ @param Cs The 16-bit selector to load in the CS before EntryPoint
+ is called. The descriptor in the GDT that this selector
+ references must be setup for long mode.
+ @param EntryPoint The 64-bit virtual address of the function to call with
+ the new stack after paging is enabled.
+ @param Context1 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the first parameter after
+ paging is enabled.
+ @param Context2 The 64-bit virtual address of the context to pass into
+ the EntryPoint function as the second parameter after
+ paging is enabled.
+ @param NewStack The 64-bit virtual address of the new stack to use for
+ the EntryPoint function after paging is enabled.
+
+**/
+VOID
+EFIAPI
+InternalX86EnablePaging64 (
+ IN UINT16 Cs,
+ IN UINT64 EntryPoint,
+ IN UINT64 Context1, OPTIONAL
+ IN UINT64 Context2, OPTIONAL
+ IN UINT64 NewStack
+ )
+{
+ //
+ // This function cannot work on x64 platform.
+ //
+ ASSERT (FALSE);
+}
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/RdRand.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/RdRand.nasm new file mode 100644 index 000000000..7e7fe9967 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/RdRand.nasm @@ -0,0 +1,77 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; RdRand.nasm
+;
+; Abstract:
+;
+; Generates random number through CPU RdRand instruction under 64-bit platform.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; Generates a 16 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand16 (UINT16 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand16)
+ASM_PFX(InternalX86RdRand16):
+ ; rdrand ax ; generate a 16 bit RN into eax,
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"
+ jc rn16_ok ; jmp if CF=1
+ xor rax, rax ; reg=0 if CF=0
+ ret ; return with failure status
+rn16_ok:
+ mov [rcx], ax
+ mov rax, 1
+ ret
+
+;------------------------------------------------------------------------------
+; Generates a 32 bit random number through RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand32 (UINT32 *Rand);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand32)
+ASM_PFX(InternalX86RdRand32):
+ ; rdrand eax ; generate a 32 bit RN into eax,
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"
+ jc rn32_ok ; jmp if CF=1
+ xor rax, rax ; reg=0 if CF=0
+ ret ; return with failure status
+rn32_ok:
+ mov [rcx], eax
+ mov rax, 1
+ ret
+
+;------------------------------------------------------------------------------
+; Generates a 64 bit random number through one RDRAND instruction.
+; Return TRUE if Rand generated successfully, or FALSE if not.
+;
+; BOOLEAN EFIAPI InternalX86RdRand64 (UINT64 *Random);
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86RdRand64)
+ASM_PFX(InternalX86RdRand64):
+ ; rdrand rax ; generate a 64 bit RN into rax,
+ ; CF=1 if RN generated ok, otherwise CF=0
+ db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)"
+ jc rn64_ok ; jmp if CF=1
+ xor rax, rax ; reg=0 if CF=0
+ ret ; return with failure status
+rn64_ok:
+ mov [rcx], rax
+ mov rax, 1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr0.nasm new file mode 100644 index 000000000..aaa6f81a7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr0.Asm
+;
+; Abstract:
+;
+; AsmReadCr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr0)
+ASM_PFX(AsmReadCr0):
+ mov rax, cr0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr2.nasm new file mode 100644 index 000000000..74c4778e1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr2.Asm
+;
+; Abstract:
+;
+; AsmReadCr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr2)
+ASM_PFX(AsmReadCr2):
+ mov rax, cr2
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr3.nasm new file mode 100644 index 000000000..ea8173f64 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr3.Asm
+;
+; Abstract:
+;
+; AsmReadCr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr3)
+ASM_PFX(AsmReadCr3):
+ mov rax, cr3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr4.nasm new file mode 100644 index 000000000..70c2650ee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCr4.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCr4.Asm
+;
+; Abstract:
+;
+; AsmReadCr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadCr4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCr4)
+ASM_PFX(AsmReadCr4):
+ mov rax, cr4
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCs.nasm new file mode 100644 index 000000000..ec069b8f5 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadCs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadCs.Asm
+;
+; Abstract:
+;
+; AsmReadCs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadCs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadCs)
+ASM_PFX(AsmReadCs):
+ mov eax, cs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr0.nasm new file mode 100644 index 000000000..7973e52b6 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr0.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr0.Asm
+;
+; Abstract:
+;
+; AsmReadDr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr0)
+ASM_PFX(AsmReadDr0):
+ mov rax, dr0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr1.nasm new file mode 100644 index 000000000..1a4b15917 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr1.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr1.Asm
+;
+; Abstract:
+;
+; AsmReadDr1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr1 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr1)
+ASM_PFX(AsmReadDr1):
+ mov rax, dr1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr2.nasm new file mode 100644 index 000000000..d1e403d6a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr2.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr2.Asm
+;
+; Abstract:
+;
+; AsmReadDr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr2)
+ASM_PFX(AsmReadDr2):
+ mov rax, dr2
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr3.nasm new file mode 100644 index 000000000..96a9c5b0c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr3.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr3.Asm
+;
+; Abstract:
+;
+; AsmReadDr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr3)
+ASM_PFX(AsmReadDr3):
+ mov rax, dr3
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr4.nasm new file mode 100644 index 000000000..82c0a9a58 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr4.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr4.Asm
+;
+; Abstract:
+;
+; AsmReadDr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr4)
+ASM_PFX(AsmReadDr4):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR7 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x21, 0xe0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr5.nasm new file mode 100644 index 000000000..c309c66df --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr5.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr5.Asm
+;
+; Abstract:
+;
+; AsmReadDr5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr5 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr5)
+ASM_PFX(AsmReadDr5):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR7 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x21, 0xe8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr6.nasm new file mode 100644 index 000000000..7bdc10313 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr6.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr6.Asm
+;
+; Abstract:
+;
+; AsmReadDr6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr6 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr6)
+ASM_PFX(AsmReadDr6):
+ mov rax, dr6
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr7.nasm new file mode 100644 index 000000000..219d2e459 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDr7.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDr7.Asm
+;
+; Abstract:
+;
+; AsmReadDr7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadDr7 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDr7)
+ASM_PFX(AsmReadDr7):
+ mov rax, dr7
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDs.nasm new file mode 100644 index 000000000..597450d53 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadDs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadDs.Asm
+;
+; Abstract:
+;
+; AsmReadDs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadDs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadDs)
+ASM_PFX(AsmReadDs):
+ mov eax, ds
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEflags.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEflags.nasm new file mode 100644 index 000000000..e0a5ea065 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEflags.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadEflags.Asm
+;
+; Abstract:
+;
+; AsmReadEflags function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmReadEflags (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEflags)
+ASM_PFX(AsmReadEflags):
+ pushfq
+ pop rax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEs.nasm new file mode 100644 index 000000000..963394572 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadEs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadEs.Asm
+;
+; Abstract:
+;
+; AsmReadEs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadEs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadEs)
+ASM_PFX(AsmReadEs):
+ mov eax, es
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadFs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadFs.nasm new file mode 100644 index 000000000..9d032ff48 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadFs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadFs.Asm
+;
+; Abstract:
+;
+; AsmReadFs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadFs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadFs)
+ASM_PFX(AsmReadFs):
+ mov eax, fs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGdtr.nasm new file mode 100644 index 000000000..1712c11eb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadGdtr.Asm
+;
+; Abstract:
+;
+; AsmReadGdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86ReadGdtr (
+; OUT IA32_DESCRIPTOR *Gdtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86ReadGdtr)
+ASM_PFX(InternalX86ReadGdtr):
+ sgdt [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGs.nasm new file mode 100644 index 000000000..953fe9c0c --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadGs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadGs.Asm
+;
+; Abstract:
+;
+; AsmReadGs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadGs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadGs)
+ASM_PFX(AsmReadGs):
+ mov eax, gs
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadIdtr.nasm new file mode 100644 index 000000000..086ab7087 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadIdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadIdtr.Asm
+;
+; Abstract:
+;
+; AsmReadIdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86ReadIdtr (
+; OUT IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86ReadIdtr)
+ASM_PFX(InternalX86ReadIdtr):
+ sidt [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadLdtr.nasm new file mode 100644 index 000000000..9339161a3 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadLdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadLdtr.Asm
+;
+; Abstract:
+;
+; AsmReadLdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadLdtr (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadLdtr)
+ASM_PFX(AsmReadLdtr):
+ sldt eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm0.nasm new file mode 100644 index 000000000..615721b6a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm0.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm0.Asm
+;
+; Abstract:
+;
+; AsmReadMm0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm0 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm0)
+ASM_PFX(AsmReadMm0):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xc0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm1.nasm new file mode 100644 index 000000000..7b2739349 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm1.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm1.Asm
+;
+; Abstract:
+;
+; AsmReadMm1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm1 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm1)
+ASM_PFX(AsmReadMm1):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xc8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm2.nasm new file mode 100644 index 000000000..c654b91a7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm2.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm2.Asm
+;
+; Abstract:
+;
+; AsmReadMm2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm2 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm2)
+ASM_PFX(AsmReadMm2):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xd0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm3.nasm new file mode 100644 index 000000000..88d51c078 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm3.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm3.Asm
+;
+; Abstract:
+;
+; AsmReadMm3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm3 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm3)
+ASM_PFX(AsmReadMm3):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xd8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm4.nasm new file mode 100644 index 000000000..4252d20bb --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm4.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm4.Asm
+;
+; Abstract:
+;
+; AsmReadMm4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm4 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm4)
+ASM_PFX(AsmReadMm4):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xe0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm5.nasm new file mode 100644 index 000000000..d8f530dec --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm5.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm5.Asm
+;
+; Abstract:
+;
+; AsmReadMm5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm5 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm5)
+ASM_PFX(AsmReadMm5):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xe8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm6.nasm new file mode 100644 index 000000000..6f6883c2b --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm6.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm6.Asm
+;
+; Abstract:
+;
+; AsmReadMm6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm6 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm6)
+ASM_PFX(AsmReadMm6):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xf0
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm7.nasm new file mode 100644 index 000000000..573f15dfc --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMm7.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMm7.Asm
+;
+; Abstract:
+;
+; AsmReadMm7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMm7 (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMm7)
+ASM_PFX(AsmReadMm7):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x7e, 0xf8
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.c new file mode 100644 index 000000000..5ee7ca53f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.c @@ -0,0 +1,33 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+unsigned __int64 __readmsr (int register);
+
+#pragma intrinsic(__readmsr)
+
+/**
+ Read data to MSR.
+
+ @param Index Register index of MSR.
+
+ @return Value read from MSR.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ return __readmsr (Index);
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.nasm new file mode 100644 index 000000000..df6925529 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadMsr64.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadMsr64.Asm
+;
+; Abstract:
+;
+; AsmReadMsr64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadMsr64 (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadMsr64)
+ASM_PFX(AsmReadMsr64):
+ rdmsr ; edx & eax are zero extended
+ shl rdx, 0x20
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadPmc.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadPmc.nasm new file mode 100644 index 000000000..1785a09de --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadPmc.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadPmc.Asm
+;
+; Abstract:
+;
+; AsmReadPmc function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadPmc (
+; IN UINT32 PmcIndex
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadPmc)
+ASM_PFX(AsmReadPmc):
+ rdpmc
+ shl rdx, 0x20
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadSs.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadSs.nasm new file mode 100644 index 000000000..5fbe6985a --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadSs.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadSs.Asm
+;
+; Abstract:
+;
+; AsmReadSs function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadSs (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadSs)
+ASM_PFX(AsmReadSs):
+ mov eax, ss
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTr.nasm new file mode 100644 index 000000000..492ef6cd1 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadTr.Asm
+;
+; Abstract:
+;
+; AsmReadTr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; AsmReadTr (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadTr)
+ASM_PFX(AsmReadTr):
+ str eax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTsc.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTsc.nasm new file mode 100644 index 000000000..45672d680 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/ReadTsc.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadTsc.Asm
+;
+; Abstract:
+;
+; AsmReadTsc function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmReadTsc (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmReadTsc)
+ASM_PFX(AsmReadTsc):
+ rdtsc
+ shl rdx, 0x20
+ or rax, rdx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/SetJump.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/SetJump.nasm new file mode 100644 index 000000000..5a68396ee --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/SetJump.nasm @@ -0,0 +1,81 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; SetJump.Asm
+;
+; Abstract:
+;
+; Implementation of SetJump() on x64.
+;
+;------------------------------------------------------------------------------
+
+%include "Nasm.inc"
+
+ DEFAULT REL
+ SECTION .text
+
+extern ASM_PFX(InternalAssertJumpBuffer)
+extern ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; SetJump (
+; OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SetJump)
+ASM_PFX(SetJump):
+ push rcx
+ add rsp, -0x20
+ call ASM_PFX(InternalAssertJumpBuffer)
+ add rsp, 0x20
+ pop rcx
+ pop rdx
+
+ xor rax, rax
+ mov [rcx + 0xF8], rax ; save 0 to SSP
+
+ mov eax, [ASM_PFX(PcdGet32 (PcdControlFlowEnforcementPropertyMask))]
+ test eax, eax
+ jz CetDone
+ mov rax, cr4
+ bt eax, 23 ; check if CET is enabled
+ jnc CetDone
+
+ mov rax, 1
+ INCSSP_RAX ; to read original SSP
+ READSSP_RAX
+ mov [rcx + 0xF8], rax ; save SSP
+
+CetDone:
+
+ mov [rcx], rbx
+ mov [rcx + 8], rsp
+ mov [rcx + 0x10], rbp
+ mov [rcx + 0x18], rdi
+ mov [rcx + 0x20], rsi
+ mov [rcx + 0x28], r12
+ mov [rcx + 0x30], r13
+ mov [rcx + 0x38], r14
+ mov [rcx + 0x40], r15
+ mov [rcx + 0x48], rdx
+ ; save non-volatile fp registers
+ stmxcsr [rcx + 0x50]
+ movdqu [rcx + 0x58], xmm6
+ movdqu [rcx + 0x68], xmm7
+ movdqu [rcx + 0x78], xmm8
+ movdqu [rcx + 0x88], xmm9
+ movdqu [rcx + 0x98], xmm10
+ movdqu [rcx + 0xA8], xmm11
+ movdqu [rcx + 0xB8], xmm12
+ movdqu [rcx + 0xC8], xmm13
+ movdqu [rcx + 0xD8], xmm14
+ movdqu [rcx + 0xE8], xmm15
+ xor rax, rax
+ jmp rdx
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/SwitchStack.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/SwitchStack.nasm new file mode 100644 index 000000000..7be666dbd --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/SwitchStack.nasm @@ -0,0 +1,45 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; SwitchStack.Asm
+;
+; Abstract:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; Routine Description:
+;
+; Routine for switching stacks with 2 parameters
+;
+; Arguments:
+;
+; (rcx) EntryPoint - Entry point with new stack.
+; (rdx) Context1 - Parameter1 for entry point.
+; (r8) Context2 - Parameter2 for entry point.
+; (r9) NewStack - The pointer to new stack.
+;
+; Returns:
+;
+; None
+;
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSwitchStack)
+ASM_PFX(InternalSwitchStack):
+ mov rax, rcx
+ mov rcx, rdx
+ mov rdx, r8
+ ;
+ ; Reserve space for register parameters (rcx, rdx, r8 & r9) on the stack,
+ ; in case the callee wishes to spill them.
+ ;
+ lea rsp, [r9 - 0x20]
+ call rax
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Thunk16.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Thunk16.nasm new file mode 100644 index 000000000..e83b31c59 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Thunk16.nasm @@ -0,0 +1,319 @@ +
+#include "BaseLibInternals.h"
+
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Thunk.asm
+;
+; Abstract:
+;
+; Real mode thunk
+;
+;------------------------------------------------------------------------------
+
+global ASM_PFX(m16Size)
+global ASM_PFX(mThunk16Attr)
+global ASM_PFX(m16Gdt)
+global ASM_PFX(m16GdtrBase)
+global ASM_PFX(mTransition)
+global ASM_PFX(m16Start)
+
+struc IA32_REGS
+
+ ._EDI: resd 1
+ ._ESI: resd 1
+ ._EBP: resd 1
+ ._ESP: resd 1
+ ._EBX: resd 1
+ ._EDX: resd 1
+ ._ECX: resd 1
+ ._EAX: resd 1
+ ._DS: resw 1
+ ._ES: resw 1
+ ._FS: resw 1
+ ._GS: resw 1
+ ._EFLAGS: resq 1
+ ._EIP: resd 1
+ ._CS: resw 1
+ ._SS: resw 1
+ .size:
+
+endstruc
+
+SECTION .data
+
+;
+; These are global constant to convey information to C code.
+;
+ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
+ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)
+ASM_PFX(m16Gdt) DW _NullSeg - ASM_PFX(m16Start)
+ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
+ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
+
+SECTION .text
+
+ASM_PFX(m16Start):
+
+SavedGdt:
+ dw 0
+ dq 0
+
+;------------------------------------------------------------------------------
+; _BackFromUserCode() takes control in real mode after 'retf' has been executed
+; by user code. It will be shadowed to somewhere in memory below 1MB.
+;------------------------------------------------------------------------------
+_BackFromUserCode:
+ ;
+ ; The order of saved registers on the stack matches the order they appears
+ ; in IA32_REGS structure. This facilitates wrapper function to extract them
+ ; into that structure.
+ ;
+BITS 16
+ push ss
+ push cs
+ ;
+ ; Note: We can't use o32 on the next instruction because of a bug
+ ; in NASM 2.09.04 through 2.10rc1.
+ ;
+ call dword .Base ; push eip
+.Base:
+ push dword 0 ; reserved high order 32 bits of EFlags
+ pushfd
+ cli ; disable interrupts
+ push gs
+ push fs
+ push es
+ push ds
+ pushad
+ mov edx, strict dword 0
+.ThunkAttrEnd:
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
+ jz .1
+ mov ax, 2401h
+ int 15h
+ cli ; disable interrupts
+ jnc .2
+.1:
+ test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
+ jz .2
+ in al, 92h
+ or al, 2
+ out 92h, al ; deactivate A20M#
+.2:
+ xor eax, eax
+ mov ax, ss
+ lea ebp, [esp + IA32_REGS.size]
+ mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp
+ mov ebx, [bp - IA32_REGS.size + IA32_REGS._EIP]
+ shl eax, 4 ; shl eax, 4
+ add ebp, eax ; add ebp, eax
+ mov eax, cs
+ shl eax, 4
+ lea eax, [eax + ebx + (.X64JmpEnd - .Base)]
+ mov [cs:bx + (.X64JmpEnd - 6 - .Base)], eax
+ mov eax, strict dword 0
+.SavedCr4End:
+ mov cr4, eax
+o32 lgdt [cs:bx + (SavedGdt - .Base)]
+ mov ecx, 0c0000080h
+ rdmsr
+ or ah, 1
+ wrmsr
+ mov eax, strict dword 0
+.SavedCr0End:
+ mov cr0, eax
+ jmp 0:strict dword 0
+.X64JmpEnd:
+BITS 64
+ nop
+ mov rsp, strict qword 0
+.SavedSpEnd:
+ nop
+ ret
+
+_EntryPoint:
+ DD _ToUserCode - ASM_PFX(m16Start)
+ DW CODE16
+_16Gdtr:
+ DW GDT_SIZE - 1
+_16GdtrBase:
+ DQ 0
+_16Idtr:
+ DW (1 << 10) - 1
+ DD 0
+
+;------------------------------------------------------------------------------
+; _ToUserCode() takes control in real mode before passing control to user code.
+; It will be shadowed to somewhere in memory below 1MB.
+;------------------------------------------------------------------------------
+_ToUserCode:
+BITS 16
+ mov ss, dx ; set new segment selectors
+ mov ds, dx
+ mov es, dx
+ mov fs, dx
+ mov gs, dx
+ mov ecx, 0c0000080h
+ mov cr0, eax ; real mode starts at next instruction
+ rdmsr
+ and ah, ~1
+ wrmsr
+ mov cr4, ebp
+ mov ss, si ; set up 16-bit stack segment
+ mov esp, ebx ; set up 16-bit stack pointer
+ call dword .Base ; push eip
+.Base:
+ pop ebp ; ebp <- address of .Base
+ push word [dword esp + IA32_REGS.size + 2]
+ lea ax, [bp + (.RealMode - .Base)]
+ push ax
+ retf ; execution begins at next instruction
+.RealMode:
+
+o32 lidt [cs:bp + (_16Idtr - .Base)]
+
+ popad
+ pop ds
+ pop es
+ pop fs
+ pop gs
+ popfd
+ lea esp, [esp + 4] ; skip high order 32 bits of EFlags
+
+o32 retf ; transfer control to user code
+
+ALIGN 8
+
+CODE16 equ _16Code - $
+DATA16 equ _16Data - $
+DATA32 equ _32Data - $
+
+_NullSeg DQ 0
+_16Code:
+ DW -1
+ DW 0
+ DB 0
+ DB 9bh
+ DB 8fh ; 16-bit segment, 4GB limit
+ DB 0
+_16Data:
+ DW -1
+ DW 0
+ DB 0
+ DB 93h
+ DB 8fh ; 16-bit segment, 4GB limit
+ DB 0
+_32Data:
+ DW -1
+ DW 0
+ DB 0
+ DB 93h
+ DB 0cfh ; 16-bit segment, 4GB limit
+ DB 0
+
+GDT_SIZE equ $ - _NullSeg
+
+;------------------------------------------------------------------------------
+; IA32_REGISTER_SET *
+; EFIAPI
+; InternalAsmThunk16 (
+; IN IA32_REGISTER_SET *RegisterSet,
+; IN OUT VOID *Transition
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalAsmThunk16)
+ASM_PFX(InternalAsmThunk16):
+BITS 64
+ push rbp
+ push rbx
+ push rsi
+ push rdi
+
+ mov ebx, ds
+ push rbx ; Save ds segment register on the stack
+ mov ebx, es
+ push rbx ; Save es segment register on the stack
+ mov ebx, ss
+ push rbx ; Save ss segment register on the stack
+
+ push fs
+ push gs
+ mov rsi, rcx
+ movzx r8d, word [rsi + IA32_REGS._SS]
+ mov edi, [rsi + IA32_REGS._ESP]
+ lea rdi, [edi - (IA32_REGS.size + 4)]
+ imul eax, r8d, 16 ; eax <- r8d(stack segment) * 16
+ mov ebx, edi ; ebx <- stack for 16-bit code
+ push IA32_REGS.size / 4
+ add edi, eax ; edi <- linear address of 16-bit stack
+ pop rcx
+ rep movsd ; copy RegSet
+ lea ecx, [rdx + (_BackFromUserCode.SavedCr4End - ASM_PFX(m16Start))]
+ mov eax, edx ; eax <- transition code address
+ and edx, 0fh
+ shl eax, 12 ; segment address in high order 16 bits
+ lea ax, [rdx + (_BackFromUserCode - ASM_PFX(m16Start))] ; offset address
+ stosd ; [edi] <- return address of user code
+
+ sgdt [rsp + 60h] ; save GDT stack in argument space
+ movzx r10, word [rsp + 60h] ; r10 <- GDT limit
+ lea r11, [rcx + (ASM_PFX(InternalAsmThunk16) - _BackFromUserCode.SavedCr4End) + 0xf]
+ and r11, ~0xf ; r11 <- 16-byte aligned shadowed GDT table in real mode buffer
+
+ mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End)], r10w ; save the limit of shadowed GDT table
+ mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End) + 2], r11 ; save the base address of shadowed GDT table
+
+ mov rsi, [rsp + 62h] ; rsi <- the original GDT base address
+ xchg rcx, r10 ; save rcx to r10 and initialize rcx to be the limit of GDT table
+ inc rcx ; rcx <- the size of memory to copy
+ xchg rdi, r11 ; save rdi to r11 and initialize rdi to the base address of shadowed GDT table
+ rep movsb ; perform memory copy to shadow GDT table
+ mov rcx, r10 ; restore the orignal rcx before memory copy
+ mov rdi, r11 ; restore the original rdi before memory copy
+
+ sidt [rsp + 50h] ; save IDT stack in argument space
+ mov rax, cr0
+ mov [rcx + (_BackFromUserCode.SavedCr0End - 4 - _BackFromUserCode.SavedCr4End)], eax
+ and eax, 7ffffffeh ; clear PE, PG bits
+ mov rbp, cr4
+ mov [rcx - 4], ebp ; save CR4 in _BackFromUserCode.SavedCr4End - 4
+ and ebp, ~30h ; clear PAE, PSE bits
+ mov esi, r8d ; esi <- 16-bit stack segment
+ push DATA32
+ pop rdx ; rdx <- 32-bit data segment selector
+ lgdt [rcx + (_16Gdtr - _BackFromUserCode.SavedCr4End)]
+ mov ss, edx
+ pushfq
+ lea edx, [rdx + DATA16 - DATA32]
+ lea r8, [REL .RetFromRealMode]
+ push r8
+ mov r8d, cs
+ mov [rcx + (_BackFromUserCode.X64JmpEnd - 2 - _BackFromUserCode.SavedCr4End)], r8w
+ mov [rcx + (_BackFromUserCode.SavedSpEnd - 8 - _BackFromUserCode.SavedCr4End)], rsp
+ jmp dword far [rcx + (_EntryPoint - _BackFromUserCode.SavedCr4End)]
+.RetFromRealMode:
+ popfq
+ lgdt [rsp + 60h] ; restore protected mode GDTR
+ lidt [rsp + 50h] ; restore protected mode IDTR
+ lea eax, [rbp - IA32_REGS.size]
+ pop gs
+ pop fs
+ pop rbx
+ mov ss, ebx
+ pop rbx
+ mov es, ebx
+ pop rbx
+ mov ds, ebx
+
+ pop rdi
+ pop rsi
+ pop rbx
+ pop rbp
+
+ ret
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/VmgExit.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/VmgExit.nasm new file mode 100644 index 000000000..26f034593 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/VmgExit.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; VmgExit.Asm
+;
+; Abstract:
+;
+; AsmVmgExit function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmVmgExit (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmVmgExit)
+ASM_PFX(AsmVmgExit):
+ rep vmmcall
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/Wbinvd.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/Wbinvd.nasm new file mode 100644 index 000000000..90427fe20 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/Wbinvd.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; Wbinvd.Asm
+;
+; Abstract:
+;
+; AsmWbinvd function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWbinvd (
+; VOID
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWbinvd)
+ASM_PFX(AsmWbinvd):
+ wbinvd
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr0.nasm new file mode 100644 index 000000000..d351396ff --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr0.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr0.Asm
+;
+; Abstract:
+;
+; AsmWriteCr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr0 (
+; UINTN Cr0
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr0)
+ASM_PFX(AsmWriteCr0):
+ mov cr0, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr2.nasm new file mode 100644 index 000000000..2b6bce03f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr2.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr2.Asm
+;
+; Abstract:
+;
+; AsmWriteCr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr2 (
+; UINTN Cr2
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr2)
+ASM_PFX(AsmWriteCr2):
+ mov cr2, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr3.nasm new file mode 100644 index 000000000..fb0b5bad2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr3.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr3.Asm
+;
+; Abstract:
+;
+; AsmWriteCr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr3 (
+; UINTN Cr3
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr3)
+ASM_PFX(AsmWriteCr3):
+ mov cr3, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr4.nasm new file mode 100644 index 000000000..483a996d8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteCr4.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteCr4.Asm
+;
+; Abstract:
+;
+; AsmWriteCr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteCr4 (
+; UINTN Cr4
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteCr4)
+ASM_PFX(AsmWriteCr4):
+ mov cr4, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr0.nasm new file mode 100644 index 000000000..3c8815468 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr0.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr0.Asm
+;
+; Abstract:
+;
+; AsmWriteDr0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr0 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr0)
+ASM_PFX(AsmWriteDr0):
+ mov dr0, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr1.nasm new file mode 100644 index 000000000..6fcbbfc9e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr1.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr1.Asm
+;
+; Abstract:
+;
+; AsmWriteDr1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr1 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr1)
+ASM_PFX(AsmWriteDr1):
+ mov dr1, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr2.nasm new file mode 100644 index 000000000..a8e0bfc05 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr2.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr2.Asm
+;
+; Abstract:
+;
+; AsmWriteDr2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr2 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr2)
+ASM_PFX(AsmWriteDr2):
+ mov dr2, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr3.nasm new file mode 100644 index 000000000..ac46ab8b7 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr3.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr3.Asm
+;
+; Abstract:
+;
+; AsmWriteDr3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr3 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr3)
+ASM_PFX(AsmWriteDr3):
+ mov dr3, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr4.nasm new file mode 100644 index 000000000..c4b12c9e9 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr4.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr4.Asm
+;
+; Abstract:
+;
+; AsmWriteDr4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr4 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr4)
+ASM_PFX(AsmWriteDr4):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR6 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x23, 0xe1
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr5.nasm new file mode 100644 index 000000000..986a4a95d --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr5.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr5.Asm
+;
+; Abstract:
+;
+; AsmWriteDr5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr5 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr5)
+ASM_PFX(AsmWriteDr5):
+ ;
+ ; There's no obvious reason to access this register, since it's aliased to
+ ; DR7 when DE=0 or an exception generated when DE=1
+ ;
+ DB 0xf, 0x23, 0xe9
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr6.nasm new file mode 100644 index 000000000..196993df2 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr6.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr6.Asm
+;
+; Abstract:
+;
+; AsmWriteDr6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr6 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr6)
+ASM_PFX(AsmWriteDr6):
+ mov dr6, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr7.nasm new file mode 100644 index 000000000..1b3c18114 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteDr7.nasm @@ -0,0 +1,33 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteDr7.Asm
+;
+; Abstract:
+;
+; AsmWriteDr7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINTN
+; EFIAPI
+; AsmWriteDr7 (
+; IN UINTN Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteDr7)
+ASM_PFX(AsmWriteDr7):
+ mov dr7, rcx
+ mov rax, rcx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteGdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteGdtr.nasm new file mode 100644 index 000000000..0a26ba099 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteGdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteGdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteGdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86WriteGdtr (
+; IN CONST IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86WriteGdtr)
+ASM_PFX(InternalX86WriteGdtr):
+ lgdt [rcx]
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteIdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteIdtr.nasm new file mode 100644 index 000000000..c6155c018 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteIdtr.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteIdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteIdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; InternalX86WriteIdtr (
+; IN CONST IA32_DESCRIPTOR *Idtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalX86WriteIdtr)
+ASM_PFX(InternalX86WriteIdtr):
+ pushfq
+ cli
+ lidt [rcx]
+ popfq
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteLdtr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteLdtr.nasm new file mode 100644 index 000000000..55881db16 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteLdtr.nasm @@ -0,0 +1,32 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteLdtr.Asm
+;
+; Abstract:
+;
+; AsmWriteLdtr function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteLdtr (
+; IN UINT16 Ldtr
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteLdtr)
+ASM_PFX(AsmWriteLdtr):
+ lldt cx
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm0.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm0.nasm new file mode 100644 index 000000000..3f03529ed --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm0.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm0.Asm
+;
+; Abstract:
+;
+; AsmWriteMm0 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm0 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm0)
+ASM_PFX(AsmWriteMm0):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xc1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm1.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm1.nasm new file mode 100644 index 000000000..f552d4071 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm1.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm1.Asm
+;
+; Abstract:
+;
+; AsmWriteMm1 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm1 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm1)
+ASM_PFX(AsmWriteMm1):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xc9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm2.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm2.nasm new file mode 100644 index 000000000..1bd176ced --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm2.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm2.Asm
+;
+; Abstract:
+;
+; AsmWriteMm2 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm2 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm2)
+ASM_PFX(AsmWriteMm2):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xd1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm3.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm3.nasm new file mode 100644 index 000000000..403f14073 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm3.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm3.Asm
+;
+; Abstract:
+;
+; AsmWriteMm3 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm3 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm3)
+ASM_PFX(AsmWriteMm3):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xd9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm4.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm4.nasm new file mode 100644 index 000000000..d99709d49 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm4.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm4.Asm
+;
+; Abstract:
+;
+; AsmWriteMm4 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm4 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm4)
+ASM_PFX(AsmWriteMm4):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xe1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm5.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm5.nasm new file mode 100644 index 000000000..0467ac422 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm5.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm5.Asm
+;
+; Abstract:
+;
+; AsmWriteMm5 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm5 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm5)
+ASM_PFX(AsmWriteMm5):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xe9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm6.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm6.nasm new file mode 100644 index 000000000..6d2e5eb8f --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm6.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm6.Asm
+;
+; Abstract:
+;
+; AsmWriteMm6 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm6 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm6)
+ASM_PFX(AsmWriteMm6):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xf1
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm7.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm7.nasm new file mode 100644 index 000000000..de72adf68 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMm7.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMm7.Asm
+;
+; Abstract:
+;
+; AsmWriteMm7 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmWriteMm7 (
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMm7)
+ASM_PFX(AsmWriteMm7):
+ ;
+ ; 64-bit MASM doesn't support MMX instructions, so use opcode here
+ ;
+ DB 0x48, 0xf, 0x6e, 0xf9
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.c b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.c new file mode 100644 index 000000000..98c5458d8 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.c @@ -0,0 +1,36 @@ +/** @file
+ CpuBreakpoint function.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+void __writemsr (unsigned long Register, unsigned __int64 Value);
+
+#pragma intrinsic(__writemsr)
+
+/**
+ Write data to MSR.
+
+ @param Index The register index of MSR.
+ @param Value Data wants to be written.
+
+ @return Value written to MSR.
+
+**/
+UINT64
+EFIAPI
+AsmWriteMsr64 (
+ IN UINT32 Index,
+ IN UINT64 Value
+ )
+{
+ __writemsr (Index, Value);
+ return Value;
+}
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.nasm new file mode 100644 index 000000000..11224d304 --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteMsr64.nasm @@ -0,0 +1,35 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteMsr64.Asm
+;
+; Abstract:
+;
+; AsmWriteMsr64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmWriteMsr64 (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteMsr64)
+ASM_PFX(AsmWriteMsr64):
+ mov rax, rdx ; meanwhile, rax <- return value
+ shr rdx, 0x20 ; edx:eax contains the value to write
+ wrmsr
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/WriteTr.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteTr.nasm new file mode 100644 index 000000000..4e364bc8e --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/WriteTr.nasm @@ -0,0 +1,31 @@ +;------------------------------------------------------------------------------ ;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteTr.nasm
+;
+; Abstract:
+;
+; Write TR register
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; AsmWriteTr (
+; UINT16 Selector
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmWriteTr)
+ASM_PFX(AsmWriteTr):
+ mov eax, ecx
+ ltr ax
+ ret
+
diff --git a/roms/edk2/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/roms/edk2/MdePkg/Library/BaseLib/X64/XGetBv.nasm new file mode 100644 index 000000000..09f3be8ae --- /dev/null +++ b/roms/edk2/MdePkg/Library/BaseLib/X64/XGetBv.nasm @@ -0,0 +1,34 @@ +;------------------------------------------------------------------------------
+;
+; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XGetBv.Asm
+;
+; Abstract:
+;
+; AsmXgetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXGetBv (
+; IN UINT32 Index
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXGetBv)
+ASM_PFX(AsmXGetBv):
+ xgetbv
+ shl rdx, 32
+ or rax, rdx
+ ret
+
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