diff options
Diffstat (limited to 'roms/opensbi/platform/fpga')
| -rw-r--r-- | roms/opensbi/platform/fpga/ariane/config.mk | 36 | ||||
| -rw-r--r-- | roms/opensbi/platform/fpga/ariane/objects.mk | 8 | ||||
| -rw-r--r-- | roms/opensbi/platform/fpga/ariane/platform.c | 177 | ||||
| -rw-r--r-- | roms/opensbi/platform/fpga/openpiton/config.mk | 35 | ||||
| -rw-r--r-- | roms/opensbi/platform/fpga/openpiton/objects.mk | 7 | ||||
| -rw-r--r-- | roms/opensbi/platform/fpga/openpiton/platform.c | 203 |
6 files changed, 466 insertions, 0 deletions
diff --git a/roms/opensbi/platform/fpga/ariane/config.mk b/roms/opensbi/platform/fpga/ariane/config.mk new file mode 100644 index 000000000..3556461a1 --- /dev/null +++ b/roms/opensbi/platform/fpga/ariane/config.mk @@ -0,0 +1,36 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (C) 2019 FORTH-ICS/CARV +# Panagiotis Peristerakis <perister@ics.forth.gr> +# + +#for more infos, check out /platform/template/config.mk + +PLATFORM_RISCV_XLEN = 64 + +# Blobs to build +FW_TEXT_START=0x80000000 +FW_JUMP=n + +ifeq ($(PLATFORM_RISCV_XLEN), 32) + # This needs to be 4MB aligned for 32-bit support + FW_JUMP_ADDR=0x80400000 + else + # This needs to be 2MB aligned for 64-bit support + FW_JUMP_ADDR=0x80200000 + endif +FW_JUMP_FDT_ADDR=0x82200000 + +# Firmware with payload configuration. +FW_PAYLOAD=y + +ifeq ($(PLATFORM_RISCV_XLEN), 32) +# This needs to be 4MB aligned for 32-bit support + FW_PAYLOAD_OFFSET=0x400000 +else +# This needs to be 2MB aligned for 64-bit support + FW_PAYLOAD_OFFSET=0x200000 +endif +FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_ALIGN=0x1000 diff --git a/roms/opensbi/platform/fpga/ariane/objects.mk b/roms/opensbi/platform/fpga/ariane/objects.mk new file mode 100644 index 000000000..814e6da63 --- /dev/null +++ b/roms/opensbi/platform/fpga/ariane/objects.mk @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (C) 2019 FORTH-ICS/CARV +# Panagiotis Peristerakis <perister@ics.forth.gr> +# + +platform-objs-y += platform.o diff --git a/roms/opensbi/platform/fpga/ariane/platform.c b/roms/opensbi/platform/fpga/ariane/platform.c new file mode 100644 index 000000000..ea179e52d --- /dev/null +++ b/roms/opensbi/platform/fpga/ariane/platform.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2019 FORTH-ICS/CARV + * Panagiotis Peristerakis <perister@ics.forth.gr> + */ + +#include <sbi/riscv_asm.h> +#include <sbi/riscv_encoding.h> +#include <sbi/riscv_io.h> +#include <sbi/sbi_console.h> +#include <sbi/sbi_const.h> +#include <sbi/sbi_hart.h> +#include <sbi/sbi_platform.h> +#include <sbi_utils/fdt/fdt_fixup.h> +#include <sbi_utils/irqchip/plic.h> +#include <sbi_utils/serial/uart8250.h> +#include <sbi_utils/sys/clint.h> + +#define ARIANE_UART_ADDR 0x10000000 +#define ARIANE_UART_FREQ 50000000 +#define ARIANE_UART_BAUDRATE 115200 +#define ARIANE_UART_REG_SHIFT 2 +#define ARIANE_UART_REG_WIDTH 4 +#define ARIANE_PLIC_ADDR 0xc000000 +#define ARIANE_PLIC_NUM_SOURCES 3 +#define ARIANE_HART_COUNT 1 +#define ARIANE_CLINT_ADDR 0x2000000 + +static struct plic_data plic = { + .addr = ARIANE_PLIC_ADDR, + .num_src = ARIANE_PLIC_NUM_SOURCES, +}; + +static struct clint_data clint = { + .addr = ARIANE_CLINT_ADDR, + .first_hartid = 0, + .hart_count = ARIANE_HART_COUNT, + .has_64bit_mmio = TRUE, +}; + +/* + * Ariane platform early initialization. + */ +static int ariane_early_init(bool cold_boot) +{ + /* For now nothing to do. */ + return 0; +} + +/* + * Ariane platform final initialization. + */ +static int ariane_final_init(bool cold_boot) +{ + void *fdt; + + if (!cold_boot) + return 0; + + fdt = sbi_scratch_thishart_arg1_ptr(); + fdt_fixups(fdt); + + return 0; +} + +/* + * Initialize the ariane console. + */ +static int ariane_console_init(void) +{ + return uart8250_init(ARIANE_UART_ADDR, + ARIANE_UART_FREQ, + ARIANE_UART_BAUDRATE, + ARIANE_UART_REG_SHIFT, + ARIANE_UART_REG_WIDTH); +} + +static int plic_ariane_warm_irqchip_init(int m_cntx_id, int s_cntx_id) +{ + size_t i, ie_words = ARIANE_PLIC_NUM_SOURCES / 32 + 1; + + /* By default, enable all IRQs for M-mode of target HART */ + if (m_cntx_id > -1) { + for (i = 0; i < ie_words; i++) + plic_set_ie(&plic, m_cntx_id, i, 1); + } + /* Enable all IRQs for S-mode of target HART */ + if (s_cntx_id > -1) { + for (i = 0; i < ie_words; i++) + plic_set_ie(&plic, s_cntx_id, i, 1); + } + /* By default, enable M-mode threshold */ + if (m_cntx_id > -1) + plic_set_thresh(&plic, m_cntx_id, 1); + /* By default, disable S-mode threshold */ + if (s_cntx_id > -1) + plic_set_thresh(&plic, s_cntx_id, 0); + + return 0; +} + +/* + * Initialize the ariane interrupt controller for current HART. + */ +static int ariane_irqchip_init(bool cold_boot) +{ + u32 hartid = current_hartid(); + int ret; + + if (cold_boot) { + ret = plic_cold_irqchip_init(&plic); + if (ret) + return ret; + } + return plic_ariane_warm_irqchip_init(2 * hartid, 2 * hartid + 1); +} + +/* + * Initialize IPI for current HART. + */ +static int ariane_ipi_init(bool cold_boot) +{ + int ret; + + if (cold_boot) { + ret = clint_cold_ipi_init(&clint); + if (ret) + return ret; + } + + return clint_warm_ipi_init(); +} + +/* + * Initialize ariane timer for current HART. + */ +static int ariane_timer_init(bool cold_boot) +{ + int ret; + + if (cold_boot) { + ret = clint_cold_timer_init(&clint, NULL); + if (ret) + return ret; + } + + return clint_warm_timer_init(); +} + +/* + * Platform descriptor. + */ +const struct sbi_platform_operations platform_ops = { + .early_init = ariane_early_init, + .final_init = ariane_final_init, + .console_init = ariane_console_init, + .console_putc = uart8250_putc, + .console_getc = uart8250_getc, + .irqchip_init = ariane_irqchip_init, + .ipi_init = ariane_ipi_init, + .ipi_send = clint_ipi_send, + .ipi_clear = clint_ipi_clear, + .timer_init = ariane_timer_init, + .timer_value = clint_timer_value, + .timer_event_start = clint_timer_event_start, + .timer_event_stop = clint_timer_event_stop, +}; + +const struct sbi_platform platform = { + .opensbi_version = OPENSBI_VERSION, + .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), + .name = "ARIANE RISC-V", + .features = SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count = ARIANE_HART_COUNT, + .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, + .platform_ops_addr = (unsigned long)&platform_ops +}; diff --git a/roms/opensbi/platform/fpga/openpiton/config.mk b/roms/opensbi/platform/fpga/openpiton/config.mk new file mode 100644 index 000000000..a969b250a --- /dev/null +++ b/roms/opensbi/platform/fpga/openpiton/config.mk @@ -0,0 +1,35 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (c) 2020 Western Digital Corporation or its affiliates. +# + +#for more infos, check out /platform/template/config.mk + +PLATFORM_RISCV_XLEN = 64 + +# Blobs to build +FW_TEXT_START=0x80000000 +FW_JUMP=n + +ifeq ($(PLATFORM_RISCV_XLEN), 32) + # This needs to be 4MB aligned for 32-bit support + FW_JUMP_ADDR=0x80400000 + else + # This needs to be 2MB aligned for 64-bit support + FW_JUMP_ADDR=0x80200000 + endif +FW_JUMP_FDT_ADDR=0x82200000 + +# Firmware with payload configuration. +FW_PAYLOAD=y + +ifeq ($(PLATFORM_RISCV_XLEN), 32) +# This needs to be 4MB aligned for 32-bit support + FW_PAYLOAD_OFFSET=0x400000 +else +# This needs to be 2MB aligned for 64-bit support + FW_PAYLOAD_OFFSET=0x200000 +endif +FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_ALIGN=0x1000 diff --git a/roms/opensbi/platform/fpga/openpiton/objects.mk b/roms/opensbi/platform/fpga/openpiton/objects.mk new file mode 100644 index 000000000..30a3c4fb8 --- /dev/null +++ b/roms/opensbi/platform/fpga/openpiton/objects.mk @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: BSD-2-Clause +# +# Copyright (c) 2020 Western Digital Corporation or its affiliates. +# + +platform-objs-y += platform.o diff --git a/roms/opensbi/platform/fpga/openpiton/platform.c b/roms/opensbi/platform/fpga/openpiton/platform.c new file mode 100644 index 000000000..5eae47799 --- /dev/null +++ b/roms/opensbi/platform/fpga/openpiton/platform.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ + +#include <sbi/riscv_asm.h> +#include <sbi/riscv_encoding.h> +#include <sbi/riscv_io.h> +#include <sbi/sbi_console.h> +#include <sbi/sbi_const.h> +#include <sbi/sbi_hart.h> +#include <sbi/sbi_platform.h> +#include <sbi_utils/fdt/fdt_helper.h> +#include <sbi_utils/fdt/fdt_fixup.h> +#include <sbi_utils/irqchip/plic.h> +#include <sbi_utils/serial/uart8250.h> +#include <sbi_utils/sys/clint.h> + +#define OPENPITON_DEFAULT_UART_ADDR 0xfff0c2c000 +#define OPENPITON_DEFAULT_UART_FREQ 60000000 +#define OPENPITON_DEFAULT_UART_BAUDRATE 115200 +#define OPENPITON_DEFAULT_UART_REG_SHIFT 0 +#define OPENPITON_DEFAULT_UART_REG_WIDTH 1 +#define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000 +#define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2 +#define OPENPITON_DEFAULT_HART_COUNT 3 +#define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000 + +static struct platform_uart_data uart = { + OPENPITON_DEFAULT_UART_ADDR, + OPENPITON_DEFAULT_UART_FREQ, + OPENPITON_DEFAULT_UART_BAUDRATE, +}; +static struct plic_data plic = { + .addr = OPENPITON_DEFAULT_PLIC_ADDR, + .num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES, +}; + +static struct clint_data clint = { + .addr = OPENPITON_DEFAULT_CLINT_ADDR, + .first_hartid = 0, + .hart_count = OPENPITON_DEFAULT_HART_COUNT, + .has_64bit_mmio = TRUE, +}; + +/* + * OpenPiton platform early initialization. + */ +static int openpiton_early_init(bool cold_boot) +{ + void *fdt; + struct platform_uart_data uart_data; + struct plic_data plic_data; + unsigned long clint_addr; + int rc; + + if (!cold_boot) + return 0; + fdt = sbi_scratch_thishart_arg1_ptr(); + + rc = fdt_parse_uart8250(fdt, &uart_data, "ns16550"); + if (!rc) + uart = uart_data; + + rc = fdt_parse_plic(fdt, &plic_data, "riscv,plic0"); + if (!rc) + plic = plic_data; + + rc = fdt_parse_compat_addr(fdt, &clint_addr, "riscv,clint0"); + if (!rc) + clint.addr = clint_addr; + + return 0; +} + +/* + * OpenPiton platform final initialization. + */ +static int openpiton_final_init(bool cold_boot) +{ + void *fdt; + + if (!cold_boot) + return 0; + + fdt = sbi_scratch_thishart_arg1_ptr(); + fdt_fixups(fdt); + + return 0; +} + +/* + * Initialize the openpiton console. + */ +static int openpiton_console_init(void) +{ + return uart8250_init(uart.addr, + uart.freq, + uart.baud, + OPENPITON_DEFAULT_UART_REG_SHIFT, + OPENPITON_DEFAULT_UART_REG_WIDTH); +} + +static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id) +{ + size_t i, ie_words = plic.num_src / 32 + 1; + + /* By default, enable all IRQs for M-mode of target HART */ + if (m_cntx_id > -1) { + for (i = 0; i < ie_words; i++) + plic_set_ie(&plic, m_cntx_id, i, 1); + } + /* Enable all IRQs for S-mode of target HART */ + if (s_cntx_id > -1) { + for (i = 0; i < ie_words; i++) + plic_set_ie(&plic, s_cntx_id, i, 1); + } + /* By default, enable M-mode threshold */ + if (m_cntx_id > -1) + plic_set_thresh(&plic, m_cntx_id, 1); + /* By default, disable S-mode threshold */ + if (s_cntx_id > -1) + plic_set_thresh(&plic, s_cntx_id, 0); + + return 0; +} + +/* + * Initialize the openpiton interrupt controller for current HART. + */ +static int openpiton_irqchip_init(bool cold_boot) +{ + u32 hartid = current_hartid(); + int ret; + + if (cold_boot) { + ret = plic_cold_irqchip_init(&plic); + if (ret) + return ret; + } + return plic_openpiton_warm_irqchip_init(2 * hartid, 2 * hartid + 1); +} + +/* + * Initialize IPI for current HART. + */ +static int openpiton_ipi_init(bool cold_boot) +{ + int ret; + + if (cold_boot) { + ret = clint_cold_ipi_init(&clint); + if (ret) + return ret; + } + + return clint_warm_ipi_init(); +} + +/* + * Initialize openpiton timer for current HART. + */ +static int openpiton_timer_init(bool cold_boot) +{ + int ret; + + if (cold_boot) { + ret = clint_cold_timer_init(&clint, NULL); + if (ret) + return ret; + } + + return clint_warm_timer_init(); +} + +/* + * Platform descriptor. + */ +const struct sbi_platform_operations platform_ops = { + .early_init = openpiton_early_init, + .final_init = openpiton_final_init, + .console_init = openpiton_console_init, + .console_putc = uart8250_putc, + .console_getc = uart8250_getc, + .irqchip_init = openpiton_irqchip_init, + .ipi_init = openpiton_ipi_init, + .ipi_send = clint_ipi_send, + .ipi_clear = clint_ipi_clear, + .timer_init = openpiton_timer_init, + .timer_value = clint_timer_value, + .timer_event_start = clint_timer_event_start, + .timer_event_stop = clint_timer_event_stop, +}; + +const struct sbi_platform platform = { + .opensbi_version = OPENSBI_VERSION, + .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01), + .name = "OPENPITON RISC-V", + .features = SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count = OPENPITON_DEFAULT_HART_COUNT, + .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE, + .platform_ops_addr = (unsigned long)&platform_ops +}; |