diff options
Diffstat (limited to 'roms/skiboot/hdata')
31 files changed, 17431 insertions, 0 deletions
diff --git a/roms/skiboot/hdata/Makefile.inc b/roms/skiboot/hdata/Makefile.inc new file mode 100644 index 000000000..49690f3c5 --- /dev/null +++ b/roms/skiboot/hdata/Makefile.inc @@ -0,0 +1,8 @@ +# -*-Makefile-*- + +SUBDIRS += hdata +HDATA_OBJS = naca.o spira.o pcia.o hdif.o memory.o fsp.o iohub.o vpd.o slca.o +HDATA_OBJS += cpu-common.o vpd-common.o hostservices.o i2c.o tpmrel.o +DEVSRC_OBJ = hdata/built-in.a + +$(DEVSRC_OBJ): $(HDATA_OBJS:%=hdata/%) diff --git a/roms/skiboot/hdata/cpu-common.c b/roms/skiboot/hdata/cpu-common.c new file mode 100644 index 000000000..bf821c154 --- /dev/null +++ b/roms/skiboot/hdata/cpu-common.c @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#include <skiboot.h> +#include "spira.h" +#include <cpu.h> +#include <ccan/str/str.h> +#include <device.h> + +#include "hdata.h" + +struct dt_node * add_core_common(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + const struct sppcia_cpu_timebase *tb, + uint32_t int_server, bool okay) +{ + const char *name; + struct dt_node *cpu; + uint32_t version; + uint64_t freq; + const uint8_t pa_features_p8[] = { + 24, 0, + 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, + }; + const uint8_t pa_features_p9n_dd20[] = { + 64, 0, + 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */ + }; + const uint8_t pa_features_p9[] = { + 64, 0, + 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */ + }; + const uint8_t pa_features_p10[] = { + 66, 0, + 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xd0, 0x80, 0x00, /* 0 .. 7 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 .. 15 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 16 .. 23 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 24 .. 31 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, /* 32 .. 39 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 40 .. 47 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 .. 55 */ + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 56 .. 63 */ + 0x80, 0x00, /* 64 .. 65 */ + }; + + const uint8_t *pa_features; + size_t pa_features_size; + + prlog(PR_INFO, " Cache: I=%u D=%u/%u/%u/%u\n", + be32_to_cpu(cache->icache_size_kb), + be32_to_cpu(cache->l1_dcache_size_kb), + be32_to_cpu(cache->l2_dcache_size_kb), + be32_to_cpu(cache->l3_dcache_size_kb), + be32_to_cpu(cache->l35_dcache_size_kb)); + + /* Use the boot CPU PVR to make up a CPU name in the device-tree + * since the HDAT doesn't seem to tell.... + */ + version = mfspr(SPR_PVR); + switch(PVR_TYPE(version)) { + case PVR_TYPE_P8E: + case PVR_TYPE_P8: + case PVR_TYPE_P8NVL: + name = "PowerPC,POWER8"; + pa_features = pa_features_p8; + pa_features_size = sizeof(pa_features_p8); + break; + case PVR_TYPE_P9: + case PVR_TYPE_P9P: + name = "PowerPC,POWER9"; + if (is_power9n(version) && + (PVR_VERS_MAJ(version) == 2) && + (PVR_VERS_MIN(version) == 0)) { + /* P9N DD2.0 */ + pa_features = pa_features_p9n_dd20; + pa_features_size = sizeof(pa_features_p9n_dd20); + } else { + pa_features = pa_features_p9; + pa_features_size = sizeof(pa_features_p9); + } + break; + case PVR_TYPE_P10: + name = "PowerPC,POWER10"; + pa_features = pa_features_p10; + pa_features_size = sizeof(pa_features_p10); + break; + default: + name = "PowerPC,Unknown"; + pa_features = NULL; + } + + cpu = dt_new_addr(cpus, name, int_server); + assert(cpu); + dt_add_property_string(cpu, "device_type", "cpu"); + dt_add_property_string(cpu, "status", okay ? "okay" : "bad"); + dt_add_property_cells(cpu, "reg", int_server); + dt_add_property_cells(cpu, "cpu-version", version); + dt_add_property(cpu, "64-bit", NULL, 0); + dt_add_property(cpu, "32-64-bridge", NULL, 0); + dt_add_property(cpu, "graphics", NULL, 0); + dt_add_property(cpu, "general-purpose", NULL, 0); + dt_add_property_cells(cpu, "ibm,processor-segment-sizes", + 0x1c, 0x28, 0xffffffff, 0xffffffff); + dt_add_property_cells(cpu, "ibm,processor-page-sizes", + 0xc, 0x10, 0x18, 0x22); + + if (proc_gen >= proc_gen_p9) + dt_add_property_cells(cpu, "ibm,processor-radix-AP-encodings", + 0x0000000c, 0xa0000010, 0x20000015, 0x4000001e); + + /* HPT segment page size encodings, common to all supported CPUs */ + dt_add_property_cells(cpu, "ibm,segment-page-sizes", + 0x0c, 0x000, 3, 0x0c, 0x0000, /* 4K seg 4k pages */ + 0x10, 0x0007, /* 4K seg 64k pages */ + 0x18, 0x0038, /* 4K seg 16M pages */ + 0x10, 0x110, 2, 0x10, 0x0001, /* 64K seg 64k pages */ + 0x18, 0x0008, /* 64K seg 16M pages */ + 0x18, 0x100, 1, 0x18, 0x0000, /* 16M seg 16M pages */ + 0x22, 0x120, 1, 0x22, 0x0003); /* 16G seg 16G pages */ + + + if (pa_features) { + dt_add_property(cpu, "ibm,pa-features", + pa_features, pa_features_size); + } + dt_add_property_cells(cpu, "ibm,slb-size", 0x20); + + dt_add_property_cells(cpu, "ibm,vmx", 0x2); + dt_add_property_cells(cpu, "ibm,dfp", 0x2); + dt_add_property_cells(cpu, "ibm,purr", 0x1); + dt_add_property_cells(cpu, "ibm,spurr", 0x1); + + /* + * Do not create "clock-frequency" if the frequency doesn't + * fit in a single cell + */ + freq = ((uint64_t)be32_to_cpu(tb->actual_clock_speed)) * 1000000ul; + if (freq <= 0xfffffffful) + dt_add_property_cells(cpu, "clock-frequency", freq); + dt_add_property_u64(cpu, "ibm,extended-clock-frequency", freq); + + /* FIXME: Hardcoding is bad. */ + dt_add_property_cells(cpu, "timebase-frequency", 512000000); + dt_add_property_cells(cpu, "ibm,extended-timebase-frequency", + 0, 512000000); + + dt_add_property_cells(cpu, "reservation-granule-size", + be32_to_cpu(cache->reservation_size)); + + dt_add_property_cells(cpu, "d-tlb-size", + be32_to_cpu(cache->dtlb_entries)); + dt_add_property_cells(cpu, "i-tlb-size", + be32_to_cpu(cache->itlb_entries)); + /* Assume unified TLB */ + dt_add_property_cells(cpu, "tlb-size", + be32_to_cpu(cache->dtlb_entries)); + dt_add_property_cells(cpu, "d-tlb-sets", + be32_to_cpu(cache->dtlb_assoc_sets)); + dt_add_property_cells(cpu, "i-tlb-sets", + be32_to_cpu(cache->itlb_assoc_sets)); + dt_add_property_cells(cpu, "tlb-sets", + be32_to_cpu(cache->dtlb_assoc_sets)); + + dt_add_property_cells(cpu, "d-cache-block-size", + be32_to_cpu(cache->dcache_block_size)); + dt_add_property_cells(cpu, "i-cache-block-size", + be32_to_cpu(cache->icache_block_size)); + dt_add_property_cells(cpu, "d-cache-size", + be32_to_cpu(cache->l1_dcache_size_kb)*1024); + dt_add_property_cells(cpu, "i-cache-size", + be32_to_cpu(cache->icache_size_kb)*1024); + dt_add_property_cells(cpu, "i-cache-sets", + be32_to_cpu(cache->icache_assoc_sets)); + dt_add_property_cells(cpu, "d-cache-sets", + be32_to_cpu(cache->dcache_assoc_sets)); + + if (cache->icache_line_size != cache->icache_block_size) + dt_add_property_cells(cpu, "i-cache-line-size", + be32_to_cpu(cache->icache_line_size)); + if (cache->l1_dcache_line_size != cache->dcache_block_size) + dt_add_property_cells(cpu, "d-cache-line-size", + be32_to_cpu(cache->l1_dcache_line_size)); + return cpu; +} + +void add_core_attr(struct dt_node *cpu, uint32_t attr) +{ + if (attr & CPU_ATTR_UNIFIED_PL1) + dt_add_property(cpu, "cache-unified", NULL, 0); + if (attr & CPU_ATTR_SPLIT_TLB) + dt_add_property(cpu, "tlb-split", NULL, 0); + if (attr & CPU_ATTR_TLBIA) + dt_add_property(cpu, "tlbia", NULL, 0); + if (attr & CPU_ATTR_PERF_MONITOR) + dt_add_property_cells(cpu, "performance-monitor", 0, 1); + if (attr & CPU_ATTR_EXTERN_CONT) + dt_add_property(cpu, "external-control", NULL, 0); +} + +static struct dt_node *create_cache_node(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + const char *name, uint32_t unit_addr, + int okay) +{ + struct dt_node *node; + + node = dt_new_addr(cpus, name, unit_addr); + assert(node); + + dt_add_property_string(node, "device_type", "cache"); + dt_add_property_cells(node, "reg", unit_addr); + dt_add_property_string(node, "status", okay ? "okay" : "bad"); + dt_add_property(node, "cache-unified", NULL, 0); + + /* Assume cache associavitity sets is same for L2, L3 and L3.5 */ + dt_add_property_cells(node, "d-cache-sets", + be32_to_cpu(cache->l2_cache_assoc_sets)); + dt_add_property_cells(node, "i-cache-sets", + be32_to_cpu(cache->l2_cache_assoc_sets)); + + return node; +} + +static struct dt_node *l35_cache_node(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + uint32_t unit_addr, int okay) +{ + struct dt_node *node; + + node = create_cache_node(cpus, cache, "l35-cache", unit_addr, okay); + + dt_add_property_cells(node, "d-cache-size", + be32_to_cpu(cache->l35_dcache_size_kb) * 1024); + dt_add_property_cells(node, "i-cache-size", + be32_to_cpu(cache->l35_dcache_size_kb) * 1024); + + if (cache->icache_line_size != cache->icache_block_size) + dt_add_property_cells(node, "i-cache-line-size", + be32_to_cpu(cache->icache_line_size)); + if (cache->l35_cache_line_size != cache->dcache_block_size) + dt_add_property_cells(node, "d-cache-line-size", + be32_to_cpu(cache->l35_cache_line_size)); + + return node; +} + +static struct dt_node *l3_cache_node(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + uint32_t unit_addr, int okay) +{ + struct dt_node *node; + + node = create_cache_node(cpus, cache, "l3-cache", unit_addr, okay); + + dt_add_property_cells(node, "d-cache-size", + be32_to_cpu(cache->l3_dcache_size_kb) * 1024); + dt_add_property_cells(node, "i-cache-size", + be32_to_cpu(cache->l3_dcache_size_kb) * 1024); + + if (cache->icache_line_size != cache->icache_block_size) + dt_add_property_cells(node, "i-cache-line-size", + be32_to_cpu(cache->icache_line_size)); + if (cache->l3_line_size != cache->dcache_block_size) + dt_add_property_cells(node, "d-cache-line-size", + be32_to_cpu(cache->l3_line_size)); + + return node; +} + +static struct dt_node *l2_cache_node(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + uint32_t unit_addr, int okay) +{ + struct dt_node *node; + + node = create_cache_node(cpus, cache, "l2-cache", unit_addr, okay); + + dt_add_property_cells(node, "d-cache-size", + be32_to_cpu(cache->l2_dcache_size_kb) * 1024); + dt_add_property_cells(node, "i-cache-size", + be32_to_cpu(cache->l2_dcache_size_kb) * 1024); + + if (cache->icache_line_size != cache->icache_block_size) + dt_add_property_cells(node, "i-cache-line-size", + be32_to_cpu(cache->icache_line_size)); + if (cache->l2_line_size != cache->dcache_block_size) + dt_add_property_cells(node, "d-cache-line-size", + be32_to_cpu(cache->l2_line_size)); + + return node; +} + +static struct dt_node *find_l2_node(struct dt_node *cpus, u32 unit_addr) +{ + char name[32]; + + snprintf(name, sizeof(name), "l2-cache@%.08x", unit_addr); + return dt_find_by_name(cpus, name); +} + +uint32_t add_core_cache_info(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + uint32_t core_pir, int okay) +{ + struct dt_node *l2_node, *l3_node, *l35_node; + uint32_t unit_addr; + + /* + * On P9 the L2 is shared by pairs of SMT=4 cores. We only want + * to create a cache node for the first of these so we mask off + * the low PIR bits to get the unit address of the shared cache. + */ + if (proc_gen == proc_gen_p9) { + core_pir &= ~0x7; + + l2_node = find_l2_node(cpus, 0x20 << 24 | core_pir); + if (l2_node) + return l2_node->phandle; + } + + unit_addr = 0x20 << 24 | core_pir; + l2_node = l2_cache_node(cpus, cache, unit_addr, okay); + + unit_addr = 0x30 << 24 | core_pir; + l3_node = l3_cache_node(cpus, cache, unit_addr, okay); + + /* Represents the next level of cache in the memory hierarchy */ + dt_add_property_cells(l2_node, "l2-cache", l3_node->phandle); + + if (be32_to_cpu(cache->l35_dcache_size_kb)) { + unit_addr = 0x35 << 24 | core_pir; + l35_node = l35_cache_node(cpus, cache, unit_addr, okay); + dt_add_property_cells(l3_node, "l2-cache", l35_node->phandle); + } + + return l2_node->phandle; +} diff --git a/roms/skiboot/hdata/fsp.c b/roms/skiboot/hdata/fsp.c new file mode 100644 index 000000000..30cda53f6 --- /dev/null +++ b/roms/skiboot/hdata/fsp.c @@ -0,0 +1,560 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2017 IBM Corp. */ + +#include <device.h> +#include "spira.h" +#include <cpu.h> +#include <vpd.h> +#include <ccan/str/str.h> +#include <interrupts.h> +#include <inttypes.h> +#include <phys-map.h> +#include <chip.h> +#include <ipmi.h> + +#include "hdata.h" + +enum sp_type { + SP_BAD = 0, + SP_UNKNOWN, + SP_FSP, + SP_BMC, +}; + +static const char * const sp_names[] = { + "Broken", "Unknown", "FSP", "BMC", +}; + +static enum sp_type find_service_proc_type(const struct HDIF_common_hdr *spss, + int index) +{ + const struct spss_sp_impl *sp_impl; + int hw_ver, sw_ver, flags; + enum sp_type sp_type; + bool functional, installed; + + /* Find an check the SP Implementation structure */ + sp_impl = HDIF_get_idata(spss, SPSS_IDATA_SP_IMPL, NULL); + if (!CHECK_SPPTR(sp_impl)) { + prerror("SP #%d: SPSS/SP_Implementation not found !\n", index); + return SP_BAD; + } + + hw_ver = be16_to_cpu(sp_impl->hw_version); + sw_ver = be16_to_cpu(sp_impl->sw_version); + flags = be16_to_cpu(sp_impl->func_flags); + + switch (hw_ver) { + case 0x1: + case 0x2: /* We only support FSP2 */ + sp_type = SP_FSP; + break; + case 0x3: + sp_type = SP_BMC; + break; + default: + sp_type = SP_UNKNOWN; + } + + if (sp_type == SP_UNKNOWN) + return SP_UNKNOWN; + + installed = !!(flags & SPSS_SP_IMPL_FLAGS_INSTALLED); + functional = !!(flags & SPSS_SP_IMPL_FLAGS_FUNCTIONAL); + + if (!installed || !functional) { + prerror("%s #%d not usable: %sinstalled, %sfunctional\n", + sp_names[sp_type], index, + installed ? "" : "not ", + functional ? "" : "not "); + + return SP_BAD; + } + + prlog(PR_INFO, "%s #%d: HW version %d, SW version %d, chip DD%d.%d\n", + sp_names[sp_type], index, hw_ver, sw_ver, + sp_impl->chip_version >> 4, + sp_impl->chip_version & 0xf); + + return sp_type; +} + +/* + * Note on DT representation of the PSI links and FSPs: + * + * We create a XSCOM node for each PSI host bridge(one per chip), + * + * This is done in spira.c + * + * We do not create the /psi MMIO variant at this stage, it will + * be added by the psi driver in skiboot. + * + * We do not put the FSP(s) as children of these. Instead, we create + * a top-level /fsps node with the FSPs as children. + * + * Each FSP then has a "links" property which is an array of chip IDs + */ + +static struct dt_node *fsp_create_node(const void *spss, int i, + struct dt_node *parent) +{ + const struct spss_sp_impl *sp_impl; + struct dt_node *node; + + sp_impl = HDIF_get_idata(spss, SPSS_IDATA_SP_IMPL, NULL); + + node = dt_new_addr(parent, "fsp", i); + assert(node); + + dt_add_property_cells(node, "reg", i); + + if (be16_to_cpu(sp_impl->hw_version) == 1) { + dt_add_property_strings(node, "compatible", "ibm,fsp", + "ibm,fsp1"); + /* Offset into the FSP MMIO space where the mailbox + * registers are */ + /* seen in the FSP1 spec */ + dt_add_property_cells(node, "reg-offset", 0xb0016000); + } else if (be16_to_cpu(sp_impl->hw_version) == 2) { + dt_add_property_strings(node, "compatible", "ibm,fsp", + "ibm,fsp2"); + dt_add_property_cells(node, "reg-offset", 0xb0011000); + } + dt_add_property_cells(node, "hw-version", be16_to_cpu(sp_impl->hw_version)); + dt_add_property_cells(node, "sw-version", be16_to_cpu(sp_impl->sw_version)); + + if (be16_to_cpu(sp_impl->func_flags) & SPSS_SP_IMPL_FLAGS_PRIMARY) + dt_add_property(node, "primary", NULL, 0); + + return node; +} + +static uint32_t fsp_create_link(const struct spss_iopath *iopath, int index, + int fsp_index) +{ + struct dt_node *node; + const char *ststr; + bool current = false; + bool working = false; + uint32_t chip_id; + + switch(be16_to_cpu(iopath->psi.link_status)) { + case SPSS_IO_PATH_PSI_LINK_BAD_FRU: + ststr = "Broken"; + break; + case SPSS_IO_PATH_PSI_LINK_CURRENT: + ststr = "Active"; + current = working = true; + break; + case SPSS_IO_PATH_PSI_LINK_BACKUP: + ststr = "Backup"; + working = true; + break; + default: + ststr = "Unknown"; + } + prlog(PR_DEBUG, "FSP #%d: IO PATH %d is %s PSI Link, GXHB at %" PRIx64 "\n", + fsp_index, index, ststr, be64_to_cpu(iopath->psi.gxhb_base)); + + chip_id = pcid_to_chip_id(be32_to_cpu(iopath->psi.proc_chip_id)); + node = dt_find_compatible_node_on_chip(dt_root, NULL, "ibm,psihb-x", + chip_id); + if (!node) { + prerror("FSP #%d: Can't find psihb node for link %d\n", + fsp_index, index); + } else { + if (current) + dt_add_property(node, "boot-link", NULL, 0); + dt_add_property_strings(node, "status", working ? "ok" : "bad"); + } + + return chip_id; +} + +static void fsp_create_links(const void *spss, int index, + struct dt_node *fsp_node) +{ + __be32 *links = NULL; + unsigned int i, lp, lcount = 0; + int count; + + count = HDIF_get_iarray_size(spss, SPSS_IDATA_SP_IOPATH); + if (count < 0) { + prerror("FSP #%d: Can't find IO PATH array size !\n", index); + return; + } + prlog(PR_DEBUG, "FSP #%d: Found %d IO PATH\n", index, count); + + /* Iterate all links */ + for (i = 0; i < count; i++) { + const struct spss_iopath *iopath; + unsigned int iopath_sz; + uint32_t chip; + + iopath = HDIF_get_iarray_item(spss, SPSS_IDATA_SP_IOPATH, + i, &iopath_sz); + if (!CHECK_SPPTR(iopath)) { + prerror("FSP #%d: Can't find IO PATH %d\n", index, i); + break; + } + if (be16_to_cpu(iopath->iopath_type) != SPSS_IOPATH_TYPE_PSI) { + prerror("FSP #%d: Unsupported IO PATH %d type 0x%04x\n", + index, i, iopath->iopath_type); + continue; + } + + chip = fsp_create_link(iopath, i, index); + lp = lcount++; + links = realloc(links, 4 * lcount); + links[lp] = cpu_to_be32(chip); + } + if (links) + dt_add_property(fsp_node, "ibm,psi-links", links, lcount * 4); + + free(links); +} + +static struct dt_node *add_lpc_io_node(struct dt_node *parent, + const char *name, u32 offset, u32 size) +{ + struct dt_node *n; + char buffer[32]; + + /* + * LPC bus addresses have strange DT names, they have the + * Bus address space embedded into the unit address e.g. + * serial@i3f8 - refers to offset 0x3f8 in the IO space + */ + + snprintf(buffer, sizeof(buffer), "%s@i%x", name, offset); + n = dt_new(parent, buffer); + assert(n); + + /* first address cell of 1 indicates the LPC IO space */ + dt_add_property_cells(n, "reg", 1, offset, size); + + return n; +} + +static void add_uart(const struct spss_iopath *iopath, struct dt_node *lpc) +{ + struct dt_node *serial; + u64 base; + + /* XXX: The spec says this is supposed to be a MMIO address. + * However, in practice we get an LPC IO Space offset. + */ + base = be64_to_cpu(iopath->lpc.uart_base); + + serial = add_lpc_io_node(lpc, "serial", base, + be32_to_cpu(iopath->lpc.uart_size)); + + dt_add_property_string(serial, "compatible", "ns16550"); + + dt_add_property_cells(serial, "current-speed", + be32_to_cpu(iopath->lpc.uart_baud)); + dt_add_property_cells(serial, "clock-frequency", + be32_to_cpu(iopath->lpc.uart_clk)); + dt_add_property_cells(serial, "interrupts", + iopath->lpc.uart_int_number); + dt_add_property_string(serial, "device_type", "serial"); + + + prlog(PR_DEBUG, "LPC UART: base addr = %#" PRIx64" (%#" PRIx64 ") size = %#x clk = %u, baud = %u\n", + be64_to_cpu(iopath->lpc.uart_base), + base, + be32_to_cpu(iopath->lpc.uart_size), + be32_to_cpu(iopath->lpc.uart_clk), + be32_to_cpu(iopath->lpc.uart_baud)); +} + +static void add_chip_id_to_sensors(struct dt_node *sensor_node, uint32_t slca_index) +{ + unsigned int i; + const void *hdif; + const struct slca_entry *slca; + const struct spira_fru_id *fru_id; + const struct sppcrd_chip_info *cinfo; + + slca = slca_get_entry(slca_index); + if (slca == NULL) { + prlog(PR_WARNING, "SENSORS: Invalid slca index\n"); + return; + } + + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, SPPCRD_HDIF_SIG) { + fru_id = HDIF_get_idata(hdif, SPPCRD_IDATA_FRU_ID, NULL); + if (!fru_id) + return; + + if (fru_id->rsrc_id != slca->rsrc_id) + continue; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL); + if (!CHECK_SPPTR(cinfo)) { + prlog(PR_ERR, "SENSORS: Bad ChipID data %d\n", i); + return; + } + + dt_add_property_cells(sensor_node, + "ibm,chip-id", get_xscom_id(cinfo)); + return; + } +} + +static void add_ipmi_sensors(struct dt_node *bmc_node) +{ + int i; + const struct HDIF_common_hdr *hdif_sensor; + const struct ipmi_sensors *ipmi_sensors; + struct dt_node *sensors_node, *sensor_node; + + hdif_sensor = get_hdif(&spira.ntuples.ipmi_sensor, IPMI_SENSORS_HDIF_SIG); + if (!hdif_sensor) { + prlog(PR_DEBUG, "SENSORS: Missing IPMI sensors mappings tuple\n"); + return; + } + + ipmi_sensors = HDIF_get_idata(hdif_sensor, IPMI_SENSORS_IDATA_SENSORS, NULL); + if (!ipmi_sensors) { + prlog(PR_DEBUG, "SENSORS: bad data\n"); + return; + } + + sensors_node = dt_new(bmc_node, "sensors"); + assert(sensors_node); + + dt_add_property_cells(sensors_node, "#address-cells", 1); + dt_add_property_cells(sensors_node, "#size-cells", 0); + + for (i = 0; i < be32_to_cpu(ipmi_sensors->count); i++) { + if(dt_find_by_name_addr(sensors_node, "sensor", + ipmi_sensors->data[i].id)) { + prlog(PR_WARNING, "SENSORS: Duplicate sensor ID : %x\n", + ipmi_sensors->data[i].id); + continue; + } + + /* We support only < MAX_IPMI_SENSORS sensors */ + if (!(ipmi_sensors->data[i].type < MAX_IPMI_SENSORS)) + continue; + + sensor_node = dt_new_addr(sensors_node, "sensor", + ipmi_sensors->data[i].id); + assert(sensor_node); + dt_add_property_string(sensor_node, "compatible", "ibm,ipmi-sensor"); + dt_add_property_cells(sensor_node, "reg", ipmi_sensors->data[i].id); + dt_add_property_cells(sensor_node, "ipmi-sensor-type", + ipmi_sensors->data[i].type); + + add_chip_id_to_sensors(sensor_node, + be32_to_cpu(ipmi_sensors->data[i].slca_index)); + } +} + +static void bmc_create_node(const struct HDIF_common_hdr *sp) +{ + struct dt_node *bmc_node; + u32 fw_bar, io_bar, mem_bar, internal_bar, mctp_base; + const struct spss_iopath *iopath; + const struct spss_sp_impl *sp_impl; + struct dt_node *lpcm, *lpc, *n; + u64 lpcm_base, lpcm_end; + uint32_t chip_id; + uint32_t topology_idx; + int size; + + bmc_node = dt_new(dt_root, "bmc"); + assert(bmc_node); + + dt_add_property_cells(bmc_node, "#address-cells", 1); + dt_add_property_cells(bmc_node, "#size-cells", 0); + + /* Add sensor info under /bmc */ + if (proc_gen < proc_gen_p10) + add_ipmi_sensors(bmc_node); + + sp_impl = HDIF_get_idata(sp, SPSS_IDATA_SP_IMPL, &size); + if (CHECK_SPPTR(sp_impl) && (size > 8)) { + dt_add_property_strings(bmc_node, "compatible", sp_impl->sp_family); + prlog(PR_INFO, "SP Family is %s\n", sp_impl->sp_family); + } + + iopath = HDIF_get_iarray_item(sp, SPSS_IDATA_SP_IOPATH, 0, NULL); + + if (be16_to_cpu(iopath->iopath_type) != SPSS_IOPATH_TYPE_LPC) { + prerror("BMC: Non-LPC IOPATH, this is probably broken\n"); + return; + } + + /* + * For now we only instantiate the LPC node for the LPC that is used + * for Host <-> BMC comms. The secondary LPCs can be skipped. + */ + if (be16_to_cpu(iopath->lpc.link_status) != LPC_STATUS_ACTIVE) + return; + +#define GB (1024ul * 1024ul * 1024ul) + /* + * convert the hdat chip ID the HW chip id so we get the right + * phys map offset + */ + chip_id = pcid_to_chip_id(be32_to_cpu(iopath->lpc.chip_id)); + topology_idx = pcid_to_topology_idx(be32_to_cpu(iopath->lpc.chip_id)); + + __phys_map_get(topology_idx, chip_id, LPC_BUS, 0, &lpcm_base, NULL); + lpcm = dt_new_addr(dt_root, "lpcm-opb", lpcm_base); + assert(lpcm); + + dt_add_property_cells(lpcm, "#address-cells", 1); + dt_add_property_cells(lpcm, "#size-cells", 1); + dt_add_property_strings(lpcm, "compatible", + "ibm,power9-lpcm-opb", "simple-bus"); + dt_add_property_u64s(lpcm, "reg", lpcm_base, 0x100000000ul); + + dt_add_property_cells(lpcm, "ibm,chip-id", chip_id); + + /* Setup the ranges for the MMIO LPC */ + lpcm_end = lpcm_base + 2 * GB; + dt_add_property_cells(lpcm, "ranges", + 0x00000000, hi32(lpcm_base), lo32(lpcm_base), 2 * GB, + 0x80000000, hi32(lpcm_end), lo32(lpcm_end), 2 * GB); + + /* + * Despite the name the "BAR" values provided through the HDAT are + * the base addresses themselves rather than the BARs + */ + fw_bar = be32_to_cpu(iopath->lpc.firmware_bar); + mem_bar = be32_to_cpu(iopath->lpc.memory_bar); + io_bar = be32_to_cpu(iopath->lpc.io_bar); + internal_bar = be32_to_cpu(iopath->lpc.internal_bar); + mctp_base = be32_to_cpu(iopath->lpc.mctp_base); + + prlog(PR_DEBUG, "LPC: IOPATH chip id = %x\n", chip_id); + prlog(PR_DEBUG, "LPC: FW BAR = %#x\n", fw_bar); + prlog(PR_DEBUG, "LPC: MEM BAR = %#x\n", mem_bar); + prlog(PR_DEBUG, "LPC: IO BAR = %#x\n", io_bar); + prlog(PR_DEBUG, "LPC: Internal BAR = %#x\n", internal_bar); + if (proc_gen >= proc_gen_p10) { + /* MCTP is part of FW BAR */ + prlog(PR_DEBUG, "LPC: MCTP base = %#x\n", mctp_base); + } + + /* + * The internal address space BAR actually points to the LPC master + * registers. So we "fix" it by masking off the low bits. + * + * XXX: we probably need separate base addresses for all these things + */ + internal_bar &= 0xf0000000; + + /* Add the various internal bus devices */ + n = dt_new_addr(lpcm, "opb-master", internal_bar + 0x10000); + dt_add_property_string(n, "compatible", "ibm,power9-lpcm-opb-master"); + dt_add_property_cells(n, "reg", internal_bar + 0x10000, 0x60); + + n = dt_new_addr(lpcm, "opb-arbiter", internal_bar + 0x11000); + dt_add_property_string(n, "compatible", "ibm,power9-lpcm-opb-arbiter"); + dt_add_property_cells(n, "reg", internal_bar + 0x11000, 0x8); + + n = dt_new_addr(lpcm, "lpc-controller", internal_bar + 0x12000); + dt_add_property_string(n, "compatible", "ibm,power9-lpc-controller"); + dt_add_property_cells(n, "reg", internal_bar + 0x12000, 0x100); + + /* + * FIXME: lpc@0 might not be accurate, but i'm pretty sure + * lpc@f0000000 isn't right either. + */ + lpc = dt_new_addr(lpcm, "lpc", 0x0); + dt_add_property_cells(lpc, "#address-cells", 2); + dt_add_property_cells(lpc, "#size-cells", 1); + dt_add_property_strings(lpc, "compatible", + "ibm,power9-lpc", "ibm,power8-lpc"); + + dt_add_property_cells(lpc, "ranges", + 0, 0, mem_bar, 0x10000000, /* MEM space */ + 1, 0, io_bar, 0x00010000, /* IO space */ + /* we don't expose the internal space */ + 3, 0, fw_bar, 0x10000000 /* FW space */ + ); + + add_uart(iopath, lpc); + + /* BT device info isn't currently populated */ + prlog(PR_DEBUG, "LPC: BT [%#"PRIx64", %#x] sms_int: %u, bmc_int: %u\n", + iopath->lpc.bt_base, iopath->lpc.bt_size, + iopath->lpc.bt_sms_int_num, iopath->lpc.bt_bmc_response_int_num + ); +} + +/* + * Search for and instanciate BMC nodes. This is mostly the same as fsp_parse() + * below, but it can be called earlier since BMCs don't depend on the psihb + * nodes being added. + */ +void bmc_parse(void) +{ + bool found = false; + const void *sp; + int i; + + sp = get_hdif(&spira.ntuples.sp_subsys, SPSS_HDIF_SIG); + if (!sp) + return; + + for_each_ntuple_idx(&spira.ntuples.sp_subsys, sp, i, SPSS_HDIF_SIG) { + if (find_service_proc_type(sp, i) == SP_BMC) { + bmc_create_node(sp); + found = true; + } + } + + if (found) + early_uart_init(); +} + +void fsp_parse(void) +{ + struct dt_node *fsp_root = NULL, *fsp_node; + const void *sp; + int index; + + /* Find SPSS tuple in SPIRA */ + sp = get_hdif(&spira.ntuples.sp_subsys, SPSS_HDIF_SIG); + if (!sp) { + prlog(PR_WARNING, "HDAT: No FSP/BMC found!\n"); + return; + } + + for_each_ntuple_idx(&spira.ntuples.sp_subsys, sp, index, SPSS_HDIF_SIG) { + switch (find_service_proc_type(sp, index)) { + case SP_FSP: + if (!fsp_root) { + fsp_root = dt_new(dt_root, "fsps"); + assert(fsp_root); + + dt_add_property_cells(fsp_root, + "#address-cells", 1); + dt_add_property_cells(fsp_root, + "#size-cells", 0); + } + + fsp_node = fsp_create_node(sp, index, fsp_root); + if (fsp_node) + fsp_create_links(sp, index, fsp_node); + + break; + + case SP_BMC: + /* Handled above */ + break; + + case SP_BAD: + break; + + default: + prerror("SP #%d: This service processor is not supported\n", index); + break; + } + } +} diff --git a/roms/skiboot/hdata/hdata.h b/roms/skiboot/hdata/hdata.h new file mode 100644 index 000000000..6aad82932 --- /dev/null +++ b/roms/skiboot/hdata/hdata.h @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2018 IBM Corp. */ + +#ifndef __HDATA_H +#define __HDATA_H + +#include <processor.h> +#include "hdif.h" +#include "spira.h" + +struct dt_node; + +extern void memory_parse(void); +extern bool pcia_parse(void); +extern void fsp_parse(void); +extern void bmc_parse(void); +extern void io_parse(void); +extern void dt_init_vpd_node(void); +extern struct dt_node *dt_add_vpd_node(const struct HDIF_common_hdr *hdr, + int indx_fru, int indx_vpd); +extern void vpd_parse(void); +extern void vpd_data_parse(struct dt_node *node, + const void *fruvpd, u32 fruvpd_sz); + +extern struct dt_node *find_xscom_for_chip(uint32_t chip_id); +extern uint32_t pcid_to_chip_id(uint32_t proc_chip_id); +extern uint32_t pcid_to_topology_idx(uint32_t proc_chip_id); +extern uint32_t get_xscom_id(const struct sppcrd_chip_info *cinfo); + +extern struct dt_node *add_core_common(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + const struct sppcia_cpu_timebase *tb, + uint32_t int_server, bool okay); +extern void add_core_attr(struct dt_node *cpu, uint32_t attr); +extern uint32_t add_core_cache_info(struct dt_node *cpus, + const struct sppcia_cpu_cache *cache, + uint32_t int_server, int okay); +extern const struct slca_entry *slca_get_entry(uint16_t slca_index); +extern const char *slca_get_vpd_name(uint16_t slca_index); +extern const char *slca_get_loc_code_index(uint16_t slca_index); +extern void slca_vpd_add_loc_code(struct dt_node *node, uint16_t slca_index); +extern void slca_dt_add_sai_node(void); +extern void dt_add_proc_vendor(struct dt_node *proc_node, + const void *mvpd, unsigned int mvpd_sz); + +extern bool hservices_from_hdat(const void *fdt, size_t size); +int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index, + struct dt_node *xscom); +extern void node_stb_parse(void); + +/* used to look up the device-tree node representing a slot */ +struct dt_node *find_slot_entry_node(struct dt_node *root, u32 entry_id); + +#endif /* __HDATA_H */ + diff --git a/roms/skiboot/hdata/hdif.c b/roms/skiboot/hdata/hdif.c new file mode 100644 index 000000000..2dfa94cf6 --- /dev/null +++ b/roms/skiboot/hdata/hdif.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2017 IBM Corp. */ + +#include "hdif.h" +#include <stack.h> + +const void *HDIF_get_idata(const struct HDIF_common_hdr *hdif, unsigned int di, + unsigned int *size) +{ + const struct HDIF_common_hdr *hdr = hdif; + const struct HDIF_idata_ptr *iptr; + + if (be16_to_cpu(hdr->d1f0) != 0xd1f0) { + prerror("HDIF: Bad header format !\n"); + backtrace(); + return NULL; + } + + if (di >= be16_to_cpu(hdr->idptr_count)) { + prlog(PR_DEBUG, "HDIF: idata %d out of range for %.6s!\n", + di, hdr->id); + return NULL; + } + + iptr = (void *)hdif + be32_to_cpu(hdr->idptr_off) + + di * sizeof(struct HDIF_idata_ptr); + + if (size) + *size = be32_to_cpu(iptr->size); + + return (void *)hdif + be32_to_cpu(iptr->offset); +} + +const void *HDIF_get_iarray_item(const struct HDIF_common_hdr *hdif, + unsigned int di, unsigned int ai, + unsigned int *size) +{ + const struct HDIF_array_hdr *ahdr; + unsigned int asize; + const void *arr; + + arr = HDIF_get_idata(hdif, di, &asize); + if (!arr) + return NULL; + + if (asize < sizeof(struct HDIF_array_hdr)) { + prerror("HDIF: idata block too small for array !\n"); + backtrace(); + return NULL; + } + + ahdr = arr; + + if (ai >= be32_to_cpu(ahdr->ecnt)) { + prerror("HDIF: idata array index out of range !\n"); + backtrace(); + return NULL; + } + + if (size) + *size = be32_to_cpu(ahdr->eactsz); + + return arr + be32_to_cpu(ahdr->offset) + ai * be32_to_cpu(ahdr->esize); +} + +int HDIF_get_iarray_size(const struct HDIF_common_hdr *hdif, unsigned int di) +{ + const struct HDIF_array_hdr *ahdr; + unsigned int asize; + const void *arr; + + arr = HDIF_get_idata(hdif, di, &asize); + if (!arr) + return -1; + + if (asize < sizeof(struct HDIF_array_hdr)) { + prerror("HDIF: idata block too small for array !\n"); + backtrace(); + return -1; + } + + ahdr = arr; + return be32_to_cpu(ahdr->ecnt); +} + +/* + * Returns NULL and sets *items to zero when: + * + * a) Array extends beyond bounds (hard error) + * b) The array is empty (soft error) + * c) The item size is zero (soft error) + * d) The array is missing (soft error) + * + * b, c) are bugs in the input data so they generate backtraces. + * + * If you care about the soft error cases, retrive the array header manually + * with HDIF_get_idata(). + */ +const struct HDIF_array_hdr *HDIF_get_iarray(const struct HDIF_common_hdr *hdif, + unsigned int di, unsigned int *items) +{ + const struct HDIF_array_hdr *arr; + unsigned int req_size, size, elements; + unsigned int actual_sz, alloc_sz, offset; + + arr = HDIF_get_idata(hdif, di, &size); + + if(items) + *items = 0; + + if (!arr || !size) + return NULL; + + /* base size of an Idata array header */ + offset = be32_to_cpu(arr->offset); + actual_sz = be32_to_cpu(arr->eactsz); + alloc_sz = be32_to_cpu(arr->esize); + elements = be32_to_cpu(arr->ecnt); + + /* actual size should always be smaller than allocated */ + if (alloc_sz < actual_sz) { + prerror("HDIF %.6s iarray %u has actsz (%u) < alloc_sz (%u)\n)", + hdif->id, di, actual_sz, alloc_sz); + backtrace(); + return NULL; + } + + req_size = elements * alloc_sz + offset; + if (req_size > size) { + prerror("HDIF: %.6s iarray %u requires %#x bytes, but only %#x are allocated!\n", + hdif->id, di, req_size, size); + backtrace(); + return NULL; + } + + if (!elements || !actual_sz) + return NULL; + + if (items) + *items = elements; + + return arr; +} + +const void *HDIF_iarray_item(const struct HDIF_array_hdr *ahdr, + unsigned int index) +{ + if (!ahdr || index >= be32_to_cpu(ahdr->ecnt)) + return NULL; + + return (const void * )ahdr + be32_to_cpu(ahdr->offset) + + index * be32_to_cpu(ahdr->esize); +} + +struct HDIF_child_ptr * +HDIF_child_arr(const struct HDIF_common_hdr *hdif, unsigned int idx) +{ + struct HDIF_child_ptr *children; + + children = (void *)hdif + be32_to_cpu(hdif->child_off); + + if (idx >= be16_to_cpu(hdif->child_count)) { + prerror("HDIF: child array idx out of range!\n"); + backtrace(); + return NULL; + } + + return &children[idx]; +} + +struct HDIF_common_hdr *HDIF_child(const struct HDIF_common_hdr *hdif, + const struct HDIF_child_ptr *child, + unsigned int idx, + const char *eyecatcher) +{ + void *base = (void *)hdif; + struct HDIF_common_hdr *ret; + long child_off; + + /* child must be in hdif's child array */ + child_off = (void *)child - (base + be32_to_cpu(hdif->child_off)); + assert(child_off % sizeof(struct HDIF_child_ptr) == 0); + assert(child_off / sizeof(struct HDIF_child_ptr) + < be16_to_cpu(hdif->child_count)); + + assert(idx < be32_to_cpu(child->count)); + + if (be32_to_cpu(child->size) < sizeof(struct HDIF_common_hdr)) { + prerror("HDIF: %s child #%i too small: %u\n", + eyecatcher, idx, be32_to_cpu(child->size)); + backtrace(); + return NULL; + } + + ret = base + be32_to_cpu(child->offset) + + be32_to_cpu(child->size) * idx; + if (!HDIF_check(ret, eyecatcher)) { + prerror("HDIF: #%i bad type (wanted %6s, got %6s)\n", + idx, eyecatcher, ret->id); + backtrace(); + return NULL; + } + + return ret; +} diff --git a/roms/skiboot/hdata/hdif.h b/roms/skiboot/hdata/hdif.h new file mode 100644 index 000000000..52df0f16d --- /dev/null +++ b/roms/skiboot/hdata/hdif.h @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2017 IBM Corp. */ + +#ifndef __HDIF_H +#define __HDIF_H + +#include <skiboot.h> +#include <types.h> +#include <ccan/endian/endian.h> + +struct HDIF_common_hdr { + __be16 d1f0; /* 0xd1f0 */ + char id[6]; /* eye catcher string */ + __be16 instnum; /* instance number */ + __be16 version; /* version */ + __be32 total_len; /* total structure length */ + __be32 hdr_len; /* header length (currently 0x20) */ + __be32 idptr_off; /* offset to idata pointers */ + __be16 idptr_count; /* number of idata pointers */ + __be16 child_count; /* number of child structures */ + __be32 child_off; /* offset to child structures array */ +} __packed __align(0x10); + +struct HDIF_idata_ptr { + __be32 offset; + __be32 size; +} __packed __align(0x8); + +struct HDIF_array_hdr { + __be32 offset; + __be32 ecnt; + __be32 esize; + __be32 eactsz; +} __packed __align(0x4); + +struct HDIF_child_ptr { + __be32 offset; + __be32 size; + __be32 count; +} __packed; + +#define HDIF_HDR_LEN (sizeof(struct HDIF_common_hdr)) +#define HDIF_ARRAY_OFFSET (sizeof(struct HDIF_array_hdr)) + +#define HDIF_ID(_id) .d1f0 = CPU_TO_BE16(0xd1f0), .id = _id + +#define HDIF_SIMPLE_HDR(id, vers, type) \ +{ \ + HDIF_ID(id), \ + .instnum = CPU_TO_BE16(0), \ + .version = CPU_TO_BE16(vers), \ + .total_len = CPU_TO_BE32(sizeof(type)), \ + .hdr_len = CPU_TO_BE32(HDIF_HDR_LEN), \ + .idptr_off = CPU_TO_BE32(HDIF_HDR_LEN), \ + .idptr_count = CPU_TO_BE16(1), \ + .child_count = CPU_TO_BE16(0), \ + .child_off = CPU_TO_BE32(0), \ +} + +#define HDIF_IDATA_PTR(_offset, _size) \ +{ \ + .offset = CPU_TO_BE32(_offset), \ + .size = CPU_TO_BE32(_size), \ +} + +static inline bool HDIF_check(const void *hdif, const char id[]) +{ + const struct HDIF_common_hdr *hdr = hdif; + + return hdr->d1f0 == CPU_TO_BE16(0xd1f0) && + memcmp(hdr->id, id, sizeof(hdr->id)) == 0; +} + +/* HDIF_get_idata - Get a pointer to internal data block + * + * @hdif : HDIF structure pointer + * @di : Index of the idata pointer + * @size : Return the data size (or NULL if ignored) + */ +extern const void *HDIF_get_idata(const struct HDIF_common_hdr *hdif, + unsigned int di, + unsigned int *size); + +/* HDIF_get_iarray - Get a pointer to an elemnt of an internal data array + * + * @hdif : HDIF structure pointer + * @di : Index of the idata pointer + * @ai : Index in the resulting array + * @size : Return the entry actual size (or NULL if ignored) + */ +extern const void *HDIF_get_iarray_item(const struct HDIF_common_hdr *hdif, + unsigned int di, + unsigned int ai, unsigned int *size); + +/* HDIF_get_iarray - Get a pointer to an internal array header + * + * @hdif : HDIF structure pointer + * @di : Index of the idata pointer + * @ai : Index in the resulting array + * @size : Return the entry actual size (or NULL if ignored) + */ +extern const struct HDIF_array_hdr *HDIF_get_iarray( + const struct HDIF_common_hdr *hdif, unsigned int di, + unsigned int *items); + +extern const void *HDIF_iarray_item(const struct HDIF_array_hdr *hdif, + unsigned int index); + +#define HDIF_iarray_for_each(arr, idx, ptr) \ + for (idx = 0, ptr = HDIF_iarray_item(arr, idx); \ + ptr; idx++, ptr = HDIF_iarray_item(arr, idx)) + +/* HDIF_get_iarray_size - Get the number of elements of an internal data array + * + * @hdif : HDIF structure pointer + * @di : Index of the idata pointer + * + * A negative result means an error + */ +extern int HDIF_get_iarray_size(const struct HDIF_common_hdr *hdif, + unsigned int di); + +/* HDIF_child_arr - Get a child array from this HDIF. + * + * @hdif : HDIF structure pointer + * @idx : the child to get + * + * NULL means an error (not that many children). + */ +extern struct HDIF_child_ptr * +HDIF_child_arr(const struct HDIF_common_hdr *hdif, unsigned int idx); + +/* HDIF_child - Deref a child_ptr entry. + * + * @hdif : HDIF structure pointer + * @child : the child returned from HDIF_child_arr + * @idx : the index of the child to get (< child->count). + * @eyecatcher: the 6-char ID expected for this child. + * + * NULL means an error. + */ +extern struct HDIF_common_hdr *HDIF_child(const struct HDIF_common_hdr *hdif, + const struct HDIF_child_ptr *child, + unsigned int idx, + const char *eyecatcher); +#endif /* __HDIF_H */ diff --git a/roms/skiboot/hdata/hostservices.c b/roms/skiboot/hdata/hostservices.c new file mode 100644 index 000000000..2181ecd8b --- /dev/null +++ b/roms/skiboot/hdata/hostservices.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2017 IBM Corp. */ + +#include <stdint.h> +#include <stdlib.h> +#include <stdio.h> + +#include <libfdt/libfdt.h> +#include <skiboot.h> +#include <device.h> +#include <compiler.h> +#include <hostservices.h> + +#include "spira.h" +#include "hdata.h" + +static void merge_property(const struct dt_node *src_root, + struct dt_node *dst_root, + const char *name) +{ + const struct dt_property *src; + struct dt_property *dst; + + /* Nothing to merge if old one doesn't exist. */ + src = dt_find_property(src_root, name); + if (!src) + return; + + /* Just create a new one if there's none in dst. */ + dst = __dt_find_property(dst_root, name); + if (!dst) { + dt_add_property(dst_root, name, src->prop, src->len); + return; + } + + /* Append src to dst. */ + dt_resize_property(&dst, dst->len + src->len); + memcpy(dst->prop + dst->len, src->prop, src->len); +} + +static void hservice_parse_dt_tree(const struct dt_node *src) +{ + const struct dt_property *sprop; + + /* Copy/merge reserved names & ranges properties. */ + list_for_each(&src->properties, sprop, list) { + if (streq(sprop->name, "reserved-names") || + streq(sprop->name, "reserved-ranges") || + streq(sprop->name, "ibm,enabled-idle-states")) + merge_property(src, dt_root, sprop->name); + } +} + +/* Get host services information from hdat. */ +bool hservices_from_hdat(const void *fdt, size_t size) +{ + int err; + struct dt_node *hservices; + + prlog(PR_DEBUG, "HBRT: Found mini-DT at 0x%p size: 0x%08lx\n", + fdt, size); + + /* For diagnostic purposes, we copy the whole blob over */ + dt_add_property(dt_root, "ibm,hbrt-mini-fdt", fdt, size); + + /* Parse & extract relevant properties */ + err = fdt_check_header(fdt); + if (err) { + prerror("HBRT: fdt blob %p hdr error %d\n", fdt, err); + return false; + } + + hservices = dt_new_root("ibm,hostservices"); + err = dt_expand_node(hservices, fdt, 0); + if (err < 0) { + prerror("HBRT: fdt blob %p parse error %d\n", fdt, err); + return false; + } + + hservice_parse_dt_tree(hservices); + dt_free(hservices); + return true; +} + diff --git a/roms/skiboot/hdata/i2c.c b/roms/skiboot/hdata/i2c.c new file mode 100644 index 000000000..7d5d655a5 --- /dev/null +++ b/roms/skiboot/hdata/i2c.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2017-2019 IBM Corp. */ + +#include <device.h> +#include <cpu.h> +#include <vpd.h> +#include <interrupts.h> +#include <ccan/str/str.h> +#include <chip.h> +#include <i2c.h> + +#include "spira.h" +#include "hdata.h" + +/* + * These should probably be in hw/p8-i2c.c. However, that would require the HDAT + * test to #include hw/p8-i2c.c which is probably going to be more trouble than + * it's worth. So these helpers are here instead. + */ +struct dt_node *p8_i2c_add_master_node(struct dt_node *xscom, int eng_id) +{ + uint64_t clk, size, xscom_base; + struct dt_node *i2cm; + + dt_for_each_compatible(xscom, i2cm, "ibm,power8-i2cm") + if (dt_prop_get_u32(i2cm, "chip-engine#") == eng_id) + return i2cm; + + /* XXX: Might need to be updated for new chips */ + if (proc_gen >= proc_gen_p9) + size = 0x1000; + else + size = 0x20; + + xscom_base = 0xa0000 + size * eng_id; + + i2cm = dt_new_addr(xscom, "i2cm", xscom_base); + if (!i2cm) + return NULL; + + if (proc_gen >= proc_gen_p9) { + dt_add_property_strings(i2cm, "compatible", "ibm,power8-i2cm", + "ibm,power9-i2cm"); + } else { + dt_add_property_strings(i2cm, "compatible", "ibm,power8-i2cm"); + } + + dt_add_property_cells(i2cm, "reg", xscom_base, size); + dt_add_property_cells(i2cm, "#size-cells", 0); + dt_add_property_cells(i2cm, "#address-cells", 1); + dt_add_property_cells(i2cm, "chip-engine#", eng_id); + + /* + * The i2cm runs at 1/4th the PIB frequency. If we don't know the PIB + * frequency then pick 150MHz which should be in the right ballpark. + */ + clk = dt_prop_get_u64_def(xscom, "bus-frequency", 0); + if (clk) + dt_add_property_cells(i2cm, "clock-frequency", clk / 4); + else + dt_add_property_cells(i2cm, "clock-frequency", 150000000); + + return i2cm; +} + +struct dt_node *__p8_i2c_add_port_node(struct dt_node *master, int port_id, + uint32_t bus_speed) +{ + struct dt_node *port; + uint32_t speed; + + dt_for_each_child(master, port) + if (dt_prop_get_u32(port, "reg") == port_id) + goto check_speed; + + port = dt_new_addr(master, "i2c-bus", port_id); + if (!port) + return NULL; + + dt_add_property_cells(port, "reg", port_id); + dt_add_property_cells(port, "#size-cells", 0); + dt_add_property_cells(port, "#address-cells", 1); + + /* The P9 I2C master is fully compatible with the P8 one */ + if (proc_gen >= proc_gen_p9) { + dt_add_property_strings(port, "compatible", "ibm,opal-i2c", + "ibm,power8-i2c-port", "ibm,power9-i2c-port"); + } else { + dt_add_property_strings(port, "compatible", "ibm,opal-i2c", + "ibm,power8-i2c-port"); + } + +check_speed: + speed = dt_prop_get_u32_def(port, "bus-frequency", 0xffffffff); + if (bus_speed < speed) { + dt_check_del_prop(port, "bus-frequency"); + dt_add_property_cells(port, "bus-frequency", bus_speed); + } + + return port; +} + + +struct dt_node *p8_i2c_add_port_node(struct dt_node *xscom, int eng_id, + int port_id, uint32_t bus_freq) +{ + struct dt_node *i2cm; + + i2cm = p8_i2c_add_master_node(xscom, eng_id); + if (!i2cm) + return NULL; + + return __p8_i2c_add_port_node(i2cm, port_id, bus_freq); +} + +struct i2c_dev { + uint8_t i2cm_engine; + uint8_t i2cm_port; + __be16 i2c_bus_freq; + + /* i2c slave info */ + uint8_t type; + uint8_t dev_addr; + uint8_t dev_port; + uint8_t __reserved; + + __be32 purpose; + __be32 i2c_link; + __be16 slca_index; +}; + +struct hdat_i2c_type { + uint32_t id; + const char *name; + const char *compat; +}; + +static struct hdat_i2c_type hdat_i2c_devs[] = { + { 0x1, "gpio", "nxp,pca9551" }, + /* XXX: Please verify that all VPD EEPROMs are of this type */ + { 0x2, "eeprom", "atmel,24c128" }, + { 0x3, "tpm", "nuvoton,npct650" }, + { 0x4, "i2c", NULL }, /* MEX-FPGA */ + { 0x5, "i2c", NULL }, /* UCX90xx devs for PCI Hotplug */ + { 0x6, "gpio", "nxp,pca9552" }, + { 0x7, "gpio", "nxp,pca9553" }, + { 0x8, "gpio", "nxp,pca9554" }, + { 0x9, "gpio", "nxp,pca9555" }, + { 0xa, "i2c", NULL }, /* SMP/OpenCAPI Cable */ + { 0xb, "eeprom", "atmel,24c256" }, + { 0xc, "i2c", NULL }, /* Thermal Sensor */ + { 0xd, "eeprom", "atmel,24c04" }, + { 0xe, "eeprom", "atmel,24c512" }, + { 0xf, "eeprom", "atmel,24c32" }, + { 0x10, "eeprom", "atmel,24c64" }, + { 0x11, "eeprom", "atmel,24c16" }, + { 0x12, "i2c", NULL }, /* NVDIA GPU */ + { 0x13, "i2c", "nxp,lpc11u35" }, +}; + +struct hdat_i2c_info { + uint32_t id; + bool allowed; /* true if the host may use the device */ + const char *label; +}; + +static struct hdat_i2c_info hdat_i2c_extra_info[] = { + { 0x1, false, "led-controller" }, + { 0x2, false, "pci-hotplug-pgood" }, + { 0x3, false, "pci-hotplug-control" }, + { 0x4, true, "tpm" }, + { 0x5, true, "module-vpd" }, + { 0x6, true, "dimm-spd" }, + { 0x7, true, "proc-vpd" }, + { 0x8, false, "sbe-eeprom"}, + { 0x9, true, "planar-vpd" }, + { 0xa, false, "opencapi-topology" }, + { 0xb, false, "opencapi-micro-reset" }, + { 0xc, false, "nvlink-cable" }, + { 0xd, false, "secure-window-open" }, + { 0xe, false, "physical-presence" }, + { 0xf, false, "mex-fpga" }, + { 0x10, false, "thermal-sensor" }, + { 0x11, false, "host-i2c-enable" }, + { 0x12, false, "gpu-config" }, +}; + +/* + * this is pretty half-assed, to generate the labels properly we need to look + * up associated SLCA index and determine what kind of module the device is on + * and why + */ +static struct hdat_i2c_type *map_type(uint32_t type) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hdat_i2c_devs); i++) + if (hdat_i2c_devs[i].id == type) + return &hdat_i2c_devs[i]; + + return NULL; +} + +static struct hdat_i2c_info *get_info(uint32_t type) +{ + static struct hdat_i2c_info no_info = + { .id = 0x0, .allowed = false, .label = "" }; + int i; + + for (i = 0; i < ARRAY_SIZE(hdat_i2c_extra_info); i++) + if (hdat_i2c_extra_info[i].id == type) + return &hdat_i2c_extra_info[i]; + + return &no_info; +} + +static bool is_zeros(const void *p, size_t size) +{ + const char *c = p; + size_t i; + + for (i = 0; i < size; i++) + if (c[i] != 0) + return false; + + return true; +} + +struct host_i2c_hdr { + const struct HDIF_array_hdr hdr; + __be32 version; +} __packed __align(0x4); + +int parse_i2c_devs(const struct HDIF_common_hdr *hdr, int idata_index, + struct dt_node *xscom) +{ + struct dt_node *bus, *node; + const struct hdat_i2c_type *type; + const struct hdat_i2c_info *info; + const struct i2c_dev *dev; + const char *name, *compat; + const struct host_i2c_hdr *ahdr; + uint32_t dev_addr; + uint32_t version; + uint32_t size; + uint32_t purpose; + int i, count; + + /* + * This code makes a few assumptions about XSCOM addrs, etc + * and will need updating for new processors + */ + assert(proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10); + + /* + * Emit an error if we get a newer version. This is an interim measure + * until the new version format is finalised. + */ + ahdr = HDIF_get_idata(hdr, idata_index, &size); + if (!ahdr || !size) + return -1; + + /* + * Some hostboots don't correctly fill the version field. On these + * the offset from the start of the header to the start of the array + * is 16 bytes. + */ + if (be32_to_cpu(ahdr->hdr.offset) == 16) { + version = 1; + prerror("I2C: HDAT device array has no version! Assuming v1\n"); + } else { + version = be32_to_cpu(ahdr->version); + } + + if (version == 2) { + prlog(PR_INFO, "I2C: v%d found, but not supported. Parsing as v1\n", + version); + } else if (version > 2) { + prerror("I2C: v%d found, but not supported! THIS IS A BUG\n", + version); + return -1; + } + + count = HDIF_get_iarray_size(hdr, idata_index); + for (i = 0; i < count; i++) { + dev = HDIF_get_iarray_item(hdr, idata_index, i, &size); + + /* + * XXX: Some broken hostboots populate i2c devs with zeros. + * Workaround them for now. + */ + if (is_zeros(dev, size)) { + prerror("I2C: Ignoring broken i2c dev %d\n", i); + continue; + } + + /* + * On some systems the CFAM I2C master is represented in the + * host I2C table as engine 6. There are only 4 (0, 1, 2, 3) + * engines accessible to the host via XSCOM so filter out + * engines outside this range so we don't create bogus + * i2cm@<addr> nodes. + */ + if (dev->i2cm_engine >= 4 && + (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10)) + continue; + + bus = p8_i2c_add_port_node(xscom, dev->i2cm_engine, dev->i2cm_port, + be16_to_cpu(dev->i2c_bus_freq) * 1000); + + if (!bus) { + prerror("Unable to add node for e%dp%d under %s\n", + dev->i2cm_engine, dev->i2cm_port, xscom->name); + continue; + } + + /* + * Looks like hostboot gives the address as an 8 bit, left + * justified quantity (i.e it includes the R/W bit). So we need + * to strip it off to get an address linux can use. + */ + dev_addr = dev->dev_addr >> 1; + + purpose = be32_to_cpu(dev->purpose); + type = map_type(dev->type); + info = get_info(purpose); + + /* HACK: Hostboot doesn't export the correct type information + * for the DIMM SPD EEPROMs. This is a problem because SPD + * EEPROMs have a different wire protocol to the atmel,24XXXX + * series. The main difference being that SPD EEPROMs have an + * 8bit offset rather than a 16bit offset. This means that the + * driver will send 2 bytes when doing a random read, + * potentially overwriting part of the SPD information. + * + * Just to make things interested the FSP also gets the device + * type wrong. To work around both just set the device-type to + * "spd" for anything in the 0x50 to 0x57 range since that's the + * SPD eeprom range. + * + * XXX: Future chips might not use engine 3 for the DIMM buses. + */ + if (dev->i2cm_engine == 3 && dev_addr >= 0x50 + && dev_addr < 0x58) { + compat = "spd"; + name = "eeprom"; + } else if (type) { + compat = type->compat; + name = type->name; + } else { + name = "unknown"; + compat = NULL; + } + + /* + * An i2c device is unknown if either the i2c device list is + * outdated or the device is marked as unknown (0xFF) in the + * hdat. Log both cases to see what/where/why. + */ + if (!type || dev->type == 0xFF) { + prlog(PR_NOTICE, "HDAT I2C: found e%dp%d - %s@%x dp:%02x (%#x:%s)\n", + dev->i2cm_engine, dev->i2cm_port, name, dev_addr, + dev->dev_port, purpose, info->label); + continue; + } + + prlog(PR_DEBUG, "HDAT I2C: found e%dp%d - %s@%x dp:%02x (%#x:%s)\n", + dev->i2cm_engine, dev->i2cm_port, name, dev_addr, + dev->dev_port, purpose, info->label); + + /* + * Multi-port device require special handling since we need to + * generate the device-specific DT bindings. For now we're just + * going to ignore them since these devices are owned by FW + * any way. + */ + if (dev->dev_port != 0xff) + continue; + + node = dt_new_addr(bus, name, dev_addr); + if (!node) + continue; + + dt_add_property_cells(node, "reg", dev_addr); + dt_add_property_cells(node, "link-id", + be32_to_cpu(dev->i2c_link)); + if (compat) + dt_add_property_string(node, "compatible", compat); + if (info->label) + dt_add_property_string(node, "label", info->label); + if (!info->allowed) + dt_add_property_string(node, "status", "reserved"); + + /* + * Set a default timeout of 2s on the ports with a TPM. This is + * to work around a bug with certain TPM firmwares that can + * clock stretch for long periods of time and will lock up + * until they are power cycled if a STOP condition is sent + * during this period. + */ + if (dev->type == 0x3) + dt_add_property_cells(bus, "timeout-ms", 2000); + + /* XXX: SLCA index? */ + } + + return 0; +} diff --git a/roms/skiboot/hdata/iohub.c b/roms/skiboot/hdata/iohub.c new file mode 100644 index 000000000..92655407e --- /dev/null +++ b/roms/skiboot/hdata/iohub.c @@ -0,0 +1,927 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#include <skiboot.h> +#include "spira.h" +#include <cpu.h> +#include <fsp.h> +#include <opal.h> +#include <ccan/str/str.h> +#include <ccan/array_size/array_size.h> +#include <device.h> +#include <vpd.h> +#include <inttypes.h> +#include <string.h> + +#include "hdata.h" + +static bool io_get_lx_info(const void *kwvpd, unsigned int kwvpd_sz, + int lx_idx, struct dt_node *hn) +{ + const void *lxr; + char recname[5]; + beint32_t lxrbuf[2] = { 0, 0 }; + + /* Find LXRn, where n is the index passed in*/ + strcpy(recname, "LXR0"); + recname[3] += lx_idx; + lxr = vpd_find(kwvpd, kwvpd_sz, recname, "LX", NULL); + if (!lxr) { + /* Not found, try VINI */ + lxr = vpd_find(kwvpd, kwvpd_sz, "VINI", + "LX", NULL); + if (lxr) + lx_idx = VPD_LOAD_LXRN_VINI; + } + if (!lxr) { + prlog(PR_DEBUG, "CEC: LXR%x not found !\n", lx_idx); + return false; + } + + memcpy(lxrbuf, lxr, sizeof(beint32_t)*2); + + prlog(PR_DEBUG, "CEC: LXRn=%d LXR=%08x%08x\n", lx_idx, be32_to_cpu(lxrbuf[0]), be32_to_cpu(lxrbuf[1])); + prlog(PR_DEBUG, "CEC: LX Info added to %llx\n", (long long)hn); + + /* Add the LX info */ + if (!dt_has_node_property(hn, "ibm,vpd-lx-info", NULL)) { + dt_add_property_cells(hn, "ibm,vpd-lx-info", + lx_idx, + be32_to_cpu(lxrbuf[0]), + be32_to_cpu(lxrbuf[1])); + } + + return true; +} + + +static void io_get_loc_code(const void *sp_iohubs, struct dt_node *hn, const char *prop_name) +{ + const struct spira_fru_id *fru_id; + unsigned int fru_id_sz; + char loc_code[LOC_CODE_SIZE + 1]; + const char *slca_loc_code; + + /* Find SLCA Index */ + fru_id = HDIF_get_idata(sp_iohubs, CECHUB_FRU_ID_DATA, &fru_id_sz); + if (fru_id) { + memset(loc_code, 0, sizeof(loc_code)); + + /* Find LOC Code from SLCA Index */ + slca_loc_code = slca_get_loc_code_index(be16_to_cpu(fru_id->slca_index)); + if (slca_loc_code) { + strncpy(loc_code, slca_loc_code, LOC_CODE_SIZE); + if (!dt_has_node_property(hn, prop_name, NULL)) { + dt_add_property(hn, prop_name, loc_code, + strlen(loc_code) + 1); + } + prlog(PR_DEBUG, "CEC: %s: %s (SLCA rsrc 0x%x)\n", + prop_name, loc_code, + be16_to_cpu(fru_id->rsrc_id)); + } else { + prlog(PR_DEBUG, "CEC: SLCA Loc not found: " + "index %d\n", fru_id->slca_index); + } + } else { + prlog(PR_DEBUG, "CEC: Hub FRU ID not found...\n"); + } +} + +static struct dt_node *io_add_phb3(const struct cechub_io_hub *hub, + const struct HDIF_common_hdr *sp_iohubs, + unsigned int index, struct dt_node *xcom, + unsigned int pe_xscom, + unsigned int pci_xscom, + unsigned int spci_xscom) +{ + struct dt_node *pbcq; + unsigned int hdif_vers; + + /* Get HDIF version */ + hdif_vers = be16_to_cpu(sp_iohubs->version); + + /* Create PBCQ node under xscom */ + pbcq = dt_new_addr(xcom, "pbcq", pe_xscom); + if (!pbcq) + return NULL; + + /* "reg" property contains in order the PE, PCI and SPCI XSCOM + * addresses + */ + dt_add_property_cells(pbcq, "reg", + pe_xscom, 0x20, + pci_xscom, 0x05, + spci_xscom, 0x15); + + /* A couple more things ... */ + dt_add_property_strings(pbcq, "compatible", "ibm,power8-pbcq"); + dt_add_property_cells(pbcq, "ibm,phb-index", index); + dt_add_property_cells(pbcq, "ibm,hub-id", be16_to_cpu(hub->hub_num)); + + /* The loc code of the PHB itself is different from the base + * loc code of the slots (It's actually the DCM's loc code). + */ + io_get_loc_code(sp_iohubs, pbcq, "ibm,loc-code"); + + /* We indicate that this is an IBM setup, which means that + * the presence detect A/B bits are meaningful. So far we + * don't know whether they make any sense on customer setups + * so we only set that when booting with HDAT + */ + dt_add_property(pbcq, "ibm,use-ab-detect", NULL, 0); + + /* HDAT spec has these in version 0x6A and later */ + if (hdif_vers >= 0x6a) { + u64 eq0 = be64_to_cpu(hub->phb_lane_eq[index][0]); + u64 eq1 = be64_to_cpu(hub->phb_lane_eq[index][1]); + u64 eq2 = be64_to_cpu(hub->phb_lane_eq[index][2]); + u64 eq3 = be64_to_cpu(hub->phb_lane_eq[index][3]); + + dt_add_property_u64s(pbcq, "ibm,lane-eq", eq0, eq1, eq2, eq3); + } + + /* Currently we only create a PBCQ node, the actual PHB nodes + * will be added by sapphire later on. + */ + return pbcq; +} + +static struct dt_node *add_pec_stack(const struct cechub_io_hub *hub, + struct dt_node *pbcq, int stack_index, + int phb_index, u8 active_phbs) +{ + struct dt_node *stack; + const char *compat; + u64 eq[12]; + u8 *ptr; + int i; + + stack = dt_new_addr(pbcq, "stack", stack_index); + assert(stack); + + if (proc_gen == proc_gen_p9) + compat = "ibm,power9-phb-stack"; + else + compat = "ibm,power10-phb-stack"; + + dt_add_property_cells(stack, "reg", stack_index); + dt_add_property_cells(stack, "ibm,phb-index", phb_index); + dt_add_property_string(stack, "compatible", compat); + + /* XXX: This should probably just return if the PHB is disabled + * rather than adding the extra properties. + */ + + if (active_phbs & (0x80 >> phb_index)) + dt_add_property_string(stack, "status", "okay"); + else + dt_add_property_string(stack, "status", "disabled"); + + for (i = 0; i < 4; i++) /* gen 3 eq settings */ + eq[i] = be64_to_cpu(hub->phb_lane_eq[phb_index][i]); + for (i = 0; i < 4; i++) /* gen 4 eq settings */ + eq[i+4] = be64_to_cpu(hub->phb4_lane_eq[phb_index][i]); + for (i = 0; i < 4; i++) /* gen 5 eq settings */ + eq[i+8] = be64_to_cpu(hub->phb5_lane_eq[phb_index][i]); + + /* Lane-eq settings are packed 2 bytes per lane for 16 lanes + * On P9 DD2 and P10, 1 byte per lane is used in the hardware + */ + + /* Repack 2 byte lane settings into 1 byte for gen 4 & 5 */ + ptr = (u8 *)&eq[4]; + for (i = 0; i < 32; i++) + ptr[i] = ptr[2*i]; + + if (proc_gen == proc_gen_p9) + dt_add_property_u64s(stack, "ibm,lane-eq", + eq[0], eq[1], eq[2], eq[3], + eq[4], eq[5]); + else + dt_add_property_u64s(stack, "ibm,lane-eq", + eq[0], eq[1], eq[2], eq[3], + eq[4], eq[5], + eq[6], eq[7]); + return stack; +} + +/* Add PHB4 on p9, PHB5 on p10 */ +static struct dt_node *io_add_phb4(const struct cechub_io_hub *hub, + const struct HDIF_common_hdr *sp_iohubs, + struct dt_node *xcom, + unsigned int pec_index, + int stacks, + int phb_base) +{ + struct dt_node *pbcq; + uint8_t active_phb_mask = hub->fab_br0_pdt; + uint32_t pe_xscom; + uint32_t pci_xscom; + const char *compat; + int i; + + if (proc_gen == proc_gen_p9) { + pe_xscom = 0x4010c00 + (pec_index * 0x0000400); + pci_xscom = 0xd010800 + (pec_index * 0x1000000); + compat = "ibm,power9-pbcq"; + } else { + pe_xscom = 0x3011800 - (pec_index * 0x1000000); + pci_xscom = 0x8010800 + (pec_index * 0x1000000); + compat = "ibm,power10-pbcq"; + } + + /* Create PBCQ node under xscom */ + pbcq = dt_new_addr(xcom, "pbcq", pe_xscom); + if (!pbcq) + return NULL; + + /* "reg" property contains (in order) the PE and PCI XSCOM addresses */ + dt_add_property_cells(pbcq, "reg", + pe_xscom, 0x100, + pci_xscom, 0x200); + + /* The hubs themselves go under the stacks */ + dt_add_property_strings(pbcq, "compatible", compat); + dt_add_property_cells(pbcq, "ibm,pec-index", pec_index); + dt_add_property_cells(pbcq, "#address-cells", 1); + dt_add_property_cells(pbcq, "#size-cells", 0); + + for (i = 0; i < stacks; i++) + add_pec_stack(hub, pbcq, i, phb_base + i, active_phb_mask); + + dt_add_property_cells(pbcq, "ibm,hub-id", be16_to_cpu(hub->hub_num)); + + /* The loc code of the PHB itself is different from the base + * loc code of the slots (It's actually the DCM's loc code). + */ + io_get_loc_code(sp_iohubs, pbcq, "ibm,loc-code"); + + prlog(PR_INFO, "CEC: Added PBCQ %d with %d stacks\n", + pec_index, stacks); + + /* the actual PHB nodes created later on by skiboot */ + return pbcq; +} + +static struct dt_node *io_add_p8(const struct cechub_io_hub *hub, + const struct HDIF_common_hdr *sp_iohubs) +{ + struct dt_node *xscom; + unsigned int i, chip_id; + + chip_id = pcid_to_chip_id(be32_to_cpu(hub->proc_chip_id)); + + prlog(PR_INFO, "CEC: HW CHIP=0x%x, HW TOPO=0x%04x\n", chip_id, + be16_to_cpu(hub->hw_topology)); + + xscom = find_xscom_for_chip(chip_id); + if (!xscom) { + prerror("P8: Can't find XSCOM for chip %d\n", chip_id); + return NULL; + } + + /* Create PHBs, max 3 */ + for (i = 0; i < 3; i++) { + if (hub->fab_br0_pdt & (0x80 >> i)) + /* XSCOM addresses are the same on Murano and Venice */ + io_add_phb3(hub, sp_iohubs, i, xscom, + 0x02012000 + (i * 0x400), + 0x09012000 + (i * 0x400), + 0x09013c00 + (i * 0x40)); + } + + /* HACK: We return the XSCOM device for the VPD info */ + return xscom; +} + +/* Add PBCQs for p9/p10 */ +static struct dt_node *io_add_p9(const struct cechub_io_hub *hub, + const struct HDIF_common_hdr *sp_iohubs) +{ + struct dt_node *xscom; + unsigned int chip_id; + + chip_id = pcid_to_chip_id(be32_to_cpu(hub->proc_chip_id)); + + prlog(PR_INFO, "CEC: HW CHIP=0x%x, HW TOPO=0x%04x\n", chip_id, + be16_to_cpu(hub->hw_topology)); + + xscom = find_xscom_for_chip(chip_id); + if (!xscom) { + prerror("IOHUB: Can't find XSCOM for chip %d\n", chip_id); + return NULL; + } + + prlog(PR_DEBUG, "IOHUB: PHB active bridge mask %x\n", + (u32) hub->fab_br0_pdt); + + /* Create PBCQs */ + if (proc_gen == proc_gen_p9) { + io_add_phb4(hub, sp_iohubs, xscom, 0, 1, 0); + io_add_phb4(hub, sp_iohubs, xscom, 1, 2, 1); + io_add_phb4(hub, sp_iohubs, xscom, 2, 3, 3); + } else { /* p10 */ + io_add_phb4(hub, sp_iohubs, xscom, 0, 3, 0); + io_add_phb4(hub, sp_iohubs, xscom, 1, 3, 3); + } + + return xscom; +} + + +static void io_add_p8_cec_vpd(const struct HDIF_common_hdr *sp_iohubs) +{ + const struct HDIF_child_ptr *iokids; + const void *iokid; + const void *kwvpd; + unsigned int kwvpd_sz; + + /* P8 LXR0 kept in IO KID Keyword VPD */ + iokids = HDIF_child_arr(sp_iohubs, CECHUB_CHILD_IO_KIDS); + if (!CHECK_SPPTR(iokids)) { + prlog(PR_WARNING, "CEC: No IOKID child array !\n"); + return; + } + if (!iokids->count) { + prlog(PR_WARNING, "CEC: IOKID count is 0 !\n"); + return; + } + if (be32_to_cpu(iokids->count) > 1) { + prlog(PR_WARNING, "CEC: WARNING ! More than 1 IO KID !!! (%d)\n", + be32_to_cpu(iokids->count)); + /* Ignoring the additional ones */ + } + + iokid = HDIF_child(sp_iohubs, iokids, 0, "IO KID"); + if (!iokid) { + prlog(PR_WARNING, "CEC: No IO KID structure in child array !\n"); + return; + } + + /* Grab base location code for slots */ + io_get_loc_code(iokid, dt_root, "ibm,io-base-loc-code"); + + kwvpd = HDIF_get_idata(iokid, CECHUB_ASCII_KEYWORD_VPD, &kwvpd_sz); + if (!kwvpd) { + prlog(PR_WARNING, "CEC: No VPD entry in IO KID !\n"); + return; + } + + /* Grab LX load info */ + io_get_lx_info(kwvpd, kwvpd_sz, 0, dt_root); +} + +/* + * Assumptions: + * + * a) the IOSLOT index is the hub ID -CHECK + * + */ + +static struct dt_node *dt_slots; + +static void add_i2c_link(struct dt_node *node, const char *link_name, + u32 i2c_link) +{ + /* FIXME: Do something not shit */ + dt_add_property_cells(node, link_name, i2c_link); +} + +/* + * the root of the slots node has #address-cells = 2, <hub-index, phb-index> + * can we ditch hub-index? + */ + + +static const struct slot_map_details *find_slot_details( + const struct HDIF_common_hdr *ioslot, int entry) +{ + const struct slot_map_details *details = NULL; + const struct HDIF_array_hdr *arr; + unsigned int i; + + arr = HDIF_get_iarray(ioslot, IOSLOT_IDATA_DETAILS, NULL); + HDIF_iarray_for_each(arr, i, details) + if (be16_to_cpu(details->entry) == entry) + break; + + return details; +} + +static void parse_slot_details(struct dt_node *slot, + const struct slot_map_details *details) +{ + u32 slot_caps; + + /* + * generic slot options + */ + + dt_add_property_cells(slot, "max-power", + be16_to_cpu(details->max_power)); + + if (details->perst_ctl_type == SLOT_PERST_PHB_OR_SW) + dt_add_property(slot, "pci-perst", NULL, 0); + else if (details->perst_ctl_type == SLOT_PERST_SW_GPIO) + dt_add_property_cells(slot, "gpio-perst", details->perst_gpio); + + if (details->presence_det_type == SLOT_PRESENCE_PCI) + dt_add_property(slot, "pci-presence-detect", NULL, 0); + + /* + * specific slot capabilities + */ + slot_caps = be32_to_cpu(details->slot_caps); + + if (slot_caps & SLOT_CAP_LSI) + dt_add_property(slot, "lsi", NULL, 0); + + if (slot_caps & SLOT_CAP_CAPI) { + /* XXX: should we be more specific here? + * + * Also we should double check that this slot + * is a root connected slot. + */ + dt_add_property(slot, "capi", NULL, 0); + } + + if (slot_caps & SLOT_CAP_CCARD) { + dt_add_property(slot, "cable-card", NULL, 0); + + if (details->presence_det_type == SLOT_PRESENCE_I2C) + add_i2c_link(slot, "i2c-presence-detect", + be32_to_cpu(details->i2c_cable_card)); + } + + if (slot_caps & SLOT_CAP_HOTPLUG) { + dt_add_property(slot, "hotplug", NULL, 0); + + /* + * Power control should only exist when the slot is hotplug + * capable + */ + if (details->power_ctrl_type == SLOT_PWR_I2C) + add_i2c_link(slot, "i2c-power-ctrl", + be32_to_cpu(details->i2c_power_ctl)); + } + + /* + * NB: Additional NVLink specific info is added to this node + * when the SMP Link structures are parsed later on. + */ + if (slot_caps & SLOT_CAP_NVLINK) + dt_add_property(slot, "nvlink", NULL, 0); +} + +struct dt_node *find_slot_entry_node(struct dt_node *root, u32 entry_id) +{ + struct dt_node *node; + + for (node = dt_first(root); node; node = dt_next(root, node)) { + if (!dt_has_node_property(node, DT_PRIVATE "entry_id", NULL)) + continue; + + if (dt_prop_get_u32(node, DT_PRIVATE "entry_id") == entry_id) + return node; + } + + return NULL; +} + +/* + * The internal HDAT representation of the various types of slot is kinda + * dumb, translate it into something more sensible + */ +enum slot_types { + st_root, + st_slot, + st_rc_slot, + st_sw_upstream, + st_sw_downstream, + st_builtin +}; + +static const char *st_name(enum slot_types type) +{ + switch(type) { + case st_root: return "root-complex"; + case st_slot: return "pluggable"; + case st_rc_slot: return "pluggable"; /* differentiate? */ + case st_sw_upstream: return "switch-up"; + case st_sw_downstream: return "switch-down"; + case st_builtin: return "builtin"; + } + + return "(none)"; +} + +static enum slot_types xlate_type(uint8_t type, u32 features) +{ + bool is_slot = features & SLOT_FEAT_SLOT; + + switch (type) { + case SLOT_TYPE_ROOT_COMPLEX: + return is_slot ? st_rc_slot : st_root; + case SLOT_TYPE_BUILTIN: + return st_builtin; + case SLOT_TYPE_SWITCH_UP: + return st_sw_upstream; + case SLOT_TYPE_SWITCH_DOWN: + return is_slot ? st_slot : st_sw_downstream; + } + + return -1; /* shouldn't happen */ +} + +static bool is_port(struct dt_node *n) +{ + //return dt_node_is_compatible(n, "compatible", "ibm,pcie-port"); + return dt_node_is_compatible(n, "ibm,pcie-port"); +} + +/* this only works inside parse_one_ioslot() */ +#define SM_LOG(level, fmt, ...) \ + prlog(level, "SLOTMAP: %x:%d:%d " \ + fmt, /* user input */ \ + chip_id, entry->phb_index, eid, \ + ##__VA_ARGS__ /* user args */) + +#define SM_ERR(fmt, ...) SM_LOG(PR_ERR, fmt, ##__VA_ARGS__) +#define SM_DBG(fmt, ...) SM_LOG(PR_DEBUG, fmt, ##__VA_ARGS__) + +static void parse_one_slot(const struct slot_map_entry *entry, + const struct slot_map_details *details, int chip_id) +{ + struct dt_node *node, *parent = NULL; + u16 eid, pid, vid, did; + u32 flags; + int type; + + flags = be32_to_cpu(entry->features); + type = xlate_type(entry->type, flags); + + eid = be16_to_cpu(entry->entry_id); + pid = be16_to_cpu(entry->parent_id); + + SM_DBG("%s - eid = %d, pid = %d, name = %8s\n", + st_name(type), eid, pid, + strnlen(entry->name, 8) ? entry->name : ""); + + /* empty slot, ignore it */ + if (eid == 0x0 && pid == 0x0) + return; + + if (type != st_root && type != st_rc_slot) { + parent = find_slot_entry_node(dt_slots, pid); + if (!parent) { + SM_ERR("Unable to find node for parent slot (id = %d)\n", + pid); + return; + } + } + + switch (type) { + case st_root: + case st_rc_slot: + node = dt_new_2addr(dt_slots, "root-complex", + chip_id, entry->phb_index); + if (!node) { + SM_ERR("Couldn't add DT node\n"); + return; + } + dt_add_property_cells(node, "reg", chip_id, entry->phb_index); + dt_add_property_cells(node, "#address-cells", 2); + dt_add_property_cells(node, "#size-cells", 0); + dt_add_property_strings(node, "compatible", + "ibm,pcie-port", "ibm,pcie-root-port"); + dt_add_property_cells(node, "ibm,chip-id", chip_id); + parent = node; + + /* + * The representation of slots attached directly to the + * root complex is a bit wierd. If this is just a root + * complex then stop here, otherwise fall through to create + * the slot node. + */ + if (type == st_root) + break; + + /* fallthrough*/ + case st_sw_upstream: + case st_builtin: + case st_slot: + if (!is_port(parent)) { + SM_ERR("%s connected to %s (%d), should be %s or %s!\n", + st_name(type), parent->name, pid, + st_name(st_root), st_name(st_sw_downstream)); + return; + } + + vid = (be32_to_cpu(entry->vendor_id) & 0xffff); + did = (be32_to_cpu(entry->device_id) & 0xffff); + + prlog(PR_DEBUG, "Found %s slot with %x:%x\n", + st_name(type), vid, did); + + /* The VID:DID is only meaningful for builtins and switches */ + if (type == st_sw_upstream && vid && did) { + node = dt_new_2addr(parent, st_name(type), vid, did); + dt_add_property_cells(node, "reg", vid, did); + } else { + /* + * If we get no vdid then create a "wildcard" slot + * that matches any device + */ + node = dt_new(parent, st_name(type)); + } + + if (type == st_sw_upstream) { + dt_add_property_cells(node, "#address-cells", 1); + dt_add_property_cells(node, "#size-cells", 0); + dt_add_property_cells(node, "upstream-port", + entry->up_port); + } + break; + + case st_sw_downstream: /* slot connected to switch output */ + node = dt_new_addr(parent, "down-port", entry->down_port); + dt_add_property_strings(node, "compatible", + "ibm,pcie-port"); + dt_add_property_cells(node, "reg", entry->down_port); + + break; + + default: + SM_ERR("Unknown slot map type %x\n", entry->type); + return; + } + + /* + * Now add any generic slot map properties. + */ + + /* private since we don't want hdat stuff leaking */ + dt_add_property_cells(node, DT_PRIVATE "entry_id", eid); + + if (entry->mrw_slot_id) + dt_add_property_cells(node, "mrw-slot-id", + be16_to_cpu(entry->mrw_slot_id)); + + if (entry->lane_mask) + dt_add_property_cells(node, "lane-mask", + be16_to_cpu(entry->lane_mask)); + + /* what is the difference between this and the lane reverse? */ + if (entry->lane_reverse) + dt_add_property_cells(node, "lanes-reversed", + be16_to_cpu(entry->lane_reverse)); + + if (strnlen(entry->name, sizeof(entry->name))) { + /* + * HACK: On some platforms (witherspoon) the slot label is + * applied to the device rather than the pcie downstream port + * that has the slot under it. Hack around this by moving the + * slot label up if the parent port doesn't have one. + */ + if (dt_node_is_compatible(node->parent, "ibm,pcie-port") && + !dt_find_property(node->parent, "ibm,slot-label")) { + dt_add_property_nstr(node->parent, "ibm,slot-label", + entry->name, sizeof(entry->name)); + } + + dt_add_property_nstr(node, "ibm,slot-label", + entry->name, sizeof(entry->name)); + } + + if (entry->type == st_slot || entry->type == st_rc_slot) + dt_add_property(node, "ibm,pluggable", NULL, 0); + + if (details) + parse_slot_details(node, details); +} + +/* + * Under the IOHUB structure we have and idata array describing + * the PHBs under each chip. The IOHUB structure also has a child + * array called IOSLOT which describes slot map. The i`th element + * of the IOSLOT array corresponds to the slot map of the i`th + * element of the iohubs idata array. + * + * Probably. + * + * Furthermore, arrayarrayarrayarrayarray. + */ + +static struct dt_node *get_slot_node(void) +{ + struct dt_node *slots = dt_find_by_name(dt_root, "ibm,pcie-slots"); + + if (!slots) { + slots = dt_new(dt_root, "ibm,pcie-slots"); + dt_add_property_cells(slots, "#address-cells", 2); + dt_add_property_cells(slots, "#size-cells", 0); + } + + return slots; +} + +static void io_parse_slots(const struct HDIF_common_hdr *sp_iohubs, int hub_id) +{ + const struct HDIF_child_ptr *ioslot_arr; + const struct HDIF_array_hdr *entry_arr; + const struct HDIF_common_hdr *ioslot; + const struct slot_map_entry *entry; + unsigned int i, count; + + if (be16_to_cpu(sp_iohubs->child_count) <= CECHUB_CHILD_IOSLOTS) + return; + + ioslot_arr = HDIF_child_arr(sp_iohubs, CECHUB_CHILD_IOSLOTS); + if (!ioslot_arr) + return; + + count = be32_to_cpu(ioslot_arr->count); /* should only be 1 */ + if (!count) + return; + + dt_slots = get_slot_node(); + + prlog(PR_DEBUG, "CEC: Found slot map for IOHUB %d\n", hub_id); + if (count > 1) + prerror("CEC: Multiple IOSLOTs found for IO HUB %d\n", hub_id); + + ioslot = HDIF_child(sp_iohubs, ioslot_arr, 0, "IOSLOT"); + if (!ioslot) + return; + + entry_arr = HDIF_get_iarray(ioslot, IOSLOT_IDATA_SLOTMAP, NULL); + HDIF_iarray_for_each(entry_arr, i, entry) { + const struct slot_map_details *details; + + details = find_slot_details(ioslot, + be16_to_cpu(entry->entry_id)); + parse_one_slot(entry, details, hub_id); + } +} + +static void io_parse_fru(const void *sp_iohubs) +{ + unsigned int i; + int count; + + count = HDIF_get_iarray_size(sp_iohubs, CECHUB_FRU_IO_HUBS); + if (count < 1) { + prerror("CEC: IO FRU with no chips !\n"); + return; + } + + prlog(PR_INFO, "CEC: %d chips in FRU\n", count); + + /* Iterate IO hub array */ + for (i = 0; i < count; i++) { + const struct cechub_io_hub *hub; + unsigned int size, hub_id; + uint32_t chip_id; + + hub = HDIF_get_iarray_item(sp_iohubs, CECHUB_FRU_IO_HUBS, + i, &size); + if (!hub || size < CECHUB_IOHUB_MIN_SIZE) { + prerror("CEC: IO-HUB Chip %d bad idata\n", i); + continue; + } + + switch (hub->flags & CECHUB_HUB_FLAG_STATE_MASK) { + case CECHUB_HUB_FLAG_STATE_OK: + prlog(PR_DEBUG, "CEC: IO Hub Chip #%d OK\n", i); + break; + case CECHUB_HUB_FLAG_STATE_FAILURES: + prlog(PR_WARNING, "CEC: IO Hub Chip #%d OK" + " with failures\n", i); + break; + case CECHUB_HUB_FLAG_STATE_NOT_INST: + prlog(PR_DEBUG, "CEC: IO Hub Chip #%d" + " Not installed\n", i); + continue; + case CECHUB_HUB_FLAG_STATE_UNUSABLE: + prlog(PR_DEBUG, "CEC: IO Hub Chip #%d Unusable\n", i); + continue; + } + + hub_id = be16_to_cpu(hub->iohub_id); + + /* GX BAR assignment */ + prlog(PR_DEBUG, "CEC: PChip: %d HUB ID: %04x [EC=0x%x]" + " Hub#=%d)\n", + be32_to_cpu(hub->proc_chip_id), hub_id, + be32_to_cpu(hub->ec_level), be16_to_cpu(hub->hub_num)); + + switch(hub_id) { + case CECHUB_HUB_MURANO: + case CECHUB_HUB_MURANO_SEGU: + prlog(PR_INFO, "CEC: Murano !\n"); + io_add_p8(hub, sp_iohubs); + break; + case CECHUB_HUB_VENICE_WYATT: + prlog(PR_INFO, "CEC: Venice !\n"); + io_add_p8(hub, sp_iohubs); + break; + case CECHUB_HUB_NIMBUS_SFORAZ: + case CECHUB_HUB_NIMBUS_MONZA: + case CECHUB_HUB_NIMBUS_LAGRANGE: + prlog(PR_INFO, "CEC: Nimbus !\n"); + io_add_p9(hub, sp_iohubs); + break; + case CECHUB_HUB_CUMULUS_DUOMO: + prlog(PR_INFO, "CEC: Cumulus !\n"); + io_add_p9(hub, sp_iohubs); + break; + case CECHUB_HUB_AXONE_HOPPER: + prlog(PR_INFO, "CEC: Axone !\n"); + io_add_p9(hub, sp_iohubs); + break; + case CECHUB_HUB_RAINIER: + prlog(PR_INFO, "CEC: Rainier !\n"); + io_add_p9(hub, sp_iohubs); + break; + case CECHUB_HUB_DENALI: + prlog(PR_INFO, "CEC: Denali !\n"); + io_add_p9(hub, sp_iohubs); + break; + default: + prlog(PR_ERR, "CEC: Hub ID 0x%04x unsupported !\n", + hub_id); + } + + chip_id = pcid_to_chip_id(be32_to_cpu(hub->proc_chip_id)); + + /* parse the slot map if we have one */ + io_parse_slots(sp_iohubs, chip_id); + } + + if (proc_gen == proc_gen_p8 || proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) + io_add_p8_cec_vpd(sp_iohubs); +} + +void io_parse(void) +{ + const struct HDIF_common_hdr *sp_iohubs; + unsigned int i, size; + + /* Look for IO Hubs */ + if (!get_hdif(&spira.ntuples.cec_iohub_fru, "IO HUB")) { + prerror("CEC: Cannot locate IO Hub FRU data !\n"); + return; + } + + /* + * Note about LXRn numbering ... + * + * I can't completely make sense of what that is supposed to be, so + * for now, what we do is look for the first one we can find and + * increment it for each chip. Works for the machines I have here + */ + + for_each_ntuple_idx(&spira.ntuples.cec_iohub_fru, sp_iohubs, i, + CECHUB_FRU_HDIF_SIG) { + const struct cechub_hub_fru_id *fru_id_data; + unsigned int type; + static const char *typestr[] = { + "Reservation", + "Card", + "CPU Card", + "Backplane", + "Backplane Extension" + }; + fru_id_data = HDIF_get_idata(sp_iohubs, CECHUB_FRU_ID_DATA_AREA, + &size); + if (!fru_id_data || size < sizeof(struct cechub_hub_fru_id)) { + prerror("CEC: IO-HUB FRU %d, bad ID data\n", i); + continue; + } + type = be32_to_cpu(fru_id_data->card_type); + + prlog(PR_INFO, "CEC: HUB FRU %d is %s\n", + i, type > 4 ? "Unknown" : typestr[type]); + + /* + * We currently only handle the backplane (Juno) and + * processor FRU (P8 machines) + */ + if (type != CECHUB_FRU_TYPE_CEC_BKPLANE && + type != CECHUB_FRU_TYPE_CPU_CARD) { + prerror("CEC: Unsupported type\n"); + continue; + } + + /* We don't support Hubs connected to pass-through ports */ + if (fru_id_data->flags & (CECHUB_FRU_FLAG_HEADLESS | + CECHUB_FRU_FLAG_PASSTHROUGH)) { + prerror("CEC: Headless or Passthrough unsupported\n"); + continue; + } + + /* Ok, we have a reasonable candidate */ + io_parse_fru(sp_iohubs); + } +} + diff --git a/roms/skiboot/hdata/memory.c b/roms/skiboot/hdata/memory.c new file mode 100755 index 000000000..efdb502b1 --- /dev/null +++ b/roms/skiboot/hdata/memory.c @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#include <cpu.h> +#include <device.h> +#include <vpd.h> +#include <ccan/str/str.h> +#include <libfdt/libfdt.h> +#include <mem_region.h> +#include <types.h> +#include <inttypes.h> +#include <processor.h> + +#include "spira.h" +#include "hdata.h" + +struct HDIF_ram_area_id { + __be16 id; +#define RAM_AREA_INSTALLED 0x8000 +#define RAM_AREA_FUNCTIONAL 0x4000 + __be16 flags; + __be32 dimm_id; + __be32 speed; +} __packed; + +struct HDIF_ram_area_size { + __be32 reserved1; + __be32 mb; +} __packed; + +struct HDIF_ms_area_address_range { + __be64 start; + __be64 end; + __be32 chip; + __be32 mirror_attr; + __be64 mirror_start; + __be32 controller_id; + __be32 phys_attr; +} __packed; +#define PHYS_ATTR_TYPE_MASK 0xff000000 +#define PHYS_ATTR_TYPE_STD 0 +#define PHYS_ATTR_TYPE_NVDIMM 1 +#define PHYS_ATTR_TYPE_MRAM 2 +#define PHYS_ATTR_TYPE_PCM 3 + +#define PHYS_ATTR_STATUS_MASK 0x00ff0000 +/* + * The values here are mutually exclusive. I have no idea why anyone + * decided encoding these are flags rather than sequential numbers was + * a good idea, but here we are. + */ +#define PHYS_ATTR_STATUS_CANT_SAVE 0x01 +#define PHYS_ATTR_STATUS_SAVE_FAILED 0x02 +#define PHYS_ATTR_STATUS_SAVED 0x04 +#define PHYS_ATTR_STATUS_NOT_SAVED 0x08 +#define PHYS_ATTR_STATUS_ENCRYPTED 0x10 +#define PHYS_ATTR_STATUS_ERR_DETECTED 0x40 +#define PHYS_ATTR_STATUS_MEM_INVALID 0xff + +/* Memory Controller ID for Nimbus P9 systems */ +#define MS_CONTROLLER_MCBIST_ID(id) GETFIELD(PPC_BITMASK32(0, 1), id) +#define MS_CONTROLLER_MCS_ID(id) GETFIELD(PPC_BITMASK32(4, 7), id) +#define MS_CONTROLLER_MCA_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) + +/* Memory Controller ID for P9 AXONE systems */ +#define MS_CONTROLLER_MC_ID(id) GETFIELD(PPC_BITMASK32(0, 1), id) +#define MS_CONTROLLER_MI_ID(id) GETFIELD(PPC_BITMASK32(4, 7), id) +#define MS_CONTROLLER_MCC_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) +#define MS_CONTROLLER_OMI_ID(id) GETFIELD(PPC_BITMASK32(16, 31), id) + +struct HDIF_ms_area_id { + __be16 id; +#define MS_PTYPE_RISER_CARD 0x8000 +#define MS_PTYPE_MEM_CARD 0x4000 +#define MS_PTYPE_CEC_FRU 0x2000 +#define MS_PTYPE_HYBRID_CARD 0x1000 + __be16 parent_type; +#define MS_AREA_INSTALLED 0x8000 +#define MS_AREA_FUNCTIONAL 0x4000 +#define MS_AREA_SHARED 0x2000 + __be16 flags; + __be16 share_id; +} __packed; + + +// FIXME: it should be 9, current HDATs are broken +#define MSAREA_IDATA_MMIO_IDX 8 +struct HDIF_ms_area_ocmb_mmio { + __be64 range_start; + __be64 range_end; + __be32 controller_id; + __be32 proc_chip_id; + __be64 hbrt_id; +#define OCMB_SCOM_8BYTE_ACCESS PPC_BIT(0) +#define OCMB_SCOM_4BYTE_ACCESS PPC_BIT(1) + __be64 flags; +} __packed; + +static void append_chip_id(struct dt_node *mem, u32 id) +{ + struct dt_property *prop; + size_t len, i; + + prop = __dt_find_property(mem, "ibm,chip-id"); + if (!prop) + return; + len = prop->len >> 2; + + /* Check if it exists already */ + for (i = 0; i < len; i++) { + if (dt_property_get_cell(prop, i) == id) + return; + } + + /* Add it to the list */ + dt_resize_property(&prop, (len + 1) << 2); + dt_property_set_cell(prop, len, id); +} + +static void update_status(struct dt_node *mem, uint32_t status) +{ + switch (status) { + case PHYS_ATTR_STATUS_CANT_SAVE: + if (!dt_find_property(mem, "save-trigged-unarmed")) + dt_add_property(mem, "save-trigger-unarmed", NULL, 0); + break; + + case PHYS_ATTR_STATUS_SAVE_FAILED: + if (!dt_find_property(mem, "save-failed")) + dt_add_property(mem, "save-failed", NULL, 0); + + break; + + case PHYS_ATTR_STATUS_MEM_INVALID: + if (dt_find_property(mem, "save-trigged-unarmed")) + dt_add_property_string(mem, "status", + "disabled-memory-invalid"); + break; + } +} + +static bool add_address_range(struct dt_node *root, + const struct HDIF_ms_area_id *id, + const struct HDIF_ms_area_address_range *arange, + uint32_t mem_type, uint32_t mem_status) +{ + const char *compat = NULL, *dev_type = NULL, *name = NULL; + struct dt_node *mem; + u32 chip_id; + u64 reg[2]; + + chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); + + prlog(PR_DEBUG, " Range: 0x%016llx..0x%016llx " + "on Chip 0x%x mattr: 0x%x pattr: 0x%x status:0x%x\n", + (long long)be64_to_cpu(arange->start), + (long long)be64_to_cpu(arange->end), + chip_id, be32_to_cpu(arange->mirror_attr), + mem_type, mem_status); + + /* reg contains start and length */ + reg[0] = cleanup_addr(be64_to_cpu(arange->start)); + reg[1] = cleanup_addr(be64_to_cpu(arange->end)) - reg[0]; + + switch (mem_type) { + case PHYS_ATTR_TYPE_STD: + name = "memory"; + dev_type = "memory"; + break; + + case PHYS_ATTR_TYPE_NVDIMM: + case PHYS_ATTR_TYPE_MRAM: + case PHYS_ATTR_TYPE_PCM: + /* fall through */ + name = "nvdimm"; + compat = "pmem-region"; + break; + + /* + * Future memory types could be volatile or non-volatile. Bail if don't + * recognise the type so we don't end up trashing data accidently. + */ + default: + return false; + } + + if (be16_to_cpu(id->flags) & MS_AREA_SHARED) { + mem = dt_find_by_name_addr(dt_root, name, reg[0]); + if (mem) { + append_chip_id(mem, chip_id); + if (mem_type == PHYS_ATTR_TYPE_NVDIMM) + update_status(mem, mem_status); + return true; + } + } + + mem = dt_new_addr(root, name, reg[0]); + if (compat) + dt_add_property_string(mem, "compatible", compat); + if (dev_type) + dt_add_property_string(mem, "device_type", dev_type); + + /* add in the nvdimm backup status flags */ + if (mem_type == PHYS_ATTR_TYPE_NVDIMM) + update_status(mem, mem_status); + + /* common properties */ + + dt_add_property_u64s(mem, "reg", reg[0], reg[1]); + dt_add_property_cells(mem, "ibm,chip-id", chip_id); + return true; +} + +static u32 add_chip_id_to_ram_area(const struct HDIF_common_hdr *msarea, + struct dt_node *ram_area) +{ + const struct HDIF_array_hdr *arr; + const struct HDIF_ms_area_address_range *arange; + unsigned int size; + u32 chip_id; + + /* Safe to assume pointers are valid here. */ + arr = HDIF_get_idata(msarea, 4, &size); + arange = (void *)arr + be32_to_cpu(arr->offset); + chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); + dt_add_property_cells(ram_area, "ibm,chip-id", chip_id); + + return chip_id; +} + +static void add_bus_freq_to_ram_area(struct dt_node *ram_node, u32 chip_id) +{ + const struct sppcia_cpu_timebase *timebase; + bool got_pcia = false; + const void *pcia; + u64 freq; + u32 size; + + pcia = get_hdif(&spira.ntuples.pcia, SPPCIA_HDIF_SIG); + if (!pcia) { + prlog(PR_WARNING, "HDAT: Failed to add memory bus frequency " + "as PCIA does not exist\n"); + return; + } + + for_each_pcia(pcia) { + const struct sppcia_core_unique *id; + + id = HDIF_get_idata(pcia, SPPCIA_IDATA_CORE_UNIQUE, &size); + if (!id || size < sizeof(*id)) { + prlog(PR_WARNING, "HDAT: Bad id size %u @ %p\n", size, id); + return; + } + + if (chip_id == pcid_to_chip_id(be32_to_cpu(id->proc_chip_id))) { + got_pcia = true; + break; + } + } + + if (got_pcia == false) + return; + + timebase = HDIF_get_idata(pcia, SPPCIA_IDATA_TIMEBASE, &size); + if (!timebase || size < sizeof(*timebase)) { + /** + * @fwts-label HDATBadTimebaseSize + * @fwts-advice HDAT described an invalid size for timebase, + * which means there's a disagreement between HDAT and OPAL. + * This is most certainly a firmware bug. + */ + prlog(PR_ERR, "HDAT: Bad timebase size %u @ %p\n", size, + timebase); + return; + } + + freq = ((u64)be32_to_cpu(timebase->memory_bus_frequency)) * 1000000ul; + dt_add_property_u64(ram_node, "ibm,memory-bus-frequency", freq); +} + +static void add_size_to_ram_area(struct dt_node *ram_node, + const struct HDIF_common_hdr *ramarea) +{ + char str[16]; + const struct HDIF_ram_area_size *ram_area_sz; + + /* DIMM size */ + ram_area_sz = HDIF_get_idata(ramarea, 3, NULL); + if (!CHECK_SPPTR(ram_area_sz)) + return; + + memset(str, 0, 16); + snprintf(str, 16, "%d", be32_to_cpu(ram_area_sz->mb)); + dt_add_property_string(ram_node, "size", str); +} + +static void vpd_add_ram_area(const struct HDIF_common_hdr *msarea) +{ + unsigned int i; + unsigned int ram_sz; + const struct HDIF_common_hdr *ramarea; + const struct HDIF_child_ptr *ramptr; + const struct HDIF_ram_area_id *ram_id; + struct dt_node *ram_node; + u32 chip_id; + const void *vpd_blob; + + ramptr = HDIF_child_arr(msarea, 0); + if (!CHECK_SPPTR(ramptr)) { + prerror("MS AREA: No RAM area at %p\n", msarea); + return; + } + + for (i = 0; i < be32_to_cpu(ramptr->count); i++) { + ramarea = HDIF_child(msarea, ramptr, i, "RAM "); + if (!CHECK_SPPTR(ramarea)) + continue; + + ram_id = HDIF_get_idata(ramarea, 2, &ram_sz); + if (!CHECK_SPPTR(ram_id)) + continue; + + /* Don't add VPD for non-existent RAM */ + if (!(be16_to_cpu(ram_id->flags) & RAM_AREA_INSTALLED)) + continue; + + ram_node = dt_add_vpd_node(ramarea, 0, 1); + if (!ram_node) + continue; + + chip_id = add_chip_id_to_ram_area(msarea, ram_node); + add_bus_freq_to_ram_area(ram_node, chip_id); + + if (ram_sz >= offsetof(struct HDIF_ram_area_id, speed)) { + dt_add_property_cells(ram_node, "frequency", + be32_to_cpu(ram_id->speed)*1000000); + } + + vpd_blob = HDIF_get_idata(ramarea, 1, &ram_sz); + + /* DIMM size */ + add_size_to_ram_area(ram_node, ramarea); + /* + * For direct-attached memory we have a DDR "Serial + * Presence Detection" blob rather than an IBM keyword + * blob. + */ + if (!vpd_valid(vpd_blob, ram_sz)) + dt_add_property(ram_node, "spd", vpd_blob, ram_sz); + } +} + +static void vpd_parse_spd(struct dt_node *dimm, const char *spd, u32 size) +{ + __be16 *vendor; + __be32 *sn; + + /* SPD is too small */ + if (size < 512) { + prlog(PR_WARNING, "MSVPD: Invalid SPD size. " + "Expected 512 bytes, got %d\n", size); + return; + } + + /* Supports DDR4 format pasing only */ + if (spd[0x2] < 0xc) { + prlog(PR_WARNING, + "MSVPD: SPD format (%x) not supported\n", spd[0x2]); + return; + } + + dt_add_property_string(dimm, "device_type", "memory-dimm-ddr4"); + + /* DRAM device type */ + dt_add_property_cells(dimm, "memory-id", spd[0x2]); + + /* Module revision code */ + dt_add_property_cells(dimm, "product-version", spd[0x15d]); + + /* Serial number */ + sn = (__be32 *)&spd[0x145]; + dt_add_property_cells(dimm, "serial-number", be32_to_cpu(*sn)); + + /* Part number */ + dt_add_property_nstr(dimm, "part-number", &spd[0x149], 20); + + /* Module manufacturer ID */ + vendor = (__be16 *)&spd[0x140]; + dt_add_property_cells(dimm, "manufacturer-id", be16_to_cpu(*vendor)); +} + +static void add_dimm_info(struct dt_node *parent, + const struct HDIF_common_hdr *msarea) +{ + unsigned int i, size; + const struct HDIF_child_ptr *ramptr; + const struct HDIF_common_hdr *ramarea; + const struct spira_fru_id *fru_id; + const struct HDIF_ram_area_id *ram_id; + const struct HDIF_ram_area_size *ram_area_sz; + struct dt_node *dimm; + const void *vpd_blob; + + ramptr = HDIF_child_arr(msarea, 0); + if (!CHECK_SPPTR(ramptr)) { + prerror("MS AREA: No RAM area at %p\n", msarea); + return; + } + + for (i = 0; i < be32_to_cpu(ramptr->count); i++) { + ramarea = HDIF_child(msarea, ramptr, i, "RAM "); + if (!CHECK_SPPTR(ramarea)) + continue; + + fru_id = HDIF_get_idata(ramarea, 0, NULL); + if (!fru_id) + continue; + + /* Use Resource ID to add dimm node */ + dimm = dt_find_by_name_addr(parent, "dimm", + be16_to_cpu(fru_id->rsrc_id)); + if (dimm) + continue; + dimm= dt_new_addr(parent, "dimm", be16_to_cpu(fru_id->rsrc_id)); + assert(dimm); + dt_add_property_cells(dimm, "reg", be16_to_cpu(fru_id->rsrc_id)); + + /* Add location code */ + slca_vpd_add_loc_code(dimm, be16_to_cpu(fru_id->slca_index)); + + /* DIMM size */ + ram_area_sz = HDIF_get_idata(ramarea, 3, NULL); + if (!CHECK_SPPTR(ram_area_sz)) + continue; + dt_add_property_cells(dimm, "size", be32_to_cpu(ram_area_sz->mb)); + + /* DIMM state */ + ram_id = HDIF_get_idata(ramarea, 2, NULL); + if (!CHECK_SPPTR(ram_id)) + continue; + + if ((be16_to_cpu(ram_id->flags) & RAM_AREA_INSTALLED) && + (be16_to_cpu(ram_id->flags) & RAM_AREA_FUNCTIONAL)) + dt_add_property_string(dimm, "status", "okay"); + else + dt_add_property_string(dimm, "status", "disabled"); + + vpd_blob = HDIF_get_idata(ramarea, 1, &size); + if (!CHECK_SPPTR(vpd_blob)) + continue; + if (vpd_valid(vpd_blob, size)) + vpd_data_parse(dimm, vpd_blob, size); + else + vpd_parse_spd(dimm, vpd_blob, size); + } +} + +static inline void dt_add_mem_reg_property(struct dt_node *node, u64 addr) +{ + dt_add_property_cells(node, "#address-cells", 1); + dt_add_property_cells(node, "#size-cells", 0); + dt_add_property_cells(node, "reg", addr); +} + +static void add_memory_controller_p9n(const struct HDIF_common_hdr *msarea, + const struct HDIF_ms_area_address_range *arange) +{ + uint32_t chip_id; + uint32_t controller_id, mcbist_id, mcs_id, mca_id; + struct dt_node *xscom, *mcbist, *mcs, *mca; + + chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); + controller_id = be32_to_cpu(arange->controller_id); + xscom = find_xscom_for_chip(chip_id); + if (!xscom) { + prlog(PR_WARNING, + "MS AREA: Can't find XSCOM for chip %d\n", chip_id); + return; + } + + mcbist_id = MS_CONTROLLER_MCBIST_ID(controller_id); + mcbist = dt_find_by_name_addr(xscom, "mcbist", mcbist_id); + if (!mcbist) { + mcbist = dt_new_addr(xscom, "mcbist", mcbist_id); + assert(mcbist); + dt_add_property_cells(mcbist, "#address-cells", 1); + dt_add_property_cells(mcbist, "#size-cells", 0); + dt_add_property_cells(mcbist, "reg", mcbist_id, 0); + } + + mcs_id = MS_CONTROLLER_MCS_ID(controller_id); + mcs = dt_find_by_name_addr(mcbist, "mcs", mcs_id); + if (!mcs) { + mcs = dt_new_addr(mcbist, "mcs", mcs_id); + assert(mcs); + dt_add_mem_reg_property(mcs, mcs_id); + } + + mca_id = MS_CONTROLLER_MCA_ID(controller_id); + mca = dt_find_by_name_addr(mcs, "mca", mca_id); + if (!mca) { + mca = dt_new_addr(mcs, "mca", mca_id); + assert(mca); + dt_add_mem_reg_property(mca, mca_id); + } + + add_dimm_info(mca, msarea); +} + +static void add_memory_buffer_mmio(const struct HDIF_common_hdr *msarea) +{ + const struct HDIF_ms_area_ocmb_mmio *mmio; + uint64_t min_addr = ~0ull, hbrt_id = 0; + const struct HDIF_array_hdr *array; + unsigned int i, count, ranges = 0; + struct dt_node *membuf; + beint64_t *reg, *flags; + + if (proc_gen <= proc_gen_p9 && PVR_TYPE(mfspr(SPR_PVR)) != PVR_TYPE_P9P) + return; + + if (be16_to_cpu(msarea->version) < 0x50) { + prlog(PR_WARNING, "MS AREA: Inconsistent MSAREA version %x for P9P system", + be16_to_cpu(msarea->version)); + return; + } + + array = HDIF_get_iarray(msarea, MSAREA_IDATA_MMIO_IDX, &count); + if (!array || count <= 0) { + prerror("MS AREA: No OCMB MMIO array at MS Area %p\n", msarea); + return; + } + + reg = zalloc(count * 2 * sizeof(*reg)); + flags = zalloc(count * sizeof(*flags)); + + /* grab the hbrt id from the first range. */ + HDIF_iarray_for_each(array, i, mmio) { + hbrt_id = be64_to_cpu(mmio->hbrt_id); + break; + } + + prlog(PR_DEBUG, "Adding memory buffer MMIO ranges for %"PRIx64"\n", + hbrt_id); + + HDIF_iarray_for_each(array, i, mmio) { + uint64_t start, end; + + if (hbrt_id != be64_to_cpu(mmio->hbrt_id)) { + prerror("HBRT ID mismatch!\n"); + continue; + } + + start = cleanup_addr(be64_to_cpu(mmio->range_start)); + end = cleanup_addr(be64_to_cpu(mmio->range_end)); + if (start < min_addr) + min_addr = start; + + prlog(PR_DEBUG, " %"PRIx64" - [%016"PRIx64"-%016"PRIx64")\n", + hbrt_id, start, end); + + reg[2 * ranges ] = cpu_to_be64(start); + reg[2 * ranges + 1] = cpu_to_be64(end - start + 1); + flags[ranges] = mmio->flags; /* both are BE */ + ranges++; + } + + membuf = dt_find_by_name_addr(dt_root, "memory-buffer", min_addr); + if (membuf) { + prerror("attempted to duplicate %s\n", membuf->name); + goto out; + } + + membuf = dt_new_addr(dt_root, "memory-buffer", min_addr); + assert(membuf); + + dt_add_property_string(membuf, "compatible", "ibm,explorer"); + dt_add_property_cells(membuf, "ibm,chip-id", hbrt_id); + + /* + * FIXME: We should probably be sorting the address ranges based + * on the starting address. + */ + dt_add_property(membuf, "reg", reg, sizeof(*reg) * 2 * ranges); + dt_add_property(membuf, "flags", flags, sizeof(*flags) * ranges); + +out: + free(flags); + free(reg); +} + +static void add_memory_controller(const struct HDIF_common_hdr *msarea, + const struct HDIF_ms_area_address_range *arange) +{ + const uint32_t version = PVR_TYPE(mfspr(SPR_PVR)); + /* + * Memory hierarchy may change between processor version. Presently + * it's only creating memory hierarchy for P9 (Nimbus) and P9P (Axone). + */ + + if (version == PVR_TYPE_P9) + return add_memory_controller_p9n(msarea, arange); + else if (version == PVR_TYPE_P9P) + return; //return add_memory_controller_p9p(msarea, arange); + else + return; +} + +static void get_msareas(struct dt_node *root, + const struct HDIF_common_hdr *ms_vpd) +{ + unsigned int i; + const struct HDIF_child_ptr *msptr; + + /* First childptr refers to msareas. */ + msptr = HDIF_child_arr(ms_vpd, MSVPD_CHILD_MS_AREAS); + if (!CHECK_SPPTR(msptr)) { + prerror("MS VPD: no children at %p\n", ms_vpd); + return; + } + + for (i = 0; i < be32_to_cpu(msptr->count); i++) { + const struct HDIF_common_hdr *msarea; + const struct HDIF_array_hdr *arr; + const struct HDIF_ms_area_address_range *arange; + const struct HDIF_ms_area_id *id; + const void *fruid; + unsigned int size, j, offset; + u16 flags; + + msarea = HDIF_child(ms_vpd, msptr, i, "MSAREA"); + if (!CHECK_SPPTR(msarea)) + return; + + id = HDIF_get_idata(msarea, 2, &size); + if (!CHECK_SPPTR(id)) + return; + if (size < sizeof(*id)) { + prerror("MS VPD: %p msarea #%i id size too small!\n", + ms_vpd, i); + return; + } + + flags = be16_to_cpu(id->flags); + prlog(PR_DEBUG, "MS VPD: %p, area %i: %s %s %s\n", + ms_vpd, i, + flags & MS_AREA_INSTALLED ? + "installed" : "not installed", + flags & MS_AREA_FUNCTIONAL ? + "functional" : "not functional", + flags & MS_AREA_SHARED ? + "shared" : "not shared"); + + if ((flags & (MS_AREA_INSTALLED|MS_AREA_FUNCTIONAL)) + != (MS_AREA_INSTALLED|MS_AREA_FUNCTIONAL)) + continue; + + arr = HDIF_get_idata(msarea, 4, &size); + if (!CHECK_SPPTR(arr)) + continue; + + if (size < sizeof(*arr)) { + prerror("MS VPD: %p msarea #%i arr size too small!\n", + ms_vpd, i); + return; + } + + offset = offsetof(struct HDIF_ms_area_address_range, mirror_start); + if (be32_to_cpu(arr->eactsz) < offset) { + prerror("MS VPD: %p msarea #%i arange size too small!\n", + ms_vpd, i); + return; + } + + fruid = HDIF_get_idata(msarea, 0, &size); + if (!CHECK_SPPTR(fruid)) + return; + + /* Add Raiser card VPD */ + if (be16_to_cpu(id->parent_type) & MS_PTYPE_RISER_CARD) + dt_add_vpd_node(msarea, 0, 1); + + /* Add RAM Area VPD */ + vpd_add_ram_area(msarea); + + add_memory_buffer_mmio(msarea); + + /* This offset is from the arr, not the header! */ + arange = (void *)arr + be32_to_cpu(arr->offset); + for (j = 0; j < be32_to_cpu(arr->ecnt); j++) { + uint32_t type = 0, status = 0; + + /* + * Check that the required fields are present in this + * version of the HDAT structure. + */ + offset = offsetof(struct HDIF_ms_area_address_range, controller_id); + if (be32_to_cpu(arr->eactsz) >= offset) + add_memory_controller(msarea, arange); + + offset = offsetof(struct HDIF_ms_area_address_range, phys_attr); + if (be32_to_cpu(arr->eactsz) >= offset) { + uint32_t attr = be32_to_cpu(arange->phys_attr); + + type = GETFIELD(PHYS_ATTR_TYPE_MASK, attr); + status = GETFIELD(PHYS_ATTR_STATUS_MASK, attr); + } + + if (!add_address_range(root, id, arange, type, status)) + prerror("Unable to use memory range %d from MSAREA %d\n", j, i); + + arange = (void *)arange + be32_to_cpu(arr->esize); + } + } +} + +static struct dt_node *dt_hb_reserves; + +static struct dt_node *add_hb_reserve_node(const char *name, u64 start, u64 end) +{ + /* label size + "ibm," + NULL */ + char node_name[HB_RESERVE_MEM_LABEL_SIZE + 5] = { 0 }; + struct dt_node *node, *hb; + + if (!dt_hb_reserves) { + hb = dt_new_check(dt_root, "ibm,hostboot"); + dt_add_property_cells(hb, "#size-cells", 2); + dt_add_property_cells(hb, "#address-cells", 2); + + dt_hb_reserves = dt_new_check(hb, "reserved-memory"); + dt_add_property(dt_hb_reserves, "ranges", NULL, 0); + dt_add_property_cells(dt_hb_reserves, "#size-cells", 2); + dt_add_property_cells(dt_hb_reserves, "#address-cells", 2); + } + + /* Add "ibm," to reserved node name */ + if (strncasecmp(name, "ibm", 3)) + snprintf(node_name, 5, "ibm,"); + strcat(node_name, name); + + node = dt_new_addr(dt_hb_reserves, node_name, start); + if (!node) { + prerror("Unable to create node for %s@%llx\n", + node_name, (unsigned long long) start); + return NULL; + } + + dt_add_property_u64s(node, "reg", start, end - start + 1); + + return node; +} + +static void get_hb_reserved_mem(struct HDIF_common_hdr *ms_vpd) +{ + const struct msvpd_hb_reserved_mem *hb_resv_mem; + u64 start_addr, end_addr, label_size; + struct dt_node *node; + int count, i; + char label[HB_RESERVE_MEM_LABEL_SIZE + 1]; + + /* + * XXX: Reservation names only exist on P9 and on P7/8 we get the + * reserved ranges through the hostboot mini-FDT instead. + */ + if (proc_gen < proc_gen_p9) + return; + + count = HDIF_get_iarray_size(ms_vpd, MSVPD_IDATA_HB_RESERVED_MEM); + if (count <= 0) { + prerror("MS VPD: No hostboot reserved memory found\n"); + return; + } + + for (i = 0; i < count; i++) { + hb_resv_mem = HDIF_get_iarray_item(ms_vpd, + MSVPD_IDATA_HB_RESERVED_MEM, + i, NULL); + if (!CHECK_SPPTR(hb_resv_mem)) + continue; + + label_size = be32_to_cpu(hb_resv_mem->label_size); + start_addr = be64_to_cpu(hb_resv_mem->start_addr); + end_addr = be64_to_cpu(hb_resv_mem->end_addr); + + /* Zero length regions are a normal, but should be ignored */ + if (start_addr - end_addr == 0) { + prlog(PR_DEBUG, "MEM: Ignoring zero length range\n"); + continue; + } + + /* + * Workaround broken HDAT reserve regions which are + * bigger than 512MB + */ + if ((end_addr - start_addr) > 0x20000000) { + prlog(PR_ERR, "MEM: Ignoring Bad HDAT reserve: too big\n"); + continue; + } + + /* remove the HRMOR bypass bit */ + start_addr &= ~HRMOR_BIT; + end_addr &= ~HRMOR_BIT; + if (label_size > HB_RESERVE_MEM_LABEL_SIZE) + label_size = HB_RESERVE_MEM_LABEL_SIZE; + + memset(label, 0, HB_RESERVE_MEM_LABEL_SIZE + 1); + memcpy(label, hb_resv_mem->label, label_size); + label[label_size] = '\0'; + + /* Unnamed reservations are always broken. Ignore them. */ + if (strlen(label) == 0) + continue; + + prlog(PR_DEBUG, "MEM: Reserve '%s' %#" PRIx64 "-%#" PRIx64 " (type/inst=0x%08x)\n", + label, start_addr, end_addr, be32_to_cpu(hb_resv_mem->type_instance)); + + node = add_hb_reserve_node(label, start_addr, end_addr); + if (!node) { + prerror("unable to add node?\n"); + continue; + } + + /* the three low bytes of type_instance is the instance data */ + dt_add_property_cells(node, "ibm,prd-instance", + (be32_to_cpu(hb_resv_mem->type_instance) & 0xffffff)); + + /* + * Most reservations are used by HBRT itself so we should leave + * the label as-is. The exception is hbrt-code-image which is + * used by opal-prd to locate the HBRT image. Older versions + * of opal-prd expect this to be "ibm,hbrt-code-image" so make + * sure the prefix is there. + */ + if (!strcmp(label, "hbrt-code-image")) + strcpy(label, "ibm,hbrt-code-image"); + dt_add_property_string(node, "ibm,prd-label", label); + } +} + +static void parse_trace_reservations(struct HDIF_common_hdr *ms_vpd) +{ + unsigned int size; + int count, i; + + /* + * The trace arrays are only setup when hostboot is explicitly + * configured to enable them. We need to check and gracefully handle + * when they're not present. + */ + + if (!HDIF_get_idata(ms_vpd, MSVPD_IDATA_TRACE_AREAS, &size) || !size) { + prlog(PR_DEBUG, "MS VPD: No trace areas found\n"); + return; + } + + count = HDIF_get_iarray_size(ms_vpd, MSVPD_IDATA_TRACE_AREAS); + if (count <= 0) { + prlog(PR_DEBUG, "MS VPD: No trace areas found\n"); + return; + } + + prlog(PR_INFO, "MS VPD: Found %d trace areas\n", count); + + for (i = 0; i < count; i++) { + const struct msvpd_trace *trace_area; + struct dt_node *node; + u64 start, end; + + trace_area = HDIF_get_iarray_item(ms_vpd, + MSVPD_IDATA_TRACE_AREAS, i, &size); + + if (!trace_area) + return; /* shouldn't happen */ + + start = be64_to_cpu(trace_area->start) & ~HRMOR_BIT; + end = be64_to_cpu(trace_area->end) & ~HRMOR_BIT; + + prlog(PR_INFO, + "MS VPD: Trace area: 0x%.16"PRIx64"-0x%.16"PRIx64"\n", + start, end); + + node = add_hb_reserve_node("trace-area", start, end); + if (!node) { + prerror("MEM: Unable to reserve trace area %p-%p\n", + (void *) start, (void *) end); + continue; + } + + dt_add_property(node, "no-map", NULL, 0); + } +} + +static bool __memory_parse(struct dt_node *root) +{ + struct HDIF_common_hdr *ms_vpd; + const struct msvpd_ms_addr_config *msac; + const struct msvpd_total_config_ms *tcms; + unsigned int size; + + ms_vpd = get_hdif(&spira.ntuples.ms_vpd, MSVPD_HDIF_SIG); + if (!ms_vpd) { + prerror("MS VPD: invalid\n"); + op_display(OP_FATAL, OP_MOD_MEM, 0x0000); + return false; + } + if (be32_to_cpu(spira.ntuples.ms_vpd.act_len) < sizeof(*ms_vpd)) { + prerror("MS VPD: invalid size %u\n", + be32_to_cpu(spira.ntuples.ms_vpd.act_len)); + op_display(OP_FATAL, OP_MOD_MEM, 0x0001); + return false; + } + + prlog(PR_DEBUG, "MS VPD: is at %p\n", ms_vpd); + + msac = HDIF_get_idata(ms_vpd, MSVPD_IDATA_MS_ADDR_CONFIG, &size); + if (!CHECK_SPPTR(msac) || + size < offsetof(struct msvpd_ms_addr_config, max_possible_ms_address)) { + prerror("MS VPD: bad msac size %u @ %p\n", size, msac); + op_display(OP_FATAL, OP_MOD_MEM, 0x0002); + return false; + } + prlog(PR_DEBUG, "MS VPD: MSAC is at %p\n", msac); + + dt_add_property_u64(dt_root, DT_PRIVATE "maxmem", + be64_to_cpu(msac->max_configured_ms_address)); + + tcms = HDIF_get_idata(ms_vpd, MSVPD_IDATA_TOTAL_CONFIG_MS, &size); + if (!CHECK_SPPTR(tcms) || size < sizeof(*tcms)) { + prerror("MS VPD: Bad tcms size %u @ %p\n", size, tcms); + op_display(OP_FATAL, OP_MOD_MEM, 0x0003); + return false; + } + prlog(PR_DEBUG, "MS VPD: TCMS is at %p\n", tcms); + + prlog(PR_DEBUG, "MS VPD: Maximum configured address: 0x%llx\n", + (long long)be64_to_cpu(msac->max_configured_ms_address)); + prlog(PR_DEBUG, "MS VPD: Maximum possible address: 0x%llx\n", + (long long)be64_to_cpu(msac->max_possible_ms_address)); + + get_msareas(root, ms_vpd); + + get_hb_reserved_mem(ms_vpd); + + parse_trace_reservations(ms_vpd); + + prlog(PR_INFO, "MS VPD: Total MB of RAM: 0x%llx\n", + (long long)be64_to_cpu(tcms->total_in_mb)); + + return true; +} + +void memory_parse(void) +{ + if (!__memory_parse(dt_root)) { + prerror("MS VPD: Failed memory init !\n"); + abort(); + } +} diff --git a/roms/skiboot/hdata/naca.c b/roms/skiboot/hdata/naca.c new file mode 100644 index 000000000..9581bb632 --- /dev/null +++ b/roms/skiboot/hdata/naca.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +#include <compiler.h> +#include <mem-map.h> +#include <types.h> + +#include "naca.h" +#include "spira.h" + +__section(".naca.data") struct naca naca = { + .spirah_addr = CPU_TO_BE64(SPIRAH_OFF), + .hv_release_data_addr = CPU_TO_BE64(NACA_OFF + offsetof(struct naca, hv_release_data)), + .spira_addr = CPU_TO_BE64(SPIRA_OFF), + .lid_table_addr = CPU_TO_BE64(NACA_OFF + offsetof(struct naca, hv_lid_load_table)), + .spira_size = CPU_TO_BE32(SPIRA_ACTUAL_SIZE), + .hv_load_map_addr = 0, + .attn_enabled = 0, + .pcia_supported = 1, + .__primary_thread_entry = CPU_TO_BE64(0x180), + .__secondary_thread_entry = CPU_TO_BE64(0x180), + .hv_release_data = { + .vrm = CPU_TO_BE64(0x666), /* ? */ + }, + .hv_lid_load_table = { + .w0 = CPU_TO_BE32(0x10), + .w1 = CPU_TO_BE32(0x10), + }, +}; diff --git a/roms/skiboot/hdata/naca.h b/roms/skiboot/hdata/naca.h new file mode 100644 index 000000000..74e5a2905 --- /dev/null +++ b/roms/skiboot/hdata/naca.h @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2019 IBM Corp. */ + +#ifndef __NACA_H +#define __NACA_H + +#include <compiler.h> +#include <inttypes.h> +#include <types.h> + +struct hv_release_data { + uint8_t reserved_0x0[58]; + __be64 vrm; +} __packed __attribute__((aligned(0x10))); + +struct hv_lid_load_table { + __be32 w0; + __be32 w1; + __be32 w2; + __be32 w3; +} __packed __attribute__((aligned(0x10))); + +/* + * NACA structure, accessed by the FSP to find the SPIRA + */ +struct naca { + __be64 spirah_addr; /* 0x0000 */ + uint8_t reserved_0x8[0x10]; + __be64 hv_release_data_addr; /* 0x0018 */ + uint8_t reserved_0x20[0x10]; + __be64 spira_addr; /* 0x0030 */ + __be64 lid_table_addr; /* 0x0038 */ + uint8_t reserved_0x40[0x60]; + __be32 spira_size; /* 0x00a0 */ + uint8_t reserved_0xa4[0x1c]; + __be64 hv_load_map_addr; /* 0x00c0 */ + uint8_t reserved_0xc8[0xe4]; + uint8_t flags[4]; /* 0x01ac */ + uint8_t reserved_0x1b0[0x5]; + uint8_t attn_enabled; /* 0x01b5 */ + uint8_t reserved_0x1b6[0x1]; + uint8_t pcia_supported; /* 0x01b7 */ + __be64 __primary_thread_entry; /* 0x01b8 */ + __be64 __secondary_thread_entry; /* 0x01c0 */ + uint8_t reserved_0x1d0[0xe38]; + + /* Not part of the naca but it's convenient to put them here */ + struct hv_release_data hv_release_data; + struct hv_lid_load_table hv_lid_load_table; +} __packed __attribute((aligned(0x10))); + +extern struct naca naca; + +#endif diff --git a/roms/skiboot/hdata/pcia.c b/roms/skiboot/hdata/pcia.c new file mode 100644 index 000000000..0b803e2b6 --- /dev/null +++ b/roms/skiboot/hdata/pcia.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#include <skiboot.h> +#include "spira.h" +#include <cpu.h> +#include <fsp.h> +#include <opal.h> +#include <ccan/str/str.h> +#include <device.h> + +#include "hdata.h" + +#define PCIA_MAX_THREADS 8 + +static unsigned int pcia_index(const void *pcia) +{ + return (pcia - (void *)get_hdif(&spira.ntuples.pcia, "SPPCIA")) + / be32_to_cpu(spira.ntuples.pcia.alloc_len); +} + +static const struct sppcia_cpu_thread *find_tada(const void *pcia, + unsigned int thread) +{ + int count = HDIF_get_iarray_size(pcia, SPPCIA_IDATA_THREAD_ARRAY); + int i; + + if (count < 0) + return NULL; + + for (i = 0; i < count; i++) { + const struct sppcia_cpu_thread *t; + unsigned int size; + + t = HDIF_get_iarray_item(pcia, SPPCIA_IDATA_THREAD_ARRAY, + i, &size); + if (!t || size < sizeof(*t)) + continue; + if (be32_to_cpu(t->phys_thread_id) == thread) + return t; + } + return NULL; +} + +static void add_xics_icp(const void *pcia, u32 tcount, const char *compat) +{ + const struct sppcia_cpu_thread *t; + struct dt_node *icp; + __be64 *reg; + u32 i, irange[2], rsize; + + rsize = tcount * 2 * sizeof(__be64); + reg = malloc(rsize); + assert(reg); + + /* Suppresses uninitialized warning from gcc */ + irange[0] = 0; + for (i = 0; i < tcount; i++) { + t = find_tada(pcia, i); + assert(t); + if (i == 0) + irange[0] = be32_to_cpu(t->pir); + reg[i * 2] = cpu_to_be64(cleanup_addr(be64_to_cpu(t->ibase))); + reg[i * 2 + 1] = cpu_to_be64(0x1000); + } + irange[1] = tcount; + + icp = dt_new_addr(dt_root, "interrupt-controller", be64_to_cpu(reg[0])); + if (!icp) { + free(reg); + return; + } + + if (compat) + dt_add_property_strings(icp, "compatible", "ibm,ppc-xicp", compat); + else + dt_add_property_strings(icp, "compatible", "ibm,ppc-xicp"); + dt_add_property_cells(icp, "ibm,interrupt-server-ranges", + irange[0], irange[1]); + dt_add_property(icp, "interrupt-controller", NULL, 0); + dt_add_property(icp, "reg", reg, rsize); + dt_add_property_cells(icp, "#address-cells", 0); + dt_add_property_string(icp, "device_type", + "PowerPC-External-Interrupt-Presentation"); + free(reg); +} + +static struct dt_node *add_core_node(struct dt_node *cpus, + const void *pcia, + const struct sppcia_core_unique *id, + bool okay) +{ + const struct sppcia_cpu_thread *t; + const struct sppcia_cpu_timebase *timebase; + const struct sppcia_cpu_cache *cache; + const struct sppcia_cpu_attr *attr; + struct dt_node *cpu; + const char *icp_compat; + u32 i, size, threads, ve_flags, l2_phandle, chip_id; + __be32 iserv[PCIA_MAX_THREADS]; + + /* Look for thread 0 */ + t = find_tada(pcia, 0); + if (!t) { + prerror("CORE[%i]: Failed to find thread 0 !\n", + pcia_index(pcia)); + return NULL; + } + + ve_flags = be32_to_cpu(id->verif_exist_flags); + threads = ((ve_flags & CPU_ID_NUM_SECONDARY_THREAD_MASK) + >> CPU_ID_NUM_SECONDARY_THREAD_SHIFT) + 1; + assert(threads <= PCIA_MAX_THREADS); + + prlog(PR_INFO, "CORE[%i]: PIR=%.8x %s %s(%u threads)\n", + pcia_index(pcia), be32_to_cpu(t->pir), + ve_flags & CPU_ID_PCIA_RESERVED + ? "**RESERVED**" : cpu_state(ve_flags), + be32_to_cpu(t->pir) == boot_cpu->pir ? "[boot] " : "", threads); + + timebase = HDIF_get_idata(pcia, SPPCIA_IDATA_TIMEBASE, &size); + if (!timebase || size < sizeof(*timebase)) { + prerror("CORE[%i]: bad timebase size %u @ %p\n", + pcia_index(pcia), size, timebase); + return NULL; + } + + cache = HDIF_get_idata(pcia, SPPCIA_IDATA_CPU_CACHE, &size); + if (!cache || size < sizeof(*cache)) { + prerror("CORE[%i]: bad cache size %u @ %p\n", + pcia_index(pcia), size, cache); + return NULL; + } + + cpu = add_core_common(cpus, cache, timebase, + be32_to_cpu(t->pir), okay); + + /* Core attributes */ + attr = HDIF_get_idata(pcia, SPPCIA_IDATA_CPU_ATTR, &size); + if (attr) + add_core_attr(cpu, be32_to_cpu(attr->attr)); + + /* Add cache info */ + l2_phandle = add_core_cache_info(cpus, cache, + be32_to_cpu(t->pir), okay); + dt_add_property_cells(cpu, "l2-cache", l2_phandle); + + if (proc_gen == proc_gen_p8) + icp_compat = "IBM,power8-icp"; + + /* Get HW Chip ID */ + chip_id = pcid_to_chip_id(be32_to_cpu(id->proc_chip_id)); + + dt_add_property_cells(cpu, "ibm,pir", be32_to_cpu(t->pir)); + dt_add_property_cells(cpu, "ibm,chip-id", chip_id); + + /* Build ibm,ppc-interrupt-server#s with all threads */ + for (i = 0; i < threads; i++) { + t = find_tada(pcia, i); + if (!t) { + threads = i; + break; + } + + iserv[i] = t->pir; + } + + dt_add_property(cpu, "ibm,ppc-interrupt-server#s", iserv, 4 * threads); + + /* Add the ICP node for this CPU for P8 */ + if (proc_gen == proc_gen_p8) + add_xics_icp(pcia, threads, icp_compat); + + return cpu; +} + +bool pcia_parse(void) +{ + const void *pcia; + struct dt_node *cpus; + + pcia = get_hdif(&spira.ntuples.pcia, "SPPCIA"); + if (!pcia) + return false; + + prlog(PR_INFO, "Got PCIA !\n"); + + cpus = dt_new(dt_root, "cpus"); + dt_add_property_cells(cpus, "#address-cells", 1); + dt_add_property_cells(cpus, "#size-cells", 0); + + for_each_pcia(pcia) { + const struct sppcia_core_unique *id; + u32 size, ve_flags; + bool okay; + + id = HDIF_get_idata(pcia, SPPCIA_IDATA_CORE_UNIQUE, &size); + if (!id || size < sizeof(*id)) { + prerror("CORE[%i]: bad id size %u @ %p\n", + pcia_index(pcia), size, id); + return false; + } + ve_flags = be32_to_cpu(id->verif_exist_flags); + + switch ((ve_flags & CPU_ID_VERIFY_MASK) + >> CPU_ID_VERIFY_SHIFT) { + case CPU_ID_VERIFY_USABLE_NO_FAILURES: + case CPU_ID_VERIFY_USABLE_FAILURES: + okay = true; + break; + default: + okay = false; + } + + prlog(okay ? PR_INFO : PR_WARNING, + "CORE[%i]: HW_PROC_ID=%i PROC_CHIP_ID=%i EC=0x%x %s\n", + pcia_index(pcia), be32_to_cpu(id->hw_proc_id), + be32_to_cpu(id->proc_chip_id), + be32_to_cpu(id->chip_ec_level), + okay ? "OK" : "UNAVAILABLE"); + + if (!add_core_node(cpus, pcia, id, okay)) + break; + } + return true; +} diff --git a/roms/skiboot/hdata/slca.c b/roms/skiboot/hdata/slca.c new file mode 100644 index 000000000..131e815af --- /dev/null +++ b/roms/skiboot/hdata/slca.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2015 IBM Corp. */ + +#include <device.h> +#include <include/opal-internal.h> +#include <fsp-leds.h> + +#include "spira.h" +#include "hdata.h" + +const struct slca_entry *slca_get_entry(uint16_t slca_index) +{ + struct HDIF_common_hdr *slca_hdr; + int count; + + slca_hdr = get_hdif(&spira.ntuples.slca, SLCA_HDIF_SIG); + if (!slca_hdr) { + prerror("SLCA Invalid\n"); + return NULL; + } + + count = HDIF_get_iarray_size(slca_hdr, SLCA_IDATA_ARRAY); + if (count < 0) { + prerror("SLCA: Can't find SLCA array size!\n"); + return NULL; + } + + if (slca_index < count) { + const struct slca_entry *s_entry; + unsigned int entry_sz; + s_entry = HDIF_get_iarray_item(slca_hdr, SLCA_IDATA_ARRAY, + slca_index, &entry_sz); + + if (s_entry && entry_sz >= sizeof(*s_entry)) + return s_entry; + } else + prlog(PR_NOTICE, + "SLCA: Can't find slca_entry for index %d\n", slca_index); + return NULL; +} + +const char *slca_get_vpd_name(uint16_t slca_index) +{ + const struct slca_entry *s_entry; + + s_entry = slca_get_entry(slca_index); + if (s_entry) + return (const char *)s_entry->fru_id; + else + prlog(PR_NOTICE, + "SLCA: Can't find fru_id for index %d\n", slca_index); + return NULL; +} + +const char *slca_get_loc_code_index(uint16_t slca_index) +{ + const struct slca_entry *s_entry; + + s_entry = slca_get_entry(slca_index); + if (s_entry) + return s_entry->loc_code; + else + prlog(PR_NOTICE, "SLCA: Entry %d bad idata\n", slca_index); + + return NULL; +} + +void slca_vpd_add_loc_code(struct dt_node *node, uint16_t slca_index) +{ + const char *fru_loc_code; + char loc_code[LOC_CODE_SIZE]; + + memset(loc_code, 0, sizeof(loc_code)); + fru_loc_code = slca_get_loc_code_index(slca_index); + if (!fru_loc_code) + return; + + strncpy(loc_code, fru_loc_code, LOC_CODE_SIZE - 1); + dt_add_property(node, "ibm,loc-code", loc_code, strlen(loc_code) + 1); +} + +/* + * Get System Attention Indicator SLCA entry + */ +static const struct slca_entry *slca_get_sai_entry(void) +{ + int count; + unsigned int i; + struct HDIF_common_hdr *slca_hdr; + uint16_t sai_fru_id = SLCA_SAI_INDICATOR_ID; + + slca_hdr = get_hdif(&spira.ntuples.slca, SLCA_HDIF_SIG); + if (!slca_hdr) { + prerror("SLCA Invalid\n"); + return NULL; + } + + count = HDIF_get_iarray_size(slca_hdr, SLCA_IDATA_ARRAY); + if (count < 0) { + prerror("SLCA: Can't find SLCA array size!\n"); + return NULL; + } + + if (proc_gen >= proc_gen_p9 && dt_find_by_path(dt_root, "fsps")) + sai_fru_id = SLCA_SYSTEM_VPD_ID; + + for (i = 0; i < count; i++) { + const struct slca_entry *s_entry; + unsigned int entry_sz; + + s_entry = HDIF_get_iarray_item(slca_hdr, SLCA_IDATA_ARRAY, + i, &entry_sz); + if (s_entry && + VPD_ID(s_entry->fru_id[0], + s_entry->fru_id[1]) == sai_fru_id) { + prlog(PR_TRACE, "SLCA: SAI index: 0x%x\n", + s_entry->my_index); + prlog(PR_TRACE, "SLCA: SAI location code: %s\n", + s_entry->loc_code); + return s_entry; + } + } + + return NULL; +} + +/* + * SLCA structure contains System Attention Indicator location + * code (FRU ID = SA). Add this information to device tree + * (under '/ibm,opal/led'). + */ +void slca_dt_add_sai_node(void) +{ + const struct slca_entry *s_entry; + struct dt_node *led_node, *sai_node; + + s_entry = slca_get_sai_entry(); + if (!s_entry) + return; + + /* Create /ibm,opal node, if its not created already */ + if (!opal_node) + return; + + /* Crete LED parent node */ + led_node = dt_find_by_path(opal_node, DT_PROPERTY_LED_NODE); + if (!led_node) + return; + + if (s_entry->loc_code_len == 0 || + s_entry->loc_code_len > LOC_CODE_SIZE) + return; + + /* Create SAI node */ + sai_node = dt_new(led_node, s_entry->loc_code); + assert(sai_node); + + dt_add_property_string(sai_node, + DT_PROPERTY_LED_TYPES, LED_TYPE_ATTENTION); +} diff --git a/roms/skiboot/hdata/spira.c b/roms/skiboot/hdata/spira.c new file mode 100644 index 000000000..baa23751d --- /dev/null +++ b/roms/skiboot/hdata/spira.c @@ -0,0 +1,1901 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#include <inttypes.h> +#include <device.h> +#include <cpu.h> +#include <vpd.h> +#include <interrupts.h> +#include <ccan/str/str.h> +#include <chip.h> +#include <opal-dump.h> +#include <fsp-attn.h> +#include <fsp-leds.h> +#include <skiboot.h> +#include <vas.h> + +#include "hdata.h" +#include "hostservices.h" +#include "naca.h" +#include "spira.h" + +/* Processor Initialization structure, contains + * the initial NIA and MSR values for the entry + * point + * + * Note: It appears to be ignoring the entry point + * and always going to 0x180 + */ + +static int cpu_type; + +extern struct proc_init_data proc_init_data; + +__section(".procin.data") struct proc_init_data proc_init_data = { + .hdr = HDIF_SIMPLE_HDR("PROCIN", 1, struct proc_init_data), + .regs_ptr = HDIF_IDATA_PTR(offsetof(struct proc_init_data, regs), 0x10), + .regs = { + .nia = CPU_TO_BE64(0x180), + .msr = CPU_TO_BE64(MSR_SF | MSR_HV), + }, +}; + +extern struct cpu_ctl_init_data cpu_ctl_init_data; +extern struct sp_addr_table cpu_ctl_spat_area; +extern struct sp_attn_area cpu_ctl_sp_attn_area1; +extern struct sp_attn_area cpu_ctl_sp_attn_area2; +extern struct hsr_data_area cpu_ctl_hsr_area; + +/* + * cpuctrl.data begins at CPU_CTL_OFF - cpu_ctl_init_data is located there. + * + sizeof(struct cpu_ctl_init_data) - cpu_ctl_spat_area + * + sizeof(struct sp_addr_table) - cpu_ctl_sp_attn_area1 + * + sizeof(struct sp_attn_area) - cpu_ctl_sp_attn_area2 + * + sizeof(struct sp_attn_area) - cpu_ctl_hsr_area + * + * Can't use CPU_TO_BE64 directly on the labels as a constant initialiser. + * + * CPU_CTL_INIT_DATA_OFF is offset from 0, the others are addressed from the + * relocated address (+SKIBOOT_BASE) + */ +#define CPU_CTL_INIT_DATA_OFF (CPU_CTL_OFF) +#define CPU_CTL_SPAT_AREA_OFF (CPU_CTL_INIT_DATA_OFF + sizeof(struct cpu_ctl_init_data) + SKIBOOT_BASE) +#define CPU_CTL_SP_ATTN_AREA1_OFF (ALIGN_UP((CPU_CTL_SPAT_AREA_OFF + sizeof(struct sp_addr_table)), ATTN_AREA_SZ)) +#define CPU_CTL_SP_ATTN_AREA2_OFF (CPU_CTL_SP_ATTN_AREA1_OFF + sizeof(struct sp_attn_area)) +#define CPU_CTL_HSR_AREA_OFF (CPU_CTL_SP_ATTN_AREA2_OFF + sizeof(struct sp_attn_area)) + +__section(".cpuctrl.data") struct hsr_data_area cpu_ctl_hsr_area; +__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area2; +__section(".cpuctrl.data") struct sp_attn_area cpu_ctl_sp_attn_area1; +__section(".cpuctrl.data") struct sp_addr_table cpu_ctl_spat_area; + +__section(".cpuctrl.data") struct cpu_ctl_init_data cpu_ctl_init_data = { + .hdr = HDIF_SIMPLE_HDR(CPU_CTL_HDIF_SIG, 2, struct cpu_ctl_init_data), + .cpu_ctl = HDIF_IDATA_PTR(offsetof(struct cpu_ctl_init_data, cpu_ctl_lt), + sizeof(struct cpu_ctl_legacy_table)), + .cpu_ctl_lt = { + .spat = { + .addr = CPU_TO_BE64(CPU_CTL_SPAT_AREA_OFF), + .size = CPU_TO_BE64(sizeof(struct sp_addr_table)), + }, + .sp_attn_area1 = { + .addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA1_OFF), + .size = CPU_TO_BE64(sizeof(struct sp_attn_area)), + }, + .sp_attn_area2 = { + .addr = CPU_TO_BE64(CPU_CTL_SP_ATTN_AREA2_OFF), + .size = CPU_TO_BE64(sizeof(struct sp_attn_area)), + }, + .hsr_area = { + .addr = CPU_TO_BE64(CPU_CTL_HSR_AREA_OFF), + .size = CPU_TO_BE64(sizeof(struct hsr_data_area)), + }, + }, +}; + +/* Populate MDST table + * + * Note that we only pass sapphire console buffer here so that we can + * capture early failure logs. Later dump component (fsp_dump_mdst_init) + * creates new table with all the memory sections we are interested and + * sends updated table to FSP via MBOX. + * + * To help the FSP distinguishing between TCE tokens and actual physical + * addresses, we set the top bit to 1 on physical addresses + */ + +extern struct mdst_table init_mdst_table[]; + +__section(".mdst.data") struct mdst_table init_mdst_table[2] = { + { + .addr = CPU_TO_BE64(INMEM_CON_START | HRMOR_BIT), + .data_region = DUMP_REGION_CONSOLE, + .dump_type = DUMP_TYPE_SYSDUMP, + .size = CPU_TO_BE32(INMEM_CON_LEN), + }, + { + .addr = CPU_TO_BE64(HBRT_CON_START | HRMOR_BIT), + .data_region = DUMP_REGION_HBRT_LOG, + .dump_type = DUMP_TYPE_SYSDUMP, + .size = CPU_TO_BE32(HBRT_CON_LEN), + }, +}; + +/* SP Interface Root Array, aka SPIRA */ +__section(".spira.data") struct spira spira = { + .hdr = HDIF_SIMPLE_HDR("SPIRA ", SPIRA_VERSION, struct spira), + .ntuples_ptr = HDIF_IDATA_PTR(offsetof(struct spira, ntuples), + sizeof(struct spira_ntuples)), + .ntuples = { + .array_hdr = { + .offset = CPU_TO_BE32(HDIF_ARRAY_OFFSET), + .ecnt = CPU_TO_BE32(SPIRA_NTUPLES_COUNT), + .esize + = CPU_TO_BE32(sizeof(struct spira_ntuple)), + .eactsz = CPU_TO_BE32(0x18), + }, + /* We only populate some n-tuples */ + .proc_init = { + .addr = CPU_TO_BE64(PROCIN_OFF), + .alloc_cnt = CPU_TO_BE16(1), + .act_cnt = CPU_TO_BE16(1), + .alloc_len + = CPU_TO_BE32(sizeof(struct proc_init_data)), + }, + .heap = { + .addr = CPU_TO_BE64(SPIRA_HEAP_BASE), + .alloc_cnt = CPU_TO_BE16(1), + .alloc_len = CPU_TO_BE32(SPIRA_HEAP_SIZE), + }, + .mdump_src = { + .addr = CPU_TO_BE64(MDST_TABLE_OFF), + .alloc_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)), + .act_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)), + .alloc_len = + CPU_TO_BE32(sizeof(init_mdst_table)), + }, + .cpu_ctrl = { + .addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF), + .alloc_cnt = CPU_TO_BE16(1), + .act_cnt = CPU_TO_BE16(1), + .alloc_len = CPU_TO_BE32(sizeof(cpu_ctl_init_data)), + }, + }, +}; + +/* The Hypervisor SPIRA-H Structure */ +__section(".spirah.data") struct spirah spirah = { + .hdr = HDIF_SIMPLE_HDR(SPIRAH_HDIF_SIG, SPIRAH_VERSION, struct spirah), + .ntuples_ptr = HDIF_IDATA_PTR(offsetof(struct spirah, ntuples), + sizeof(struct spirah_ntuples)), + .ntuples = { + .array_hdr = { + .offset = CPU_TO_BE32(HDIF_ARRAY_OFFSET), + .ecnt = CPU_TO_BE32(SPIRAH_NTUPLES_COUNT), + .esize + = CPU_TO_BE32(sizeof(struct spira_ntuple)), + .eactsz = CPU_TO_BE32(0x18), + }, + /* Host Data Areas */ + .hs_data_area = { + .addr = CPU_TO_BE64(SPIRA_HEAP_BASE), + .alloc_cnt = CPU_TO_BE16(1), + .alloc_len = CPU_TO_BE32(SPIRA_HEAP_SIZE), + }, + /* We only populate some n-tuples */ + .proc_init = { + .addr = CPU_TO_BE64(PROCIN_OFF), + .alloc_cnt = CPU_TO_BE16(1), + .act_cnt = CPU_TO_BE16(1), + .alloc_len + = CPU_TO_BE32(sizeof(struct proc_init_data)), + }, + .cpu_ctrl = { + .addr = CPU_TO_BE64(CPU_CTL_INIT_DATA_OFF), + .alloc_cnt = CPU_TO_BE16(1), + .act_cnt = CPU_TO_BE16(1), + .alloc_len = + CPU_TO_BE32(sizeof(cpu_ctl_init_data)), + }, + .mdump_src = { + .addr = CPU_TO_BE64(MDST_TABLE_OFF), + .alloc_cnt = CPU_TO_BE16(MDST_TABLE_SIZE / sizeof(struct mdst_table)), + .act_cnt = CPU_TO_BE16(ARRAY_SIZE(init_mdst_table)), + .alloc_len = CPU_TO_BE32(sizeof(struct mdst_table)), + .act_len = CPU_TO_BE32(sizeof(struct mdst_table)), + }, + .mdump_dst = { + .addr = CPU_TO_BE64(MDDT_TABLE_OFF), + .alloc_cnt = CPU_TO_BE16(MDDT_TABLE_SIZE / sizeof(struct mddt_table)), + .act_cnt = CPU_TO_BE16(0), + .alloc_len = CPU_TO_BE32(sizeof(struct mddt_table)), + .act_len = CPU_TO_BE32(sizeof(struct mddt_table)), + }, + .mdump_res = { + .addr = CPU_TO_BE64(MDRT_TABLE_BASE), + .alloc_cnt = CPU_TO_BE16(MDRT_TABLE_SIZE / sizeof(struct mdrt_table)), + /* + * XXX: Ideally hostboot should use allocated count and + * length. But looks like hostboot uses actual count + * and length to get MDRT table size. And post dump + * hostboot will update act_cnt. Hence update both + * alloc_cnt and act_cnt. + */ + .act_cnt = CPU_TO_BE16(MDRT_TABLE_SIZE / sizeof(struct mdrt_table)), + .alloc_len = CPU_TO_BE32(sizeof(struct mdrt_table)), + .act_len = CPU_TO_BE32(sizeof(struct mdrt_table)), + }, + .proc_dump_area = { + .addr = CPU_TO_BE64(PROC_DUMP_AREA_OFF), + .alloc_cnt = CPU_TO_BE16(1), + .act_cnt = CPU_TO_BE16(1), + .alloc_len = CPU_TO_BE32(sizeof(struct proc_dump_area)), + .act_len = CPU_TO_BE32(sizeof(struct proc_dump_area)), + }, + }, +}; + +/* The service processor SPIRA-S structure */ +struct spiras *spiras; + +/* Overridden for testing. */ +#ifndef spira_check_ptr +bool spira_check_ptr(const void *ptr, const char *file, unsigned int line) +{ + if (!ptr) + return false; + if (((unsigned long)ptr) >= SPIRA_HEAP_BASE && + ((unsigned long)ptr) < (SPIRA_HEAP_BASE + SPIRA_HEAP_SIZE)) + return true; + + prerror("SPIRA: Bad pointer %p at %s line %d\n", ptr, file, line); + return false; +} +#endif + +struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n, const char id[], + const char *file, int line) +{ + struct HDIF_common_hdr *h = ntuple_addr(n); + u16 act_cnt, alloc_cnt; + u32 act_len, alloc_len; + + if (!spira_check_ptr(h, file, line)) + return NULL; + + act_cnt = be16_to_cpu(n->act_cnt); + alloc_cnt = be16_to_cpu(n->alloc_cnt); + + if (act_cnt > alloc_cnt) { + prerror("SPIRA: bad ntuple, act_cnt > alloc_cnt (%u > %u)\n", + act_cnt, alloc_cnt); + return NULL; + } + + act_len = be32_to_cpu(n->act_len); + alloc_len = be32_to_cpu(n->alloc_len); + + if (act_len > alloc_len) { + prerror("SPIRA: bad ntuple, act_len > alloc_len (%u > %u)\n", + act_len, alloc_len); + return NULL; + } + + if (!HDIF_check(h, id)) { + prerror("SPIRA: bad tuple %p: expected %s at %s line %d\n", + h, id, file, line); + return NULL; + } + return h; +} + +uint32_t get_xscom_id(const struct sppcrd_chip_info *cinfo) +{ + if (proc_gen <= proc_gen_p9) + return be32_to_cpu(cinfo->xscom_id); + + /* On P10 use Processor fabric topology id for chip id */ + return (uint32_t)(cinfo->fab_topology_id); +} + +static struct dt_node *add_xscom_node(uint64_t base, + const struct sppcrd_chip_info *cinfo) +{ + struct dt_node *node; + uint64_t addr, size; + uint64_t freq; + uint32_t hw_id = get_xscom_id(cinfo); + uint32_t proc_chip_id = be32_to_cpu(cinfo->proc_chip_id); + + switch (proc_gen) { + case proc_gen_p8: + /* On P8 all the chip SCOMs share single region */ + addr = base | ((uint64_t)hw_id << PPC_BITLSHIFT(28)); + break; + case proc_gen_p9: + /* On P9 we need to put the chip ID in the natural powerbus + * position. + */ + addr = base | (((uint64_t)hw_id) << 42); + break; + case proc_gen_p10: + default: + /* Use Primary topology table index for xscom address */ + addr = base | (((uint64_t)cinfo->topology_id_table[cinfo->primary_topology_loc]) << 44); + break; + }; + + size = (u64)1 << PPC_BITLSHIFT(28); + + prlog(PR_INFO, "XSCOM: Found HW ID 0x%x (PCID 0x%x) @ 0x%llx\n", + hw_id, proc_chip_id, (long long)addr); + + node = dt_new_addr(dt_root, "xscom", addr); + assert(node); + + dt_add_property_cells(node, "ibm,chip-id", hw_id); + dt_add_property_cells(node, "ibm,proc-chip-id", proc_chip_id); + dt_add_property_cells(node, "#address-cells", 1); + dt_add_property_cells(node, "#size-cells", 1); + dt_add_property(node, "scom-controller", NULL, 0); + + switch(proc_gen) { + case proc_gen_p8: + dt_add_property_strings(node, "compatible", + "ibm,xscom", "ibm,power8-xscom"); + break; + case proc_gen_p9: + dt_add_property_strings(node, "compatible", + "ibm,xscom", "ibm,power9-xscom"); + break; + case proc_gen_p10: + dt_add_property_strings(node, "compatible", + "ibm,xscom", "ibm,power10-xscom"); + break; + default: + dt_add_property_strings(node, "compatible", "ibm,xscom"); + } + dt_add_property_u64s(node, "reg", addr, size); + + /* + * The bus-frequency of the xscom node is actually the PIB/PCB + * frequency. It is derived from the nest-clock via a 4:1 divider + */ + freq = dt_prop_get_u64_def(dt_root, "nest-frequency", 0); + freq /= 4; + if (freq) + dt_add_property_u64(node, "bus-frequency", freq); + + return node; +} + +/* + * Given a xscom@ node this will return a pointer into the SPPCRD + * structure corresponding to that node + */ +#define GET_HDIF_HDR -1 +static const void *xscom_to_pcrd(struct dt_node *xscom, int idata_index) +{ + struct spira_ntuple *t = &spira.ntuples.proc_chip; + const struct HDIF_common_hdr *hdif; + const void *idata; + unsigned int size; + uint32_t i; + void *base; + + i = dt_prop_get_u32_def(xscom, DT_PRIVATE "sppcrd-index", 0xffffffff); + if (i == 0xffffffff) + return NULL; + + base = get_hdif(t, "SPPCRD"); + assert(base); + assert(i < be16_to_cpu(t->act_cnt)); + + hdif = base + i * be32_to_cpu(t->alloc_len); + assert(hdif); + + if (idata_index == GET_HDIF_HDR) + return hdif; + + idata = HDIF_get_idata(hdif, idata_index, &size); + if (!idata || !size) + return NULL; + + return idata; +} + +struct dt_node *find_xscom_for_chip(uint32_t chip_id) +{ + struct dt_node *node; + uint32_t id; + + dt_for_each_compatible(dt_root, node, "ibm,xscom") { + id = dt_get_chip_id(node); + if (id == chip_id) + return node; + } + + return NULL; +} + +static void add_psihb_node(struct dt_node *np) +{ + u32 psi_scom, psi_slen; + const char *psi_comp; + + /* + * We add a few things under XSCOM that aren't added + * by any other HDAT path + */ + + /* PSI host bridge */ + switch(proc_gen) { + case proc_gen_p8: + psi_scom = 0x2010900; + psi_slen = 0x20; + psi_comp = "ibm,power8-psihb-x"; + break; + case proc_gen_p9: + psi_scom = 0x5012900; + psi_slen = 0x100; + psi_comp = "ibm,power9-psihb-x"; + break; + case proc_gen_p10: + psi_scom = 0x3011d00; + psi_slen = 0x100; + psi_comp = "ibm,power10-psihb-x"; + break; + default: + psi_comp = NULL; + } + if (psi_comp) { + struct dt_node *psi_np; + + psi_np = dt_new_addr(np, "psihb", psi_scom); + if (!psi_np) + return; + + dt_add_property_cells(psi_np, "reg", psi_scom, psi_slen); + dt_add_property_strings(psi_np, "compatible", psi_comp, + "ibm,psihb-x"); + } +} + +static void add_xive_node(struct dt_node *np) +{ + struct dt_node *xive; + const char *comp; + u32 scom, slen; + + switch (proc_gen) { + case proc_gen_p9: + scom = 0x5013000; + slen = 0x300; + comp = "ibm,power9-xive-x"; + break; + case proc_gen_p10: + scom = 0x2010800; + slen = 0x400; + comp = "ibm,power10-xive-x"; + break; + default: + return; + } + + xive = dt_new_addr(np, "xive", scom); + dt_add_property_cells(xive, "reg", scom, slen); + dt_add_property_string(xive, "compatible", comp); + + /* HACK: required for simics */ + dt_add_property(xive, "force-assign-bars", NULL, 0); +} + +static void add_vas_node(struct dt_node *np, int idx) +{ + struct dt_node *vas; + const char *comp; + uint64_t base_addr; + + if (proc_gen == proc_gen_p9) { + base_addr = P9_VAS_SCOM_BASE_ADDR; + comp = "ibm,power9-vas-x"; + } else { + base_addr = VAS_SCOM_BASE_ADDR; + comp = "ibm,power10-vas-x"; + } + + vas = dt_new_addr(np, "vas", base_addr); + dt_add_property_cells(vas, "reg", base_addr, 0x300); + dt_add_property_string(vas, "compatible", comp); + dt_add_property_cells(vas, "ibm,vas-id", idx); +} + +static void add_ecid_data(const struct HDIF_common_hdr *hdr, + struct dt_node *xscom) +{ + char wafer_id[11]; + uint8_t tmp; + int i; + uint32_t size = 0; + struct sppcrd_ecid *ecid; + const struct HDIF_array_hdr *ec_hdr; + + ec_hdr = HDIF_get_idata(hdr, SPPCRD_IDATA_EC_LEVEL, &size); + if (!ec_hdr || !size) + return; + + ecid = (void *)ec_hdr + be32_to_cpu(ec_hdr->offset); + dt_add_property_u64s(xscom, "ecid", be64_to_cpu(ecid->low), + be64_to_cpu(ecid->high)); + + /* + * bits 4:63 of ECID data contains wafter ID data (ten 6 bit fields + * each containing a code). + */ + for (i = 0; i < 10; i++) { + tmp = (u8)((be64_to_cpu(ecid->low) >> (i * 6)) & 0x3f); + if (tmp <= 9) + wafer_id[9 - i] = tmp + '0'; + else if (tmp >= 0xA && tmp <= 0x23) + wafer_id[9 - i] = tmp + '0' + 7; + else if (tmp == 0x3D) + wafer_id[9 - i] = '-'; + else if (tmp == 0x3E) + wafer_id[9 - i] = '.'; + else if (tmp == 0x3F) + wafer_id[9 - i] = ' '; + else /* Unknown code */ + wafer_id[9 - i] = tmp + '0'; + } + wafer_id[10] = '\0'; + dt_add_property_nstr(xscom, "wafer-id", wafer_id, 10); + + dt_add_property_cells(xscom, "wafer-location", + (u32)((be64_to_cpu(ecid->high) >> 56) & 0xff), + (u32)((be64_to_cpu(ecid->high) >> 48) & 0xff)); +} + +static void add_xscom_add_pcia_assoc(struct dt_node *np, uint32_t pcid) +{ + const struct HDIF_common_hdr *hdr; + u32 size; + + + /* + * The SPPCRD doesn't contain all the affinity data, we have + * to dig it out of a core. I assume this is so that node + * affinity can be different for groups of cores within the + * chip, but for now we are going to ignore that + */ + hdr = get_hdif(&spira.ntuples.pcia, SPPCIA_HDIF_SIG); + if (!hdr) + return; + + for_each_pcia(hdr) { + const struct sppcia_core_unique *id; + + id = HDIF_get_idata(hdr, SPPCIA_IDATA_CORE_UNIQUE, &size); + if (!id || size < sizeof(*id)) + continue; + + if (be32_to_cpu(id->proc_chip_id) != pcid) + continue; + + dt_add_property_cells(np, "ibm,ccm-node-id", + be32_to_cpu(id->ccm_node_id)); + dt_add_property_cells(np, "ibm,hw-card-id", + be32_to_cpu(id->hw_card_id)); + dt_add_property_cells(np, "ibm,hw-module-id", + be32_to_cpu(id->hw_module_id)); + if (!dt_find_property(np, "ibm,dbob-id")) + dt_add_property_cells(np, "ibm,dbob-id", + be32_to_cpu(id->drawer_book_octant_blade_id)); + if (proc_gen < proc_gen_p9) { + dt_add_property_cells(np, "ibm,mem-interleave-scope", + be32_to_cpu(id->memory_interleaving_scope)); + } + return; + } +} + +static bool add_xscom_sppcrd(uint64_t xscom_base) +{ + const struct HDIF_common_hdr *hdif; + unsigned int i, vpd_sz; + const void *vpd; + struct dt_node *np, *vpd_node; + + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, + SPPCRD_HDIF_SIG) { + const struct sppcrd_chip_info *cinfo; + const struct spira_fru_id *fru_id = NULL; + unsigned int csize; + u32 ve, version; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, &csize); + if (!CHECK_SPPTR(cinfo)) { + prerror("XSCOM: Bad ChipID data %d\n", i); + continue; + } + + ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK; + ve >>= CHIP_VERIFY_SHIFT; + if (ve == CHIP_VERIFY_NOT_INSTALLED || + ve == CHIP_VERIFY_UNUSABLE) + continue; + + /* Create the XSCOM node */ + np = add_xscom_node(xscom_base, cinfo); + if (!np) + continue; + + + dt_add_property_cells(np, DT_PRIVATE "sppcrd-index", i); + + version = be16_to_cpu(hdif->version); + + /* Version 0A has additional OCC related stuff */ + if (version >= 0x000a) { + if (!dt_find_property(np, "ibm,dbob-id")) + dt_add_property_cells(np, "ibm,dbob-id", + be32_to_cpu(cinfo->dbob_id)); + dt_add_property_cells(np, "ibm,occ-functional-state", + be32_to_cpu(cinfo->occ_state)); + } + + /* Add chip VPD */ + vpd_node = dt_add_vpd_node(hdif, SPPCRD_IDATA_FRU_ID, + SPPCRD_IDATA_KW_VPD); + if (vpd_node) + dt_add_property_cells(vpd_node, "ibm,chip-id", + get_xscom_id(cinfo)); + + fru_id = HDIF_get_idata(hdif, SPPCRD_IDATA_FRU_ID, NULL); + if (fru_id) + slca_vpd_add_loc_code(np, be16_to_cpu(fru_id->slca_index)); + + /* Add module VPD on version A and later */ + if (version >= 0x000a) { + vpd = HDIF_get_idata(hdif, SPPCRD_IDATA_MODULE_VPD, + &vpd_sz); + if (CHECK_SPPTR(vpd)) { + dt_add_property(np, "ibm,module-vpd", vpd, + vpd_sz); + vpd_data_parse(np, vpd, vpd_sz); + if (vpd_node) + dt_add_proc_vendor(vpd_node, vpd, vpd_sz); + } + } + + /* + * Extract additional associativity information from + * the core data. Pick one core on that chip + */ + add_xscom_add_pcia_assoc(np, be32_to_cpu(cinfo->proc_chip_id)); + + /* Add PSI Host bridge */ + add_psihb_node(np); + + if (proc_gen >= proc_gen_p9) { + add_xive_node(np); + parse_i2c_devs(hdif, SPPCRD_IDATA_HOST_I2C, np); + add_vas_node(np, i); + add_ecid_data(hdif, np); + + if (be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASTER_PROC) + dt_add_property(np, "primary", NULL, 0); + } + + /* + * Add sw checkstop scom address (ibm,sw-checkstop-fir) + * + * The latest HDAT versions have sw checkstop scom address + * info. But not sure from which version onwards (at least + * HDAT spec do not mention that explicitly). Hence use the + * sppcrd struct size returned by HDIF_get_idata to figure out + * whether it contains sw checkstop scom address info. Also + * check if sw_xstop_fir_scom address is non-zero. + */ + if ((csize >= (offsetof(struct sppcrd_chip_info, + sw_xstop_fir_bitpos) + 1)) && + cinfo->sw_xstop_fir_scom) { + uint8_t fir_bit = cinfo->sw_xstop_fir_bitpos; + + if (!dt_find_property(dt_root, "ibm,sw-checkstop-fir")) + dt_add_property_cells(dt_root, + "ibm,sw-checkstop-fir", + be32_to_cpu(cinfo->sw_xstop_fir_scom), + fir_bit); + } + + if (proc_gen >= proc_gen_p10) { + uint8_t primary_loc = cinfo->primary_topology_loc; + + if (primary_loc >= CHIP_MAX_TOPOLOGY_ENTRIES) { + prerror("XSCOM: Invalid primary topology index %d\n", + primary_loc); + continue; + } + dt_add_property_cells(np, "ibm,primary-topology-index", + cinfo->topology_id_table[primary_loc]); + } + } + + return i > 0; +} + +static void add_xscom(void) +{ + const void *ms_vpd; + const struct msvpd_pmover_bsr_synchro *pmbs; + unsigned int size; + uint64_t xscom_base; + + ms_vpd = get_hdif(&spira.ntuples.ms_vpd, MSVPD_HDIF_SIG); + if (!ms_vpd) { + prerror("XSCOM: Can't find MS VPD\n"); + return; + } + + pmbs = HDIF_get_idata(ms_vpd, MSVPD_IDATA_PMOVER_SYNCHRO, &size); + if (!CHECK_SPPTR(pmbs) || size < sizeof(*pmbs)) { + prerror("XSCOM: absent or bad PMBS size %u @ %p\n", size, pmbs); + return; + } + + if (!(be32_to_cpu(pmbs->flags) & MSVPD_PMS_FLAG_XSCOMBASE_VALID)) { + prerror("XSCOM: No XSCOM base in PMBS, using default\n"); + return; + } + + xscom_base = be64_to_cpu(pmbs->xscom_addr); + + /* Get rid of the top bits */ + xscom_base = cleanup_addr(xscom_base); + + /* First, try the new proc_chip ntuples for chip data */ + if (add_xscom_sppcrd(xscom_base)) + return; +} + +static void add_chiptod_node(unsigned int chip_id, int flags) +{ + struct dt_node *node, *xscom_node; + const char *compat_str; + uint32_t addr, len; + + if ((flags & CHIPTOD_ID_FLAGS_STATUS_MASK) != + CHIPTOD_ID_FLAGS_STATUS_OK) + return; + + xscom_node = find_xscom_for_chip(chip_id); + if (!xscom_node) { + prerror("CHIPTOD: No xscom for chiptod %d?\n", chip_id); + return; + } + + addr = 0x40000; + len = 0x34; + + switch(proc_gen) { + case proc_gen_p8: + compat_str = "ibm,power8-chiptod"; + break; + case proc_gen_p9: + compat_str = "ibm,power9-chiptod"; + break; + case proc_gen_p10: + compat_str = "ibm,power10-chiptod"; + break; + default: + return; + } + + prlog(PR_DEBUG, "CHIPTOD: Found on chip 0x%x %s\n", chip_id, + (flags & CHIPTOD_ID_FLAGS_PRIMARY) ? "[primary]" : + ((flags & CHIPTOD_ID_FLAGS_SECONDARY) ? "[secondary]" : "")); + + node = dt_new_addr(xscom_node, "chiptod", addr); + if (!node) + return; + + dt_add_property_cells(node, "reg", addr, len); + dt_add_property_strings(node, "compatible", "ibm,power-chiptod", + compat_str); + + if (flags & CHIPTOD_ID_FLAGS_PRIMARY) + dt_add_property(node, "primary", NULL, 0); + if (flags & CHIPTOD_ID_FLAGS_SECONDARY) + dt_add_property(node, "secondary", NULL, 0); +} + +static bool add_chiptod_old(void) +{ + const void *hdif; + unsigned int i; + bool found = false; + + /* + * Locate chiptod ID structures in SPIRA + */ + if (!get_hdif(&spira.ntuples.chip_tod, "TOD ")) + return found; + + for_each_ntuple_idx(&spira.ntuples.chip_tod, hdif, i, "TOD ") { + const struct chiptod_chipid *id; + + id = HDIF_get_idata(hdif, CHIPTOD_IDATA_CHIPID, NULL); + if (!CHECK_SPPTR(id)) { + prerror("CHIPTOD: Bad ChipID data %d\n", i); + continue; + } + + add_chiptod_node(pcid_to_chip_id(be32_to_cpu(id->chip_id)), + be32_to_cpu(id->flags)); + found = true; + } + return found; +} + +static bool add_chiptod_new(void) +{ + const void *hdif; + unsigned int i; + bool found = false; + + /* + * Locate Proc Chip ID structures in SPIRA + */ + if (!get_hdif(&spira.ntuples.proc_chip, SPPCRD_HDIF_SIG)) + return found; + + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, + SPPCRD_HDIF_SIG) { + const struct sppcrd_chip_info *cinfo; + const struct sppcrd_chip_tod *tinfo; + unsigned int size; + u32 ve, flags; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL); + if (!CHECK_SPPTR(cinfo)) { + prerror("CHIPTOD: Bad ChipID data %d\n", i); + continue; + } + + ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK; + ve >>= CHIP_VERIFY_SHIFT; + if (ve == CHIP_VERIFY_NOT_INSTALLED || + ve == CHIP_VERIFY_UNUSABLE) + continue; + + tinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_TOD, &size); + if (!CHECK_SPPTR(tinfo)) { + prerror("CHIPTOD: Bad TOD data %d\n", i); + continue; + } + + flags = be32_to_cpu(tinfo->flags); + + /* The FSP may strip the chiptod info from HDAT; if we find + * a zero-ed out entry, assume that the chiptod is + * present, but we don't have any primary/secondary info. In + * this case, pick chip zero as the master. + */ + if (!size) { + flags = CHIPTOD_ID_FLAGS_STATUS_OK; + if (be32_to_cpu(cinfo->xscom_id) == 0x0) + flags |= CHIPTOD_ID_FLAGS_PRIMARY; + } + + add_chiptod_node(get_xscom_id(cinfo), flags); + found = true; + } + return found; +} + +static void add_nx_node(u32 gcid) +{ + struct dt_node *nx; + u32 addr; + u32 size; + struct dt_node *xscom; + + xscom = find_xscom_for_chip(gcid); + if (xscom == NULL) { + prerror("NX%d: did not found xscom node.\n", gcid); + return; + } + + /* + * The NX register space is relatively self contained on P7+ but + * a bit more messy on P8. However it's all contained within the + * PB chiplet port 1 so we'll stick to that in the "reg" property + * and let the NX "driver" deal with the details. + */ + addr = 0x2010000; + size = 0x0004000; + + nx = dt_new_addr(xscom, "nx", addr); + if (!nx) + return; + + switch (proc_gen) { + case proc_gen_p8: + dt_add_property_strings(nx, "compatible", "ibm,power-nx", + "ibm,power8-nx"); + break; + case proc_gen_p9: + case proc_gen_p10: + /* POWER9 NX is not software compatible with P8 NX */ + dt_add_property_strings(nx, "compatible", "ibm,power9-nx"); + break; + default: + return; + } + + dt_add_property_cells(nx, "reg", addr, size); +} + +static void add_nx(void) +{ + unsigned int i; + void *hdif; + + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, + SPPCRD_HDIF_SIG) { + const struct sppcrd_chip_info *cinfo; + u32 ve; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL); + if (!CHECK_SPPTR(cinfo)) { + prerror("NX: Bad ChipID data %d\n", i); + continue; + } + + ve = be32_to_cpu(cinfo->verif_exist_flags) & CHIP_VERIFY_MASK; + ve >>= CHIP_VERIFY_SHIFT; + if (ve == CHIP_VERIFY_NOT_INSTALLED || + ve == CHIP_VERIFY_UNUSABLE) + continue; + + if (cinfo->nx_state) + add_nx_node(get_xscom_id(cinfo)); + } +} + +static void add_nmmu(void) +{ + struct dt_node *xscom, *nmmu; + u32 scom; + + /* Nest MMU only exists on POWER9 or later */ + if (proc_gen < proc_gen_p9) + return; + + if (proc_gen == proc_gen_p9) + scom = 0x5012c40; + else + scom = 0x2010c40; + + dt_for_each_compatible(dt_root, xscom, "ibm,xscom") { + nmmu = dt_new_addr(xscom, "nmmu", scom); + dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu"); + dt_add_property_cells(nmmu, "reg", scom, 0x20); + } +} + +static void dt_init_secureboot_node(const struct iplparams_sysparams *sysparams) +{ + struct dt_node *node; + u16 sys_sec_setting; + u16 hw_key_hash_size; + u16 host_fw_key_clear; + + node = dt_new(dt_root, "ibm,secureboot"); + assert(node); + + dt_add_property_strings(node, "compatible", + "ibm,secureboot", "ibm,secureboot-v2"); + + sys_sec_setting = be16_to_cpu(sysparams->sys_sec_setting); + if (sys_sec_setting & SEC_CONTAINER_SIG_CHECKING) + dt_add_property(node, "secure-enabled", NULL, 0); + if (sys_sec_setting & SEC_HASHES_EXTENDED_TO_TPM) + dt_add_property(node, "trusted-enabled", NULL, 0); + if (sys_sec_setting & PHYSICAL_PRESENCE_ASSERTED) + dt_add_property(node, "physical-presence-asserted", NULL, 0); + + host_fw_key_clear = be16_to_cpu(sysparams->host_fw_key_clear); + if (host_fw_key_clear & KEY_CLEAR_OS_KEYS) + dt_add_property(node, "clear-os-keys", NULL, 0); + if (host_fw_key_clear & KEY_CLEAR_MFG) + dt_add_property(node, "clear-mfg-keys", NULL, 0); + if (host_fw_key_clear & KEY_CLEAR_ALL) + dt_add_property(node, "clear-all-keys", NULL, 0); + + hw_key_hash_size = be16_to_cpu(sysparams->hw_key_hash_size); + + /* Prevent hw-key-hash buffer overflow by truncating hw-key-hash-size if + * it is bigger than the hw-key-hash buffer. + * Secure boot will be enforced later in skiboot, if the hw-key-hash-size + * was not supposed to be SYSPARAMS_HW_KEY_HASH_MAX. + */ + if (hw_key_hash_size > SYSPARAMS_HW_KEY_HASH_MAX) { + prlog(PR_ERR, "IPLPARAMS: hw-key-hash-size=%d too big, " + "truncating to %d\n", hw_key_hash_size, + SYSPARAMS_HW_KEY_HASH_MAX); + hw_key_hash_size = SYSPARAMS_HW_KEY_HASH_MAX; + } + + dt_add_property(node, "hw-key-hash", sysparams->hw_key_hash, + hw_key_hash_size); + dt_add_property_cells(node, "hw-key-hash-size", hw_key_hash_size); +} + +static void opal_dump_add_mpipl_boot(const struct iplparams_iplparams *p) +{ + u32 mdrt_cnt = be16_to_cpu(spira.ntuples.mdump_res.act_cnt); + u32 mdrt_max_cnt = MDRT_TABLE_SIZE / sizeof(struct mdrt_table); + struct dt_node *dump_node; + + dump_node = dt_find_by_path(opal_node, "dump"); + if (!dump_node) + return; + + /* Check boot params to detect MPIPL boot or not */ + if (p->cec_ipl_maj_type != IPLPARAMS_MAJ_TYPE_REIPL) + return; + + /* + * On FSP system we get minor type as post dump IPL and on BMC system + * we get platform reboot. Hence lets check for both values. + */ + if (p->cec_ipl_min_type != IPLPARAMS_MIN_TYPE_POST_DUMP && + p->cec_ipl_min_type != IPLPARAMS_MIN_TYPE_PLAT_REBOOT) { + prlog(PR_NOTICE, "DUMP: Non MPIPL reboot " + "[minor type = 0x%x]\n", p->cec_ipl_min_type); + return; + } + + if (be16_to_cpu(p->cec_ipl_attrib) != IPLPARAMS_ATTRIB_MEM_PRESERVE) { + prlog(PR_DEBUG, "DUMP: Memory not preserved\n"); + return; + } + + if (mdrt_cnt == 0 || mdrt_cnt >= mdrt_max_cnt) { + prlog(PR_DEBUG, "DUMP: Invalid MDRT count : %x\n", mdrt_cnt); + return; + } + + prlog(PR_NOTICE, "DUMP: Dump found, MDRT count = 0x%x\n", mdrt_cnt); + + dt_add_property(dump_node, "mpipl-boot", NULL, 0); +} + +static void add_opal_dump_node(void) +{ + __be64 fw_load_area[4]; + struct dt_node *node; + + opal_node = dt_new_check(dt_root, "ibm,opal"); + node = dt_new(opal_node, "dump"); + assert(node); + dt_add_property_string(node, "compatible", "ibm,opal-dump"); + + fw_load_area[0] = cpu_to_be64((u64)KERNEL_LOAD_BASE); + fw_load_area[1] = cpu_to_be64(KERNEL_LOAD_SIZE); + fw_load_area[2] = cpu_to_be64((u64)INITRAMFS_LOAD_BASE); + fw_load_area[3] = cpu_to_be64(INITRAMFS_LOAD_SIZE); + dt_add_property(node, "fw-load-area", fw_load_area, sizeof(fw_load_area)); +} + +static void add_iplparams_sys_params(const void *iplp, struct dt_node *node) +{ + const struct iplparams_sysparams *p; + const struct HDIF_common_hdr *hdif = iplp; + u16 version = be16_to_cpu(hdif->version); + const char *vendor = NULL; + u32 sys_attributes; + u64 bus_speed; + + p = HDIF_get_idata(iplp, IPLPARAMS_SYSPARAMS, NULL); + if (!CHECK_SPPTR(p)) { + prerror("IPLPARAMS: No SYS Parameters\n"); + /* Create a generic compatible property */ + dt_add_property_string(dt_root, "compatible", "ibm,powernv"); + return; + } + + node = dt_new(node, "sys-params"); + assert(node); + dt_add_property_cells(node, "#address-cells", 0); + dt_add_property_cells(node, "#size-cells", 0); + + dt_add_property_nstr(node, "ibm,sys-model", p->sys_model, 4); + + /* + * Compatible has up to three entries: + * "ibm,powernv", the system family and system type. + * + * On P9 and above the family and type strings come from the HDAT + * directly. On P8 we find it from the system ID numbers. + */ + if (proc_gen >= proc_gen_p9) { + dt_add_property_strings(dt_root, "compatible", "ibm,powernv", + p->sys_family_str, p->sys_type_str); + + prlog(PR_INFO, "IPLPARAMS: v0x70 Platform family/type: %s/%s\n", + p->sys_family_str, p->sys_type_str); + } else { + u32 sys_type = be32_to_cpu(p->system_type); + const char *sys_family; + + switch (sys_type >> 28) { + case 0: + sys_family = "ibm,squadrons"; + break; + case 1: + sys_family = "ibm,eclipz"; + break; + case 2: + sys_family = "ibm,apollo"; + break; + case 3: + sys_family = "ibm,firenze"; + break; + default: + sys_family = NULL; + prerror("IPLPARAMS: Unknown system family\n"); + break; + } + + dt_add_property_strings(dt_root, "compatible", "ibm,powernv", + sys_family); + prlog(PR_INFO, + "IPLPARAMS: Legacy platform family: %s" + " (sys_type=0x%08x)\n", sys_family, sys_type); + } + + /* Grab nest frequency when available */ + if (version >= 0x005b) { + u64 freq = be32_to_cpu(p->nest_freq_mhz); + + freq *= 1000000; + dt_add_property_u64(dt_root, "nest-frequency", freq); + } + + /* Grab ABC bus speed */ + bus_speed = be32_to_cpu(p->abc_bus_speed); + if (bus_speed) + dt_add_property_u64(node, "abc-bus-freq-mhz", bus_speed); + + /* Grab WXYZ bus speed */ + bus_speed = be32_to_cpu(p->wxyz_bus_speed); + if (bus_speed) + dt_add_property_u64(node, "wxyz-bus-freq-mhz", bus_speed); + + if (version >= 0x5f) + vendor = p->sys_vendor; + + /* Workaround a bug where we have NULL vendor */ + if (!vendor || vendor[0] == '\0') + vendor = "IBM"; + + dt_add_property_string(dt_root, "vendor", vendor); + + sys_attributes = be32_to_cpu(p->sys_attributes); + if (sys_attributes & SYS_ATTR_RISK_LEVEL) + dt_add_property(node, "elevated-risk-level", NULL, 0); + + /* Populate OPAL dump node */ + if (sys_attributes & SYS_ATTR_MPIPL_SUPPORTED) + add_opal_dump_node(); + + if (version >= 0x60 && proc_gen >= proc_gen_p9) + dt_init_secureboot_node(p); +} + +static void add_iplparams_ipl_params(const void *iplp, struct dt_node *node) +{ + const struct iplparams_iplparams *p; + struct dt_node *led_node; + + p = HDIF_get_idata(iplp, IPLPARAMS_IPLPARAMS, NULL); + if (!CHECK_SPPTR(p)) { + prerror("IPLPARAMS: No IPL Parameters\n"); + return; + } + + node = dt_new(node, "ipl-params"); + assert(node); + dt_add_property_cells(node, "#address-cells", 0); + dt_add_property_cells(node, "#size-cells", 0); + + /* On an ASM initiated factory reset, this bit will be set + * and the FSP expects the firmware to reset the PCI bus + * numbers and respond with a Power Down (CE,4D,02) message + */ + if (be32_to_cpu(p->other_attrib) & IPLPARAMS_OATTR_RST_PCI_BUSNO) + dt_add_property_cells(node, "pci-busno-reset-ipl", 1); + dt_add_property_strings(node, "cec-ipl-side", + (p->ipl_side & IPLPARAMS_CEC_FW_IPL_SIDE_TEMP) ? + "temp" : "perm"); + if (proc_gen >= proc_gen_p9) { + dt_add_property_strings(node, "sp-ipl-side", + (p->ipl_side & IPLPARAMS_FSP_FW_IPL_SIDE_TEMP) ? + "temp" : "perm"); + } else { + dt_add_property_strings(node, "fsp-ipl-side", + (p->ipl_side & IPLPARAMS_FSP_FW_IPL_SIDE_TEMP) ? + "temp" : "perm"); + } + dt_add_property_cells(node, "os-ipl-mode", p->os_ipl_mode); + dt_add_property_strings(node, "cec-major-type", + p->cec_ipl_maj_type ? "hot" : "cold"); + + /* Add LED type info under '/ibm,opal/led' node */ + led_node = dt_find_by_path(opal_node, DT_PROPERTY_LED_NODE); + assert(led_node); + + if (be32_to_cpu(p->other_attrib) & IPLPARAMS_OATRR_LIGHT_PATH) + dt_add_property_strings(led_node, DT_PROPERTY_LED_MODE, + LED_MODE_LIGHT_PATH); + else + dt_add_property_strings(led_node, DT_PROPERTY_LED_MODE, + LED_MODE_GUIDING_LIGHT); + + /* Populate opal dump result table */ + opal_dump_add_mpipl_boot(p); +} + +static void add_iplparams_serials(const void *iplp, struct dt_node *node) +{ + const struct iplparms_serial *ipser; + struct dt_node *ser_node; + int count, i; + + count = HDIF_get_iarray_size(iplp, IPLPARMS_IDATA_SERIAL); + if (count <= 0) + return; + prlog(PR_INFO, "IPLPARAMS: %d serial ports in array\n", count); + + node = dt_new(node, "fsp-serial"); + assert(node); + dt_add_property_cells(node, "#address-cells", 1); + dt_add_property_cells(node, "#size-cells", 0); + + for (i = 0; i < count; i++) { + u16 rsrc_id; + ipser = HDIF_get_iarray_item(iplp, IPLPARMS_IDATA_SERIAL, + i, NULL); + if (!CHECK_SPPTR(ipser)) + continue; + rsrc_id = be16_to_cpu(ipser->rsrc_id); + prlog(PR_INFO, "IPLPARAMS: Serial %d rsrc: %04x loc: %s\n", + i, rsrc_id, ipser->loc_code); + ser_node = dt_new_addr(node, "serial", rsrc_id); + if (!ser_node) + continue; + + dt_add_property_cells(ser_node, "reg", rsrc_id); + dt_add_property_nstr(ser_node, "ibm,loc-code", + ipser->loc_code, LOC_CODE_SIZE); + dt_add_property_string(ser_node, "compatible", + "ibm,fsp-serial"); + /* XXX handle CALLHOME flag ? */ + } +} + +/* + * Check for platform dump, if present populate DT + */ +static void add_iplparams_platform_dump(const void *iplp, struct dt_node *node) +{ + const struct iplparams_dump *ipl_dump; + + ipl_dump = HDIF_get_idata(iplp, IPLPARAMS_PLATFORM_DUMP, NULL); + if (!CHECK_SPPTR(ipl_dump)) + return; + + node = dt_new(node, "platform-dump"); + assert(node); + + if (be32_to_cpu(ipl_dump->dump_id)) { + dt_add_property_cells(node, "dump-id", + be32_to_cpu(ipl_dump->dump_id)); + dt_add_property_u64(node, "total-size", + be64_to_cpu(ipl_dump->act_dump_sz)); + dt_add_property_u64(node, "hw-dump-size", + be32_to_cpu(ipl_dump->act_hw_dump_sz)); + dt_add_property_cells(node, "plog-id", + be32_to_cpu(ipl_dump->plid)); + } +} + +static void add_iplparams_features(const struct HDIF_common_hdr *iplp) +{ + const struct iplparams_feature *feature; + const struct HDIF_array_hdr *array; + struct dt_node *fw_features; + unsigned int count, i; + char name[65]; + + array = HDIF_get_iarray(iplp, IPLPARAMS_FEATURES, &count); + if (!array || !count) + return; + + opal_node = dt_new_check(dt_root, "ibm,opal"); + fw_features = dt_new(opal_node, "fw-features"); + if (!fw_features) + return; + + HDIF_iarray_for_each(array, i, feature) { + struct dt_node *n; + uint64_t flags; + + /* the name field isn't necessarily null terminated */ + BUILD_ASSERT(sizeof(name) > sizeof(feature->name)); + strncpy(name, feature->name, sizeof(name)-1); + name[sizeof(name)-1] = '\0'; + flags = be64_to_cpu(feature->flags); + + if (strlen(name) == 0) { + prlog(PR_DEBUG, "IPLPARAMS: FW feature name is NULL\n"); + continue; + } + + prlog(PR_DEBUG, "IPLPARAMS: FW feature %s = %016"PRIx64"\n", + name, flags); + + /* get rid of tm-suspend-mode-enabled being disabled */ + if (strcmp(name, "tm-suspend-mode-enabled") == 0) + strcpy(name, "tm-suspend-mode"); + + n = dt_new(fw_features, name); + + /* + * This is a bit overkill, but we'll want seperate properties + * for each flag bit(s). + */ + if (flags & PPC_BIT(0)) + dt_add_property(n, "enabled", NULL, 0); + else + dt_add_property(n, "disabled", NULL, 0); + } +} + +static void add_iplparams(void) +{ + struct dt_node *iplp_node; + const void *ipl_parms; + + ipl_parms = get_hdif(&spira.ntuples.ipl_parms, "IPLPMS"); + if (!ipl_parms) { + prerror("IPLPARAMS: Cannot find IPL Parms in SPIRA\n"); + return; + } + + iplp_node = dt_new(dt_root, "ipl-params"); + assert(iplp_node); + dt_add_property_cells(iplp_node, "#address-cells", 0); + dt_add_property_cells(iplp_node, "#size-cells", 0); + + add_iplparams_sys_params(ipl_parms, iplp_node); + add_iplparams_ipl_params(ipl_parms, iplp_node); + add_iplparams_serials(ipl_parms, iplp_node); + add_iplparams_platform_dump(ipl_parms, iplp_node); + add_iplparams_features(ipl_parms); +} + +/* Various structure contain a "proc_chip_id" which is an arbitrary + * numbering used by HDAT to reference chips, which doesn't correspond + * to the HW IDs. We want to use the HW IDs everywhere in the DT so + * we convert using this. + */ +uint32_t pcid_to_chip_id(uint32_t proc_chip_id) +{ + unsigned int i; + const void *hdif; + + /* First, try the proc_chip ntuples for chip data */ + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, + SPPCRD_HDIF_SIG) { + const struct sppcrd_chip_info *cinfo; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, + NULL); + if (!CHECK_SPPTR(cinfo)) { + prerror("XSCOM: Bad ChipID data %d\n", i); + continue; + } + if (proc_chip_id == be32_to_cpu(cinfo->proc_chip_id)) + return get_xscom_id(cinfo); + } + + /* Not found, what to do ? Assert ? For now return a number + * guaranteed to not exist + */ + return (uint32_t)-1; +} + +uint32_t pcid_to_topology_idx(uint32_t proc_chip_id) +{ + unsigned int i; + const void *hdif; + + /* First, try the proc_chip ntuples for chip data */ + for_each_ntuple_idx(&spira.ntuples.proc_chip, hdif, i, + SPPCRD_HDIF_SIG) { + const struct sppcrd_chip_info *cinfo; + + cinfo = HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, NULL); + if (!CHECK_SPPTR(cinfo)) { + prerror("XSCOM: Bad ChipID data %d\n", i); + continue; + } + if (proc_chip_id == be32_to_cpu(cinfo->proc_chip_id)) { + if (proc_gen <= proc_gen_p9) + return get_xscom_id(cinfo); + else + return ((u32)cinfo->topology_id_table[cinfo->primary_topology_loc]); + } + } + + /* Not found, what to do ? Assert ? For now return a number + * guaranteed to not exist + */ + return (uint32_t)-1; +} +/* Create '/ibm,opal/led' node */ +static void dt_init_led_node(void) +{ + struct dt_node *led_node; + + /* Create /ibm,opal node, if its not created already */ + if (!opal_node) { + opal_node = dt_new(dt_root, "ibm,opal"); + assert(opal_node); + } + + /* Crete LED parent node */ + led_node = dt_new(opal_node, DT_PROPERTY_LED_NODE); + assert(led_node); +} + +static void hostservices_parse(void) +{ + struct HDIF_common_hdr *hs_hdr; + const void *dt_blob; + unsigned int size; + unsigned int ntuples_size; + + /* Deprecated on P9 */ + if (proc_gen >= proc_gen_p9) + return; + + ntuples_size = sizeof(struct HDIF_array_hdr) + + be32_to_cpu(spira.ntuples.array_hdr.ecnt) * + sizeof(struct spira_ntuple); + + if (offsetof(struct spira_ntuples, hs_data) >= ntuples_size) { + prerror("SPIRA: No host services data found\n"); + return; + } + + hs_hdr = get_hdif(&spira.ntuples.hs_data, HSERV_HDIF_SIG); + if (!hs_hdr) { + prerror("SPIRA: No host services data found\n"); + return; + } + + dt_blob = HDIF_get_idata(hs_hdr, 0, &size); + if (!dt_blob) { + prerror("SPIRA: No host services idata found\n"); + return; + } + hservices_from_hdat(dt_blob, size); +} + +static void add_stop_levels(void) +{ + struct spira_ntuple *t = &spira.ntuples.proc_chip; + struct HDIF_common_hdr *hdif; + u32 stop_levels = ~0; + bool valid = false; + int i; + + if (proc_gen < proc_gen_p9) + return; + + /* + * OPAL only exports a single set of flags to indicate the supported + * STOP modes while the HDAT descibes the support top levels *per chip* + * We parse the list of chips to find a common set of STOP levels to + * export. + */ + for_each_ntuple_idx(t, hdif, i, SPPCRD_HDIF_SIG) { + unsigned int size; + const struct sppcrd_chip_info *cinfo = + HDIF_get_idata(hdif, SPPCRD_IDATA_CHIP_INFO, &size); + u32 ve, chip_levels; + + if (!cinfo) + continue; + + /* + * If the chip info field is too small then assume we have no + * STOP level information. + */ + if (size < 0x44) { + stop_levels = 0; + break; + } + + ve = be32_to_cpu(cinfo->verif_exist_flags) & CPU_ID_VERIFY_MASK; + ve >>= CPU_ID_VERIFY_SHIFT; + if (ve == CHIP_VERIFY_NOT_INSTALLED || + ve == CHIP_VERIFY_UNUSABLE) + continue; + + chip_levels = be32_to_cpu(cinfo->stop_levels); + + prlog(PR_INSANE, "CHIP[%x] supported STOP mask 0x%.8x\n", + be32_to_cpu(cinfo->proc_chip_id), chip_levels); + + stop_levels &= chip_levels; + valid = true; + } + + if (!valid) + stop_levels = 0; + + dt_add_property_cells(dt_new_check(opal_node, "power-mgt"), + "ibm,enabled-stop-levels", stop_levels); +} + +#define NPU_BASE 0x5011000 +#define NPU_SIZE 0x2c +#define NPU_INDIRECT0 0x8000000009010c3fULL +#define NPU_INDIRECT1 0x800000000c010c3fULL + +static void add_npu(struct dt_node *xscom, const struct HDIF_array_hdr *links, + int npu_index) +{ + const struct sppcrd_smp_link *link; + struct dt_node *npu; + int group_target[6]; /* Tracks the PCI slot targeted each link group */ + int group_count = 0; + int link_count = 0; + uint32_t size, chip_id; + int i; + + size = be32_to_cpu(links->esize); + chip_id = dt_get_chip_id(xscom); + + memset(group_target, 0, sizeof(group_target)); + + npu = dt_new_addr(xscom, "npu", NPU_BASE); + dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE); + dt_add_property_cells(npu, "#size-cells", 0); + dt_add_property_cells(npu, "#address-cells", 1); + + dt_add_property_strings(npu, "compatible", "ibm,power9-npu"); + dt_add_property_cells(npu, "ibm,npu-index", npu_index); + + HDIF_iarray_for_each(links, i, link) { + uint16_t slot_id = be16_to_cpu(link->pci_slot_idx); + uint32_t link_id = be32_to_cpu(link->link_id); + uint64_t speed = 0, nvlink_speed = 0; + struct dt_node *node; + + /* + * Only add a link node if this link is targeted at a + * GPU device. + * + * If we ever activate it for an opencapi device, we + * should revisit the link definitions hard-coded + * on ZZ. + */ + if (be32_to_cpu(link->usage) != SMP_LINK_USE_GPU) + continue; + + /* + * XXX: The link_id that we get from HDAT is essentially an + * arbitrary ID number so we can't use it as the reg for the + * link node. + * + * a) There's a 1-1 mapping between entries in the SMP link + * structure and the NPU links. + * + * b) The SMP link array contains them in ascending order. + * + * We have some assurances that b) is correct, but if we get + * broken link numbering it's something to watch for. + * + * If we every have actual A-Bus (SMP) link info in here + * this is going to break. + */ + + prlog(PR_DEBUG, "NPU: %04x:%d: Link (%d) targets slot %u\n", + chip_id, link_count, link_count, slot_id); + + if (link_count >= 6) { + prerror("NPU: %04x:%d: Ignoring extra link (max 6)\n", + chip_id, link_count); + break; + } + + node = dt_new_addr(npu, "link", link_count); + if (!node) { + prerror("NPU: %04x:%d: Creating link node failed\n", + chip_id, link_count); + continue; + } + + dt_add_property_string(node, "compatible", "ibm,npu-link"); + dt_add_property_cells(node, "reg", link_count); + dt_add_property_cells(node, "ibm,npu-link-index", link_count); + dt_add_property_cells(node, "ibm,workbook-link-id", link_id); + + dt_add_property_u64s(node, "ibm,npu-phy", + link_count < 3 ? NPU_INDIRECT0 : NPU_INDIRECT1); + dt_add_property_cells(node, "ibm,npu-lane-mask", + be32_to_cpu(link->lane_mask)); + dt_add_property_cells(node, "ibm,npu-brick-id", + be32_to_cpu(link->brick_id)); + + link_count++; + + /* + * Add the group details if this is an NVlink. + * + * TODO: Cable card stuff. + */ + if (slot_id) { + struct dt_node *slot; + const char *name; + int group; + + /* + * Search the existing groups for one targeting + * this PCI slot + */ + for (group = 0; group < group_count; group++) + if (group_target[group] == slot_id) + break; + + /* no group, make a new one */ + if (group == group_count) { + group_target[group] = slot_id; + group_count++; + } + + dt_add_property_cells(node, "ibm,npu-group-id", group); + + slot = find_slot_entry_node(dt_root, slot_id); + if (!slot) { + prerror("NPU: %04x:%d: Unable find node for targeted PCIe slot\n", + chip_id, link_count - 1); + continue; + } + + /* + * The slot_id points to a node that indicates that + * this GPU should appear under the slot. Grab the + * slot-label from the parent node that represents + * the actual slot. + */ + name = dt_prop_get_def(slot->parent, "ibm,slot-label", + (char *)"<SLOT NAME MISSING>"); + + prlog(PR_DEBUG, "NPU: %04x:%d: Target slot %s\n", + chip_id, link_count - 1, name); + + dt_add_property_string(node, "ibm,slot-label", name); + dt_add_property_cells(node, "ibm,pcie-slot", + slot->phandle); + } + + /* Newer fields which might not be populated */ + if (size <= 0x24) + continue; + + switch (link->link_speed) { + case 0: /* 20Gbps */ + speed = 20000000000ul; + nvlink_speed = 0x3; + break; + case 1: /* 25Gbps */ + speed = 25000000000ul; + nvlink_speed = 0x9; + break; + case 2: /* 25.78125 Gbps */ + nvlink_speed = 0x8; + speed = 25781250000ul; + break; + } + + /* ibm,link-speed is in bps and nvidia,link-speed is ~magic~ */ + dt_add_property_u64s(node, "ibm,link-speed", speed); + dt_add_property_cells(node, "nvidia,link-speed", nvlink_speed); + + dt_add_property_cells(node, DT_PRIVATE "occ-flag-pos", + PPC_BIT(link->occ_flag_bit)); + } + + dt_add_property_cells(npu, "ibm,npu-links", link_count); +} + +static void add_npus(void) +{ + struct dt_node *xscom; + int npu_index = 0; + + /* Only consult HDAT for npu2 */ + if (cpu_type != PVR_TYPE_P9) + return; + + dt_for_each_compatible(dt_root, xscom, "ibm,xscom") { + const struct HDIF_array_hdr *links; + + links = xscom_to_pcrd(xscom, SPPCRD_IDATA_SMP_LINK); + if (!links) { + prerror("NPU: Unable to find matching SPPCRD for %s\n", + xscom->name); + continue; + } + + /* should never happen, but stranger things have */ + if (!dt_find_by_name(dt_root, "ibm,pcie-slots")) { + prerror("PCIe slot information missing, can't add npu"); + continue; + } + + /* some hostboots will give us an empty array */ + if (be32_to_cpu(links->ecnt)) + add_npu(xscom, links, npu_index++); + } +} + +/* + * Legacy SPIRA is being deprecated and we have new SPIRA-H/S structures. + * But on older system (p7?) we will continue to get legacy SPIRA. + * + * SPIRA-S is initialized and provided by FSP. We use SPIRA-S signature + * to identify supported format. Also if required adjust spira pointer. + */ +static void fixup_spira(void) +{ +#if !defined(TEST) + spiras = (struct spiras *)SPIRA_HEAP_BASE; +#endif + + /* Validate SPIRA-S signature */ + if (!spiras) + return; + if (!HDIF_check(&spiras->hdr, SPIRAS_HDIF_SIG)) + return; + + prlog(PR_DEBUG, "SPIRA-S found.\n"); + + spira.ntuples.sp_subsys = spiras->ntuples.sp_subsys; + spira.ntuples.ipl_parms = spiras->ntuples.ipl_parms; + spira.ntuples.nt_enclosure_vpd = spiras->ntuples.nt_enclosure_vpd; + spira.ntuples.slca = spiras->ntuples.slca; + spira.ntuples.backplane_vpd = spiras->ntuples.backplane_vpd; + spira.ntuples.system_vpd = spiras->ntuples.system_vpd; + spira.ntuples.proc_init = spirah.ntuples.proc_init; + spira.ntuples.clock_vpd = spiras->ntuples.clock_vpd; + spira.ntuples.anchor_vpd = spiras->ntuples.anchor_vpd; + spira.ntuples.op_panel_vpd = spiras->ntuples.op_panel_vpd; + spira.ntuples.misc_cec_fru_vpd = spiras->ntuples.misc_cec_fru_vpd; + spira.ntuples.ms_vpd = spiras->ntuples.ms_vpd; + spira.ntuples.cec_iohub_fru = spiras->ntuples.cec_iohub_fru; + spira.ntuples.cpu_ctrl = spirah.ntuples.cpu_ctrl; + spira.ntuples.mdump_src = spirah.ntuples.mdump_src; + spira.ntuples.mdump_dst = spirah.ntuples.mdump_dst; + spira.ntuples.mdump_res = spirah.ntuples.mdump_res; + spira.ntuples.proc_dump_area = spirah.ntuples.proc_dump_area; + spira.ntuples.pcia = spiras->ntuples.pcia; + spira.ntuples.proc_chip = spiras->ntuples.proc_chip; + spira.ntuples.hs_data = spiras->ntuples.hs_data; + spira.ntuples.ipmi_sensor = spiras->ntuples.ipmi_sensor; + spira.ntuples.node_stb_data = spiras->ntuples.node_stb_data; +} + +/* + * All the data structure addresses are relative to payload base. Hence adjust + * structures that are needed to capture OPAL dump during MPIPL. + */ +static void update_spirah_addr(void) +{ +#if !defined(TEST) + if (proc_gen < proc_gen_p9) + return; + + naca.spirah_addr = CPU_TO_BE64(SPIRAH_OFF); + naca.spira_addr = CPU_TO_BE64(SPIRA_OFF); + spirah.ntuples.hs_data_area.addr = CPU_TO_BE64(SPIRA_HEAP_BASE - SKIBOOT_BASE); + spirah.ntuples.mdump_res.addr = CPU_TO_BE64(MDRT_TABLE_BASE - SKIBOOT_BASE); +#endif +} + +int parse_hdat(bool is_opal) +{ + cpu_type = PVR_TYPE(mfspr(SPR_PVR)); + + prlog(PR_DEBUG, "Parsing HDAT...\n"); + + fixup_spira(); + + update_spirah_addr(); + + /* + * Basic DT root stuff + */ + dt_add_property_cells(dt_root, "#address-cells", 2); + dt_add_property_cells(dt_root, "#size-cells", 2); + + if (proc_gen < proc_gen_p9) + dt_add_property_string(dt_root, "lid-type", is_opal ? "opal" : "phyp"); + + /* Add any BMCs and enable the LPC UART */ + bmc_parse(); + + /* Create and populate /vpd node */ + dt_init_vpd_node(); + + /* Create /ibm,opal/led node */ + dt_init_led_node(); + + /* Parse PCIA */ + if (!pcia_parse()) + return -1; + + /* IPL params */ + add_iplparams(); + + /* Add XSCOM node (must be before chiptod, IO and FSP) */ + add_xscom(); + + /* Parse MS VPD */ + memory_parse(); + + /* Add any FSPs */ + fsp_parse(); + + /* Add ChipTOD's */ + if (!add_chiptod_old() && !add_chiptod_new()) + prerror("CHIPTOD: No ChipTOD found !\n"); + + /* Add NX */ + add_nx(); + + /* Add nest mmu */ + add_nmmu(); + + /* Add IO HUBs and/or PHBs */ + io_parse(); + + /* Add NPU nodes */ + add_npus(); + + /* Parse VPD */ + vpd_parse(); + + /* Host services information. */ + hostservices_parse(); + + /* Parse System Attention Indicator inforamtion */ + slca_dt_add_sai_node(); + + add_stop_levels(); + + /* Parse node secure and trusted boot data */ + if (proc_gen >= proc_gen_p9) + node_stb_parse(); + + prlog(PR_DEBUG, "Parsing HDAT...done\n"); + + return 0; +} diff --git a/roms/skiboot/hdata/spira.h b/roms/skiboot/hdata/spira.h new file mode 100644 index 000000000..afdc9228a --- /dev/null +++ b/roms/skiboot/hdata/spira.h @@ -0,0 +1,1265 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#ifndef __SPIRA_H +#define __SPIRA_H + +#include "hdif.h" + +/* + * The SPIRA structure + * + * NOTE: This is one of the only HDIF structure that we layout entirely + * as a C struct because it's provided by us to the FSP. Almost everything + * else is generated by the FSP, and thus must be "parsed" since the various + * offsets and alignments might change. + */ + +#define SPIRA_VERSION 0x20 /* Like 730 ? */ + +struct spira_ntuple { + __be64 addr; + __be16 alloc_cnt; + __be16 act_cnt; + __be32 alloc_len; + __be32 act_len; + __be32 tce_off; + __be64 padding; +} __packed; + +#define SPIRA_NTUPLES_COUNT 0x19 + +struct spira_ntuples { + struct HDIF_array_hdr array_hdr; + struct spira_ntuple sp_subsys; /* 0x040 */ + struct spira_ntuple ipl_parms; /* 0x060 */ + struct spira_ntuple nt_enclosure_vpd; /* 0x080 */ + struct spira_ntuple slca; /* 0x0a0 */ + struct spira_ntuple backplane_vpd; /* 0x0c0 */ + struct spira_ntuple system_vpd; /* 0x0e0 */ + struct spira_ntuple chip_tod; /* 0x100 */ + struct spira_ntuple proc_init; /* 0x120 */ + struct spira_ntuple clock_vpd; /* 0x140 */ + struct spira_ntuple anchor_vpd; /* 0x160 */ + struct spira_ntuple op_panel_vpd; /* 0x180 */ + struct spira_ntuple ext_cache_fru_vpd; /* 0x1a0 */ + struct spira_ntuple misc_cec_fru_vpd; /* 0x1c0 */ + struct spira_ntuple paca; /* 0x1e0 */ + struct spira_ntuple ms_vpd; /* 0x200 */ + struct spira_ntuple cec_iohub_fru; /* 0x220 */ + struct spira_ntuple cpu_ctrl; /* 0x240 */ + struct spira_ntuple mdump_src; /* 0x260 */ + struct spira_ntuple mdump_dst; /* 0x280 */ + struct spira_ntuple mdump_res; /* 0x2a0 */ + struct spira_ntuple heap; /* 0x2c0 */ + struct spira_ntuple pcia; /* 0x2e0 */ + struct spira_ntuple proc_chip; /* 0x300 */ + struct spira_ntuple hs_data; /* 0x320 */ + struct spira_ntuple ipmi_sensor; /* 0x360 */ + struct spira_ntuple node_stb_data; /* 0x380 */ + struct spira_ntuple proc_dump_area; /* 0x400 */ +}; + +#define SPIRA_RESERVED_BYTES 0x60 + +struct spira { + struct HDIF_common_hdr hdr; + struct HDIF_idata_ptr ntuples_ptr; + __be64 pad; + struct spira_ntuples ntuples; + /* + * We reserve 0xc0 rather than 0x4c0 so we fit SPIRAH/SPIRAS here + * while preserving compatibility with existing P8 systems. + * + * According to FSP engineers, this is an okay thing to do. + */ + u8 reserved[SPIRA_RESERVED_BYTES]; +} __packed __align(0x100); + +#define SPIRA_ACTUAL_SIZE (sizeof(struct spira) - SPIRA_RESERVED_BYTES) + +extern struct spira spira; + +/* SPIRA-H signature */ +#define SPIRAH_HDIF_SIG "SPIRAH" + +/* First version of the secure boot compliant design. */ +#define SPIRAH_VERSION 0x50 + +/* N-tuples in SPIRAH */ +#define SPIRAH_NTUPLES_COUNT 0x6 + +struct spirah_ntuples { + struct HDIF_array_hdr array_hdr; /* 0x030 */ + struct spira_ntuple hs_data_area; /* 0x040 */ + struct spira_ntuple proc_init; /* 0x060 */ + struct spira_ntuple cpu_ctrl; /* 0x080 */ + struct spira_ntuple mdump_src; /* 0x0a0 */ + struct spira_ntuple mdump_dst; /* 0x0c0 */ + struct spira_ntuple mdump_res; /* 0x0e0 */ + struct spira_ntuple proc_dump_area; /* 0x100 */ +}; + +struct spirah { + struct HDIF_common_hdr hdr; + struct HDIF_idata_ptr ntuples_ptr; + __be64 pad; + struct spirah_ntuples ntuples; + u8 reserved[0xE0]; +} __packed __align(0x100); + +extern struct spirah spirah; + +/* SPIRA-S signature */ +#define SPIRAS_HDIF_SIG "SPIRAS" + +/* First version on 810 release */ +#define SPIRAS_VERSION_P8 0x40 +#define SPIRAS_VERSION_P9 0x50 + +/* N-tuples in SPIRAS */ +#define SPIRAS_NTUPLES_COUNT 0x10 + +struct spiras_ntuples { + struct HDIF_array_hdr array_hdr; /* 0x030 */ + struct spira_ntuple sp_subsys; /* 0x040 */ + struct spira_ntuple ipl_parms; /* 0x060 */ + struct spira_ntuple nt_enclosure_vpd; /* 0x080 */ + struct spira_ntuple slca; /* 0x0a0 */ + struct spira_ntuple backplane_vpd; /* 0x0c0 */ + struct spira_ntuple system_vpd; /* 0x0e0 */ + struct spira_ntuple clock_vpd; /* 0x100 */ + struct spira_ntuple anchor_vpd; /* 0x120 */ + struct spira_ntuple op_panel_vpd; /* 0x140 */ + struct spira_ntuple misc_cec_fru_vpd; /* 0x160 */ + struct spira_ntuple ms_vpd; /* 0x180 */ + struct spira_ntuple cec_iohub_fru; /* 0x1a0 */ + struct spira_ntuple pcia; /* 0x1c0 */ + struct spira_ntuple proc_chip; /* 0x1e0 */ + struct spira_ntuple hs_data; /* 0x200 */ + struct spira_ntuple hbrt_data; /* 0x220 */ + struct spira_ntuple ipmi_sensor; /* 0x240 */ + struct spira_ntuple node_stb_data; /* 0x260 */ +}; + +struct spiras { + struct HDIF_common_hdr hdr; + struct HDIF_idata_ptr ntuples_ptr; + __be64 pad; + struct spiras_ntuples ntuples; + u8 reserved[0x180]; +} __packed __align(0x100); + +extern struct spiras *spiras; + + +/* This macro can be used to check the validity of a pointer returned + * by one of the HDIF API functions. It returns true if the pointer + * appears valid. If it's not valid and not NULL, it will print some + * error in the log as well. + */ +#define CHECK_SPPTR(_ptr) spira_check_ptr(_ptr, __FILE__, __LINE__) + +#define get_hdif(ntuple, id) __get_hdif((ntuple), (id), __FILE__, __LINE__) + +extern struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n, + const char id[], + const char *file, int line); + +#define for_each_ntuple_idx(_ntuples, _p, _idx, _id) \ + for (_p = get_hdif((_ntuples), _id ""), _idx = 0; \ + _p && _idx < be16_to_cpu((_ntuples)->act_cnt); \ + _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len), _idx++) + +#define for_each_ntuple(_ntuples, _p, _id) \ + for (_p = get_hdif((_ntuples), _id ""); \ + _p && (void *)_p < ntuple_addr(_ntuples) \ + + (be16_to_cpu((_ntuples)->act_cnt) * \ + be32_to_cpu((_ntuples)->alloc_len)); \ + _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len)) + +#define for_each_pcia(p) for_each_ntuple(&spira.ntuples.pcia, p, SPPCIA_HDIF_SIG) + +/* We override these for testing. */ +#ifndef ntuple_addr +#define ntuple_addr(_ntuples) ((void *)BE64_TO_CPU((_ntuples)->addr)) +#endif + +#ifndef spira_check_ptr +extern bool spira_check_ptr(const void *ptr, const char *file, + unsigned int line); +#endif + +struct proc_init_data { + struct HDIF_common_hdr hdr; + struct HDIF_idata_ptr regs_ptr; + struct { + __be64 nia; + __be64 msr; + __be64 nia_charm_time; + __be64 msr_charm_time; + } regs; +} __packed __align(0x10); + +/* + * The FRU ID structure is used in several tuples, so we + * define it generically here + */ +struct spira_fru_id { + __be16 slca_index; + __be16 rsrc_id; /* formerly VPD port number */ +} __packed; + +/* + * The FRU operational status structure is used in several + * tuples, so we define it generically here + */ +struct spira_fru_op_status { + uint8_t flags; +#define FRU_OP_STATUS_FLAG_USED 0x02 /* If 0 -> not used (redundant) */ +#define FRU_OP_STATUS_FLAG_FUNCTIONAL 0x01 /* If 0 -> non-functional */ + uint8_t reserved[3]; +} __packed; + +/* + * Move VPD related stuff to another file ... + */ +#define VPD_ID(_a, _b) ((_a) << 8 | (_b)) + +/* + * Service Processor Subsystem Structure + * + * This structure contains several internal data blocks + * describing the service processor(s) in the system + */ + +#define SPSS_HDIF_SIG "SPINFO" + +/* Idata index 0 : FRU ID Data */ +#define SPSS_IDATA_FRU_ID 0 + +/* Idata index 1 : Keyword VPD for the FSP instance */ +#define SPSS_IDATA_KEYWORD_VPD 1 + +/* Idata index 2 : SP Implementation */ +#define SPSS_IDATA_SP_IMPL 2 + +struct spss_sp_impl { + __be16 hw_version; + __be16 sw_version; + __be16 func_flags; +#define SPSS_SP_IMPL_FLAGS_INSTALLED 0x8000 +#define SPSS_SP_IMPL_FLAGS_FUNCTIONAL 0x4000 +#define SPSS_SP_IMPL_FLAGS_PRIMARY 0x2000 + u8 chip_version; + u8 reserved; + u8 sp_family[64]; +} __packed; + +/* Idata index 3 is deprecated */ + +/* Idata index 4 : SP Memory Locator */ +#define SPSS_IDATA_SP_MEMLOC 4 + +/* Idata index 5 : SP I/O path array */ +#define SPSS_IDATA_SP_IOPATH 5 + +/* An HDIF array of IO path */ +struct spss_iopath { + __be16 iopath_type; +#define SPSS_IOPATH_TYPE_IOHUB_PHB 0x0001 +#define SPSS_IOPATH_TYPE_PSI 0x0002 +#define SPSS_IOPATH_TYPE_LPC 0x0003 + union { + struct { + __be16 iohub_chip_inst; + __be16 iohub_chip_port; + __be16 phb_id; + } __packed iohub_phb; + + struct { + __be16 link_status; +#define SPSS_IO_PATH_PSI_LINK_BAD_FRU 0x0000 +#define SPSS_IO_PATH_PSI_LINK_CURRENT 0x0001 +#define SPSS_IO_PATH_PSI_LINK_BACKUP 0x0002 + u8 ml2_version; + u8 reserved; + __be16 slca_count; + u8 slca_idx[16]; + __be32 proc_chip_id; + __be32 reserved2; + __be64 gxhb_base; + } __packed psi; + + struct { /* only populated after version 0x30 */ + __be16 link_status; +#define LPC_STATUS_STUFFED 0x0000 +#define LPC_STATUS_ACTIVE 0x0001 + uint8_t ml2_version; + uint8_t reserved[3]; + __be32 chip_id; + + __be32 io_bar; + __be32 memory_bar; + __be32 firmware_bar; + __be32 internal_bar; + + __be32 mctp_base; + + __be64 uart_base; + __be32 uart_size; + __be32 uart_clk; /* UART baud clock in Hz */ + __be32 uart_baud; /* UART baud rate */ + + uint8_t uart_int_number; + uint8_t uart_int_type; +#define UART_INT_LVL_LOW 0x1 +#define UART_INT_RISING 0x2 +#define UART_INT_LVL_HIGH 0x3 + uint8_t uart_valid; + uint8_t reserved3; + + __be64 bt_base; + __be32 bt_size; + uint8_t bt_sms_int_num; + uint8_t bt_bmc_response_int_num; + uint8_t reserved4[2]; + + __be16 kcs_data_reg_addr; + __be16 kcs_status_reg_addr; + uint8_t kcs_int_number; + + __be64 uart2_base; + __be32 uart2_size; + __be32 uart2_clk; /* UART baud clock in Hz */ + __be32 uart2_baud; /* UART baud rate */ + uint8_t uart2_int_number; + uint8_t uart2_int_type; + uint8_t uart2_valid; + uint8_t reserved5; + } __packed lpc; + }; +} __packed; + +/* + * IPL Parms structure + * + */ + +/* Idata index 0: System Parameters */ +#define IPLPARAMS_SYSPARAMS 0 + +struct iplparams_sysparams { + char sys_model[4]; + char cpu_feature_code[4]; + __be32 effective_pvr; + __be32 system_type; + uint8_t num_lpar_oct[8]; + __be32 abc_bus_speed; + __be32 wxyz_bus_speed; + __be32 sys_eco_mode; +#define SYS_ATTR_MULTIPLE_TPM PPC_BIT32(0) +#define SYS_ATTR_RISK_LEVEL PPC_BIT32(3) +#define SYS_ATTR_MPIPL_SUPPORTED PPC_BIT32(5) + __be32 sys_attributes; + __be32 mem_scrubbing; + __be16 cur_spl_value; + uint8_t pump_mode; /* Reserved */ + uint8_t use_pore_sleep; + __be32 pore_image_size; /* Reserved */ + uint8_t vtpm_enabled; + uint8_t hw_page_table_size; /* >= 0x59 */ + __be16 hv_disp_wheel; /* >= 0x58 */ + __be32 nest_freq_mhz; /* >= 0x5b */ + uint8_t split_core_mode; /* >= 0x5c */ + uint8_t reserved[1]; +#define KEY_CLEAR_ALL PPC_BIT16(0) +#define KEY_CLEAR_OS_KEYS PPC_BIT16(1) +#define KEY_CLEAR_MFG PPC_BIT16(7) + __be16 host_fw_key_clear; + uint8_t sys_vendor[64]; /* >= 0x5f */ +#define SEC_CONTAINER_SIG_CHECKING PPC_BIT16(0) +#define SEC_HASHES_EXTENDED_TO_TPM PPC_BIT16(1) +#define PHYSICAL_PRESENCE_ASSERTED PPC_BIT16(3) + __be16 sys_sec_setting; /* >= 0x60 */ + __be16 tpm_config_bit; /* >= 0x60 */ + __be16 tpm_drawer; /* >= 0x60 */ + __be16 hw_key_hash_size; /* >= 0x60 */ +#define SYSPARAMS_HW_KEY_HASH_MAX 64 + uint8_t hw_key_hash[SYSPARAMS_HW_KEY_HASH_MAX]; /* >= 0x60 */ + uint8_t sys_family_str[64]; /* vendor,name */ + uint8_t sys_type_str[64]; /* vendor,type */ +} __packed; + +/* Idata index 1: IPL parameters */ +#define IPLPARAMS_IPLPARAMS 1 + +struct iplparams_iplparams { + uint8_t reserved; + uint8_t hv_ipl_dest; + uint8_t ipl_side; +#define IPLPARAMS_CEC_FW_IPL_SIDE_TEMP 0x10 +#define IPLPARAMS_FSP_FW_IPL_SIDE_TEMP 0x01 + uint8_t ipl_speed; + __be16 cec_ipl_attrib; +#define IPLPARAMS_ATTRIB_MEM_PRESERVE PPC_BIT16(2) + uint8_t cec_ipl_maj_type; +#define IPLPARAMS_MAJ_TYPE_REIPL 0x1 + uint8_t cec_ipl_min_type; +#define IPLPARAMS_MIN_TYPE_POST_DUMP 0xc +#define IPLPARAMS_MIN_TYPE_PLAT_REBOOT 0xd + uint8_t os_ipl_mode; + uint8_t keylock_pos; + uint8_t lmb_size; + uint8_t deprecated; + __be32 max_hsl_opticonnect; + __be32 other_attrib; +#define IPLPARAMS_OATTR_RST_PCI_BUSNO 0x08000000 +#define IPLPARAMS_OATTR_CLEAR_NVRAM 0x04000000 +#define IPLPARAMS_OATRR_LIGHT_PATH 0x00000004 + __be16 huge_page_count; + uint8_t huge_page_size; +#define IPLPARAMS_HUGE_PG_SIZE_16G 0 + uint8_t num_vlan_switches; + __be32 reserved2; + __be32 enlarge_io; /* >= 0x5a */ + uint8_t core_config; +#define IPLPARAMS_CORE_NORMAL 0x00 +#define IPLPARAMS_CORE_FUSE 0x01 +} __packed; + +/* Idata index 4: Platform Dump Descriptor */ +#define IPLPARAMS_PLATFORM_DUMP 4 + +struct iplparams_dump { + __be16 flags; + uint8_t reserved1; + uint8_t policy; +#define HYP_DUMP_POLICY_NORMAL 0x00 + __be32 dump_id; + __be64 reserved2; + __be64 act_dump_sz; + __be32 max_hw_dump_sz; + __be32 act_hw_dump_sz; + __be32 max_sp_dump_sz; + __be32 plid; +} __packed; + +/* Idata index 8: serial ports */ +#define IPLPARMS_IDATA_SERIAL 8 + +/* An HDIF array of serial descriptions */ +struct iplparms_serial { + uint8_t loc_code[LOC_CODE_SIZE]; + __be16 rsrc_id; + __be16 flags; +#define PLPARMS_SERIAL_FLAGS_CALLHOME 0x8000 +} __packed; + +/* Idata index 9: FW features */ +#define IPLPARAMS_FEATURES 9 +struct iplparams_feature { + char name[64]; + __be64 flags; +} __packed; + +/* + * Chip TOD structure + * + * This is an array of 32 entries (I assume per possible chip) + */ + +/* Idata index 0: Chip ID data (array) */ +#define CHIPTOD_IDATA_CHIPID 0 + +struct chiptod_chipid { + __be32 chip_id; + __be32 flags; +#define CHIPTOD_ID_FLAGS_PRIMARY 0x02 +#define CHIPTOD_ID_FLAGS_SECONDARY 0x01 +#define CHIPTOD_ID_FLAGS_STATUS_MASK 0x0c +#define CHIPTOD_ID_FLAGS_STATUS_OK 0x04 +#define CHIPTOD_ID_FLAGS_STATUS_NOK 0x08 +} __packed; + +/* Idata index 0: Chip Initialization data */ +#define CHIPTOD_IDATA_CHIPINIT 1 + +struct chiptod_chipinit { + __be32 ctrl_reg_internal; + __be32 tod_ctrl_reg; +} __packed; + +/* + * MS VPD - Memory Description Tree + * + * One such structure pointing to the various memory arrays + * along with other infos about the BCRs, Page Mover, XSCOM,... + */ +#define MSVPD_HDIF_SIG "MS VPD" + +/* Idata index 0: Mainstore address config */ +#define MSVPD_IDATA_MS_ADDR_CONFIG 0 + +/* Mainstore Address Configuration */ +struct msvpd_ms_addr_config { + __be64 max_configured_ms_address; + __be64 max_possible_ms_address; + __be32 deprecated; + __be64 mirrorable_memory_starting_address; + __be64 hrmor_stash_loc_address; +} __packed; + +/* Idata index 1: Total configured mainstore */ +#define MSVPD_IDATA_TOTAL_CONFIG_MS 1 + +struct msvpd_total_config_ms { + __be64 total_in_mb; +} __packed; + +/* Idata index 2: Page mover and sync structure */ +#define MSVPD_IDATA_PMOVER_SYNCHRO 2 + +struct msvpd_pmover_bsr_synchro { + __be32 flags; +#define MSVPD_PMS_FLAG_HWLOCK_EN 0x80000000 +#define MSVPD_PMS_FLAG_PMOVER_EN 0x40000000 +#define MSVPD_PMS_FLAG_BSR_EN 0x20000000 +#define MSVPD_PMS_FLAG_XSCOMBASE_VALID 0x10000000 + __be32 hwlocks_per_page; + __be64 hwlock_addr; + __be64 pmover_addr; + __be64 bsr_addr; + __be64 xscom_addr; +} __packed; + +/* Idata index 3: Memory Trace Array */ +#define MSVPD_IDATA_TRACE_AREAS 3 +struct msvpd_trace { + __be64 start, end; + char reserved[16]; +}; + +/* Idata index 4: UE Address Array */ + +/* Idata index 5: Hostboot reserved memory address range */ +#define MSVPD_IDATA_HB_RESERVED_MEM 5 +#define HB_RESERVE_MEM_LABEL_SIZE 64 +struct msvpd_hb_reserved_mem { +#define MSVPD_HBRMEM_RANGE_TYPE PPC_BITMASK32(0,7) +#define HBRMEM_CONTAINER_VERIFICATION_CODE 0x3 + __be32 type_instance; + __be64 start_addr; + __be64 end_addr; + __be32 label_size; + uint8_t label[HB_RESERVE_MEM_LABEL_SIZE]; + uint8_t rw_perms; +#define HB_RESERVE_READABLE 0x80 +#define HB_RESERVE_WRITEABLE 0x40 + uint8_t reserved[7]; +} __packed; + +/* Child index 0: MS area child structure */ +#define MSVPD_CHILD_MS_AREAS 0 + +/* + * CEC I/O Hub FRU + * + * This is an array of CEC Hub FRU HDIF structures + * + * Each of these has some idata pointers to generic info about the + * hub and a possible child pointer for daughter card. + * + * Actual ports are in the SLCA and need to be cross referenced + * + * Note that slots meant for the addition of GX+ adapters that + * are currently unpopulated but support hotplug will have a + * minimum "placeholder" entry, which will be fully populated + * when the array is rebuild during concurrent maintenance. + * This "placeholder" is called a "reservation". + * + * WARNING: The array rebuild by concurrent maintenance is not + * guaranteed to be in the same order as the IPL array, not is + * the order stable between concurrent maintenance operations. + * + * There's also a child pointer to daughter card structures but + * we aren't going to handle that just yet. + */ +#define CECHUB_FRU_HDIF_SIG "IO HUB" +#define IOKID_FRU_HDIF_SIG "IO KID" +#define IOSLOT_FRU_HDIF_SIG "IOSLOT" + +/* Idata index 0: FRU ID data + * + * This is a generic struct spira_fru_id defined above + */ +#define CECHUB_FRU_ID_DATA 0 + +/* Idata index 1: ASCII Keyword VPD */ +#define CECHUB_ASCII_KEYWORD_VPD 1 + +/* Idata index 2: Hub FRU ID data area */ +#define CECHUB_FRU_ID_DATA_AREA 2 + +struct cechub_hub_fru_id { + __be32 card_type; +#define CECHUB_FRU_TYPE_IOHUB_RSRV 0 +#define CECHUB_FRU_TYPE_IOHUB_CARD 1 +#define CECHUB_FRU_TYPE_CPU_CARD 2 +#define CECHUB_FRU_TYPE_CEC_BKPLANE 3 +#define CECHUB_FRU_TYPE_BKPLANE_EXT 4 + __be32 unused; + __be16 total_chips; + uint8_t flags; +#define CECHUB_FRU_FLAG_HEADLESS 0x80 /* not connected to CPU */ +#define CECHUB_FRU_FLAG_PASSTHROUGH 0x40 /* connected to passhtrough + port of another hub */ + uint8_t reserved; + __be16 parent_hub_id; /* chip instance number of the + hub that contains the passthrough + port this one is connected to */ + __be16 reserved2; +} __packed; + + +/* Idata index 3: IO HUB array */ + +#define CECHUB_FRU_IO_HUBS 3 + +/* This is an HDIF array of IO Hub structures */ +struct cechub_io_hub { + __be64 fmtc_address; + __be32 fmtc_tce_size; + __be16 hub_num; /* unique hub number (I/O Hub ID) */ + uint8_t flags; +#define CECHUB_HUB_FLAG_STATE_MASK 0xc0 +#define CECHUB_HUB_FLAG_STATE_OK 0x00 +#define CECHUB_HUB_FLAG_STATE_FAILURES 0x40 +#define CECHUB_HUB_FLAG_STATE_NOT_INST 0x80 +#define CECHUB_HUB_FLAG_STATE_UNUSABLE 0xc0 +#define CECHUB_HUB_FLAG_MASTER_HUB 0x20 /* HDAT < v9.x only */ +#define CECHUB_HUB_FLAG_GARD_MASK_VALID 0x08 /* HDAT < v9.x only */ +#define CECHUB_HUB_FLAG_SWITCH_MASK_PDT 0x04 /* HDAT < v9.x only */ +#define CECHUB_HUB_FLAG_FAB_BR0_PDT 0x02 /* HDAT < v9.x only */ +#define CECHUB_HUB_FLAG_FAB_BR1_PDT 0x01 /* HDAT < v9.x only */ + uint8_t nr_ports; /* HDAT < v9.x only */ + uint8_t fab_br0_pdt; /* p5ioc2 PCI-X or P8 PHB3's */ +#define CECHUB_HUB_FAB_BR0_PDT_PHB0 0x80 +#define CECHUB_HUB_FAB_BR0_PDT_PHB1 0x40 +#define CECHUB_HUB_FAB_BR0_PDT_PHB2 0x20 +#define CECHUB_HUB_FAB_BR0_PDT_PHB3 0x10 +#define CECHUB_HUB_FAB_BR0_PDT_PHB4 0x08 +#define CECHUB_HUB_FAB_BR0_PDT_PHB5 0x04 + uint8_t fab_br1_pdt; /* p5ioc2 & p7ioc PCI-E */ +#define CECHUB_HUB_FAB_BR1_PDT_PHB0 0x80 +#define CECHUB_HUB_FAB_BR1_PDT_PHB1 0x40 +#define CECHUB_HUB_FAB_BR1_PDT_PHB2 0x20 +#define CECHUB_HUB_FAB_BR1_PDT_PHB3 0x10 +#define CECHUB_HUB_FAB_BR1_PDT_PHB4 0x08 /* p7ioc only */ +#define CECHUB_HUB_FAB_BR1_PDT_PHB5 0x04 /* p7ioc only */ + __be16 iohub_id; /* the type of hub */ +#define CECHUB_HUB_MURANO 0x20ef /* Murano from spec */ +#define CECHUB_HUB_MURANO_SEGU 0x0001 /* Murano+Seguso from spec */ +#define CECHUB_HUB_VENICE_WYATT 0x0010 /* Venice+Wyatt from spec */ +#define CECHUB_HUB_NIMBUS_SFORAZ 0x0020 /* Nimbus+sforaz from spec */ +#define CECHUB_HUB_NIMBUS_MONZA 0x0021 /* Nimbus+monza from spec */ +#define CECHUB_HUB_NIMBUS_LAGRANGE 0x0022 /* Nimbus+lagrange from spec */ +#define CECHUB_HUB_CUMULUS_DUOMO 0x0030 /* cumulus+duomo from spec */ +#define CECHUB_HUB_AXONE_HOPPER 0x0040 /* axone+hopper */ +#define CECHUB_HUB_RAINIER 0x0050 +#define CECHUB_HUB_DENALI 0x0051 + __be32 ec_level; + __be32 aff_dom2; /* HDAT < v9.x only */ + __be32 aff_dom3; /* HDAT < v9.x only */ + __be64 reserved; + __be32 proc_chip_id; + + union { + /* HDAT < v9.x */ + struct { + __be32 gx_index; /* GX bus index on cpu */ + __be32 buid_ext; /* BUID Extension */ + __be32 xscom_chip_id; /* TORRENT ONLY */ + }; + /* HDAT >= v9.x */ + struct { + __be32 reserved1; + __be32 reserved2; + __be16 reserved3; + __be16 hw_topology; + }; + }; + __be32 mrid; + __be32 mem_map_vers; + union { + /* HDAT < v9.x */ + struct { + __be64 gx_ctrl_bar0; + __be64 gx_ctrl_bar1; + __be64 gx_ctrl_bar2; + __be64 gx_ctrl_bar3; + __be64 gx_ctrl_bar4; + __be32 sw_mask_pdt; + __be16 gard_mask; + __be16 gx_bus_speed; /* Version 0x58 */ + }; + + /* HDAT >= v9.x, HDIF version 0x6A adds phb_lane_eq with four + * words per PHB (4 PHBs). + * + * HDAT >= 10.x, HDIF version 0x7A adds space for another + * two PHBs (6 total) and the gen4 EQ values. + * + * HDAT >= 10.5x, HDIF version 0x8B adds space for the + * gen5 EQ values. + */ + struct { + /* Gen 3 PHB eq values, 6 PHBs */ + __be64 phb_lane_eq[6][4]; + + /* Gen 4 PHB eq values */ + __be64 phb4_lane_eq[6][4]; + + /* Gen 5 PHB eq values */ + __be64 phb5_lane_eq[6][4]; + }; + }; +} __packed; + +/* We support structures as small as 0x68 bytes */ +#define CECHUB_IOHUB_MIN_SIZE 0x68 + +/* Child index 0: IO Daugther Card */ +#define CECHUB_CHILD_IO_KIDS 0 + +/* Child index 1: PCIe Slot Mapping Information */ +#define CECHUB_CHILD_IOSLOTS 1 + +#define IOSLOT_IDATA_SLOTMAP 0 + +struct slot_map_entry { + __be16 entry_id; + __be16 parent_id; + uint8_t phb_index; /* only valid for ROOT and SWITCH_UP */ + + uint8_t type; +#define SLOT_TYPE_ROOT_COMPLEX 0x0 +#define SLOT_TYPE_SWITCH_UP 0x1 +#define SLOT_TYPE_SWITCH_DOWN 0x2 +#define SLOT_TYPE_BUILTIN 0x3 + + uint8_t lane_swapped; + uint8_t reserved; + __be16 lane_mask; + __be16 lane_reverse; + + /* what can I do with this? reference something under/vpd/ ? */ + __be16 slca_idx; + + __be16 mrw_slot_id; + + __be32 features; +#define SLOT_FEAT_SLOT 0x1 + + uint8_t up_port; + uint8_t down_port; /* the switch port this device is attached to */ + + __be32 vendor_id; + __be32 device_id; + __be32 sub_vendor_id; + __be32 sub_device_id; + char name[8]; +} __packed; + +#define IOSLOT_IDATA_DETAILS 1 + +struct slot_map_details { + __be16 entry; + + /* Phyp junk, ignore */ + uint8_t mgc_load_source; + uint8_t hddw_order; + __be16 mmio_size_32; /* In MB */ + __be16 mmio_size_64; + __be16 dma_size_32; + __be16 dma_size_64; + + uint8_t power_ctrl_type; /* slot power control source */ +#define SLOT_PWR_NONE 0x0 +#define SLOT_PWR_I2C 0x1 + + uint8_t presence_det_type; /* slot presence detect source */ +#define SLOT_PRESENCE_NONE 0x0 +#define SLOT_PRESENCE_PCI 0x1 +#define SLOT_PRESENCE_I2C 0x2 + + uint8_t perst_ctl_type; /* slot PERST source */ +#define SLOT_PERST_NONE 0x0 +#define SLOT_PERST_PHB_OR_SW 0x1 +#define SLOT_PERST_SW_GPIO 0x2 + uint8_t perst_gpio; + + __be16 max_power; /* in W? */ + + __be32 slot_caps; +#define SLOT_CAP_LSI 0x01 /* phyp junk? */ +#define SLOT_CAP_CAPI 0x02 +#define SLOT_CAP_CCARD 0x04 +#define SLOT_CAP_HOTPLUG 0x08 +#define SLOT_CAP_SRIOV 0x10 /* phyp junk */ +#define SLOT_CAP_ELLOCO 0x20 /* why is this seperate from the nvlink cap? */ +#define SLOT_CAP_NVLINK 0x30 + + __be16 reserved1; + + /* I2C Link IDs */ + __be32 i2c_power_ctl; + __be32 i2c_pgood; + __be32 i2c_cable_card; /* opencapi presence detect? */ + __be32 i2c_mex_fpga; +}; + +/* + * IO KID is a dauther card structure + */ +#define IOKID_FRU_ID_DATA 0 +#define IOKID_KW_VPD 1 + +/* + * CPU Controls Legacy Structure + */ +struct cpu_ctl_legacy { + __be64 addr; + __be64 size; +} __packed; + +/* + * CPU Control Legacy table + * + * Format of this table is defined in FIPS PHYP Attn spec. + */ +struct cpu_ctl_legacy_table { + struct cpu_ctl_legacy spat; + struct cpu_ctl_legacy sp_attn_area1; + struct cpu_ctl_legacy sp_attn_area2; + struct cpu_ctl_legacy hsr_area; + struct cpu_ctl_legacy reserved[12]; +} __packed; + +/* + * CPU Controls Header Structure + */ +#define CPU_CTL_HDIF_SIG "CPUCTL" +struct cpu_ctl_init_data { + struct HDIF_common_hdr hdr; + struct HDIF_idata_ptr cpu_ctl; + uint8_t reserved[8]; + struct cpu_ctl_legacy_table cpu_ctl_lt; +} __packed __align(0x10); + +/* + * Slot Location Code Array (aka SLCA) + * + * This is a pile of location codes referenced by various other + * structures such as the IO Hubs for things on the CEC. Not + * everything in there is a physical port. The SLCA is actually + * a tree which represent the topology of the system. + * + * The tree works as follow: A parent has a pointer to the first + * child. A child has a pointer to its parent. Siblings are + * consecutive entries. + * + * Note: If we ever support concurrent maintenance... this is + * completely rebuilt, invalidating all indices, though other + * structures that may reference SLCA by index will be rebuilt + * as well. + * + * Note that a lot of that stuff is based on VPD documentation + * such as the identification keywords. I will list the ones + * I manage to figure out without the doc separately. + */ +#define SLCA_HDIF_SIG "SLCA " + +/* Idata index 0 : SLCA root pointer + * + * The SLCA array is an HDIF array of all the entries. The tree + * structure is based on indices inside the entries and order of + * the entries + */ +#define SLCA_IDATA_ARRAY 0 + +#define SLCA_ROOT_INDEX 0 + +/* Note: An "index" (or idx) is always an index into the SLCA array + * and "id" is a reference to some other object. + */ +struct slca_entry { + __be16 my_index; /* redundant, useful */ + __be16 rsrc_id; /* formerly VPD port number */ + uint8_t fru_id[2]; /* ASCII VPD ID */ +#define SLCA_ROOT_VPD_ID VPD_ID('V','V') +#define SLCA_SYSTEM_VPD_ID VPD_ID('S','V') +#define SLCA_SAI_INDICATOR_ID VPD_ID('S','A') + __be16 parent_index; /* Parent entry index */ + uint8_t flags; +#define SLCA_FLAG_NON_FUNCTIONAL 0x02 /* For redundant entries */ +#define SLCA_FLAG_IMBEDDED 0x01 /* not set => pluggable */ + uint8_t old_nr_child; /* Legacy: Nr of children */ + __be16 child_index; /* First child index */ + __be16 child_rsrc_id; /* Resource ID of first child */ + uint8_t loc_code_allen; /* Alloc len of loc code */ + uint8_t loc_code_len; /* Loc code len */ + uint8_t loc_code[LOC_CODE_SIZE]; /* NULL terminated (thus max 79 chr) */ + __be16 first_dup_idx; /* First redundant resource index */ + uint8_t nr_dups; /* Number of redundant entries */ + uint8_t reserved; + __be16 nr_child; /* New version */ + uint8_t install_indic; /* Installed indicator */ +#define SLCA_INSTALL_NO_HW_PDT 1 /* No HW presence detect */ +#define SLCA_INSTALL_INSTALLED 2 +#define SLCA_INSTALL_NOT_INSTALLED 3 + uint8_t vpd_collected; +#define SLCA_VPD_COLLECTED 2 +#define SLCA_VPD_NOT_COLLECTED 3 +} __packed; + +/* + * System VPD + */ +#define SYSVPD_HDIF_SIG "SYSVPD" + +/* Idata index 0 : FRU ID Data */ +#define SYSVPD_IDATA_FRU_ID 0 + +/* Idata index 1 : Keyword VPD */ +#define SYSVPD_IDATA_KW_VPD 1 + +/* Idata index 2 : Operational status */ +#define SYSVPD_IDATA_OP_STATUS 2 + +/* + * FRU keyword VPD structure + */ +#define FRUVPD_HDIF_SIG "FRUVPD" + +/* Idata index 0 : FRU ID Data */ +#define FRUVPD_IDATA_FRU_ID 0 + +/* Idata index 1 : Keyword VPD */ +#define FRUVPD_IDATA_KW_VPD 1 + +/* Idata index 2 : Operational status */ +#define FRUVPD_IDATA_OP_STATUS 2 + + +/* + * SPPCIA structure. The SPIRA contain an array of these, one + * per processor core + */ +#define SPPCIA_HDIF_SIG "SPPCIA" + +/* Idata index 0 : Core unique data */ +#define SPPCIA_IDATA_CORE_UNIQUE 0 + +struct sppcia_core_unique { + __be32 reserved; + __be32 proc_fru_id; + __be32 hw_proc_id; +#define CPU_ID_VERIFY_MASK 0xC0000000 +#define CPU_ID_VERIFY_SHIFT 30 +#define CPU_ID_VERIFY_USABLE_NO_FAILURES 0 +#define CPU_ID_VERIFY_USABLE_FAILURES 1 +#define CPU_ID_VERIFY_NOT_INSTALLED 2 +#define CPU_ID_VERIFY_UNUSABLE 3 +#define CPU_ID_SECONDARY_THREAD 0x20000000 +#define CPU_ID_PCIA_RESERVED 0x10000000 +#define CPU_ID_NUM_SECONDARY_THREAD_MASK 0x00FF0000 +#define CPU_ID_NUM_SECONDARY_THREAD_SHIFT 16 + __be32 verif_exist_flags; + __be32 chip_ec_level; + __be32 proc_chip_id; + __be32 reserved2; + __be32 reserved3; + __be32 reserved4; + __be32 hw_module_id; + __be64 reserved5; + __be32 reserved6; + __be32 reserved7; + __be32 reserved8; + __be32 ccm_node_id; + __be32 hw_card_id; + __be32 internal_drawer_node_id; + __be32 drawer_book_octant_blade_id; + __be32 memory_interleaving_scope; + __be32 lco_target; + __be32 reserved9; +} __packed; + +/* Idata index 1 : CPU Time base structure */ +#define SPPCIA_IDATA_TIMEBASE 1 + +struct sppcia_cpu_timebase { + __be32 cycle_time; + __be32 time_base; + __be32 actual_clock_speed; + __be32 memory_bus_frequency; +} __packed; + +/* Idata index 2 : CPU Cache Size Structure */ +#define SPPCIA_IDATA_CPU_CACHE 2 + +struct sppcia_cpu_cache { + __be32 icache_size_kb; + __be32 icache_line_size; + __be32 l1_dcache_size_kb; + __be32 l1_dcache_line_size; + __be32 l2_dcache_size_kb; + __be32 l2_line_size; + __be32 l3_dcache_size_kb; + __be32 l3_line_size; + __be32 dcache_block_size; + __be32 icache_block_size; + __be32 dcache_assoc_sets; + __be32 icache_assoc_sets; + __be32 dtlb_entries; + __be32 dtlb_assoc_sets; + __be32 itlb_entries; + __be32 itlb_assoc_sets; + __be32 reservation_size; + __be32 l2_cache_assoc_sets; + __be32 l35_dcache_size_kb; + __be32 l35_cache_line_size; +} __packed; + + +/* Idata index 3 : Thread Array Data + * + * HDIF array of + */ +#define SPPCIA_IDATA_THREAD_ARRAY 3 + +struct sppcia_cpu_thread { + __be32 proc_int_line; + __be32 phys_thread_id; + __be64 ibase; + __be32 pir; +} __packed; + +/* Idata index 4 : CPU Attributes */ +#define SPPCIA_IDATA_CPU_ATTR 4 + +struct sppcia_cpu_attr { +#define CPU_ATTR_UNIFIED_PL1 0x80 +#define CPU_ATTR_SPLIT_TLB 0x40 +#define CPU_ATTR_TLBIA 0x20 +#define CPU_ATTR_PERF_MONITOR 0x10 +#define CPU_ATTR_EXTERN_CONT 0x02 + __be32 attr; +} __packed; + +/* + * Processor Chip Related Data. The SPIRA contain an array of these, one + * per chip + */ +#define SPPCRD_HDIF_SIG "SPPCRD" + +/* Idata index 0 : Chip info */ +#define SPPCRD_IDATA_CHIP_INFO 0 + +struct sppcrd_chip_info { + __be32 proc_chip_id; + __be32 verif_exist_flags; +#define CHIP_VERIFY_MASK 0xC0000000 +#define CHIP_VERIFY_SHIFT 30 +#define CHIP_VERIFY_USABLE_NO_FAILURES 0 +#define CHIP_VERIFY_USABLE_FAILURES 1 +#define CHIP_VERIFY_NOT_INSTALLED 2 +#define CHIP_VERIFY_UNUSABLE 3 +#define CHIP_VERIFY_MASTER_PROC PPC_BIT32(4) + __be32 nx_state; + __be32 pore_state; + __be32 xscom_id; + /* Version 0xA */ + __be32 reserved; + __be32 dbob_id; + __be32 occ_state; + /* Version 0xC - none of these are used */ + __be32 processor_fru_id; + __be32 chip_ec_level; + __be32 hw_module_id; + __be32 hw_card_id; + __be32 internal_drawer_nid; + __be32 ccm_nid; + /* Version 0xD */ + __be32 capp0_func_state; + /* Version 0xE */ + __be32 capp1_func_state; + /* *possibly* from Version 0x20 - check spec */ + __be32 stop_levels; + /* From latest version (possibly 0x21 and later) */ + __be32 sw_xstop_fir_scom; + uint8_t sw_xstop_fir_bitpos; + /* Latest version for P10 */ +#define CHIP_MAX_TOPOLOGY_ENTRIES 32 + uint8_t topology_id_table[CHIP_MAX_TOPOLOGY_ENTRIES]; + uint8_t primary_topology_loc; /* Index in topology_id_table */ + __be32 abc_bus_speed; /* SMP A */ + __be32 wxyz_bus_speed; /* SMP X */ + uint8_t fab_topology_id;/* topology id associated with the chip. */ +} __packed; + +/* Idata index 1 : Chip TOD */ +#define SPPCRD_IDATA_CHIP_TOD 1 + +struct sppcrd_chip_tod { + __be32 flags; + /* CHIPTOD_ID_... values */ + __be32 ctrl_reg_internal; + __be32 tod_ctrl_reg; +} __packed; + +/* Idata index 2 : FRU ID */ +#define SPPCRD_IDATA_FRU_ID 2 + +/* Idata index 3 : ASCII Keyword data */ +#define SPPCRD_IDATA_KW_VPD 3 + +/* Idata index 4 : Module VPD */ +#define SPPCRD_IDATA_MODULE_VPD 4 + +/* Idata index 5 : Chip attached I2C devices */ +#define SPPCRD_IDATA_HOST_I2C 5 + +/* Idata index 5 : Chip attached I2C devices */ +#define SPPCRD_IDATA_PNOR 6 + +/* Idata index 6 : OpenCAPI/NVlink info */ +#define SPPCRD_IDATA_SMP_LINK 7 +struct sppcrd_smp_link { + __be32 link_id; + __be32 usage; +#define SMP_LINK_USE_NONE 0 +#define SMP_LINK_USE_GPU 1 +#define SMP_LINK_USE_OPENCAPI 2 +#define SMP_LINK_USE_INTERPOSER 3 +#define SMP_LINK_USE_DRAWER 4 +#define SMP_LINK_USE_D2D 5 /* GPU to GPU */ + __be32 brick_id; + __be32 lane_mask; + + /* bonded pci slots (mostly a NVLink thing) */ + __be16 pci_slot_idx; + __be16 pci_sideband_slot_idx; + + __be16 slca_idx; /* SLCA index of the *external* port */ + __be16 reserved; + + /* nvlink/ocapi detection devices */ + __be32 i2c_link_cable; + __be32 i2c_presence; + __be32 i2c_micro; + uint8_t link_speed; + uint8_t occ_flag_bit; + __be16 gpu_slca; +} __packed; + +/* Idata index 8 : chip EC Level array */ +#define SPPCRD_IDATA_EC_LEVEL 8 + +struct sppcrd_ecid { + __be32 chip_id; + __be32 ec_level; + __be64 low; /* Processor ECID bit 0-63 */ + __be64 high; /* Processor ECID bit 64-127 */ +} __packed; + +/* + * Host Services Data. + */ +#define HSERV_HDIF_SIG "HOSTSR" + +/* Idata index 0 : System attribute data */ +#define HSERV_IDATA_SYS_ATTR 0 + +/* IPMI sensors mapping data */ +#define IPMI_SENSORS_HDIF_SIG "FRUSE " + +/* Idata index 0 : Sensor mapping data */ +#define IPMI_SENSORS_IDATA_SENSORS 0 + +struct ipmi_sensors_data { + __be32 slca_index; + uint8_t type; + uint8_t id; + uint8_t entity_id; + uint8_t reserved; +} __packed; + +struct ipmi_sensors { + __be32 count; + struct ipmi_sensors_data data[]; +} __packed; + +/* Idata index 1 : LED - sensors ID mapping data */ +#define IPMI_SENSORS_IDATA_LED 1 + +/* + * Node Secure and Trusted Boot Related Data + */ +#define STB_HDIF_SIG "TPMREL" + +/* + * Idata index 0 : Secure Boot and TPM Instance Info + * + * There can be multiple entries with each entry corresponding to + * a master processor that has a TPM device + */ +#define TPMREL_IDATA_SECUREBOOT_TPM_INFO 0 + +struct secureboot_tpm_info { + __be32 chip_id; + __be32 dbob_id; + uint8_t locality1; + uint8_t locality2; + uint8_t locality3; + uint8_t locality4; +#define TPM_PRESENT_AND_FUNCTIONAL 0x01 +#define TPM_PRESENT_AND_NOT_FUNCTIONAL 0x02 +#define TPM_NOT_PRESENT 0x03 + uint8_t tpm_status; + uint8_t reserved[3]; + /* zero indicates no tpm log data */ + __be32 srtm_log_offset; + __be32 srtm_log_size; + /* zero indicates no tpm log data */ + __be32 drtm_log_offset; + __be32 drtm_log_size; +} __packed; + +/* Idata index 2: Hash and Verification Function Offsets Array */ +#define TPMREL_IDATA_HASH_VERIF_OFFSETS 2 + +struct hash_and_verification { +#define TPMREL_HV_SHA512 0x00 +#define TPMREL_HV_VERIFY 0x01 + __be32 type; + __be32 version; + __be32 dbob_id; + __be32 offset; +} __packed; + +static inline const char *cpu_state(u32 flags) +{ + switch ((flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) { + case CPU_ID_VERIFY_USABLE_NO_FAILURES: + return "OK"; + case CPU_ID_VERIFY_USABLE_FAILURES: + return "FAILURES"; + case CPU_ID_VERIFY_NOT_INSTALLED: + return "NOT-INSTALLED"; + case CPU_ID_VERIFY_UNUSABLE: + return "UNUSABLE"; + } + return "**UNKNOWN**"; +} +#endif /* __SPIRA_H */ diff --git a/roms/skiboot/hdata/test/Makefile.check b/roms/skiboot/hdata/test/Makefile.check new file mode 100644 index 000000000..b3cb7e350 --- /dev/null +++ b/roms/skiboot/hdata/test/Makefile.check @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +# -*-Makefile-*- + +HDATA_TEST := hdata/test/hdata_to_dt + +.PHONY : hdata-check hdata-coverage +hdata-check: $(HDATA_TEST:%=%-check) +hdata-coverage: $(HDATA_TEST:%=%-gcov-run) + +check: hdata-check hdata-coverage +coverage: hdata-coverage + +LCOV_EXCLUDE += $(HDATA_TEST:%=%.c) hdata/test/stubs.c +LCOV_EXCLUDE += /usr/include/valgrind/memcheck.h + +hdata/test/hdata_to_dt-check: hdata/test/hdata_to_dt-check-q +hdata/test/hdata_to_dt-check: hdata/test/hdata_to_dt-check-dt + +# Add some test ntuples for open source version... +hdata/test/hdata_to_dt-check-q: hdata/test/hdata_to_dt + $(call Q, TEST , $(VALGRIND) hdata/test/hdata_to_dt -8E -q hdata/test/p81-811.spira hdata/test/p81-811.spira.heap, $<) + $(call Q, TEST , $(VALGRIND) hdata/test/hdata_to_dt -8E -s -q hdata/test/p8-840-spira.spirah hdata/test/p8-840-spira.spiras, $<) + $(call Q, TEST , $(VALGRIND) hdata/test/hdata_to_dt -9 -s -q hdata/test/p8-840-spira.spirah hdata/test/op920.wsp.heap, $<) + +hdata/test/hdata_to_dt-check-dt: hdata/test/hdata_to_dt + $(call Q, TEST , $(VALGRIND) hdata/test/hdata_to_dt -8E hdata/test/p81-811.spira hdata/test/p81-811.spira.heap 2>/dev/null | hdata/test/dtdiff_wrap.sh hdata/test/p81-811.spira.dts, $< device-tree) + $(call Q, TEST , $(VALGRIND) hdata/test/hdata_to_dt -8E -s hdata/test/p8-840-spira.spirah hdata/test/p8-840-spira.spiras 2>/dev/null | hdata/test/dtdiff_wrap.sh hdata/test/p8-840-spira.dts, $< device-tree) + $(call Q, TEST , $(VALGRIND) hdata/test/hdata_to_dt -9 -s hdata/test/p8-840-spira.spirah hdata/test/op920.wsp.heap 2>/dev/null | hdata/test/dtdiff_wrap.sh hdata/test/op920.wsp.dts, $< device-tree) + +hdata/test/hdata_to_dt-gcov-run: hdata/test/hdata_to_dt-check-dt-gcov-run + +hdata/test/hdata_to_dt-check-dt-gcov-run: hdata/test/hdata_to_dt-gcov + $(call Q, TEST-COVERAGE , ./hdata/test/hdata_to_dt-gcov -8E hdata/test/p81-811.spira hdata/test/p81-811.spira.heap 2>/dev/null | hdata/test/dtdiff_wrap.sh hdata/test/p81-811.spira.dts, $< device-tree) + $(call Q, TEST-COVERAGE , ./hdata/test/hdata_to_dt-gcov -8E -s hdata/test/p8-840-spira.spirah hdata/test/p8-840-spira.spiras 2>/dev/null | hdata/test/dtdiff_wrap.sh hdata/test/p8-840-spira.dts, $< device-tree) + $(call Q, TEST-COVERAGE , ./hdata/test/hdata_to_dt -9 -s hdata/test/p8-840-spira.spirah hdata/test/op920.wsp.heap 2>/dev/null | hdata/test/dtdiff_wrap.sh hdata/test/op920.wsp.dts, $< device-tree) + +hdata/test/stubs.o: hdata/test/stubs.c + $(call Q, HOSTCC , $(HOSTCC) $(HOSTCFLAGS) -g -c -o $@ $<, $<) + +$(HDATA_TEST) : hdata/test/stubs.o + +$(CORE_TEST:%=%-gcov): hdata/test/stubs.o + +$(HDATA_TEST) : % : %.c + $(call Q, HOSTCC , $(HOSTCC) $(HOSTCFLAGS) -DTEST -O0 -g -I hdata -I include -I . -I libfdt -o $@ $< hdata/test/stubs.o, $<) + +$(HDATA_TEST:%=%-gcov): %-gcov : %.c % + $(call Q, HOSTCC ,$(HOSTCC) $(HOSTCFLAGS) $(HOSTGCOVCFLAGS) -DTEST -I include -I . -I data -I libfdt -lgcov -o $@ $< hdata/test/stubs.o, $<) + +-include $(wildcard hdata/test/*.d) + +clean: hdata-test-clean + +hdata-test-clean: + $(RM) hdata/test/*.[od] hdata/test/hdata_to_dt + $(RM) $(HDATA_TEST) $(HDATA_TEST:%=%-gcov) diff --git a/roms/skiboot/hdata/test/dtdiff_wrap.sh b/roms/skiboot/hdata/test/dtdiff_wrap.sh new file mode 100755 index 000000000..f92c944b6 --- /dev/null +++ b/roms/skiboot/hdata/test/dtdiff_wrap.sh @@ -0,0 +1,16 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +# +# Takes /dev/stdin as dtb, saves to file, does dtdiff +# Also runs parameter through a dts->dtb->dts conversion +# in order to work around dtc bugs. +# +# Copyright 2018 IBM Corp. + +T=$(mktemp) +cp /dev/stdin $T.dtb +dtc -I dts -O dtb $1 > $T.orig.dtb +dtdiff $T.orig.dtb $T.dtb +R=$? +if [ $R == 0 ]; then rm -f $T $T.orig.dtb $T.dtb; fi +exit $R diff --git a/roms/skiboot/hdata/test/hdata_to_dt.c b/roms/skiboot/hdata/test/hdata_to_dt.c new file mode 100644 index 000000000..1729f1ca9 --- /dev/null +++ b/roms/skiboot/hdata/test/hdata_to_dt.c @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* + * Given a hdata dump, output the device tree. + * + * Copyright 2013-2020 IBM Corp. + */ + +#include <sys/types.h> +#include <sys/stat.h> +#include <sys/mman.h> +#include <fcntl.h> +#include <assert.h> +#include <stdlib.h> +#include <unistd.h> +#include <stdint.h> +#include <mem_region-malloc.h> + +#include <interrupts.h> +#include <bitutils.h> + +#include <skiboot-valgrind.h> + +#include "../../libfdt/fdt.c" +#include "../../libfdt/fdt_ro.c" +#include "../../libfdt/fdt_sw.c" +#include "../../libfdt/fdt_strerror.c" + +struct dt_node *opal_node; + +/* Our actual map. */ +static void *spira_heap; +static off_t spira_heap_size; +static uint64_t base_addr; + +/* Override ntuple_addr. */ +#define ntuple_addr ntuple_addr +struct spira_ntuple; +static void *ntuple_addr(const struct spira_ntuple *n); + +/* Stuff which core expects. */ +struct cpu_thread *my_fake_cpu; +static struct cpu_thread *this_cpu(void) +{ + return my_fake_cpu; +} + +unsigned long tb_hz = 512000000; + +/* Don't include processor-specific stuff. */ +#define __PROCESSOR_H +/* PVR bits */ +#define SPR_PVR_TYPE 0xffff0000 +#define SPR_PVR_VERS_MAJ 0x00000f00 +#define SPR_PVR_VERS_MIN 0x000000ff + +#define PVR_TYPE(_pvr) GETFIELD(SPR_PVR_TYPE, _pvr) +#define PVR_VERS_MAJ(_pvr) GETFIELD(SPR_PVR_VERS_MAJ, _pvr) +#define PVR_VERS_MIN(_pvr) GETFIELD(SPR_PVR_VERS_MIN, _pvr) + +/* PVR definitions - copied from skiboot include/processor.h */ +#define PVR_TYPE_P8E 0x004b +#define PVR_TYPE_P8 0x004d +#define PVR_TYPE_P8NVL 0x004c +#define PVR_TYPE_P9 0x004e +#define PVR_TYPE_P9P 0x004f +#define PVR_TYPE_P10 0x0080 +#define PVR_P8E 0x004b0201 +#define PVR_P8 0x004d0200 +#define PVR_P8NVL 0x004c0100 +#define PVR_P9 0x004e0200 +#define PVR_P9P 0x004f0100 +#define PVR_P10 0x00800100 + +#define SPR_PVR 0x11f /* RO: Processor version register */ + +#define MSR_SF 0x8000000000000000ULL +#define MSR_HV 0x1000000000000000ULL + +#define __CPU_H +struct cpu_thread { + uint32_t pir; + uint32_t chip_id; + bool is_fused_core; +}; +struct cpu_job *__cpu_queue_job(struct cpu_thread *cpu, + const char *name, + void (*func)(void *data), void *data, + bool no_return); +void cpu_wait_job(struct cpu_job *job, bool free_it); +void cpu_process_local_jobs(void); +struct cpu_job *cpu_queue_job_on_node(uint32_t chip_id, + const char *name, + void (*func)(void *data), void *data); +static inline struct cpu_job *cpu_queue_job(struct cpu_thread *cpu, + const char *name, + void (*func)(void *data), + void *data) +{ + return __cpu_queue_job(cpu, name, func, data, false); +} + +struct cpu_thread __boot_cpu, *boot_cpu = &__boot_cpu; +static unsigned long fake_pvr = PVR_P8; + +unsigned int cpu_thread_count = 8; + +static inline unsigned long mfspr(unsigned int spr) +{ + assert(spr == SPR_PVR); + return fake_pvr; +} + +struct dt_node *add_ics_node(void) +{ + return NULL; +} + +// Copied from processor.h: +static inline bool is_power9n(uint32_t version) +{ + if (PVR_TYPE(version) != PVR_TYPE_P9) + return false; + /* + * Bit 13 tells us: + * 0 = Scale out (aka Nimbus) + * 1 = Scale up (aka Cumulus) + */ + if ((version >> 13) & 1) + return false; + return true; +} + +#include <config.h> +#include <bitutils.h> + +/* Your pointers won't be correct, that's OK. */ +#define spira_check_ptr spira_check_ptr + +static bool spira_check_ptr(const void *ptr, const char *file, unsigned int line); + +/* should probably check this */ +#define BITS_PER_LONG 64 +/* not used, just needs to exist */ +#define cpu_max_pir 0x7 + +#include "../cpu-common.c" +#include "../fsp.c" +#include "../hdif.c" +#include "../iohub.c" +#include "../memory.c" +#include "../pcia.c" +#include "../spira.c" +#include "../vpd.c" +#include "../vpd-common.c" +#include "../slca.c" +#include "../hostservices.c" +#include "../i2c.c" +#include "../tpmrel.c" +#include "../../core/vpd.c" +#include "../../core/device.c" +#include "../../core/chip.c" +#include "../../test/dt_common.c" +#include "../../core/fdt.c" +#include "../../hw/phys-map.c" +#include "../../core/mem_region.c" + +#include <err.h> + +#include <op-panel.h> + +bool fsp_present() +{ + return false; +} + +void op_display(enum op_severity s, enum op_module m, uint16_t code) +{ + fprintf(stderr, "op_panel Severity: 0x%x (%s), module %x, %x\n", + s, (s == OP_FATAL) ? "FATAL" : "non-fatal", + m, code); + if (s == OP_FATAL) + exit(EXIT_FAILURE); +} + +char __rodata_start[1], __rodata_end[1]; + +enum proc_gen proc_gen = proc_gen_p8; + +static bool spira_check_ptr(const void *ptr, const char *file, unsigned int line) +{ + if (!ptr) + return false; + /* we fake the SPIRA pointer as it's relative to where it was loaded + * on real hardware */ + (void)file; + (void)line; + return true; +} + +static void *ntuple_addr(const struct spira_ntuple *n) +{ + uint64_t addr = be64_to_cpu(n->addr); + if (n->addr == 0) + return NULL; + if (addr < base_addr) { + fprintf(stderr, "assert failed: addr >= base_addr (%"PRIu64" >= %"PRIu64")\n", addr, base_addr); + exit(EXIT_FAILURE); + } + if (addr >= base_addr + spira_heap_size) { + fprintf(stderr, "assert failed: addr not in spira_heap\n"); + exit(EXIT_FAILURE); + } + return spira_heap + ((unsigned long)addr - base_addr); +} + +/* Make sure valgrind knows these are undefined bytes. */ +static void undefined_bytes(void *p, size_t len) +{ + VALGRIND_MAKE_MEM_UNDEFINED(p, len); +} + +static u32 hash_prop(const struct dt_property *p) +{ + u32 i, hash = 0; + + /* a stupid checksum */ + for (i = 0; i < p->len; i++) + hash += (((signed char)p->prop[i] & ~0x10) + 1) * i; + + return hash; +} + +/* + * This filters out VPD blobs and other annoyances from the devicetree output. + * We don't actually care about the contents of the blob, we just want to make + * sure it's there and that we aren't accidently corrupting the contents. + */ +static void squash_blobs(struct dt_node *root) +{ + struct dt_node *n; + struct dt_property *p; + + list_for_each(&root->properties, p, list) { + if (strstarts(p->name, DT_PRIVATE)) + continue; + + /* + * Consider any property larger than 512 bytes a blob that can + * be removed. This number was picked out of thin in so don't + * feel bad about changing it. + */ + if (p->len > 512) { + u32 hash = hash_prop(p); + u32 *val = (u32 *) p->prop; + + /* Add a sentinel so we know it was truncated */ + val[0] = cpu_to_be32(0xcafebeef); + val[1] = cpu_to_be32(p->len); + val[2] = cpu_to_be32(hash); + p->len = 3 * sizeof(u32); + } + } + + list_for_each(&root->children, n, list) + squash_blobs(n); +} + +static void dump_hdata_fdt(struct dt_node *root) +{ + struct dt_node *n; + void *fdt_blob; + + /* delete some properties that hardcode pointers */ + dt_for_each_node(dt_root, n) { + struct dt_property *base; + + /* + * sml-base is a raw pointer into the HDAT area so it changes + * on each execution of hdata_to_dt. Work around this by + * zeroing it. + */ + base = __dt_find_property(n, "linux,sml-base"); + if (base) + memset(base->prop, 0, base->len); + } + + fdt_blob = create_dtb(root, false); + + if (!fdt_blob) { + fprintf(stderr, "Unable to make flattened DT, no FDT written\n"); + return; + } + + fwrite(fdt_blob, fdt_totalsize(fdt_blob), 1, stdout); + + free(fdt_blob); +} + +int main(int argc, char *argv[]) +{ + int fd, r, i = 0, opt_count = 0; + bool verbose = false, quiet = false, new_spira = false, blobs = false; + + while (argv[++i]) { + if (strcmp(argv[i], "-v") == 0) { + verbose = true; + opt_count++; + } else if (strcmp(argv[i], "-q") == 0) { + quiet = true; + opt_count++; + } else if (strcmp(argv[i], "-s") == 0) { + new_spira = true; + opt_count++; + } else if (strcmp(argv[i], "-b") == 0) { + blobs = true; + opt_count++; + } else if (strcmp(argv[i], "-8E") == 0) { + fake_pvr = PVR_P8E; + proc_gen = proc_gen_p8; + opt_count++; + } else if (strcmp(argv[i], "-8") == 0) { + fake_pvr = PVR_P8; + proc_gen = proc_gen_p8; + opt_count++; + } else if (strcmp(argv[i], "-9") == 0) { + fake_pvr = PVR_P9; + proc_gen = proc_gen_p9; + opt_count++; + } else if (strcmp(argv[i], "-9P") == 0) { + fake_pvr = PVR_P9P; + proc_gen = proc_gen_p9; + opt_count++; + } else if (strcmp(argv[i], "-10") == 0) { + fake_pvr = PVR_P10; + proc_gen = proc_gen_p10; + opt_count++; + } + } + + argc -= opt_count; + argv += opt_count; + if (argc != 3) { + errx(1, "Converts HDAT dumps to DTB.\n" + "\n" + "Usage:\n" + " hdata <opts> <spira-dump> <heap-dump>\n" + " hdata <opts> -s <spirah-dump> <spiras-dump>\n" + "Options: \n" + " -v Verbose\n" + " -q Quiet mode\n" + " -b Keep blobs in the output\n" + "\n" + " -8 Force PVR to POWER8\n" + " -8E Force PVR to POWER8E\n" + " -9 Force PVR to POWER9 (nimbus)\n" + " -9P Force PVR to POWER9P (Axone)\n" + " -10 Force PVR to POWER10\n" + "\n" + "When no PVR is specified -8 is assumed" + "\n" + "Pipe to 'dtc -I dtb -O dts' for human readable output\n"); + } + + /* We don't have phys mapping for P8 */ + if (proc_gen != proc_gen_p8) + phys_map_init(fake_pvr); + + /* Copy in spira dump (assumes little has changed!). */ + if (new_spira) { + fd = open(argv[1], O_RDONLY); + if (fd < 0) + err(1, "opening %s", argv[1]); + r = read(fd, &spirah, sizeof(spirah)); + if (r < sizeof(spirah.hdr)) + err(1, "reading %s gave %i", argv[1], r); + if (verbose) + printf("verbose: read spirah %u bytes\n", r); + close(fd); + + undefined_bytes((void *)&spirah + r, sizeof(spirah) - r); + + base_addr = be64_to_cpu(spirah.ntuples.hs_data_area.addr); + } else { + fd = open(argv[1], O_RDONLY); + if (fd < 0) + err(1, "opening %s", argv[1]); + r = read(fd, &spira, sizeof(spira)); + if (r < sizeof(spira.hdr)) + err(1, "reading %s gave %i", argv[1], r); + if (verbose) + printf("verbose: read spira %u bytes\n", r); + close(fd); + + undefined_bytes((void *)&spira + r, sizeof(spira) - r); + + base_addr = be64_to_cpu(spira.ntuples.heap.addr); + } + + if (!base_addr) + errx(1, "Invalid base addr"); + if (verbose) + printf("verbose: map.base_addr = %llx\n", (long long)base_addr); + + fd = open(argv[2], O_RDONLY); + if (fd < 0) + err(1, "opening %s", argv[2]); + spira_heap_size = lseek(fd, 0, SEEK_END); + if (spira_heap_size < 0) + err(1, "lseek on %s", argv[2]); + spira_heap = mmap(NULL, spira_heap_size, PROT_READ, MAP_SHARED, fd, 0); + if (spira_heap == MAP_FAILED) + err(1, "mmaping %s", argv[3]); + if (verbose) + printf("verbose: mapped %zu at %p\n", + spira_heap_size, spira_heap); + close(fd); + + if (new_spira) + spiras = (struct spiras *)spira_heap; + + if (quiet) { + fclose(stdout); + fclose(stderr); + } + + dt_root = dt_new_root(""); + + if(parse_hdat(false) < 0) { + fprintf(stderr, "FATAL ERROR parsing HDAT\n"); + dt_free(dt_root); + exit(EXIT_FAILURE); + } + + mem_region_init(); + mem_region_release_unused(); + + if (!blobs) + squash_blobs(dt_root); + + if (!quiet) + dump_hdata_fdt(dt_root); + + dt_free(dt_root); + return 0; +} diff --git a/roms/skiboot/hdata/test/op920.wsp.dts b/roms/skiboot/hdata/test/op920.wsp.dts new file mode 100644 index 000000000..f9ead9235 --- /dev/null +++ b/roms/skiboot/hdata/test/op920.wsp.dts @@ -0,0 +1,4910 @@ +/dts-v1/; + +/ { + phandle = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "ibm,powernv", "ibm,p9-openbmc", "ibm,witherspoon"; + ibm,io-base-loc-code = "UOPWR.7887E6A-Node0"; + nest-frequency = <0x0 0x77359400>; + vendor = "IBM"; + ibm,sw-checkstop-fir = <0x5012000 0x1f>; + model = "8335-GTH"; + system-id = "7887E6A"; + model-name = "ibm,witherspoon"; + + bmc { + phandle = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "ibm,ast2500,openbmc"; + + sensors { + phandle = <0x3>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + sensor@1 { + phandle = <0xc>; + compatible = "ibm,ipmi-sensor"; + reg = <0x1>; + ipmi-sensor-type = <0x12>; + }; + + sensor@2 { + phandle = <0xe>; + compatible = "ibm,ipmi-sensor"; + reg = <0x2>; + ipmi-sensor-type = <0x22>; + }; + + sensor@3 { + phandle = <0xb>; + compatible = "ibm,ipmi-sensor"; + reg = <0x3>; + ipmi-sensor-type = <0xf>; + }; + + sensor@4 { + phandle = <0x12>; + compatible = "ibm,ipmi-sensor"; + reg = <0x4>; + ipmi-sensor-type = <0xc4>; + }; + + sensor@5 { + phandle = <0xd>; + compatible = "ibm,ipmi-sensor"; + reg = <0x5>; + ipmi-sensor-type = <0x1f>; + }; + + sensor@6 { + phandle = <0x10>; + compatible = "ibm,ipmi-sensor"; + reg = <0x6>; + ipmi-sensor-type = <0xc2>; + }; + + sensor@7 { + phandle = <0x11>; + compatible = "ibm,ipmi-sensor"; + reg = <0x7>; + ipmi-sensor-type = <0xc3>; + }; + + sensor@8 { + phandle = <0x2b>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x00>; + reg = <0x8>; + ipmi-sensor-type = <0x7>; + }; + + sensor@9 { + phandle = <0x3f>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x08>; + reg = <0x9>; + ipmi-sensor-type = <0x7>; + }; + + sensor@a { + phandle = <0xf>; + compatible = "ibm,ipmi-sensor"; + reg = <0xa>; + ipmi-sensor-type = <0xc1>; + }; + + sensor@b { + phandle = <0x15>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb>; + ipmi-sensor-type = <0xca>; + }; + + sensor@c { + phandle = <0x4>; + compatible = "ibm,ipmi-sensor"; + reg = <0xc>; + ipmi-sensor-type = <0xc7>; + }; + + sensor@d { + phandle = <0x5>; + compatible = "ibm,ipmi-sensor"; + reg = <0xd>; + ipmi-sensor-type = <0xc7>; + }; + + sensor@e { + phandle = <0x6>; + compatible = "ibm,ipmi-sensor"; + reg = <0xe>; + ipmi-sensor-type = <0xc7>; + }; + + sensor@f { + phandle = <0x7>; + compatible = "ibm,ipmi-sensor"; + reg = <0xf>; + ipmi-sensor-type = <0xc7>; + }; + + sensor@10 { + phandle = <0x8>; + compatible = "ibm,ipmi-sensor"; + reg = <0x10>; + ipmi-sensor-type = <0xc7>; + }; + + sensor@59 { + phandle = <0x18>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x00>; + reg = <0x59>; + ipmi-sensor-type = <0x1>; + }; + + sensor@5a { + phandle = <0x1a>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x00>; + reg = <0x5a>; + ipmi-sensor-type = <0x7>; + }; + + sensor@a3 { + phandle = <0x2c>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x08>; + reg = <0xa3>; + ipmi-sensor-type = <0x1>; + }; + + sensor@a4 { + phandle = <0x2e>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x08>; + reg = <0xa4>; + ipmi-sensor-type = <0x7>; + }; + + sensor@a5 { + phandle = <0x1b>; + compatible = "ibm,ipmi-sensor"; + reg = <0xa5>; + ipmi-sensor-type = <0x1>; + }; + + sensor@a6 { + phandle = <0x1c>; + compatible = "ibm,ipmi-sensor"; + reg = <0xa6>; + ipmi-sensor-type = <0xc>; + }; + + sensor@a7 { + phandle = <0x1d>; + compatible = "ibm,ipmi-sensor"; + reg = <0xa7>; + ipmi-sensor-type = <0x1>; + }; + + sensor@a8 { + phandle = <0x1e>; + compatible = "ibm,ipmi-sensor"; + reg = <0xa8>; + ipmi-sensor-type = <0xc>; + }; + + sensor@a9 { + phandle = <0x1f>; + compatible = "ibm,ipmi-sensor"; + reg = <0xa9>; + ipmi-sensor-type = <0x1>; + }; + + sensor@aa { + phandle = <0x20>; + compatible = "ibm,ipmi-sensor"; + reg = <0xaa>; + ipmi-sensor-type = <0xc>; + }; + + sensor@ab { + phandle = <0x21>; + compatible = "ibm,ipmi-sensor"; + reg = <0xab>; + ipmi-sensor-type = <0x1>; + }; + + sensor@ac { + phandle = <0x22>; + compatible = "ibm,ipmi-sensor"; + reg = <0xac>; + ipmi-sensor-type = <0xc>; + }; + + sensor@ad { + phandle = <0x27>; + compatible = "ibm,ipmi-sensor"; + reg = <0xad>; + ipmi-sensor-type = <0x1>; + }; + + sensor@ae { + phandle = <0x28>; + compatible = "ibm,ipmi-sensor"; + reg = <0xae>; + ipmi-sensor-type = <0xc>; + }; + + sensor@af { + phandle = <0x29>; + compatible = "ibm,ipmi-sensor"; + reg = <0xaf>; + ipmi-sensor-type = <0x1>; + }; + + sensor@b0 { + phandle = <0x2a>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb0>; + ipmi-sensor-type = <0xc>; + }; + + sensor@b1 { + phandle = <0x23>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb1>; + ipmi-sensor-type = <0x1>; + }; + + sensor@b2 { + phandle = <0x24>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb2>; + ipmi-sensor-type = <0xc>; + }; + + sensor@b3 { + phandle = <0x25>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb3>; + ipmi-sensor-type = <0x1>; + }; + + sensor@b4 { + phandle = <0x26>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb4>; + ipmi-sensor-type = <0xc>; + }; + + sensor@b5 { + phandle = <0x2f>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb5>; + ipmi-sensor-type = <0x1>; + }; + + sensor@b6 { + phandle = <0x30>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb6>; + ipmi-sensor-type = <0xc>; + }; + + sensor@b7 { + phandle = <0x31>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb7>; + ipmi-sensor-type = <0x1>; + }; + + sensor@b8 { + phandle = <0x32>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb8>; + ipmi-sensor-type = <0xc>; + }; + + sensor@b9 { + phandle = <0x33>; + compatible = "ibm,ipmi-sensor"; + reg = <0xb9>; + ipmi-sensor-type = <0x1>; + }; + + sensor@ba { + phandle = <0x34>; + compatible = "ibm,ipmi-sensor"; + reg = <0xba>; + ipmi-sensor-type = <0xc>; + }; + + sensor@bb { + phandle = <0x35>; + compatible = "ibm,ipmi-sensor"; + reg = <0xbb>; + ipmi-sensor-type = <0x1>; + }; + + sensor@bc { + phandle = <0x36>; + compatible = "ibm,ipmi-sensor"; + reg = <0xbc>; + ipmi-sensor-type = <0xc>; + }; + + sensor@bd { + phandle = <0x3b>; + compatible = "ibm,ipmi-sensor"; + reg = <0xbd>; + ipmi-sensor-type = <0x1>; + }; + + sensor@be { + phandle = <0x3c>; + compatible = "ibm,ipmi-sensor"; + reg = <0xbe>; + ipmi-sensor-type = <0xc>; + }; + + sensor@bf { + phandle = <0x3d>; + compatible = "ibm,ipmi-sensor"; + reg = <0xbf>; + ipmi-sensor-type = <0x1>; + }; + + sensor@c0 { + phandle = <0x3e>; + compatible = "ibm,ipmi-sensor"; + reg = <0xc0>; + ipmi-sensor-type = <0xc>; + }; + + sensor@c1 { + phandle = <0x37>; + compatible = "ibm,ipmi-sensor"; + reg = <0xc1>; + ipmi-sensor-type = <0x1>; + }; + + sensor@c2 { + phandle = <0x38>; + compatible = "ibm,ipmi-sensor"; + reg = <0xc2>; + ipmi-sensor-type = <0xc>; + }; + + sensor@c3 { + phandle = <0x39>; + compatible = "ibm,ipmi-sensor"; + reg = <0xc3>; + ipmi-sensor-type = <0x1>; + }; + + sensor@c4 { + phandle = <0x3a>; + compatible = "ibm,ipmi-sensor"; + reg = <0xc4>; + ipmi-sensor-type = <0xc>; + }; + + sensor@d7 { + phandle = <0x17>; + compatible = "ibm,ipmi-sensor"; + reg = <0xd7>; + ipmi-sensor-type = <0xcc>; + }; + + sensor@d8 { + phandle = <0x14>; + compatible = "ibm,ipmi-sensor"; + reg = <0xd8>; + ipmi-sensor-type = <0xc8>; + }; + + sensor@d9 { + phandle = <0x13>; + compatible = "ibm,ipmi-sensor"; + reg = <0xd9>; + ipmi-sensor-type = <0xc6>; + }; + + sensor@da { + phandle = <0x9>; + compatible = "ibm,ipmi-sensor"; + reg = <0xda>; + ipmi-sensor-type = <0x9>; + }; + + sensor@db { + phandle = <0xa>; + compatible = "ibm,ipmi-sensor"; + reg = <0xdb>; + ipmi-sensor-type = <0xc>; + }; + + sensor@dc { + phandle = <0x16>; + compatible = "ibm,ipmi-sensor"; + reg = <0xdc>; + ipmi-sensor-type = <0xcb>; + }; + + sensor@e0 { + phandle = <0x19>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x00>; + reg = <0xe0>; + ipmi-sensor-type = <0x1>; + }; + + sensor@e1 { + phandle = <0x2d>; + compatible = "ibm,ipmi-sensor"; + ibm,chip-id = <0x08>; + reg = <0xe1>; + ipmi-sensor-type = <0x1>; + }; + }; + }; + + cpus { + phandle = <0x60>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + PowerPC,POWER9@0 { + phandle = <0x61>; + device_type = "cpu"; + status = "okay"; + reg = <0x0>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x62>; + ibm,pir = <0x0>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x0 0x1 0x2 0x3>; + }; + + PowerPC,POWER9@4 { + phandle = <0x64>; + device_type = "cpu"; + status = "okay"; + reg = <0x4>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x62>; + ibm,pir = <0x4>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x4 0x5 0x6 0x7>; + }; + + PowerPC,POWER9@8 { + phandle = <0x65>; + device_type = "cpu"; + status = "okay"; + reg = <0x8>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x66>; + ibm,pir = <0x8>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x8 0x9 0xa 0xb>; + }; + + PowerPC,POWER9@c { + phandle = <0x68>; + device_type = "cpu"; + status = "okay"; + reg = <0xc>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x66>; + ibm,pir = <0xc>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0xc 0xd 0xe 0xf>; + }; + + PowerPC,POWER9@10 { + phandle = <0x69>; + device_type = "cpu"; + status = "okay"; + reg = <0x10>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x6a>; + ibm,pir = <0x10>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x10 0x11 0x12 0x13>; + }; + + PowerPC,POWER9@14 { + phandle = <0x6c>; + device_type = "cpu"; + status = "okay"; + reg = <0x14>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x6a>; + ibm,pir = <0x14>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x14 0x15 0x16 0x17>; + }; + + PowerPC,POWER9@18 { + phandle = <0x6d>; + device_type = "cpu"; + status = "okay"; + reg = <0x18>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x6e>; + ibm,pir = <0x18>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x18 0x19 0x1a 0x1b>; + }; + + PowerPC,POWER9@1c { + phandle = <0x70>; + device_type = "cpu"; + status = "okay"; + reg = <0x1c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x6e>; + ibm,pir = <0x1c>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x1c 0x1d 0x1e 0x1f>; + }; + + PowerPC,POWER9@28 { + phandle = <0x71>; + device_type = "cpu"; + status = "okay"; + reg = <0x28>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x72>; + ibm,pir = <0x28>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x28 0x29 0x2a 0x2b>; + }; + + PowerPC,POWER9@2c { + phandle = <0x74>; + device_type = "cpu"; + status = "okay"; + reg = <0x2c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x72>; + ibm,pir = <0x2c>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x2c 0x2d 0x2e 0x2f>; + }; + + PowerPC,POWER9@30 { + phandle = <0x75>; + device_type = "cpu"; + status = "okay"; + reg = <0x30>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x76>; + ibm,pir = <0x30>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x30 0x31 0x32 0x33>; + }; + + PowerPC,POWER9@34 { + phandle = <0x78>; + device_type = "cpu"; + status = "okay"; + reg = <0x34>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x76>; + ibm,pir = <0x34>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x34 0x35 0x36 0x37>; + }; + + PowerPC,POWER9@38 { + phandle = <0x79>; + device_type = "cpu"; + status = "okay"; + reg = <0x38>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x7a>; + ibm,pir = <0x38>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x38 0x39 0x3a 0x3b>; + }; + + PowerPC,POWER9@3c { + phandle = <0x7c>; + device_type = "cpu"; + status = "okay"; + reg = <0x3c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x7a>; + ibm,pir = <0x3c>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x3c 0x3d 0x3e 0x3f>; + }; + + PowerPC,POWER9@48 { + phandle = <0x7d>; + device_type = "cpu"; + status = "okay"; + reg = <0x48>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x7e>; + ibm,pir = <0x48>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x48 0x49 0x4a 0x4b>; + }; + + PowerPC,POWER9@4c { + phandle = <0x80>; + device_type = "cpu"; + status = "okay"; + reg = <0x4c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x7e>; + ibm,pir = <0x4c>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x4c 0x4d 0x4e 0x4f>; + }; + + PowerPC,POWER9@50 { + phandle = <0x81>; + device_type = "cpu"; + status = "okay"; + reg = <0x50>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x82>; + ibm,pir = <0x50>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x50 0x51 0x52 0x53>; + }; + + PowerPC,POWER9@54 { + phandle = <0x84>; + device_type = "cpu"; + status = "okay"; + reg = <0x54>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x82>; + ibm,pir = <0x54>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x54 0x55 0x56 0x57>; + }; + + PowerPC,POWER9@58 { + phandle = <0x85>; + device_type = "cpu"; + status = "okay"; + reg = <0x58>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x86>; + ibm,pir = <0x58>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x58 0x59 0x5a 0x5b>; + }; + + PowerPC,POWER9@5c { + phandle = <0x88>; + device_type = "cpu"; + status = "okay"; + reg = <0x5c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x86>; + ibm,pir = <0x5c>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x5c 0x5d 0x5e 0x5f>; + }; + + PowerPC,POWER9@800 { + phandle = <0x89>; + device_type = "cpu"; + status = "okay"; + reg = <0x800>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x8a>; + ibm,pir = <0x800>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x800 0x801 0x802 0x803>; + }; + + PowerPC,POWER9@804 { + phandle = <0x8c>; + device_type = "cpu"; + status = "okay"; + reg = <0x804>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x8a>; + ibm,pir = <0x804>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x804 0x805 0x806 0x807>; + }; + + PowerPC,POWER9@808 { + phandle = <0x8d>; + device_type = "cpu"; + status = "okay"; + reg = <0x808>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x8e>; + ibm,pir = <0x808>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x808 0x809 0x80a 0x80b>; + }; + + PowerPC,POWER9@80c { + phandle = <0x90>; + device_type = "cpu"; + status = "okay"; + reg = <0x80c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x8e>; + ibm,pir = <0x80c>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x80c 0x80d 0x80e 0x80f>; + }; + + PowerPC,POWER9@810 { + phandle = <0x91>; + device_type = "cpu"; + status = "okay"; + reg = <0x810>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x92>; + ibm,pir = <0x810>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x810 0x811 0x812 0x813>; + }; + + PowerPC,POWER9@814 { + phandle = <0x94>; + device_type = "cpu"; + status = "okay"; + reg = <0x814>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x92>; + ibm,pir = <0x814>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x814 0x815 0x816 0x817>; + }; + + PowerPC,POWER9@820 { + phandle = <0x95>; + device_type = "cpu"; + status = "okay"; + reg = <0x820>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x96>; + ibm,pir = <0x820>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x820 0x821 0x822 0x823>; + }; + + PowerPC,POWER9@824 { + phandle = <0x98>; + device_type = "cpu"; + status = "okay"; + reg = <0x824>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x96>; + ibm,pir = <0x824>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x824 0x825 0x826 0x827>; + }; + + PowerPC,POWER9@828 { + phandle = <0x99>; + device_type = "cpu"; + status = "okay"; + reg = <0x828>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x9a>; + ibm,pir = <0x828>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x828 0x829 0x82a 0x82b>; + }; + + PowerPC,POWER9@82c { + phandle = <0x9c>; + device_type = "cpu"; + status = "okay"; + reg = <0x82c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x9a>; + ibm,pir = <0x82c>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x82c 0x82d 0x82e 0x82f>; + }; + + PowerPC,POWER9@830 { + phandle = <0x9d>; + device_type = "cpu"; + status = "okay"; + reg = <0x830>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x9e>; + ibm,pir = <0x830>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x830 0x831 0x832 0x833>; + }; + + PowerPC,POWER9@834 { + phandle = <0xa0>; + device_type = "cpu"; + status = "okay"; + reg = <0x834>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x9e>; + ibm,pir = <0x834>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x834 0x835 0x836 0x837>; + }; + + PowerPC,POWER9@838 { + phandle = <0xa1>; + device_type = "cpu"; + status = "okay"; + reg = <0x838>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xa2>; + ibm,pir = <0x838>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x838 0x839 0x83a 0x83b>; + }; + + PowerPC,POWER9@83c { + phandle = <0xa4>; + device_type = "cpu"; + status = "okay"; + reg = <0x83c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xa2>; + ibm,pir = <0x83c>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x83c 0x83d 0x83e 0x83f>; + }; + + PowerPC,POWER9@840 { + phandle = <0xa5>; + device_type = "cpu"; + status = "okay"; + reg = <0x840>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xa6>; + ibm,pir = <0x840>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x840 0x841 0x842 0x843>; + }; + + PowerPC,POWER9@844 { + phandle = <0xa8>; + device_type = "cpu"; + status = "okay"; + reg = <0x844>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xa6>; + ibm,pir = <0x844>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x844 0x845 0x846 0x847>; + }; + + PowerPC,POWER9@850 { + phandle = <0xa9>; + device_type = "cpu"; + status = "okay"; + reg = <0x850>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xaa>; + ibm,pir = <0x850>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x850 0x851 0x852 0x853>; + }; + + PowerPC,POWER9@854 { + phandle = <0xac>; + device_type = "cpu"; + status = "okay"; + reg = <0x854>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xaa>; + ibm,pir = <0x854>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x854 0x855 0x856 0x857>; + }; + + PowerPC,POWER9@858 { + phandle = <0xad>; + device_type = "cpu"; + status = "okay"; + reg = <0x858>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xae>; + ibm,pir = <0x858>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x858 0x859 0x85a 0x85b>; + }; + + PowerPC,POWER9@85c { + phandle = <0xb0>; + device_type = "cpu"; + status = "okay"; + reg = <0x85c>; + cpu-version = <0x4e0200>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,processor-radix-AP-encodings = <0xc 0xa0000010 0x20000015 0x4000001e>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [40 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0x8f0d1800>; + ibm,extended-clock-frequency = <0x0 0x8f0d1800>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x400>; + i-tlb-size = <0x0>; + tlb-size = <0x400>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x8>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0xae>; + ibm,pir = <0x85c>; + ibm,chip-id = <0x8>; + ibm,ppc-interrupt-server#s = <0x85c 0x85d 0x85e 0x85f>; + }; + + l2-cache@20000000 { + phandle = <0x62>; + device_type = "cache"; + reg = <0x20000000>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x63>; + }; + + l2-cache@20000008 { + phandle = <0x66>; + device_type = "cache"; + reg = <0x20000008>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x67>; + }; + + l2-cache@20000010 { + phandle = <0x6a>; + device_type = "cache"; + reg = <0x20000010>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x6b>; + }; + + l2-cache@20000018 { + phandle = <0x6e>; + device_type = "cache"; + reg = <0x20000018>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x6f>; + }; + + l2-cache@20000028 { + phandle = <0x72>; + device_type = "cache"; + reg = <0x20000028>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x73>; + }; + + l2-cache@20000030 { + phandle = <0x76>; + device_type = "cache"; + reg = <0x20000030>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x77>; + }; + + l2-cache@20000038 { + phandle = <0x7a>; + device_type = "cache"; + reg = <0x20000038>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x7b>; + }; + + l2-cache@20000048 { + phandle = <0x7e>; + device_type = "cache"; + reg = <0x20000048>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x7f>; + }; + + l2-cache@20000050 { + phandle = <0x82>; + device_type = "cache"; + reg = <0x20000050>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x83>; + }; + + l2-cache@20000058 { + phandle = <0x86>; + device_type = "cache"; + reg = <0x20000058>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x87>; + }; + + l2-cache@20000800 { + phandle = <0x8a>; + device_type = "cache"; + reg = <0x20000800>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x8b>; + }; + + l2-cache@20000808 { + phandle = <0x8e>; + device_type = "cache"; + reg = <0x20000808>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x8f>; + }; + + l2-cache@20000810 { + phandle = <0x92>; + device_type = "cache"; + reg = <0x20000810>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x93>; + }; + + l2-cache@20000820 { + phandle = <0x96>; + device_type = "cache"; + reg = <0x20000820>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x97>; + }; + + l2-cache@20000828 { + phandle = <0x9a>; + device_type = "cache"; + reg = <0x20000828>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x9b>; + }; + + l2-cache@20000830 { + phandle = <0x9e>; + device_type = "cache"; + reg = <0x20000830>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x9f>; + }; + + l2-cache@20000838 { + phandle = <0xa2>; + device_type = "cache"; + reg = <0x20000838>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0xa3>; + }; + + l2-cache@20000840 { + phandle = <0xa6>; + device_type = "cache"; + reg = <0x20000840>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0xa7>; + }; + + l2-cache@20000850 { + phandle = <0xaa>; + device_type = "cache"; + reg = <0x20000850>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0xab>; + }; + + l2-cache@20000858 { + phandle = <0xae>; + device_type = "cache"; + reg = <0x20000858>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0xaf>; + }; + + l3-cache@30000000 { + phandle = <0x63>; + device_type = "cache"; + reg = <0x30000000>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000008 { + phandle = <0x67>; + device_type = "cache"; + reg = <0x30000008>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000010 { + phandle = <0x6b>; + device_type = "cache"; + reg = <0x30000010>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000018 { + phandle = <0x6f>; + device_type = "cache"; + reg = <0x30000018>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000028 { + phandle = <0x73>; + device_type = "cache"; + reg = <0x30000028>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000030 { + phandle = <0x77>; + device_type = "cache"; + reg = <0x30000030>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000038 { + phandle = <0x7b>; + device_type = "cache"; + reg = <0x30000038>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000048 { + phandle = <0x7f>; + device_type = "cache"; + reg = <0x30000048>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000050 { + phandle = <0x83>; + device_type = "cache"; + reg = <0x30000050>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000058 { + phandle = <0x87>; + device_type = "cache"; + reg = <0x30000058>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000800 { + phandle = <0x8b>; + device_type = "cache"; + reg = <0x30000800>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000808 { + phandle = <0x8f>; + device_type = "cache"; + reg = <0x30000808>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000810 { + phandle = <0x93>; + device_type = "cache"; + reg = <0x30000810>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000820 { + phandle = <0x97>; + device_type = "cache"; + reg = <0x30000820>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000828 { + phandle = <0x9b>; + device_type = "cache"; + reg = <0x30000828>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000830 { + phandle = <0x9f>; + device_type = "cache"; + reg = <0x30000830>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000838 { + phandle = <0xa3>; + device_type = "cache"; + reg = <0x30000838>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000840 { + phandle = <0xa7>; + device_type = "cache"; + reg = <0x30000840>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000850 { + phandle = <0xab>; + device_type = "cache"; + reg = <0x30000850>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + + l3-cache@30000858 { + phandle = <0xaf>; + device_type = "cache"; + reg = <0x30000858>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0xa00000>; + i-cache-size = <0xa00000>; + }; + }; + + ibm,hostboot { + phandle = <0x12a>; + #size-cells = <0x2>; + #address-cells = <0x2>; + + reserved-memory { + phandle = <0x12b>; + ranges; + #size-cells = <0x2>; + #address-cells = <0x2>; + + ibm,HCODE@203ffcea0000 { + phandle = <0x138>; + reg = <0x203f 0xfcea0000 0x0 0x80000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "HCODE"; + }; + + ibm,OCC@203ffd160000 { + phandle = <0x136>; + reg = <0x203f 0xfd160000 0x0 0xa0000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "OCC"; + }; + + ibm,RINGOVD@203ffce70000 { + phandle = <0x139>; + reg = <0x203f 0xfce70000 0x0 0x30000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "RINGOVD"; + }; + + ibm,WOFDATA@203ffcf20000 { + phandle = <0x137>; + reg = <0x203f 0xfcf20000 0x0 0x240000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "WOFDATA"; + }; + + ibm,hbrt-code-image@203ffd250000 { + phandle = <0x130>; + reg = <0x203f 0xfd250000 0x0 0x410000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,hbrt-code-image"; + }; + + ibm,hbrt-data@203ffd660000 { + phandle = <0x12f>; + reg = <0x203f 0xfd660000 0x0 0x1a0000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,hbrt-data"; + }; + + ibm,homer-image@203ffd800000 { + phandle = <0x12c>; + reg = <0x203f 0xfd800000 0x0 0x400000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,homer-image"; + }; + + ibm,homer-image@203ffdc00000 { + phandle = <0x12d>; + reg = <0x203f 0xfdc00000 0x0 0x400000>; + ibm,prd-instance = <0x8>; + ibm,prd-label = "ibm,homer-image"; + }; + + ibm,occ-common-area@203fff800000 { + phandle = <0x12e>; + reg = <0x203f 0xff800000 0x0 0x800000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,occ-common-area"; + }; + + ibm,sbe-comm@203ffd220000 { + phandle = <0x133>; + reg = <0x203f 0xfd220000 0x0 0x10000>; + ibm,prd-instance = <0x8>; + ibm,prd-label = "ibm,sbe-comm"; + }; + + ibm,sbe-comm@203ffd240000 { + phandle = <0x131>; + reg = <0x203f 0xfd240000 0x0 0x10000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,sbe-comm"; + }; + + ibm,sbe-ffdc@203ffd210000 { + phandle = <0x134>; + reg = <0x203f 0xfd210000 0x0 0x10000>; + ibm,prd-instance = <0x8>; + ibm,prd-label = "ibm,sbe-ffdc"; + }; + + ibm,sbe-ffdc@203ffd230000 { + phandle = <0x132>; + reg = <0x203f 0xfd230000 0x0 0x10000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,sbe-ffdc"; + }; + + ibm,secure-crypt-algo-code@203ffd200000 { + phandle = <0x135>; + reg = <0x203f 0xfd200000 0x0 0x10000>; + ibm,prd-instance = <0x0>; + ibm,prd-label = "ibm,secure-crypt-algo-code"; + }; + }; + }; + + ibm,opal { + phandle = <0x5e>; + + fw-features { + phandle = <0xb6>; + + fw-bcctrl-serialized { + phandle = <0xb9>; + enabled; + }; + + fw-branch-hints-honored { + phandle = <0xbd>; + enabled; + }; + + fw-count-cache-disabled { + phandle = <0xbf>; + disabled; + }; + + fw-l1d-thread-split { + phandle = <0xbc>; + enabled; + }; + + fw-ltptr-serialized { + phandle = <0xc0>; + disabled; + }; + + inst-l1d-flush-ori30,30,0 { + phandle = <0xba>; + disabled; + }; + + inst-l1d-flush-trig2 { + phandle = <0xbb>; + enabled; + }; + + inst-spec-barrier-ori31,31,0 { + phandle = <0xb8>; + enabled; + }; + + inst-thread-reconfig-control-trig0-1 { + phandle = <0xbe>; + disabled; + }; + + needs-l1d-flush-msr-hv-1-to-0 { + phandle = <0xc3>; + enabled; + }; + + needs-l1d-flush-msr-pr-0-to-1 { + phandle = <0xc4>; + enabled; + }; + + needs-spec-barrier-for-bound-checks { + phandle = <0xc5>; + enabled; + }; + + speculation-policy-favor-security { + phandle = <0xc1>; + enabled; + }; + + tm-suspend-mode { + phandle = <0xb7>; + enabled; + }; + + user-mode-branch-speculation { + phandle = <0xc2>; + enabled; + }; + }; + + leds { + phandle = <0x5f>; + led-mode = "lightpath"; + }; + + power-mgt { + phandle = <0x181>; + ibm,enabled-stop-levels = <0xec000000>; + }; + }; + + ibm,pcie-slots { + phandle = <0x149>; + #address-cells = <0x2>; + #size-cells = <0x0>; + + root-complex@0,0 { + phandle = <0x14a>; + reg = <0x0 0x0>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x0>; + ibm,slot-label = "SLOT3"; + + pluggable { + phandle = <0x14b>; + mrw-slot-id = <0x3>; + lane-mask = <0xffff>; + ibm,slot-label = "SLOT3"; + }; + }; + + root-complex@0,1 { + phandle = <0x14c>; + reg = <0x0 0x1>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x0>; + lane-mask = <0xff00>; + lanes-reversed = <0x1111>; + + builtin { + phandle = <0x14d>; + }; + }; + + root-complex@0,2 { + phandle = <0x14e>; + reg = <0x0 0x2>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x0>; + lane-mask = <0xff>; + + builtin { + phandle = <0x14f>; + }; + }; + + root-complex@0,3 { + phandle = <0x150>; + reg = <0x0 0x3>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x0>; + ibm,slot-label = "SLOT1"; + + pluggable { + phandle = <0x151>; + mrw-slot-id = <0x1>; + lane-mask = <0xff00>; + ibm,slot-label = "SLOT1"; + }; + }; + + root-complex@0,4 { + phandle = <0x152>; + reg = <0x0 0x4>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x0>; + lane-mask = <0xf0>; + + switch-up@10b5,8725 { + phandle = <0x153>; + reg = <0x10b5 0x8725>; + #address-cells = <0x1>; + #size-cells = <0x0>; + upstream-port = <0x0>; + ibm,pluggable; + + down-port@a { + phandle = <0x154>; + compatible = "ibm,pcie-port"; + reg = <0xa>; + ibm,pluggable; + ibm,slot-label = "GPU0"; + + builtin { + phandle = <0x155>; + ibm,slot-label = "GPU0"; + }; + }; + + down-port@b { + phandle = <0x156>; + compatible = "ibm,pcie-port"; + reg = <0xb>; + ibm,pluggable; + ibm,slot-label = "GPU1"; + + builtin { + phandle = <0x157>; + ibm,slot-label = "GPU1"; + }; + }; + + down-port@c { + phandle = <0x158>; + compatible = "ibm,pcie-port"; + reg = <0xc>; + ibm,pluggable; + ibm,slot-label = "GPU2"; + + builtin { + phandle = <0x159>; + ibm,slot-label = "GPU2"; + }; + }; + }; + }; + + root-complex@0,5 { + phandle = <0x15a>; + reg = <0x0 0x5>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x0>; + lane-mask = <0xf>; + + builtin { + phandle = <0x15b>; + }; + }; + + root-complex@8,0 { + phandle = <0x165>; + reg = <0x8 0x0>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x8>; + ibm,slot-label = "SLOT2"; + + pluggable { + phandle = <0x166>; + mrw-slot-id = <0x2>; + lane-mask = <0xffff>; + ibm,slot-label = "SLOT2"; + max-power = <0x0>; + }; + }; + + root-complex@8,3 { + phandle = <0x167>; + reg = <0x8 0x3>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x8>; + ibm,slot-label = "SLOT1"; + + pluggable { + phandle = <0x168>; + mrw-slot-id = <0x1>; + lane-mask = <0xff00>; + ibm,slot-label = "SLOT1"; + max-power = <0x0>; + }; + }; + + root-complex@8,4 { + phandle = <0x169>; + reg = <0x8 0x4>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x8>; + ibm,slot-label = "SLOT0"; + + pluggable { + phandle = <0x16a>; + lane-mask = <0xf0>; + ibm,slot-label = "SLOT0"; + max-power = <0x0>; + }; + }; + + root-complex@8,5 { + phandle = <0x16b>; + reg = <0x8 0x5>; + #address-cells = <0x2>; + #size-cells = <0x0>; + compatible = "ibm,pcie-port", "ibm,pcie-root-port"; + ibm,chip-id = <0x8>; + lane-mask = <0xf>; + + switch-up@10b5,8725 { + phandle = <0x16c>; + reg = <0x10b5 0x8725>; + #address-cells = <0x1>; + #size-cells = <0x0>; + upstream-port = <0x1>; + ibm,pluggable; + + down-port@4 { + phandle = <0x16d>; + compatible = "ibm,pcie-port"; + reg = <0x4>; + ibm,pluggable; + ibm,slot-label = "GPU3"; + + builtin { + phandle = <0x16e>; + ibm,slot-label = "GPU3"; + }; + }; + + down-port@5 { + phandle = <0x16f>; + compatible = "ibm,pcie-port"; + reg = <0x5>; + ibm,pluggable; + ibm,slot-label = "GPU4"; + + builtin { + phandle = <0x170>; + ibm,slot-label = "GPU4"; + }; + }; + + down-port@d { + phandle = <0x171>; + compatible = "ibm,pcie-port"; + reg = <0xd>; + ibm,pluggable; + ibm,slot-label = "GPU5"; + + builtin { + phandle = <0x172>; + ibm,slot-label = "GPU5"; + }; + }; + }; + }; + }; + + ibm,secureboot { + phandle = <0xb3>; + compatible = "ibm,secureboot", "ibm,secureboot-v2"; + trusted-enabled; + hw-key-hash = <0x40d487ff 0x7380ed6a 0xd54775d5 0x795fea0d 0xe2f541fe 0xa9db06b8 0x466a42a3 0x20e65f75 0xb4866546 0x17d907 0x515dc2a5 0xf9fc5095 0x4d6ee0c9 0xb67d219d 0xfb708535 0x1d01d6d1>; + hw-key-hash-size = <0x40>; + + ibm,cvc { + phandle = <0x182>; + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "ibm,container-verification-code"; + memory-region = <0x135>; + + ibm,cvc-service@40 { + phandle = <0x183>; + compatible = "ibm,cvc-sha512"; + reg = <0x40>; + version = <0x1>; + }; + + ibm,cvc-service@50 { + phandle = <0x184>; + compatible = "ibm,cvc-verify"; + reg = <0x50>; + version = <0x1>; + }; + }; + }; + + ipl-params { + phandle = <0xb1>; + #address-cells = <0x0>; + #size-cells = <0x0>; + + ipl-params { + phandle = <0xb4>; + #address-cells = <0x0>; + #size-cells = <0x0>; + cec-ipl-side = "perm"; + sp-ipl-side = "perm"; + os-ipl-mode = <0x0>; + cec-major-type = "cold"; + }; + + platform-dump { + phandle = <0xb5>; + }; + + sys-params { + phandle = <0xb2>; + #address-cells = <0x0>; + #size-cells = <0x0>; + abc-bus-freq-mhz = < 0x00 0x1250 >; + ibm,sys-model = " GTH"; + elevated-risk-level; + wxyz-bus-freq-mhz = < 0x00 0x7d0 >; + }; + }; + + lpcm-opb@6030000000000 { + phandle = <0x40>; + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "ibm,power9-lpcm-opb", "simple-bus"; + reg = <0x60300 0x0 0x1 0x0>; + ibm,chip-id = <0x0>; + ranges = <0x0 0x60300 0x0 0x80000000 0x80000000 0x60300 0x80000000 0x80000000>; + + lpc-controller@c0012000 { + phandle = <0x43>; + compatible = "ibm,power9-lpc-controller"; + reg = <0xc0012000 0x100>; + }; + + lpc@0 { + phandle = <0x44>; + #address-cells = <0x2>; + #size-cells = <0x1>; + compatible = "ibm,power9-lpc", "ibm,power8-lpc"; + ranges = <0x0 0x0 0xe0000000 0x10000000 0x1 0x0 0xd0010000 0x10000 0x3 0x0 0xf0000000 0x10000000>; + + serial@i3f8 { + phandle = <0x45>; + reg = <0x1 0x3f8 0x1>; + compatible = "ns16550"; + current-speed = <0x1c200>; + clock-frequency = <0x1c2000>; + interrupts = <0x04>; + device_type = "serial"; + }; + }; + + opb-arbiter@c0011000 { + phandle = <0x42>; + compatible = "ibm,power9-lpcm-opb-arbiter"; + reg = <0xc0011000 0x8>; + }; + + opb-master@c0010000 { + phandle = <0x41>; + compatible = "ibm,power9-lpcm-opb-master"; + reg = <0xc0010000 0x60>; + }; + }; + + memory@0 { + phandle = <0x100>; + device_type = "memory"; + reg = <0x0 0x0 0x40 0x0>; + ibm,chip-id = <0x0>; + }; + + memory@200000000000 { + phandle = <0x117>; + device_type = "memory"; + reg = <0x2000 0x0 0x40 0x0>; + ibm,chip-id = <0x8>; + }; + + vpd { + phandle = <0x46>; + compatible = "ibm,opal-v3-vpd"; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0xcafebeef 0x2ed 0x28f118>; + ibm,loc-code = "UOPWR.7887E6A-Sys0"; + + root-node-vpd@a000 { + phandle = <0x47>; + ibm,loc-code = "UOPWR.7887E6A-Sys0"; + fru-type = [56 56]; + reg = <0xa000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84640044 0x52105052 0x4f434553 0x534f5220 0x4d4f4455 0x4c45565a 0x2202043 0x43044142 0x32324345 0x131464e 0x7463132 0x30333038 0x504e0720 0x20202020 0x2020534e 0xc202020 0x20202020 0x20202020 0x20505208 0x36000001 0x33008000 0x48450430 0x30303143 0x54040000 0x4857 0x2000178 0x0 0x0>; + + enclosure@1e00 { + phandle = <0x49>; + ibm,loc-code = "UOPWR.7887E6A-Sys0"; + fru-type = [45 56]; + reg = <0x1e00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + + backplane@800 { + phandle = <0x4a>; + ibm,loc-code = "UOPWR.7887E6A-Node0"; + fru-type = [42 50]; + reg = <0x800>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0xcafebeef 0x2ed 0x28f118>; + vendor = "IBM WS"; + description = "FRU DESCRIPTION"; + part-number = "02CL707"; + serial-number = "YL10UF86B07E"; + build-date = [00]; + + ms-dimm@d000 { + phandle = <0x4b>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM0"; + fru-type = [4d 53]; + reg = <0xd000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e010 0x4b4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d001 { + phandle = <0x4c>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM1"; + fru-type = [4d 53]; + reg = <0xd001>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e01c 0x5b4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d002 { + phandle = <0x4d>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM2"; + fru-type = [4d 53]; + reg = <0xd002>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e01c 0xb34d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000124 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d003 { + phandle = <0x4e>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM3"; + fru-type = [4d 53]; + reg = <0xd003>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393ccf 0xa4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d004 { + phandle = <0x4f>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM6"; + fru-type = [4d 53]; + reg = <0xd004>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e009 0xcf4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d005 { + phandle = <0x50>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM7"; + fru-type = [4d 53]; + reg = <0xd005>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e00f 0xe04d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d006 { + phandle = <0x51>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM4"; + fru-type = [4d 53]; + reg = <0xd006>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e00f 0x9a4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d007 { + phandle = <0x52>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM5"; + fru-type = [4d 53]; + reg = <0xd007>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x1438e00f 0xdf4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533050 0x55413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d008 { + phandle = <0x53>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM8"; + fru-type = [4d 53]; + reg = <0xd008>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cc8 0x6b4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d009 { + phandle = <0x54>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM9"; + fru-type = [4d 53]; + reg = <0xd009>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cc8 0xcb4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d00a { + phandle = <0x55>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM10"; + fru-type = [4d 53]; + reg = <0xd00a>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cc8 0x864d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d00b { + phandle = <0x56>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM11"; + fru-type = [4d 53]; + reg = <0xd00b>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cc8 0xcf4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d00c { + phandle = <0x57>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM14"; + fru-type = [4d 53]; + reg = <0xd00c>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cd5 0x1f4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d00d { + phandle = <0x58>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM15"; + fru-type = [4d 53]; + reg = <0xd00d>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cd5 0x1e4d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d00e { + phandle = <0x59>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM12"; + fru-type = [4d 53]; + reg = <0xd00e>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393cd1 0xb04d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + ms-dimm@d00f { + phandle = <0x5a>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM13"; + fru-type = [4d 53]; + reg = <0xd00f>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,chip-id = <0x8>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + spd = <0x23120c01 0x85290008 0x600003 0x80b8000 0x60d 0xf83f0000 0x6e6e6e11 0x6ef00a 0x20080005 0x601828 0x28007800 0x143c0000 0x0 0x0 0x0 0x16161516 0x3160316 0x3160316 0xd161616 0x16160000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9c00 0x0 0xe7007516 0x11114119 0x8632a0 0x1650500 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7be4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80ce0218 0x19393ced 0x794d3339 0x3341344b 0x34304242 0x322d4354 0x44202020 0x200080ce 0x533036 0x56413330 0x5000100 0x0 0x1010101 0x0 0x0 0xdd0000 0xbadd4471 0x1000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; + + processor@1000 { + phandle = <0x5b>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc0"; + fru-type = [50 46]; + reg = <0x1000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 25 00 52 54 04 56 52 4d 4c 56 44 02 30 31 50 4e 07 30 32 43 59 32 31 30 53 4e 0c 59 41 31 39 33 34 37 34 30 34 35 39 78]; + part-number = "02CY210"; + serial-number = "YA1934740459"; + ibm,chip-id = <0x0>; + vendor = "IBM"; + }; + + processor@1001 { + phandle = <0x5c>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc1"; + fru-type = [50 46]; + reg = <0x1001>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 25 00 52 54 04 56 52 4d 4c 56 44 02 30 31 50 4e 07 30 32 43 59 32 31 30 53 4e 0c 59 41 31 39 33 34 37 32 37 34 36 39 78]; + part-number = "02CY210"; + serial-number = "YA1934727469"; + ibm,chip-id = <0x8>; + vendor = "IBM"; + }; + }; + + service-processor@200 { + phandle = <0x5d>; + ibm,loc-code = "UOPWR.7887E6A-BMC0"; + fru-type = [53 50]; + reg = <0x200>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + + system-vpd@1c00 { + phandle = <0x48>; + ibm,loc-code = "UOPWR.7887E6A-Sys0"; + fru-type = [53 56]; + reg = <0x1c00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + }; + + xscom@603fc00000000 { + phandle = <0xc6>; + ibm,chip-id = <0x0>; + ibm,proc-chip-id = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power9-xscom"; + reg = <0x603fc 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc0"; + ibm,module-vpd = <0xcafebeef 0xffff 0x7972efb8>; + part-number = "02CY210"; + serial-number = "YA1934740459"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x1>; + ecid = <0x18a0057 0x82205718 0x15210000 0xc504e0>; + wafer-id = "6A05U285SO"; + wafer-location = <0x15 0x21>; + primary; + + chiptod@40000 { + phandle = <0x13a>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power9-chiptod"; + primary; + }; + + i2cm@a1000 { + phandle = <0xcd>; + reg = <0xa1000 0x1000>; + compatible = "ibm,power8-i2cm", "ibm,power9-i2cm"; + #size-cells = <0x0>; + #address-cells = <0x1>; + chip-engine# = <0x1>; + clock-frequency = <0x7735940>; + + i2c-bus@0 { + phandle = <0xce>; + reg = <0x0>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@50 { + phandle = <0xcf>; + reg = <0x50>; + link-id = <0x2>; + compatible = "atmel,24c128"; + label = "module-vpd"; + }; + }; + + i2c-bus@2 { + phandle = <0xd1>; + reg = <0x2>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@50 { + phandle = <0xd2>; + reg = <0x50>; + link-id = <0x4>; + compatible = "atmel,24c128"; + label = "module-vpd"; + }; + }; + + i2c-bus@4 { + phandle = <0xd6>; + reg = <0x4>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + gpio@50 { + phandle = <0xd7>; + reg = <0x50>; + link-id = <0x7>; + compatible = "nxp,pca9552"; + label = "opencapi-micro-reset"; + status = "reserved"; + }; + + gpio@51 { + phandle = <0xdf>; + reg = <0x51>; + link-id = <0x13>; + compatible = "nxp,pca9552"; + label = "opencapi-micro-reset"; + status = "reserved"; + }; + }; + + i2c-bus@5 { + phandle = <0xd9>; + reg = <0x5>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + gpio@60 { + phandle = <0xda>; + reg = <0x60>; + link-id = <0x9>; + compatible = "nxp,pca9551"; + label = [00]; + status = "reserved"; + }; + }; + }; + + i2cm@a2000 { + phandle = <0xdc>; + reg = <0xa2000 0x1000>; + compatible = "ibm,power8-i2cm", "ibm,power9-i2cm"; + #size-cells = <0x0>; + #address-cells = <0x1>; + chip-engine# = <0x2>; + clock-frequency = <0x7735940>; + + i2c-bus@0 { + phandle = <0xdd>; + reg = <0x0>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + timeout-ms = <0x7d0>; + + eeprom@50 { + phandle = <0xe1>; + reg = <0x50>; + link-id = <0x17>; + compatible = "atmel,24c128"; + label = "module-vpd"; + }; + + tpm@57 { + phandle = <0xde>; + reg = <0x57>; + link-id = <0xb>; + compatible = "nuvoton,npct650"; + label = "tpm"; + linux,sml-base = <0x0 0x0>; + linux,sml-size = <0x10000>; + }; + }; + }; + + i2cm@a3000 { + phandle = <0xc9>; + reg = <0xa3000 0x1000>; + compatible = "ibm,power8-i2cm", "ibm,power9-i2cm"; + #size-cells = <0x0>; + #address-cells = <0x1>; + chip-engine# = <0x3>; + clock-frequency = <0x7735940>; + + i2c-bus@0 { + phandle = <0xd3>; + reg = <0x0>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@52 { + phandle = <0xd4>; + reg = <0x52>; + link-id = <0x5>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@53 { + phandle = <0xd5>; + reg = <0x53>; + link-id = <0x6>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@54 { + phandle = <0xd8>; + reg = <0x54>; + link-id = <0x8>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@55 { + phandle = <0xdb>; + reg = <0x55>; + link-id = <0xa>; + compatible = "spd"; + label = "dimm-spd"; + }; + }; + + i2c-bus@1 { + phandle = <0xca>; + reg = <0x1>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@52 { + phandle = <0xe0>; + reg = <0x52>; + link-id = <0x14>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@53 { + phandle = <0xcb>; + reg = <0x53>; + link-id = <0x0>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@54 { + phandle = <0xcc>; + reg = <0x54>; + link-id = <0x1>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@55 { + phandle = <0xd0>; + reg = <0x55>; + link-id = <0x3>; + compatible = "spd"; + label = "dimm-spd"; + }; + }; + }; + + mcbist@1 { + phandle = <0x108>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1 0x0>; + + mcs@1 { + phandle = <0x10e>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1>; + + mca@1 { + phandle = <0x111>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1>; + + dimm@d007 { + phandle = <0x112>; + reg = <0xd007>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM5"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e00fdf>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@2 { + phandle = <0x10f>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2>; + + dimm@d006 { + phandle = <0x110>; + reg = <0xd006>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM4"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e00f9a>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + + mcs@2 { + phandle = <0x109>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2>; + + mca@4 { + phandle = <0x10c>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x4>; + + dimm@d005 { + phandle = <0x10d>; + reg = <0xd005>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM7"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e00fe0>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@8 { + phandle = <0x10a>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x8>; + + dimm@d004 { + phandle = <0x10b>; + reg = <0xd004>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM6"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e009cf>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + }; + + mcbist@2 { + phandle = <0xfc>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2 0x0>; + + mcs@4 { + phandle = <0x103>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x4>; + + mca@10 { + phandle = <0x106>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x10>; + + dimm@d003 { + phandle = <0x107>; + reg = <0xd003>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM3"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393ccf0a>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@20 { + phandle = <0x104>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x20>; + + dimm@d002 { + phandle = <0x105>; + reg = <0xd002>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM2"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e01cb3>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + + mcs@8 { + phandle = <0xfd>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x8>; + + mca@40 { + phandle = <0x101>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x40>; + + dimm@d001 { + phandle = <0x102>; + reg = <0xd001>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM1"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e01c5b>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@80 { + phandle = <0xfe>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x80>; + + dimm@d000 { + phandle = <0xff>; + reg = <0xd000>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM0"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x38e0104b>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + }; + + nmmu@5012c40 { + phandle = <0x13e>; + compatible = "ibm,power9-nest-mmu"; + reg = <0x5012c40 0x20>; + }; + + npu@5011000 { + phandle = <0x173>; + reg = <0x5011000 0x2c>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,power9-npu"; + ibm,npu-index = <0x0>; + ibm,npu-links = <0x6>; + + link@0 { + phandle = <0x174>; + compatible = "ibm,npu-link"; + reg = <0x0>; + ibm,npu-link-index = <0x0>; + ibm,workbook-link-id = <0x1>; + ibm,npu-phy = <0x80000000 0x9010c3f>; + ibm,npu-lane-mask = <0xf1e000>; + ibm,npu-brick-id = <0x0>; + ibm,npu-group-id = <0x0>; + ibm,slot-label = "GPU0"; + ibm,pcie-slot = <0x155>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@1 { + phandle = <0x175>; + compatible = "ibm,npu-link"; + reg = <0x1>; + ibm,npu-link-index = <0x1>; + ibm,workbook-link-id = <0x3>; + ibm,npu-phy = <0x80000000 0x9010c3f>; + ibm,npu-lane-mask = <0xe1870>; + ibm,npu-brick-id = <0x1>; + ibm,npu-group-id = <0x0>; + ibm,slot-label = "GPU0"; + ibm,pcie-slot = <0x155>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@2 { + phandle = <0x176>; + compatible = "ibm,npu-link"; + reg = <0x2>; + ibm,npu-link-index = <0x2>; + ibm,workbook-link-id = <0x5>; + ibm,npu-phy = <0x80000000 0x9010c3f>; + ibm,npu-lane-mask = <0x78f>; + ibm,npu-brick-id = <0x2>; + ibm,npu-group-id = <0x0>; + ibm,slot-label = "GPU0"; + ibm,pcie-slot = <0x155>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@3 { + phandle = <0x177>; + compatible = "ibm,npu-link"; + reg = <0x3>; + ibm,npu-link-index = <0x3>; + ibm,workbook-link-id = <0x7>; + ibm,npu-phy = <0x80000000 0xc010c3f>; + ibm,npu-lane-mask = <0x78f>; + ibm,npu-brick-id = <0x9>; + ibm,npu-group-id = <0x1>; + ibm,slot-label = "GPU1"; + ibm,pcie-slot = <0x157>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@4 { + phandle = <0x178>; + compatible = "ibm,npu-link"; + reg = <0x4>; + ibm,npu-link-index = <0x4>; + ibm,workbook-link-id = <0x9>; + ibm,npu-phy = <0x80000000 0xc010c3f>; + ibm,npu-lane-mask = <0xe1870>; + ibm,npu-brick-id = <0xa>; + ibm,npu-group-id = <0x1>; + ibm,slot-label = "GPU1"; + ibm,pcie-slot = <0x157>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@5 { + phandle = <0x179>; + compatible = "ibm,npu-link"; + reg = <0x5>; + ibm,npu-link-index = <0x5>; + ibm,workbook-link-id = <0xb>; + ibm,npu-phy = <0x80000000 0xc010c3f>; + ibm,npu-lane-mask = <0xf1e000>; + ibm,npu-brick-id = <0xb>; + ibm,npu-group-id = <0x1>; + ibm,slot-label = "GPU1"; + ibm,pcie-slot = <0x157>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + }; + + nx@2010000 { + phandle = <0x13c>; + compatible = "ibm,power9-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@4010c00 { + phandle = <0x140>; + reg = <0x4010c00 0x100 0xd010800 0x200>; + compatible = "ibm,power9-pbcq"; + ibm,pec-index = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + ibm,hub-id = <0x0>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc0"; + + stack@0 { + phandle = <0x141>; + reg = <0x0>; + ibm,phb-index = <0x0>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + }; + + pbcq@4011000 { + phandle = <0x142>; + reg = <0x4011000 0x100 0xe010800 0x200>; + compatible = "ibm,power9-pbcq"; + ibm,pec-index = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + ibm,hub-id = <0x0>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc0"; + + stack@0 { + phandle = <0x143>; + reg = <0x0>; + ibm,phb-index = <0x1>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + stack@1 { + phandle = <0x144>; + reg = <0x1>; + ibm,phb-index = <0x2>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + }; + + pbcq@4011400 { + phandle = <0x145>; + reg = <0x4011400 0x100 0xf010800 0x200>; + compatible = "ibm,power9-pbcq"; + ibm,pec-index = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + ibm,hub-id = <0x0>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc0"; + + stack@0 { + phandle = <0x146>; + reg = <0x0>; + ibm,phb-index = <0x3>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + stack@1 { + phandle = <0x147>; + reg = <0x1>; + ibm,phb-index = <0x4>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + stack@2 { + phandle = <0x148>; + reg = <0x2>; + ibm,phb-index = <0x5>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + }; + + psihb@5012900 { + phandle = <0xc7>; + reg = <0x5012900 0x100>; + compatible = "ibm,power9-psihb-x", "ibm,psihb-x"; + }; + + vas@3011800 { + phandle = <0xe3>; + reg = <0x3011800 0x300>; + compatible = "ibm,power9-vas-x"; + ibm,vas-id = <0x0>; + }; + + xive@5013000 { + phandle = <0xc8>; + reg = <0x5013000 0x300>; + compatible = "ibm,power9-xive-x"; + force-assign-bars; + }; + }; + + xscom@623fc00000000 { + phandle = <0xe4>; + ibm,chip-id = <0x8>; + ibm,proc-chip-id = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power9-xscom"; + reg = <0x623fc 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc1"; + ibm,module-vpd = <0xcafebeef 0xffff 0x5edb17e4>; + part-number = "02CY210"; + serial-number = "YA1934727469"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x2>; + ecid = <0x18a0055 0x42105718 0x4d210000 0xf30477>; + wafer-id = "6A05L245SO"; + wafer-location = <0x4d 0x21>; + + chiptod@40000 { + phandle = <0x13b>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power9-chiptod"; + secondary; + }; + + i2cm@a1000 { + phandle = <0xe7>; + reg = <0xa1000 0x1000>; + compatible = "ibm,power8-i2cm", "ibm,power9-i2cm"; + #size-cells = <0x0>; + #address-cells = <0x1>; + chip-engine# = <0x1>; + clock-frequency = <0x7735940>; + + i2c-bus@0 { + phandle = <0xe8>; + reg = <0x0>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@50 { + phandle = <0xe9>; + reg = <0x50>; + link-id = <0x10000>; + compatible = "atmel,24c128"; + label = "module-vpd"; + }; + }; + + i2c-bus@2 { + phandle = <0xf0>; + reg = <0x2>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@50 { + phandle = <0xf1>; + reg = <0x50>; + link-id = <0x10004>; + compatible = "atmel,24c128"; + label = "module-vpd"; + }; + }; + + i2c-bus@4 { + phandle = <0xf3>; + reg = <0x4>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + gpio@50 { + phandle = <0xf4>; + reg = <0x50>; + link-id = <0x10006>; + compatible = "nxp,pca9552"; + label = "opencapi-micro-reset"; + status = "reserved"; + }; + + gpio@51 { + phandle = <0xf5>; + reg = <0x51>; + link-id = <0x10008>; + compatible = "nxp,pca9552"; + label = "opencapi-micro-reset"; + status = "reserved"; + }; + }; + }; + + i2cm@a3000 { + phandle = <0xea>; + reg = <0xa3000 0x1000>; + compatible = "ibm,power8-i2cm", "ibm,power9-i2cm"; + #size-cells = <0x0>; + #address-cells = <0x1>; + chip-engine# = <0x3>; + clock-frequency = <0x7735940>; + + i2c-bus@0 { + phandle = <0xeb>; + reg = <0x0>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@52 { + phandle = <0xfa>; + reg = <0x52>; + link-id = <0x10014>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@53 { + phandle = <0xec>; + reg = <0x53>; + link-id = <0x10001>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@54 { + phandle = <0xef>; + reg = <0x54>; + link-id = <0x10003>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@55 { + phandle = <0xf2>; + reg = <0x55>; + link-id = <0x10005>; + compatible = "spd"; + label = "dimm-spd"; + }; + }; + + i2c-bus@1 { + phandle = <0xed>; + reg = <0x1>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,opal-i2c", "ibm,power8-i2c-port", "ibm,power9-i2c-port"; + bus-frequency = <0x61a80>; + + eeprom@52 { + phandle = <0xf6>; + reg = <0x52>; + link-id = <0x1000e>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@53 { + phandle = <0xf8>; + reg = <0x53>; + link-id = <0x10010>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@54 { + phandle = <0xf9>; + reg = <0x54>; + link-id = <0x10012>; + compatible = "spd"; + label = "dimm-spd"; + }; + + eeprom@55 { + phandle = <0xee>; + reg = <0x55>; + link-id = <0x10002>; + compatible = "spd"; + label = "dimm-spd"; + }; + }; + }; + + mcbist@1 { + phandle = <0x11f>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1 0x0>; + + mcs@1 { + phandle = <0x125>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1>; + + mca@1 { + phandle = <0x128>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1>; + + dimm@d00f { + phandle = <0x129>; + reg = <0xd00f>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM13"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393ced79>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@2 { + phandle = <0x126>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2>; + + dimm@d00e { + phandle = <0x127>; + reg = <0xd00e>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM12"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cd1b0>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + + mcs@2 { + phandle = <0x120>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2>; + + mca@4 { + phandle = <0x123>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x4>; + + dimm@d00d { + phandle = <0x124>; + reg = <0xd00d>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM15"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cd51e>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@8 { + phandle = <0x121>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x8>; + + dimm@d00c { + phandle = <0x122>; + reg = <0xd00c>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM14"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cd51f>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + }; + + mcbist@2 { + phandle = <0x113>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2 0x0>; + + mcs@4 { + phandle = <0x11a>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x4>; + + mca@10 { + phandle = <0x11d>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x10>; + + dimm@d00b { + phandle = <0x11e>; + reg = <0xd00b>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM11"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cc8cf>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@20 { + phandle = <0x11b>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x20>; + + dimm@d00a { + phandle = <0x11c>; + reg = <0xd00a>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM10"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cc886>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + + mcs@8 { + phandle = <0x114>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x8>; + + mca@40 { + phandle = <0x118>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x40>; + + dimm@d009 { + phandle = <0x119>; + reg = <0xd009>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM9"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cc8cb>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + + mca@80 { + phandle = <0x115>; + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x80>; + + dimm@d008 { + phandle = <0x116>; + reg = <0xd008>; + ibm,loc-code = "UOPWR.7887E6A-Node0-DIMM8"; + size = <0x8000>; + status = "okay"; + device_type = "memory-dimm-ddr4"; + memory-id = <0xc>; + product-version = <0x0>; + serial-number = <0x393cc86b>; + part-number = "M393A4K40BB2-CTD "; + manufacturer-id = <0x80ce>; + }; + }; + }; + }; + + nmmu@5012c40 { + phandle = <0x13f>; + compatible = "ibm,power9-nest-mmu"; + reg = <0x5012c40 0x20>; + }; + + npu@5011000 { + phandle = <0x17a>; + reg = <0x5011000 0x2c>; + #size-cells = <0x0>; + #address-cells = <0x1>; + compatible = "ibm,power9-npu"; + ibm,npu-index = <0x1>; + ibm,npu-links = <0x6>; + + link@0 { + phandle = <0x17b>; + compatible = "ibm,npu-link"; + reg = <0x0>; + ibm,npu-link-index = <0x0>; + ibm,workbook-link-id = <0x1>; + ibm,npu-phy = <0x80000000 0x9010c3f>; + ibm,npu-lane-mask = <0xf1e000>; + ibm,npu-brick-id = <0x0>; + ibm,npu-group-id = <0x0>; + ibm,slot-label = "GPU3"; + ibm,pcie-slot = <0x16e>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@1 { + phandle = <0x17c>; + compatible = "ibm,npu-link"; + reg = <0x1>; + ibm,npu-link-index = <0x1>; + ibm,workbook-link-id = <0x3>; + ibm,npu-phy = <0x80000000 0x9010c3f>; + ibm,npu-lane-mask = <0xe1870>; + ibm,npu-brick-id = <0x1>; + ibm,npu-group-id = <0x0>; + ibm,slot-label = "GPU3"; + ibm,pcie-slot = <0x16e>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@2 { + phandle = <0x17d>; + compatible = "ibm,npu-link"; + reg = <0x2>; + ibm,npu-link-index = <0x2>; + ibm,workbook-link-id = <0x5>; + ibm,npu-phy = <0x80000000 0x9010c3f>; + ibm,npu-lane-mask = <0x78f>; + ibm,npu-brick-id = <0x2>; + ibm,npu-group-id = <0x0>; + ibm,slot-label = "GPU3"; + ibm,pcie-slot = <0x16e>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@3 { + phandle = <0x17e>; + compatible = "ibm,npu-link"; + reg = <0x3>; + ibm,npu-link-index = <0x3>; + ibm,workbook-link-id = <0x7>; + ibm,npu-phy = <0x80000000 0xc010c3f>; + ibm,npu-lane-mask = <0x78f>; + ibm,npu-brick-id = <0x9>; + ibm,npu-group-id = <0x1>; + ibm,slot-label = "GPU4"; + ibm,pcie-slot = <0x170>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@4 { + phandle = <0x17f>; + compatible = "ibm,npu-link"; + reg = <0x4>; + ibm,npu-link-index = <0x4>; + ibm,workbook-link-id = <0x9>; + ibm,npu-phy = <0x80000000 0xc010c3f>; + ibm,npu-lane-mask = <0xe1870>; + ibm,npu-brick-id = <0xa>; + ibm,npu-group-id = <0x1>; + ibm,slot-label = "GPU4"; + ibm,pcie-slot = <0x170>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + + link@5 { + phandle = <0x180>; + compatible = "ibm,npu-link"; + reg = <0x5>; + ibm,npu-link-index = <0x5>; + ibm,workbook-link-id = <0xb>; + ibm,npu-phy = <0x80000000 0xc010c3f>; + ibm,npu-lane-mask = <0xf1e000>; + ibm,npu-brick-id = <0xb>; + ibm,npu-group-id = <0x1>; + ibm,slot-label = "GPU4"; + ibm,pcie-slot = <0x170>; + ibm,link-speed = <0x6 0xaea7d0>; + nvidia,link-speed = <0x8>; + }; + }; + + nx@2010000 { + phandle = <0x13d>; + compatible = "ibm,power9-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@4010c00 { + phandle = <0x15c>; + reg = <0x4010c00 0x100 0xd010800 0x200>; + compatible = "ibm,power9-pbcq"; + ibm,pec-index = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + ibm,hub-id = <0x1>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc1"; + + stack@0 { + phandle = <0x15d>; + reg = <0x0>; + ibm,phb-index = <0x0>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + }; + + pbcq@4011000 { + phandle = <0x15e>; + reg = <0x4011000 0x100 0xe010800 0x200>; + compatible = "ibm,power9-pbcq"; + ibm,pec-index = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + ibm,hub-id = <0x1>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc1"; + + stack@0 { + phandle = <0x15f>; + reg = <0x0>; + ibm,phb-index = <0x1>; + compatible = "ibm,power9-phb-stack"; + status = "disabled"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + stack@1 { + phandle = <0x160>; + reg = <0x1>; + ibm,phb-index = <0x2>; + compatible = "ibm,power9-phb-stack"; + status = "disabled"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + }; + + pbcq@4011400 { + phandle = <0x161>; + reg = <0x4011400 0x100 0xf010800 0x200>; + compatible = "ibm,power9-pbcq"; + ibm,pec-index = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + ibm,hub-id = <0x1>; + ibm,loc-code = "UOPWR.7887E6A-Node0-Proc1"; + + stack@0 { + phandle = <0x162>; + reg = <0x0>; + ibm,phb-index = <0x3>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + stack@1 { + phandle = <0x163>; + reg = <0x1>; + ibm,phb-index = <0x4>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + stack@2 { + phandle = <0x164>; + reg = <0x2>; + ibm,phb-index = <0x5>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + ibm,lane-eq = <0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x54545454 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + }; + + psihb@5012900 { + phandle = <0xe5>; + reg = <0x5012900 0x100>; + compatible = "ibm,power9-psihb-x", "ibm,psihb-x"; + }; + + vas@3011800 { + phandle = <0xfb>; + reg = <0x3011800 0x300>; + compatible = "ibm,power9-vas-x"; + ibm,vas-id = <0x1>; + }; + + xive@5013000 { + phandle = <0xe6>; + reg = <0x5013000 0x300>; + compatible = "ibm,power9-xive-x"; + force-assign-bars; + }; + }; +}; diff --git a/roms/skiboot/hdata/test/op920.wsp.heap b/roms/skiboot/hdata/test/op920.wsp.heap Binary files differnew file mode 100644 index 000000000..77bff65c9 --- /dev/null +++ b/roms/skiboot/hdata/test/op920.wsp.heap diff --git a/roms/skiboot/hdata/test/p8-840-spira.dts b/roms/skiboot/hdata/test/p8-840-spira.dts new file mode 100644 index 000000000..625935d30 --- /dev/null +++ b/roms/skiboot/hdata/test/p8-840-spira.dts @@ -0,0 +1,1085 @@ +/dts-v1/; + +/memreserve/ 0x00000007fd510000 0x0000000000190000; +/memreserve/ 0x00000007fd6a0000 0x0000000000060000; +/memreserve/ 0x00000007fd700000 0x0000000000100000; +/ { + phandle = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + lid-type = "phyp"; + compatible = "ibm,powernv", "ibm,firenze"; + nest-frequency = <0x0 0x77359400>; + vendor = "IBM"; + ibm,io-base-loc-code = "U78C9.001.WZS0CWX-P1"; + ibm,vpd-lx-info = <0x0 0x31000401 0x300043>; + model = "8286-41A"; + system-id = "TU00163"; + system-brand = "S0"; + model-name = "IBM Power System S814"; + ibm,hbrt-mini-fdt = <0xcafebeef 0x1000 0x31ce42d>; + reserved-ranges = <0x7 0xfd700000 0x0 0x100000 0x7 0xfd6a0000 0x0 0x60000 0x7 0xfd510000 0x0 0x190000>; + reserved-names = "ibm,hbrt-vpd-image", "ibm,hbrt-target-image", "ibm,hbrt-code-image"; + ibm,enabled-idle-states = "nap", "fast-sleep", "rvwinkle"; + + cpus { + phandle = <0x22>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + PowerPC,POWER8@28 { + phandle = <0x23>; + device_type = "cpu"; + status = "okay"; + reg = <0x28>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xb45d1880>; + ibm,extended-clock-frequency = <0x0 0xb45d1880>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x24>; + ibm,pir = <0x28>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f>; + }; + + PowerPC,POWER8@60 { + phandle = <0x27>; + device_type = "cpu"; + status = "okay"; + reg = <0x60>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xb45d1880>; + ibm,extended-clock-frequency = <0x0 0xb45d1880>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x28>; + ibm,pir = <0x60>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67>; + }; + + PowerPC,POWER8@68 { + phandle = <0x2b>; + device_type = "cpu"; + status = "okay"; + reg = <0x68>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xb45d1880>; + ibm,extended-clock-frequency = <0x0 0xb45d1880>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x2c>; + ibm,pir = <0x68>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + }; + + PowerPC,POWER8@b0 { + phandle = <0x2f>; + device_type = "cpu"; + status = "okay"; + reg = <0xb0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xb45d1880>; + ibm,extended-clock-frequency = <0x0 0xb45d1880>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x30>; + ibm,pir = <0xb0>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7>; + }; + + PowerPC,POWER8@e8 { + phandle = <0x33>; + device_type = "cpu"; + status = "okay"; + reg = <0xe8>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xb45d1880>; + ibm,extended-clock-frequency = <0x0 0xb45d1880>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x34>; + ibm,pir = <0xe8>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef>; + }; + + PowerPC,POWER8@f0 { + phandle = <0x37>; + device_type = "cpu"; + status = "okay"; + reg = <0xf0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xb45d1880>; + ibm,extended-clock-frequency = <0x0 0xb45d1880>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x38>; + ibm,pir = <0xf0>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7>; + }; + + l2-cache@20000028 { + phandle = <0x24>; + device_type = "cache"; + reg = <0x20000028>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x25>; + }; + + l2-cache@20000060 { + phandle = <0x28>; + device_type = "cache"; + reg = <0x20000060>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x29>; + }; + + l2-cache@20000068 { + phandle = <0x2c>; + device_type = "cache"; + reg = <0x20000068>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x2d>; + }; + + l2-cache@200000b0 { + phandle = <0x30>; + device_type = "cache"; + reg = <0x200000b0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x31>; + }; + + l2-cache@200000e8 { + phandle = <0x34>; + device_type = "cache"; + reg = <0x200000e8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x35>; + }; + + l2-cache@200000f0 { + phandle = <0x38>; + device_type = "cache"; + reg = <0x200000f0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x39>; + }; + + l3-cache@30000028 { + phandle = <0x25>; + device_type = "cache"; + reg = <0x30000028>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000060 { + phandle = <0x29>; + device_type = "cache"; + reg = <0x30000060>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000068 { + phandle = <0x2d>; + device_type = "cache"; + reg = <0x30000068>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000b0 { + phandle = <0x31>; + device_type = "cache"; + reg = <0x300000b0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000e8 { + phandle = <0x35>; + device_type = "cache"; + reg = <0x300000e8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000f0 { + phandle = <0x39>; + device_type = "cache"; + reg = <0x300000f0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + }; + + fsps { + phandle = <0x46>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + fsp@0 { + phandle = <0x47>; + reg = <0x0>; + compatible = "ibm,fsp", "ibm,fsp2"; + reg-offset = <0xb0011000>; + hw-version = <0x2>; + sw-version = <0x1>; + primary; + ibm,psi-links = <0x0>; + }; + }; + + ibm,opal { + phandle = <0x20>; + + leds { + phandle = <0x21>; + led-mode = "lightpath"; + + U78C9.001.WZS0CWX-D1 { + phandle = <0x7000015>; + led-types = "attention"; + }; + }; + }; + + interrupt-controller@3ffff80028000 { + phandle = <0x26>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x28 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80028000 0x0 0x1000 0x3ffff 0x80029000 0x0 0x1000 0x3ffff 0x8002a000 0x0 0x1000 0x3ffff 0x8002b000 0x0 0x1000 0x3ffff 0x8002c000 0x0 0x1000 0x3ffff 0x8002d000 0x0 0x1000 0x3ffff 0x8002e000 0x0 0x1000 0x3ffff 0x8002f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80060000 { + phandle = <0x2a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x60 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80060000 0x0 0x1000 0x3ffff 0x80061000 0x0 0x1000 0x3ffff 0x80062000 0x0 0x1000 0x3ffff 0x80063000 0x0 0x1000 0x3ffff 0x80064000 0x0 0x1000 0x3ffff 0x80065000 0x0 0x1000 0x3ffff 0x80066000 0x0 0x1000 0x3ffff 0x80067000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80068000 { + phandle = <0x2e>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x68 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80068000 0x0 0x1000 0x3ffff 0x80069000 0x0 0x1000 0x3ffff 0x8006a000 0x0 0x1000 0x3ffff 0x8006b000 0x0 0x1000 0x3ffff 0x8006c000 0x0 0x1000 0x3ffff 0x8006d000 0x0 0x1000 0x3ffff 0x8006e000 0x0 0x1000 0x3ffff 0x8006f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80130000 { + phandle = <0x32>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xb0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80130000 0x0 0x1000 0x3ffff 0x80131000 0x0 0x1000 0x3ffff 0x80132000 0x0 0x1000 0x3ffff 0x80133000 0x0 0x1000 0x3ffff 0x80134000 0x0 0x1000 0x3ffff 0x80135000 0x0 0x1000 0x3ffff 0x80136000 0x0 0x1000 0x3ffff 0x80137000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80168000 { + phandle = <0x36>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xe8 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80168000 0x0 0x1000 0x3ffff 0x80169000 0x0 0x1000 0x3ffff 0x8016a000 0x0 0x1000 0x3ffff 0x8016b000 0x0 0x1000 0x3ffff 0x8016c000 0x0 0x1000 0x3ffff 0x8016d000 0x0 0x1000 0x3ffff 0x8016e000 0x0 0x1000 0x3ffff 0x8016f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80170000 { + phandle = <0x3a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xf0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80170000 0x0 0x1000 0x3ffff 0x80171000 0x0 0x1000 0x3ffff 0x80172000 0x0 0x1000 0x3ffff 0x80173000 0x0 0x1000 0x3ffff 0x80174000 0x0 0x1000 0x3ffff 0x80175000 0x0 0x1000 0x3ffff 0x80176000 0x0 0x1000 0x3ffff 0x80177000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + ipl-params { + phandle = <0x3b>; + #address-cells = <0x0>; + #size-cells = <0x0>; + + fsp-serial { + phandle = <0x3e>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + serial@2a00 { + phandle = <0x3f>; + reg = <0x2a00>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C1-T1"; + compatible = "ibm,fsp-serial"; + }; + }; + + ipl-params { + phandle = <0x3d>; + #address-cells = <0x0>; + #size-cells = <0x0>; + cec-ipl-side = "temp"; + fsp-ipl-side = "temp"; + os-ipl-mode = <0x0>; + cec-major-type = "cold"; + }; + + platform-dump { + phandle = <0x40>; + }; + + sys-params { + phandle = <0x3c>; + #address-cells = <0x0>; + #size-cells = <0x0>; + abc-bus-freq-mhz = < 0x00 0x1900 >; + ibm,sys-model = " 41A"; + wxyz-bus-freq-mhz = < 0x00 0xfa0 >; + + }; + }; + + memory@0 { + phandle = <0x45>; + device_type = "memory"; + ibm,chip-id = <0x0>; + reg = <0x0 0x0 0x8 0x0>; + }; + + vpd { + phandle = <0x2>; + compatible = "ibm,opal-v3-vpd"; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84b00052 0x54045653 0x59534452 0x6535953 0x54454d42 0x52025330 0x53450754 0x55303031 0x36335347 0x7202020 0x20202020 0x544d0838 0x3238362d 0x34314154 0x4e082020 0x20202020 0x20204d4e 0x7202020 0x20202020 0x49440220 0x20535506 0x4ac19 0x77064e4e 0x10202020 0x20202020 0x20202020 0x20202020 0x20524704 0xf0c00000 0x52420433 0x20202057 0x4e0c4330 0x35303736 0x30364237 0x30344656 0x20202020 0x20202020 0x20202020 0x20202020 0x20202020 0x20202020 0x20202020 0x20202020 0x20504603 0x78 0x0>; + ibm,loc-code = "U8286.41A.TU00163"; + + root-node-vpd@a000 { + phandle = <0x3>; + ibm,loc-code = "U8286.41A.TU00163"; + fru-type = [56 56]; + reg = <0xa000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + + enclosure@1e00 { + phandle = <0x5>; + ibm,loc-code = "U78C9.001.WZS0CWX"; + fru-type = [45 56]; + reg = <0x1e00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x848c0052 0x54045649 0x4e494452 0x10492f4f 0x20424143 0x4b504c41 0x4e452020 0x20434501 0x31565a02 0x3031464e 0x7373459 0x34333434 0x504e0730 0x30453432 0x3431534e 0xc594c33 0x30554635 0x354e3030 0x36434304 0x32434435 0x50520821 0x0 0x48 0x45043030 0x30324354 0x480f300 0x26485702 0x74233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x5046 0x2000078 0x841c0052 0x54044c58 0x5230565a 0x230314c 0x58083100 0x4010030 0x435046 0x2000078 0x84440052 0x54045643 0x454e4452 0x6434543 0x20202053 0x4507575a 0x53304357 0x58544d08 0x20202020 0x20202020 0x46430837 0x3843392d 0x30303152 0x470400a0 0xb32c5242 0x4202020 0x20504603 0x78 0x0>; + fru-number = "74Y4344"; + serial-number = "YL30UF55N006"; + part-number = "00E4241"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 f3 00]; + hw-characteristics = [00]; + ccin = "2CD5"; + description = "System planar 1S4U"; + + air-mover@3a00 { + phandle = <0xd>; + ibm,loc-code = "U78C9.001.WZS0CWX-A1"; + fru-type = [41 4d]; + reg = <0x3a00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + air-mover@3a01 { + phandle = <0xe>; + ibm,loc-code = "U78C9.001.WZS0CWX-A2"; + fru-type = [41 4d]; + reg = <0x3a01>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + backplane@800 { + phandle = <0x6>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1"; + fru-type = [42 50]; + reg = <0x800>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x848c0052 0x54045649 0x4e494452 0x10492f4f 0x20424143 0x4b504c41 0x4e452020 0x20434501 0x31565a02 0x3031464e 0x7373459 0x34333434 0x504e0730 0x30453432 0x3431534e 0xc594c33 0x30554635 0x354e3030 0x36434304 0x32434435 0x50520821 0x0 0x48 0x45043030 0x30324354 0x480f300 0x26485702 0x74233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x5046 0x2000078 0x841c0052 0x54044c58 0x5230565a 0x230314c 0x58083100 0x4010030 0x435046 0x2000078 0x0>; + fru-number = "74Y4344"; + serial-number = "YL30UF55N006"; + part-number = "00E4241"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 f3 00]; + hw-characteristics = [00]; + ccin = "2CD5"; + description = "System planar 1S4U"; + + anchor-card@500 { + phandle = <0x14>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C13"; + fru-type = [41 56]; + reg = <0x500>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84cc0052 0x54045649 0x4e494452 0x10414e43 0x484f5220 0x20202020 0x20202020 0x20434501 0x31565a02 0x3031464e 0x7303045 0x32313532 0x504e0730 0x30453231 0x3438534e 0xc594c31 0x30424733 0x3132314e 0x4a434304 0x35324632 0x50520881 0x300000 0x48 0x45043030 0x31304354 0x440b400 0x485702 0x14233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x4239 0x3c435331 0x58150757 0x4e705f53 0x50f139a0 0xbf7efeb7 0x44d314d 0xd7cd74f2 0x862d884d 0x327cb552 0x79809378 0xa24d333e 0x6aed1eb8 0x49dab34d 0x344e1745 0x9bf468e9 0xa1504603 0x78 0x0>; + fru-number = "00E2152"; + serial-number = "YL10BG3121NJ"; + part-number = "00E2148"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [40 b4 00]; + hw-characteristics = [00]; + ccin = "52F2"; + description = "System Anchor Card - IBM Power 814"; + }; + + backplane-extender@900 { + phandle = <0x11>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C1"; + fru-type = [42 58]; + reg = <0x900>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84800052 0x54045649 0x4e494452 0x104e4154 0x49564520 0x492f4f20 0x43415244 0x20434501 0x31565a02 0x3031464e 0x7303045 0x31393630 0x504e0730 0x30453338 0x3039534e 0xc594c31 0x30554635 0x3537304c 0x39434304 0x32423042 0x48450430 0x30303143 0x540480b5 0x4857 0x2000142 0x33060000 0x0 0x42340100 0x42370c00 0x0 0x0 0x50 0x46010078 0x0>; + fru-number = "00E1960"; + serial-number = "YL10UF5570L9"; + part-number = "00E3809"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 b5 00]; + hw-characteristics = [00]; + ccin = "2B0B"; + description = "Native I/O Card"; + + serial-connector@2a00 { + phandle = <0x1f>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C1-T1"; + fru-type = [43 53]; + reg = <0x2a00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2900 { + phandle = <0x1d>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C1-T3"; + fru-type = [43 55]; + reg = <0x2900>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2901 { + phandle = <0x1e>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C1-T2"; + fru-type = [43 55]; + reg = <0x2901>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + + hmc-connector@2d00 { + phandle = <0x19>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-T3"; + fru-type = [48 4d]; + reg = <0x2d00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + hmc-connector@2d01 { + phandle = <0x1a>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-T4"; + fru-type = [48 4d]; + reg = <0x2d01>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + ms-dimm@d000 { + phandle = <0x1b>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C16"; + fru-type = [4d 53]; + reg = <0xd000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84940052 0x54045649 0x4e494452 0x1049424d 0x20313647 0x42204d53 0x20202020 0x20434501 0x31565a02 0x3034464e 0x7343154 0x39353735 0x504e0734 0x31543935 0x3735534e 0xc594833 0x314d5333 0x41343031 0x31434304 0x33314530 0x50520849 0x0 0x1000053 0x5a073030 0x31363338 0x34484504 0x30303031 0x43540400 0x48 0x57020090 0x42330600 0x0 0x423401 0x42370c 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "41T9575"; + serial-number = "YH31MS3A4011"; + part-number = "41T9575"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "31E0"; + description = "16GB CDIMM"; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "16384"; + }; + + ms-dimm@d002 { + phandle = <0x1c>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C18"; + fru-type = [4d 53]; + reg = <0xd002>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84940052 0x54045649 0x4e494452 0x1049424d 0x20313647 0x42204d53 0x20202020 0x20434501 0x31565a02 0x3034464e 0x7343154 0x39353735 0x504e0734 0x31543935 0x3735534e 0xc594833 0x314d5533 0x41433143 0x50434304 0x33314530 0x50520849 0x0 0x1000053 0x5a073030 0x31363338 0x34484504 0x30303031 0x43540400 0x48 0x57020090 0x42330600 0x0 0x423401 0x42370c 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "41T9575"; + serial-number = "YH31MU3AC1CP"; + part-number = "41T9575"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "31E0"; + description = "16GB CDIMM"; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "16384"; + }; + + processor@1000 { + phandle = <0x12>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + fru-type = [50 46]; + reg = <0x1000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 8c 00 52 54 04 56 49 4e 49 44 52 10 30 36 2d 57 41 59 20 50 52 4f 43 20 43 55 4f 44 46 4e 07 30 30 46 58 35 32 33 50 4e 07 30 30 46 58 37 34 38 53 4e 0c 59 41 31 39 33 32 30 36 33 35 36 32 43 43 04 35 34 45 31 48 45 04 30 30 30 31 43 54 04 00 00 00 00 48 57 02 00 01 42 33 06 00 00 00 00 00 00 42 34 01 00 42 37 0c 00 00 00 00 00 00 00 00 00 00 00 00 50 52 08 35 00 30 01 44 00 80 01 56 5a 02 30 31 43 45 01 31 50 46 02 00 00 78 00]; + fru-number = "00FX523"; + serial-number = "YA1932063562"; + part-number = "00FX748"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "54E1"; + description = "06-WAY PROC CUOD"; + ibm,chip-id = <0x0>; + }; + + processor@1001 { + phandle = <0x13>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + fru-type = [50 46]; + reg = <0x1001>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 8c 00 52 54 04 56 49 4e 49 44 52 10 30 36 2d 57 41 59 20 50 52 4f 43 20 43 55 4f 44 46 4e 07 30 30 46 58 35 32 33 50 4e 07 30 30 46 58 37 34 38 53 4e 0c 59 41 31 39 33 32 30 36 33 35 36 32 43 43 04 35 34 45 31 48 45 04 30 30 30 31 43 54 04 00 00 00 00 48 57 02 00 01 42 33 06 00 00 00 00 00 00 42 34 01 00 42 37 0c 00 00 00 00 00 00 00 00 00 00 00 00 50 52 08 35 00 30 01 44 00 80 01 56 5a 02 30 31 43 45 01 31 50 46 02 00 00 78 00]; + fru-number = "00FX523"; + serial-number = "YA1932063562"; + part-number = "00FX748"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "54E1"; + description = "06-WAY PROC CUOD"; + ibm,chip-id = <0x1>; + }; + + usb-connector@2902 { + phandle = <0x15>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-T1"; + fru-type = [43 55]; + reg = <0x2902>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2903 { + phandle = <0x16>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-T2"; + fru-type = [43 55]; + reg = <0x2903>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2904 { + phandle = <0x17>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-T5"; + fru-type = [43 55]; + reg = <0x2904>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2905 { + phandle = <0x18>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-T6"; + fru-type = [43 55]; + reg = <0x2905>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + + dasd-backplane@2400 { + phandle = <0x9>; + ibm,loc-code = "U78C9.001.WZS0CWX-P2"; + fru-type = [44 42]; + reg = <0x2400>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + dasd-backplane@2401 { + phandle = <0xa>; + ibm,loc-code = "U78C9.001.WZS0CWX-P2"; + fru-type = [44 42]; + reg = <0x2401>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + enclosure-fault-led@a300 { + phandle = <0x10>; + ibm,loc-code = "U78C9.001.WZS0CWX-D1"; + fru-type = [45 46]; + reg = <0xa300>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + enclosure-led@a200 { + phandle = <0xf>; + ibm,loc-code = "U78C9.001.WZS0CWX-D1"; + fru-type = [45 49]; + reg = <0xa200>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + op-panel@300 { + phandle = <0x8>; + ibm,loc-code = "U78C9.001.WZS0CWX-D1"; + fru-type = [4f 50]; + reg = <0x300>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84800052 0x54045649 0x4e494452 0x10434543 0x204f5020 0x50414e45 0x4c202020 0x20434501 0x31565a02 0x3032464e 0x7303045 0x31393636 0x504e0730 0x30453239 0x3532534e 0xc594c33 0x30554633 0x38453033 0x52434304 0x32423038 0x48450430 0x30303143 0x540480b5 0x4857 0x2000242 0x33060000 0x0 0x42340100 0x42370c00 0x0 0x0 0x50 0x46010078 0x0>; + fru-number = "00E1966"; + serial-number = "YL30UF38E03R"; + part-number = "00E2952"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 b5 00]; + hw-characteristics = [00]; + ccin = "2B08"; + description = "CEC OP PANEL"; + }; + + power-supply@3102 { + phandle = <0xb>; + ibm,loc-code = "U78C9.001.WZS0CWX-E3"; + fru-type = [50 53]; + reg = <0x3102>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + power-supply@3103 { + phandle = <0xc>; + ibm,loc-code = "U78C9.001.WZS0CWX-E4"; + fru-type = [50 53]; + reg = <0x3103>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + service-processor@200 { + phandle = <0x7>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1"; + fru-type = [53 50]; + reg = <0x200>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x848c0052 0x54045649 0x4e494452 0x10492f4f 0x20424143 0x4b504c41 0x4e452020 0x20434501 0x31565a02 0x3031464e 0x7373459 0x34333434 0x504e0730 0x30453432 0x3431534e 0xc594c33 0x30554635 0x354e3030 0x36434304 0x32434435 0x50520821 0x0 0x48 0x45043030 0x30324354 0x480f300 0x26485702 0x74233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x5046 0x2000078 0x841c0052 0x54044c58 0x5230565a 0x230314c 0x58083100 0x4010030 0x435046 0x2000078 0x84500052 0x54045652 0x31304452 0x10465350 0x20202020 0x20202020 0x20202020 0x20464704 0x564e5350 0x44430f42 0x44203230 0x31323032 0x32303038 0x3030464c 0x14503120 0x20202020 0x20202020 0x20202020 0x20202020 0x20504603 0x78 0x84400052 0x54045657 0x31304452 0x10465350 0x20565731 0x30202020 0x20202020 0x20474420 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "74Y4344"; + serial-number = "YL30UF55N006"; + part-number = "00E4241"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 f3 00]; + hw-characteristics = [00]; + ccin = "2CD5"; + description = "System planar 1S4U"; + }; + }; + + system-vpd@1c00 { + phandle = <0x4>; + ibm,loc-code = "U8286.41A.TU00163"; + fru-type = [53 56]; + reg = <0x1c00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + }; + + xscom@3fc0000000000 { + phandle = <0x41>; + ibm,chip-id = <0x0>; + ibm,proc-chip-id = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power8-xscom"; + reg = <0x3fc00 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + ibm,module-vpd = <0xcafebeef 0x10000 0xa502aa2f>; + part-number = "00KV631"; + serial-number = "YA1932063562"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x0>; + ibm,mem-interleave-scope = <0x0>; + + chiptod@40000 { + phandle = <0x48>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power8-chiptod"; + primary; + }; + + nx@2010000 { + phandle = <0x4a>; + compatible = "ibm,power-nx", "ibm,power8-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@2012000 { + phandle = <0x4c>; + reg = <0x2012000 0x20 0x9012000 0x05 0x9013c00 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x0>; + ibm,hub-id = <0x0>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + pbcq@2012400 { + phandle = <0x4d>; + reg = <0x2012400 0x20 0x9012400 0x05 0x9013c40 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x1>; + ibm,hub-id = <0x0>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x0 0x0 0x0 0x0>; + }; + + psihb@2010900 { + phandle = <0x42>; + reg = <0x2010900 0x20>; + compatible = "ibm,power8-psihb-x", "ibm,psihb-x"; + boot-link; + status = "ok"; + }; + }; + + xscom@3fc0800000000 { + phandle = <0x43>; + ibm,chip-id = <0x1>; + ibm,proc-chip-id = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power8-xscom"; + reg = <0x3fc08 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + ibm,module-vpd = <0xcafebeef 0x10000 0x9f87fa41>; + part-number = "00KV631"; + serial-number = "YA1932063562"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x0>; + ibm,mem-interleave-scope = <0x0>; + + chiptod@40000 { + phandle = <0x49>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power8-chiptod"; + secondary; + }; + + nx@2010000 { + phandle = <0x4b>; + compatible = "ibm,power-nx", "ibm,power8-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@2012000 { + phandle = <0x4e>; + reg = <0x2012000 0x20 0x9012000 0x05 0x9013c00 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x0>; + ibm,hub-id = <0x1>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + pbcq@2012400 { + phandle = <0x4f>; + reg = <0x2012400 0x20 0x9012400 0x05 0x9013c40 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x1>; + ibm,hub-id = <0x1>; + ibm,loc-code = "U78C9.001.WZS0CWX-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x68686868 0x68686868 0x68686868 0x68686868 0x0 0x0 0x0 0x0>; + }; + + psihb@2010900 { + phandle = <0x44>; + reg = <0x2010900 0x20>; + compatible = "ibm,power8-psihb-x", "ibm,psihb-x"; + }; + }; +}; diff --git a/roms/skiboot/hdata/test/p8-840-spira.spirah b/roms/skiboot/hdata/test/p8-840-spira.spirah Binary files differnew file mode 100644 index 000000000..4879b1028 --- /dev/null +++ b/roms/skiboot/hdata/test/p8-840-spira.spirah diff --git a/roms/skiboot/hdata/test/p8-840-spira.spiras b/roms/skiboot/hdata/test/p8-840-spira.spiras Binary files differnew file mode 100644 index 000000000..e3ff5c3d1 --- /dev/null +++ b/roms/skiboot/hdata/test/p8-840-spira.spiras diff --git a/roms/skiboot/hdata/test/p81-811.spira b/roms/skiboot/hdata/test/p81-811.spira Binary files differnew file mode 100644 index 000000000..369b8b7e6 --- /dev/null +++ b/roms/skiboot/hdata/test/p81-811.spira diff --git a/roms/skiboot/hdata/test/p81-811.spira.dts b/roms/skiboot/hdata/test/p81-811.spira.dts new file mode 100644 index 000000000..ed7bd5deb --- /dev/null +++ b/roms/skiboot/hdata/test/p81-811.spira.dts @@ -0,0 +1,2418 @@ +/dts-v1/; + +/memreserve/ 0x0000001ffd586000 0x0000000000137000; +/memreserve/ 0x0000001ffd6bd000 0x0000000000043000; +/memreserve/ 0x0000001ffd700000 0x0000000000100000; + +/ { + phandle = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + lid-type = "phyp"; + compatible = "ibm,powernv", "ibm,firenze"; + nest-frequency = <0x0 0x77359400>; + vendor = "IBM"; + ibm,io-base-loc-code = "U78CB.001.WZS00AL-P1"; + ibm,vpd-lx-info = <0x0 0x31000401 0x300042>; + model = "8247-22L"; + system-id = "1010C8A"; + system-brand = "S0"; + model-name = "IBM Power System S822L"; + ibm,hbrt-mini-fdt = <0xcafebeef 0x1000 0xfad5bb>; + reserved-ranges = <0x1f 0xfd700000 0x0 0x100000 0x1f 0xfd6bd000 0x0 0x43000 0x1f 0xfd586000 0x0 0x137000>; + reserved-names = "ibm,hbrt-vpd-image", "ibm,hbrt-target-image", "ibm,hbrt-code-image"; + ibm,enabled-idle-states = "nap", "fast-sleep", "rvwinkle"; + + cpus { + phandle = <0x2a>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + PowerPC,POWER8@20 { + phandle = <0x2b>; + device_type = "cpu"; + status = "okay"; + reg = <0x20>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x2c>; + ibm,pir = <0x20>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27>; + }; + + PowerPC,POWER8@30 { + phandle = <0x2f>; + device_type = "cpu"; + status = "okay"; + reg = <0x30>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x30>; + ibm,pir = <0x30>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37>; + }; + + PowerPC,POWER8@60 { + phandle = <0x33>; + device_type = "cpu"; + status = "okay"; + reg = <0x60>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x34>; + ibm,pir = <0x60>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67>; + }; + + PowerPC,POWER8@68 { + phandle = <0x37>; + device_type = "cpu"; + status = "okay"; + reg = <0x68>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x38>; + ibm,pir = <0x68>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f>; + }; + + PowerPC,POWER8@70 { + phandle = <0x3b>; + device_type = "cpu"; + status = "okay"; + reg = <0x70>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x3c>; + ibm,pir = <0x70>; + ibm,chip-id = <0x0>; + ibm,ppc-interrupt-server#s = <0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77>; + }; + + PowerPC,POWER8@a8 { + phandle = <0x3f>; + device_type = "cpu"; + status = "okay"; + reg = <0xa8>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x40>; + ibm,pir = <0xa8>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf>; + }; + + PowerPC,POWER8@b0 { + phandle = <0x43>; + device_type = "cpu"; + status = "okay"; + reg = <0xb0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x44>; + ibm,pir = <0xb0>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7>; + }; + + PowerPC,POWER8@e0 { + phandle = <0x47>; + device_type = "cpu"; + status = "okay"; + reg = <0xe0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x48>; + ibm,pir = <0xe0>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7>; + }; + + PowerPC,POWER8@e8 { + phandle = <0x4b>; + device_type = "cpu"; + status = "okay"; + reg = <0xe8>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x4c>; + ibm,pir = <0xe8>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef>; + }; + + PowerPC,POWER8@f0 { + phandle = <0x4f>; + device_type = "cpu"; + status = "okay"; + reg = <0xf0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x50>; + ibm,pir = <0xf0>; + ibm,chip-id = <0x1>; + ibm,ppc-interrupt-server#s = <0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7>; + }; + + PowerPC,POWER8@828 { + phandle = <0x53>; + device_type = "cpu"; + status = "okay"; + reg = <0x828>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x54>; + ibm,pir = <0x828>; + ibm,chip-id = <0x10>; + ibm,ppc-interrupt-server#s = <0x828 0x829 0x82a 0x82b 0x82c 0x82d 0x82e 0x82f>; + }; + + PowerPC,POWER8@830 { + phandle = <0x57>; + device_type = "cpu"; + status = "okay"; + reg = <0x830>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x58>; + ibm,pir = <0x830>; + ibm,chip-id = <0x10>; + ibm,ppc-interrupt-server#s = <0x830 0x831 0x832 0x833 0x834 0x835 0x836 0x837>; + }; + + PowerPC,POWER8@860 { + phandle = <0x5b>; + device_type = "cpu"; + status = "okay"; + reg = <0x860>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x5c>; + ibm,pir = <0x860>; + ibm,chip-id = <0x10>; + ibm,ppc-interrupt-server#s = <0x860 0x861 0x862 0x863 0x864 0x865 0x866 0x867>; + }; + + PowerPC,POWER8@868 { + phandle = <0x5f>; + device_type = "cpu"; + status = "okay"; + reg = <0x868>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x60>; + ibm,pir = <0x868>; + ibm,chip-id = <0x10>; + ibm,ppc-interrupt-server#s = <0x868 0x869 0x86a 0x86b 0x86c 0x86d 0x86e 0x86f>; + }; + + PowerPC,POWER8@870 { + phandle = <0x63>; + device_type = "cpu"; + status = "okay"; + reg = <0x870>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x64>; + ibm,pir = <0x870>; + ibm,chip-id = <0x10>; + ibm,ppc-interrupt-server#s = <0x870 0x871 0x872 0x873 0x874 0x875 0x876 0x877>; + }; + + PowerPC,POWER8@8a0 { + phandle = <0x67>; + device_type = "cpu"; + status = "okay"; + reg = <0x8a0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x68>; + ibm,pir = <0x8a0>; + ibm,chip-id = <0x11>; + ibm,ppc-interrupt-server#s = <0x8a0 0x8a1 0x8a2 0x8a3 0x8a4 0x8a5 0x8a6 0x8a7>; + }; + + PowerPC,POWER8@8a8 { + phandle = <0x6b>; + device_type = "cpu"; + status = "okay"; + reg = <0x8a8>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x6c>; + ibm,pir = <0x8a8>; + ibm,chip-id = <0x11>; + ibm,ppc-interrupt-server#s = <0x8a8 0x8a9 0x8aa 0x8ab 0x8ac 0x8ad 0x8ae 0x8af>; + }; + + PowerPC,POWER8@8b0 { + phandle = <0x6f>; + device_type = "cpu"; + status = "okay"; + reg = <0x8b0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x70>; + ibm,pir = <0x8b0>; + ibm,chip-id = <0x11>; + ibm,ppc-interrupt-server#s = <0x8b0 0x8b1 0x8b2 0x8b3 0x8b4 0x8b5 0x8b6 0x8b7>; + }; + + PowerPC,POWER8@8e8 { + phandle = <0x73>; + device_type = "cpu"; + status = "okay"; + reg = <0x8e8>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x74>; + ibm,pir = <0x8e8>; + ibm,chip-id = <0x11>; + ibm,ppc-interrupt-server#s = <0x8e8 0x8e9 0x8ea 0x8eb 0x8ec 0x8ed 0x8ee 0x8ef>; + }; + + PowerPC,POWER8@8f0 { + phandle = <0x77>; + device_type = "cpu"; + status = "okay"; + reg = <0x8f0>; + cpu-version = <0x4b0201>; + 64-bit; + 32-64-bridge; + graphics; + general-purpose; + ibm,processor-segment-sizes = <0x1c 0x28 0xffffffff 0xffffffff>; + ibm,processor-page-sizes = <0xc 0x10 0x18 0x22>; + ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,pa-features = [18 00 f6 3f c7 c0 80 d0 80 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 80 00]; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + ibm,dfp = <0x2>; + ibm,purr = <0x1>; + ibm,spurr = <0x1>; + clock-frequency = <0xcc255a40>; + ibm,extended-clock-frequency = <0x0 0xcc255a40>; + timebase-frequency = <0x1e848000>; + ibm,extended-timebase-frequency = <0x0 0x1e848000>; + reservation-granule-size = <0x80>; + d-tlb-size = <0x800>; + i-tlb-size = <0x0>; + tlb-size = <0x800>; + d-tlb-sets = <0x4>; + i-tlb-sets = <0x0>; + tlb-sets = <0x4>; + d-cache-block-size = <0x80>; + i-cache-block-size = <0x80>; + d-cache-size = <0x10000>; + i-cache-size = <0x8000>; + i-cache-sets = <0x4>; + d-cache-sets = <0x8>; + performance-monitor = <0x0 0x1>; + l2-cache = <0x78>; + ibm,pir = <0x8f0>; + ibm,chip-id = <0x11>; + ibm,ppc-interrupt-server#s = <0x8f0 0x8f1 0x8f2 0x8f3 0x8f4 0x8f5 0x8f6 0x8f7>; + }; + + l2-cache@20000020 { + phandle = <0x2c>; + device_type = "cache"; + reg = <0x20000020>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x2d>; + }; + + l2-cache@20000030 { + phandle = <0x30>; + device_type = "cache"; + reg = <0x20000030>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x31>; + }; + + l2-cache@20000060 { + phandle = <0x34>; + device_type = "cache"; + reg = <0x20000060>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x35>; + }; + + l2-cache@20000068 { + phandle = <0x38>; + device_type = "cache"; + reg = <0x20000068>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x39>; + }; + + l2-cache@20000070 { + phandle = <0x3c>; + device_type = "cache"; + reg = <0x20000070>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x3d>; + }; + + l2-cache@200000a8 { + phandle = <0x40>; + device_type = "cache"; + reg = <0x200000a8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x41>; + }; + + l2-cache@200000b0 { + phandle = <0x44>; + device_type = "cache"; + reg = <0x200000b0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x45>; + }; + + l2-cache@200000e0 { + phandle = <0x48>; + device_type = "cache"; + reg = <0x200000e0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x49>; + }; + + l2-cache@200000e8 { + phandle = <0x4c>; + device_type = "cache"; + reg = <0x200000e8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x4d>; + }; + + l2-cache@200000f0 { + phandle = <0x50>; + device_type = "cache"; + reg = <0x200000f0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x51>; + }; + + l2-cache@20000828 { + phandle = <0x54>; + device_type = "cache"; + reg = <0x20000828>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x55>; + }; + + l2-cache@20000830 { + phandle = <0x58>; + device_type = "cache"; + reg = <0x20000830>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x59>; + }; + + l2-cache@20000860 { + phandle = <0x5c>; + device_type = "cache"; + reg = <0x20000860>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x5d>; + }; + + l2-cache@20000868 { + phandle = <0x60>; + device_type = "cache"; + reg = <0x20000868>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x61>; + }; + + l2-cache@20000870 { + phandle = <0x64>; + device_type = "cache"; + reg = <0x20000870>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x65>; + }; + + l2-cache@200008a0 { + phandle = <0x68>; + device_type = "cache"; + reg = <0x200008a0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x69>; + }; + + l2-cache@200008a8 { + phandle = <0x6c>; + device_type = "cache"; + reg = <0x200008a8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x6d>; + }; + + l2-cache@200008b0 { + phandle = <0x70>; + device_type = "cache"; + reg = <0x200008b0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x71>; + }; + + l2-cache@200008e8 { + phandle = <0x74>; + device_type = "cache"; + reg = <0x200008e8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x75>; + }; + + l2-cache@200008f0 { + phandle = <0x78>; + device_type = "cache"; + reg = <0x200008f0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x80000>; + i-cache-size = <0x80000>; + l2-cache = <0x79>; + }; + + l3-cache@30000020 { + phandle = <0x2d>; + device_type = "cache"; + reg = <0x30000020>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000030 { + phandle = <0x31>; + device_type = "cache"; + reg = <0x30000030>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000060 { + phandle = <0x35>; + device_type = "cache"; + reg = <0x30000060>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000068 { + phandle = <0x39>; + device_type = "cache"; + reg = <0x30000068>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000070 { + phandle = <0x3d>; + device_type = "cache"; + reg = <0x30000070>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000a8 { + phandle = <0x41>; + device_type = "cache"; + reg = <0x300000a8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000b0 { + phandle = <0x45>; + device_type = "cache"; + reg = <0x300000b0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000e0 { + phandle = <0x49>; + device_type = "cache"; + reg = <0x300000e0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000e8 { + phandle = <0x4d>; + device_type = "cache"; + reg = <0x300000e8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300000f0 { + phandle = <0x51>; + device_type = "cache"; + reg = <0x300000f0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000828 { + phandle = <0x55>; + device_type = "cache"; + reg = <0x30000828>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000830 { + phandle = <0x59>; + device_type = "cache"; + reg = <0x30000830>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000860 { + phandle = <0x5d>; + device_type = "cache"; + reg = <0x30000860>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000868 { + phandle = <0x61>; + device_type = "cache"; + reg = <0x30000868>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@30000870 { + phandle = <0x65>; + device_type = "cache"; + reg = <0x30000870>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300008a0 { + phandle = <0x69>; + device_type = "cache"; + reg = <0x300008a0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300008a8 { + phandle = <0x6d>; + device_type = "cache"; + reg = <0x300008a8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300008b0 { + phandle = <0x71>; + device_type = "cache"; + reg = <0x300008b0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300008e8 { + phandle = <0x75>; + device_type = "cache"; + reg = <0x300008e8>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + + l3-cache@300008f0 { + phandle = <0x79>; + device_type = "cache"; + reg = <0x300008f0>; + status = "okay"; + cache-unified; + d-cache-sets = <0x8>; + i-cache-sets = <0x8>; + d-cache-size = <0x800000>; + i-cache-size = <0x800000>; + }; + }; + + fsps { + phandle = <0x8b>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + fsp@0 { + phandle = <0x8c>; + reg = <0x0>; + compatible = "ibm,fsp", "ibm,fsp2"; + reg-offset = <0xb0011000>; + hw-version = <0x2>; + sw-version = <0x1>; + primary; + ibm,psi-links = <0x0 0x10>; + }; + }; + + ibm,opal { + phandle = <0x28>; + + leds { + phandle = <0x29>; + led-mode = "lightpath"; + + U8247.22L.1010C8A { + phandle = <0x9d>; + led-types = "attention"; + }; + }; + }; + + interrupt-controller@3ffff80020000 { + phandle = <0x2e>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x20 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80020000 0x0 0x1000 0x3ffff 0x80021000 0x0 0x1000 0x3ffff 0x80022000 0x0 0x1000 0x3ffff 0x80023000 0x0 0x1000 0x3ffff 0x80024000 0x0 0x1000 0x3ffff 0x80025000 0x0 0x1000 0x3ffff 0x80026000 0x0 0x1000 0x3ffff 0x80027000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80030000 { + phandle = <0x32>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x30 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80030000 0x0 0x1000 0x3ffff 0x80031000 0x0 0x1000 0x3ffff 0x80032000 0x0 0x1000 0x3ffff 0x80033000 0x0 0x1000 0x3ffff 0x80034000 0x0 0x1000 0x3ffff 0x80035000 0x0 0x1000 0x3ffff 0x80036000 0x0 0x1000 0x3ffff 0x80037000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80060000 { + phandle = <0x36>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x60 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80060000 0x0 0x1000 0x3ffff 0x80061000 0x0 0x1000 0x3ffff 0x80062000 0x0 0x1000 0x3ffff 0x80063000 0x0 0x1000 0x3ffff 0x80064000 0x0 0x1000 0x3ffff 0x80065000 0x0 0x1000 0x3ffff 0x80066000 0x0 0x1000 0x3ffff 0x80067000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80068000 { + phandle = <0x3a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x68 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80068000 0x0 0x1000 0x3ffff 0x80069000 0x0 0x1000 0x3ffff 0x8006a000 0x0 0x1000 0x3ffff 0x8006b000 0x0 0x1000 0x3ffff 0x8006c000 0x0 0x1000 0x3ffff 0x8006d000 0x0 0x1000 0x3ffff 0x8006e000 0x0 0x1000 0x3ffff 0x8006f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80070000 { + phandle = <0x3e>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x70 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80070000 0x0 0x1000 0x3ffff 0x80071000 0x0 0x1000 0x3ffff 0x80072000 0x0 0x1000 0x3ffff 0x80073000 0x0 0x1000 0x3ffff 0x80074000 0x0 0x1000 0x3ffff 0x80075000 0x0 0x1000 0x3ffff 0x80076000 0x0 0x1000 0x3ffff 0x80077000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80128000 { + phandle = <0x42>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xa8 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80128000 0x0 0x1000 0x3ffff 0x80129000 0x0 0x1000 0x3ffff 0x8012a000 0x0 0x1000 0x3ffff 0x8012b000 0x0 0x1000 0x3ffff 0x8012c000 0x0 0x1000 0x3ffff 0x8012d000 0x0 0x1000 0x3ffff 0x8012e000 0x0 0x1000 0x3ffff 0x8012f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80130000 { + phandle = <0x46>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xb0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80130000 0x0 0x1000 0x3ffff 0x80131000 0x0 0x1000 0x3ffff 0x80132000 0x0 0x1000 0x3ffff 0x80133000 0x0 0x1000 0x3ffff 0x80134000 0x0 0x1000 0x3ffff 0x80135000 0x0 0x1000 0x3ffff 0x80136000 0x0 0x1000 0x3ffff 0x80137000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80160000 { + phandle = <0x4a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xe0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80160000 0x0 0x1000 0x3ffff 0x80161000 0x0 0x1000 0x3ffff 0x80162000 0x0 0x1000 0x3ffff 0x80163000 0x0 0x1000 0x3ffff 0x80164000 0x0 0x1000 0x3ffff 0x80165000 0x0 0x1000 0x3ffff 0x80166000 0x0 0x1000 0x3ffff 0x80167000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80168000 { + phandle = <0x4e>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xe8 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80168000 0x0 0x1000 0x3ffff 0x80169000 0x0 0x1000 0x3ffff 0x8016a000 0x0 0x1000 0x3ffff 0x8016b000 0x0 0x1000 0x3ffff 0x8016c000 0x0 0x1000 0x3ffff 0x8016d000 0x0 0x1000 0x3ffff 0x8016e000 0x0 0x1000 0x3ffff 0x8016f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80170000 { + phandle = <0x52>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0xf0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80170000 0x0 0x1000 0x3ffff 0x80171000 0x0 0x1000 0x3ffff 0x80172000 0x0 0x1000 0x3ffff 0x80173000 0x0 0x1000 0x3ffff 0x80174000 0x0 0x1000 0x3ffff 0x80175000 0x0 0x1000 0x3ffff 0x80176000 0x0 0x1000 0x3ffff 0x80177000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80828000 { + phandle = <0x56>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x828 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80828000 0x0 0x1000 0x3ffff 0x80829000 0x0 0x1000 0x3ffff 0x8082a000 0x0 0x1000 0x3ffff 0x8082b000 0x0 0x1000 0x3ffff 0x8082c000 0x0 0x1000 0x3ffff 0x8082d000 0x0 0x1000 0x3ffff 0x8082e000 0x0 0x1000 0x3ffff 0x8082f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80830000 { + phandle = <0x5a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x830 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80830000 0x0 0x1000 0x3ffff 0x80831000 0x0 0x1000 0x3ffff 0x80832000 0x0 0x1000 0x3ffff 0x80833000 0x0 0x1000 0x3ffff 0x80834000 0x0 0x1000 0x3ffff 0x80835000 0x0 0x1000 0x3ffff 0x80836000 0x0 0x1000 0x3ffff 0x80837000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80860000 { + phandle = <0x5e>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x860 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80860000 0x0 0x1000 0x3ffff 0x80861000 0x0 0x1000 0x3ffff 0x80862000 0x0 0x1000 0x3ffff 0x80863000 0x0 0x1000 0x3ffff 0x80864000 0x0 0x1000 0x3ffff 0x80865000 0x0 0x1000 0x3ffff 0x80866000 0x0 0x1000 0x3ffff 0x80867000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80868000 { + phandle = <0x62>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x868 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80868000 0x0 0x1000 0x3ffff 0x80869000 0x0 0x1000 0x3ffff 0x8086a000 0x0 0x1000 0x3ffff 0x8086b000 0x0 0x1000 0x3ffff 0x8086c000 0x0 0x1000 0x3ffff 0x8086d000 0x0 0x1000 0x3ffff 0x8086e000 0x0 0x1000 0x3ffff 0x8086f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80870000 { + phandle = <0x66>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x870 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80870000 0x0 0x1000 0x3ffff 0x80871000 0x0 0x1000 0x3ffff 0x80872000 0x0 0x1000 0x3ffff 0x80873000 0x0 0x1000 0x3ffff 0x80874000 0x0 0x1000 0x3ffff 0x80875000 0x0 0x1000 0x3ffff 0x80876000 0x0 0x1000 0x3ffff 0x80877000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80920000 { + phandle = <0x6a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x8a0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80920000 0x0 0x1000 0x3ffff 0x80921000 0x0 0x1000 0x3ffff 0x80922000 0x0 0x1000 0x3ffff 0x80923000 0x0 0x1000 0x3ffff 0x80924000 0x0 0x1000 0x3ffff 0x80925000 0x0 0x1000 0x3ffff 0x80926000 0x0 0x1000 0x3ffff 0x80927000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80928000 { + phandle = <0x6e>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x8a8 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80928000 0x0 0x1000 0x3ffff 0x80929000 0x0 0x1000 0x3ffff 0x8092a000 0x0 0x1000 0x3ffff 0x8092b000 0x0 0x1000 0x3ffff 0x8092c000 0x0 0x1000 0x3ffff 0x8092d000 0x0 0x1000 0x3ffff 0x8092e000 0x0 0x1000 0x3ffff 0x8092f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80930000 { + phandle = <0x72>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x8b0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80930000 0x0 0x1000 0x3ffff 0x80931000 0x0 0x1000 0x3ffff 0x80932000 0x0 0x1000 0x3ffff 0x80933000 0x0 0x1000 0x3ffff 0x80934000 0x0 0x1000 0x3ffff 0x80935000 0x0 0x1000 0x3ffff 0x80936000 0x0 0x1000 0x3ffff 0x80937000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80968000 { + phandle = <0x76>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x8e8 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80968000 0x0 0x1000 0x3ffff 0x80969000 0x0 0x1000 0x3ffff 0x8096a000 0x0 0x1000 0x3ffff 0x8096b000 0x0 0x1000 0x3ffff 0x8096c000 0x0 0x1000 0x3ffff 0x8096d000 0x0 0x1000 0x3ffff 0x8096e000 0x0 0x1000 0x3ffff 0x8096f000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + interrupt-controller@3ffff80970000 { + phandle = <0x7a>; + compatible = "ibm,ppc-xicp", "IBM,power8-icp"; + ibm,interrupt-server-ranges = <0x8f0 0x8>; + interrupt-controller; + reg = <0x3ffff 0x80970000 0x0 0x1000 0x3ffff 0x80971000 0x0 0x1000 0x3ffff 0x80972000 0x0 0x1000 0x3ffff 0x80973000 0x0 0x1000 0x3ffff 0x80974000 0x0 0x1000 0x3ffff 0x80975000 0x0 0x1000 0x3ffff 0x80976000 0x0 0x1000 0x3ffff 0x80977000 0x0 0x1000>; + #address-cells = <0x0>; + device_type = "PowerPC-External-Interrupt-Presentation"; + }; + + ipl-params { + phandle = <0x7b>; + #address-cells = <0x0>; + #size-cells = <0x0>; + + fsp-serial { + phandle = <0x7e>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + serial@2a00 { + phandle = <0x7f>; + reg = <0x2a00>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C1-T1"; + compatible = "ibm,fsp-serial"; + }; + }; + + ipl-params { + phandle = <0x7d>; + #address-cells = <0x0>; + #size-cells = <0x0>; + cec-ipl-side = "perm"; + fsp-ipl-side = "perm"; + os-ipl-mode = <0x0>; + cec-major-type = "cold"; + }; + + platform-dump { + phandle = <0x80>; + }; + + sys-params { + phandle = <0x7c>; + #address-cells = <0x0>; + #size-cells = <0x0>; + abc-bus-freq-mhz = < 0x00 0x1900 >; + ibm,sys-model = " 22L"; + wxyz-bus-freq-mhz = < 0x00 0xfa0 >; + }; + }; + + memory@0 { + phandle = <0x89>; + device_type = "memory"; + ibm,chip-id = <0x0>; + reg = <0x0 0x0 0x10 0x0>; + }; + + memory@1000000000 { + phandle = <0x8a>; + device_type = "memory"; + ibm,chip-id = <0x10>; + reg = <0x10 0x0 0x10 0x0>; + }; + + vpd { + phandle = <0x2>; + compatible = "ibm,opal-v3-vpd"; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84b00052 0x54045653 0x59534452 0x6535953 0x54454d42 0x52025330 0x53450731 0x30313043 0x38415347 0x7202020 0x20202020 0x544d0838 0x3234372d 0x32324c54 0x4e082020 0x20202020 0x20204d4e 0x7202020 0x20202020 0x49440220 0x20535506 0x4ac1a 0x43544e4e 0x10202020 0x20202020 0x20202020 0x20202020 0x20524704 0xf0c00000 0x52420433 0x20202057 0x4e0c4330 0x35303736 0x30373830 0x44324656 0x20535638 0x31305f30 0x32390000 0x0 0x0 0x0 0x0 0x0 0x504603 0x78 0x0>; + ibm,loc-code = "U8247.22L.1010C8A"; + + root-node-vpd@a000 { + phandle = <0x3>; + ibm,loc-code = "U8247.22L.1010C8A"; + fru-type = [56 56]; + reg = <0xa000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + + enclosure-fault-led@a300 { + phandle = <0x7>; + ibm,loc-code = "U78CB.001.WZS00AL"; + fru-type = [45 46]; + reg = <0xa300>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + enclosure-led@a200 { + phandle = <0x6>; + ibm,loc-code = "U78CB.001.WZS00AL"; + fru-type = [45 49]; + reg = <0xa200>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + enclosure@1e00 { + phandle = <0x5>; + ibm,loc-code = "U78CB.001.WZS00AL"; + fru-type = [45 56]; + reg = <0x1e00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x848c0052 0x54045649 0x4e494452 0x10492f4f 0x20424143 0x4b504c41 0x4e452020 0x20434501 0x31565a02 0x3032464e 0x7303045 0x32303232 0x504e0730 0x30453339 0x3937534e 0xc594c31 0x30554634 0x324c3031 0x33434304 0x32434436 0x50520821 0x0 0x48 0x45043030 0x30324354 0x480f300 0x26485702 0x44233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x5046 0x2000078 0x841c0052 0x54044c58 0x5230565a 0x230314c 0x58083100 0x4010030 0x425046 0x2000078 0x84440052 0x54045643 0x454e4452 0x6434543 0x20202053 0x4507575a 0x53303041 0x4c544d08 0x20202020 0x20202020 0x46430837 0x3843422d 0x30303152 0x47040000 0x5242 0x4202020 0x20504603 0x78 0x0>; + fru-number = "00E2022"; + serial-number = "YL10UF42L013"; + part-number = "00E3997"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 f3 00]; + hw-characteristics = [00]; + ccin = "2CD6"; + description = "System planar 2S2U"; + + air-mover@3a00 { + phandle = <0xf>; + ibm,loc-code = "U78CB.001.WZS00AL-A1"; + fru-type = [41 4d]; + reg = <0x3a00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + air-mover@3a01 { + phandle = <0x10>; + ibm,loc-code = "U78CB.001.WZS00AL-A3"; + fru-type = [41 4d]; + reg = <0x3a01>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + air-mover@3a02 { + phandle = <0x11>; + ibm,loc-code = "U78CB.001.WZS00AL-A4"; + fru-type = [41 4d]; + reg = <0x3a02>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + air-mover@3a03 { + phandle = <0x12>; + ibm,loc-code = "U78CB.001.WZS00AL-A6"; + fru-type = [41 4d]; + reg = <0x3a03>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + air-mover@3a04 { + phandle = <0x13>; + ibm,loc-code = "U78CB.001.WZS00AL-A2"; + fru-type = [41 4d]; + reg = <0x3a04>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + air-mover@3a05 { + phandle = <0x14>; + ibm,loc-code = "U78CB.001.WZS00AL-A5"; + fru-type = [41 4d]; + reg = <0x3a05>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + backplane@800 { + phandle = <0x8>; + ibm,loc-code = "U78CB.001.WZS00AL-P1"; + fru-type = [42 50]; + reg = <0x800>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x848c0052 0x54045649 0x4e494452 0x10492f4f 0x20424143 0x4b504c41 0x4e452020 0x20434501 0x31565a02 0x3032464e 0x7303045 0x32303232 0x504e0730 0x30453339 0x3937534e 0xc594c31 0x30554634 0x324c3031 0x33434304 0x32434436 0x50520821 0x0 0x48 0x45043030 0x30324354 0x480f300 0x26485702 0x44233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x5046 0x2000078 0x841c0052 0x54044c58 0x5230565a 0x230314c 0x58083100 0x4010030 0x425046 0x2000078 0x0>; + fru-number = "00E2022"; + serial-number = "YL10UF42L013"; + part-number = "00E3997"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 f3 00]; + hw-characteristics = [00]; + ccin = "2CD6"; + description = "System planar 2S2U"; + + anchor-card@500 { + phandle = <0x1a>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C13"; + fru-type = [41 56]; + reg = <0x500>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84cc0052 0x54045649 0x4e494452 0x10414e43 0x484f5220 0x20202020 0x20202020 0x20434501 0x31565a02 0x3031464e 0x7303045 0x33343237 0x504e0730 0x30453231 0x3438534e 0xc594c31 0x30313134 0x32523030 0x30434304 0x35323444 0x50520881 0x300000 0x48 0x45043030 0x31304354 0x440b400 0x485702 0x14233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x4239 0x3c435340 0x55110351 0xdd6da253 0x5049652f 0x45748f7b 0x44d31c5 0x31833edf 0x1e75724d 0x328d48c1 0xb4246b02 0xee4d3367 0xb454d848 0x9f3a254d 0x340dadc4 0x4124b5ed 0xd5504603 0x78 0x0>; + fru-number = "00E3427"; + serial-number = "YL101142R000"; + part-number = "00E2148"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [40 b4 00]; + hw-characteristics = [00]; + ccin = "524D"; + description = "System Anchor Card - IBM Power 822L"; + }; + + backplane-extender@900 { + phandle = <0x15>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C1"; + fru-type = [42 58]; + reg = <0x900>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84800052 0x54045649 0x4e494452 0x104e4154 0x49564520 0x492f4f20 0x43415244 0x20434501 0x31565a02 0x3031464e 0x7303045 0x32313634 0x504e0730 0x30453338 0x3131534e 0xc594c31 0x30554634 0x324c3030 0x31434304 0x32423042 0x48450430 0x30303143 0x540480b5 0x4857 0x2000142 0x33060000 0x0 0x42340100 0x42370c00 0x0 0x0 0x50 0x46010078 0x0>; + fru-number = "00E2164"; + serial-number = "YL10UF42L001"; + part-number = "00E3811"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 b5 00]; + hw-characteristics = [00]; + ccin = "2B0B"; + description = "Native I/O Card"; + + serial-connector@2a00 { + phandle = <0x27>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C1-T1"; + fru-type = [43 53]; + reg = <0x2a00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2901 { + phandle = <0x25>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C1-T2"; + fru-type = [43 55]; + reg = <0x2901>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2904 { + phandle = <0x26>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C1-T3"; + fru-type = [43 55]; + reg = <0x2904>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + + ethernet-connector@2800 { + phandle = <0x1b>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-T1 "; + fru-type = [43 45]; + reg = <0x2800>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + ethernet-connector@2801 { + phandle = <0x1c>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-T2 "; + fru-type = [43 45]; + reg = <0x2801>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + ms-dimm@d000 { + phandle = <0x21>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C16"; + fru-type = [4d 53]; + reg = <0xd000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84940052 0x54045649 0x4e494452 0x1049424d 0x20333247 0x42204d53 0x20202020 0x20434501 0x31565a02 0x3132464e 0x730304a 0x41363634 0x504e0730 0x304a4136 0x3634534e 0xc594831 0x304d5534 0x32443141 0x39434304 0x33314539 0x50520849 0x0 0x1000053 0x5a073030 0x33323736 0x38484504 0x30303031 0x43540400 0x48 0x57020100 0x42330600 0x0 0x423401 0x42370c 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "00JA664"; + serial-number = "YH10MU42D1A9"; + part-number = "00JA664"; + ccin-extension = [31 00]; + hw-version = [01 00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "31E9"; + description = "32GB CDIMM"; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + }; + + ms-dimm@d002 { + phandle = <0x22>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C18"; + fru-type = [4d 53]; + reg = <0xd002>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84940052 0x54045649 0x4e494452 0x1049424d 0x20333247 0x42204d53 0x20202020 0x20434501 0x31565a02 0x3132464e 0x730304a 0x41363634 0x504e0730 0x304a4136 0x3634534e 0xc594831 0x304d5534 0x32443141 0x36434304 0x33314539 0x50520849 0x0 0x1000053 0x5a073030 0x33323736 0x38484504 0x30303031 0x43540400 0x48 0x57020100 0x42330600 0x0 0x423401 0x42370c 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "00JA664"; + serial-number = "YH10MU42D1A6"; + part-number = "00JA664"; + ccin-extension = [31 00]; + hw-version = [01 00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "31E9"; + description = "32GB CDIMM"; + ibm,chip-id = <0x0>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + }; + + ms-dimm@d008 { + phandle = <0x23>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C24"; + fru-type = [4d 53]; + reg = <0xd008>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84940052 0x54045649 0x4e494452 0x1049424d 0x20333247 0x42204d53 0x20202020 0x20434501 0x31565a02 0x3132464e 0x730304a 0x41363634 0x504e0730 0x304a4136 0x3634534e 0xc594831 0x304d5534 0x32433137 0x54434304 0x33314539 0x50520849 0x0 0x1000053 0x5a073030 0x33323736 0x38484504 0x30303031 0x43540400 0x48 0x57020100 0x42330600 0x0 0x423401 0x42370c 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "00JA664"; + serial-number = "YH10MU42C17T"; + part-number = "00JA664"; + ccin-extension = [31 00]; + hw-version = [01 00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "31E9"; + description = "32GB CDIMM"; + ibm,chip-id = <0x10>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + }; + + ms-dimm@d00a { + phandle = <0x24>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C26"; + fru-type = [4d 53]; + reg = <0xd00a>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84940052 0x54045649 0x4e494452 0x1049424d 0x20333247 0x42204d53 0x20202020 0x20434501 0x31565a02 0x3132464e 0x730304a 0x41363634 0x504e0730 0x304a4136 0x3634534e 0xc594831 0x304d5534 0x32433141 0x48434304 0x33314539 0x50520849 0x0 0x1000053 0x5a073030 0x33323736 0x38484504 0x30303031 0x43540400 0x48 0x57020100 0x42330600 0x0 0x423401 0x42370c 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "00JA664"; + serial-number = "YH10MU42C1AH"; + part-number = "00JA664"; + ccin-extension = [31 00]; + hw-version = [01 00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "31E9"; + description = "32GB CDIMM"; + ibm,chip-id = <0x10>; + ibm,memory-bus-frequency = <0x0 0x0>; + size = "32768"; + }; + + processor@1000 { + phandle = <0x16>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + fru-type = [50 46]; + reg = <0x1000>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 8c 00 52 54 04 56 49 4e 49 44 52 10 31 30 2d 57 41 59 20 50 52 4f 43 20 43 55 4f 44 46 4e 07 30 30 46 58 35 31 38 50 4e 07 30 30 46 58 37 34 30 53 4e 0c 59 41 31 39 33 32 30 39 36 39 35 31 43 43 04 35 34 45 38 48 45 04 30 30 30 31 43 54 04 00 00 00 00 48 57 02 00 01 42 33 06 00 00 00 00 00 00 42 34 01 00 42 37 0c 00 00 00 00 00 00 00 00 00 00 00 00 50 52 08 35 00 50 01 22 00 80 01 56 5a 02 30 31 43 45 01 31 50 46 02 00 00 78 00]; + fru-number = "00FX518"; + serial-number = "YA1932096951"; + part-number = "00FX740"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "54E8"; + description = "10-WAY PROC CUOD"; + ibm,chip-id = <0x0>; + }; + + processor@1001 { + phandle = <0x17>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + fru-type = [50 46]; + reg = <0x1001>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 8c 00 52 54 04 56 49 4e 49 44 52 10 31 30 2d 57 41 59 20 50 52 4f 43 20 43 55 4f 44 46 4e 07 30 30 46 58 35 31 38 50 4e 07 30 30 46 58 37 34 30 53 4e 0c 59 41 31 39 33 32 30 39 36 39 35 31 43 43 04 35 34 45 38 48 45 04 30 30 30 31 43 54 04 00 00 00 00 48 57 02 00 01 42 33 06 00 00 00 00 00 00 42 34 01 00 42 37 0c 00 00 00 00 00 00 00 00 00 00 00 00 50 52 08 35 00 50 01 22 00 80 01 56 5a 02 30 31 43 45 01 31 50 46 02 00 00 78 00]; + fru-number = "00FX518"; + serial-number = "YA1932096951"; + part-number = "00FX740"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "54E8"; + description = "10-WAY PROC CUOD"; + ibm,chip-id = <0x1>; + }; + + processor@1002 { + phandle = <0x18>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + fru-type = [50 46]; + reg = <0x1002>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 8c 00 52 54 04 56 49 4e 49 44 52 10 31 30 2d 57 41 59 20 50 52 4f 43 20 43 55 4f 44 46 4e 07 30 30 46 58 35 31 38 50 4e 07 30 30 46 58 37 34 30 53 4e 0c 59 41 31 39 33 32 30 39 36 39 35 30 43 43 04 35 34 45 38 48 45 04 30 30 30 31 43 54 04 00 00 00 00 48 57 02 00 01 42 33 06 00 00 00 00 00 00 42 34 01 00 42 37 0c 00 00 00 00 00 00 00 00 00 00 00 00 50 52 08 35 00 50 01 22 00 80 01 56 5a 02 30 31 43 45 01 31 50 46 02 00 00 78 00]; + fru-number = "00FX518"; + serial-number = "YA1932096950"; + part-number = "00FX740"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "54E8"; + description = "10-WAY PROC CUOD"; + ibm,chip-id = <0x10>; + }; + + processor@1003 { + phandle = <0x19>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + fru-type = [50 46]; + reg = <0x1003>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = [84 8c 00 52 54 04 56 49 4e 49 44 52 10 31 30 2d 57 41 59 20 50 52 4f 43 20 43 55 4f 44 46 4e 07 30 30 46 58 35 31 38 50 4e 07 30 30 46 58 37 34 30 53 4e 0c 59 41 31 39 33 32 30 39 36 39 35 30 43 43 04 35 34 45 38 48 45 04 30 30 30 31 43 54 04 00 00 00 00 48 57 02 00 01 42 33 06 00 00 00 00 00 00 42 34 01 00 42 37 0c 00 00 00 00 00 00 00 00 00 00 00 00 50 52 08 35 00 50 01 22 00 80 01 56 5a 02 30 31 43 45 01 31 50 46 02 00 00 78 00]; + fru-number = "00FX518"; + serial-number = "YA1932096950"; + part-number = "00FX740"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [00]; + hw-characteristics = [00]; + ccin = "54E8"; + description = "10-WAY PROC CUOD"; + ibm,chip-id = <0x11>; + }; + + usb-connector@2900 { + phandle = <0x1d>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-T5"; + fru-type = [43 55]; + reg = <0x2900>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2902 { + phandle = <0x1e>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-T6"; + fru-type = [43 55]; + reg = <0x2902>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2903 { + phandle = <0x1f>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-T3"; + fru-type = [43 55]; + reg = <0x2903>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + usb-connector@2905 { + phandle = <0x20>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-T4"; + fru-type = [43 55]; + reg = <0x2905>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + + dasd-backplane@2400 { + phandle = <0xb>; + ibm,loc-code = "U78CB.001.WZS00AL-P2"; + fru-type = [44 42]; + reg = <0x2400>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + dasd-backplane@2401 { + phandle = <0xc>; + ibm,loc-code = "U78CB.001.WZS00AL-P2"; + fru-type = [44 42]; + reg = <0x2401>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + op-panel@300 { + phandle = <0xa>; + ibm,loc-code = "U78CB.001.WZS00AL-D1"; + fru-type = [4f 50]; + reg = <0x300>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x84800052 0x54045649 0x4e494452 0x10434543 0x204f5020 0x50414e45 0x4c202020 0x20434501 0x31565a02 0x3032464e 0x7303045 0x31393636 0x504e0730 0x30453337 0x3730534e 0xc594c31 0x30554634 0x31383030 0x46434304 0x32423038 0x48450430 0x30303143 0x540480b5 0x4857 0x2000342 0x33060000 0x0 0x42340100 0x42370c00 0x0 0x0 0x50 0x46010078 0x0>; + fru-number = "00E1966"; + serial-number = "YL10UF41800F"; + part-number = "00E3770"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 b5 00]; + hw-characteristics = [00]; + ccin = "2B08"; + description = "CEC OP PANEL"; + }; + + power-supply@3100 { + phandle = <0xd>; + ibm,loc-code = "U78CB.001.WZS00AL-E1"; + fru-type = [50 53]; + reg = <0x3100>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + power-supply@3101 { + phandle = <0xe>; + ibm,loc-code = "U78CB.001.WZS00AL-E2"; + fru-type = [50 53]; + reg = <0x3101>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + + service-processor@200 { + phandle = <0x9>; + ibm,loc-code = "U78CB.001.WZS00AL-P1"; + fru-type = [53 50]; + reg = <0x200>; + #size-cells = <0x0>; + #address-cells = <0x1>; + ibm,vpd = <0x848c0052 0x54045649 0x4e494452 0x10492f4f 0x20424143 0x4b504c41 0x4e452020 0x20434501 0x31565a02 0x3032464e 0x7303045 0x32303232 0x504e0730 0x30453339 0x3937534e 0xc594c31 0x30554634 0x324c3031 0x33434304 0x32434436 0x50520821 0x0 0x48 0x45043030 0x30324354 0x480f300 0x26485702 0x44233 0x6000000 0x142 0x34010042 0x370c0000 0x0 0x0 0x5046 0x2000078 0x841c0052 0x54044c58 0x5230565a 0x230314c 0x58083100 0x4010030 0x425046 0x2000078 0x84500052 0x54045652 0x31304452 0x10465350 0x20202020 0x20202020 0x20202020 0x20464704 0x564e5350 0x44430f42 0x44203230 0x31323038 0x32333038 0x3030464c 0x14503120 0x20202020 0x20202020 0x20202020 0x20202020 0x20504603 0x78 0x84400052 0x54045657 0x31304452 0x10465350 0x20565731 0x30202020 0x20202020 0x20474420 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x50460078 0x0>; + fru-number = "00E2022"; + serial-number = "YL10UF42L013"; + part-number = "00E3997"; + ccin-extension = [31 00]; + hw-version = [00]; + card-type = [80 f3 00]; + hw-characteristics = [00]; + ccin = "2CD6"; + description = "System planar 2S2U"; + }; + }; + + system-vpd@1c00 { + phandle = <0x4>; + ibm,loc-code = "U8247.22L.1010C8A"; + fru-type = [53 56]; + reg = <0x1c00>; + #size-cells = <0x0>; + #address-cells = <0x1>; + }; + }; + }; + + xscom@3fc0000000000 { + phandle = <0x81>; + ibm,chip-id = <0x0>; + ibm,proc-chip-id = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power8-xscom"; + reg = <0x3fc00 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + ibm,module-vpd = <0xcafebeef 0x10000 0x3e067c18>; + part-number = "00KV627"; + serial-number = "YA1932096951"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x0>; + ibm,mem-interleave-scope = <0x0>; + + chiptod@40000 { + phandle = <0x8d>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power8-chiptod"; + primary; + }; + + nx@2010000 { + phandle = <0x91>; + compatible = "ibm,power-nx", "ibm,power8-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@2012000 { + phandle = <0x95>; + reg = <0x2012000 0x20 0x9012000 0x05 0x9013c00 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x0>; + ibm,hub-id = <0x0>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + pbcq@2012400 { + phandle = <0x96>; + reg = <0x2012400 0x20 0x9012400 0x05 0x9013c40 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x1>; + ibm,hub-id = <0x0>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x0 0x0 0x0 0x0>; + }; + + psihb@2010900 { + phandle = <0x82>; + reg = <0x2010900 0x20>; + compatible = "ibm,power8-psihb-x", "ibm,psihb-x"; + boot-link; + status = "ok"; + }; + }; + + xscom@3fc0800000000 { + phandle = <0x83>; + ibm,chip-id = <0x1>; + ibm,proc-chip-id = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power8-xscom"; + reg = <0x3fc08 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + ibm,module-vpd = <0xcafebeef 0x10000 0x1b85218f>; + part-number = "00KV627"; + serial-number = "YA1932096951"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x0>; + ibm,mem-interleave-scope = <0x0>; + + chiptod@40000 { + phandle = <0x8e>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power8-chiptod"; + }; + + nx@2010000 { + phandle = <0x92>; + compatible = "ibm,power-nx", "ibm,power8-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@2012000 { + phandle = <0x97>; + reg = <0x2012000 0x20 0x9012000 0x05 0x9013c00 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x0>; + ibm,hub-id = <0x1>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + pbcq@2012400 { + phandle = <0x98>; + reg = <0x2012400 0x20 0x9012400 0x05 0x9013c40 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x1>; + ibm,hub-id = <0x1>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C32"; + ibm,use-ab-detect; + ibm,lane-eq = <0x68686868 0x68686868 0x68686868 0x68686868 0x0 0x0 0x0 0x0>; + }; + + psihb@2010900 { + phandle = <0x84>; + reg = <0x2010900 0x20>; + compatible = "ibm,power8-psihb-x", "ibm,psihb-x"; + }; + }; + + xscom@3fc8000000000 { + phandle = <0x85>; + ibm,chip-id = <0x10>; + ibm,proc-chip-id = <0x2>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power8-xscom"; + reg = <0x3fc80 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + ibm,module-vpd = <0xcafebeef 0x10000 0x36f99ead>; + part-number = "00KV627"; + serial-number = "YA1932096950"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x1>; + ibm,mem-interleave-scope = <0x0>; + + chiptod@40000 { + phandle = <0x8f>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power8-chiptod"; + secondary; + }; + + nx@2010000 { + phandle = <0x93>; + compatible = "ibm,power-nx", "ibm,power8-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@2012000 { + phandle = <0x99>; + reg = <0x2012000 0x20 0x9012000 0x05 0x9013c00 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x0>; + ibm,hub-id = <0x2>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + psihb@2010900 { + phandle = <0x86>; + reg = <0x2010900 0x20>; + compatible = "ibm,power8-psihb-x", "ibm,psihb-x"; + status = "ok"; + }; + }; + + xscom@3fc8800000000 { + phandle = <0x87>; + ibm,chip-id = <0x11>; + ibm,proc-chip-id = <0x3>; + #address-cells = <0x1>; + #size-cells = <0x1>; + scom-controller; + compatible = "ibm,xscom", "ibm,power8-xscom"; + reg = <0x3fc88 0x0 0x8 0x0>; + bus-frequency = <0x0 0x1dcd6500>; + ibm,dbob-id = <0x0>; + ibm,occ-functional-state = <0x1>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + ibm,module-vpd = <0xcafebeef 0x10000 0x65fe8f66>; + part-number = "00KV627"; + serial-number = "YA1932096950"; + ibm,ccm-node-id = <0x0>; + ibm,hw-card-id = <0x0>; + ibm,hw-module-id = <0x1>; + ibm,mem-interleave-scope = <0x0>; + + chiptod@40000 { + phandle = <0x90>; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power8-chiptod"; + }; + + nx@2010000 { + phandle = <0x94>; + compatible = "ibm,power-nx", "ibm,power8-nx"; + reg = <0x2010000 0x4000>; + }; + + pbcq@2012000 { + phandle = <0x9a>; + reg = <0x2012000 0x20 0x9012000 0x05 0x9013c00 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x0>; + ibm,hub-id = <0x3>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777 0x77777777>; + }; + + pbcq@2012400 { + phandle = <0x9b>; + reg = <0x2012400 0x20 0x9012400 0x05 0x9013c40 0x15>; + compatible = "ibm,power8-pbcq"; + ibm,phb-index = <0x1>; + ibm,hub-id = <0x3>; + ibm,loc-code = "U78CB.001.WZS00AL-P1-C33"; + ibm,use-ab-detect; + ibm,lane-eq = <0x77777777 0x77777777 0x77777777 0x77777777 0x0 0x0 0x0 0x0>; + }; + + psihb@2010900 { + phandle = <0x88>; + reg = <0x2010900 0x20>; + compatible = "ibm,power8-psihb-x", "ibm,psihb-x"; + }; + }; +}; diff --git a/roms/skiboot/hdata/test/p81-811.spira.heap b/roms/skiboot/hdata/test/p81-811.spira.heap Binary files differnew file mode 100644 index 000000000..3b2d73a7b --- /dev/null +++ b/roms/skiboot/hdata/test/p81-811.spira.heap diff --git a/roms/skiboot/hdata/test/stubs.c b/roms/skiboot/hdata/test/stubs.c new file mode 100644 index 000000000..f2cdd88b6 --- /dev/null +++ b/roms/skiboot/hdata/test/stubs.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2019 IBM Corp. */ + +#include <stdlib.h> +#include <stdio.h> +#include <stdarg.h> +#include <string.h> +#include <malloc.h> +#include <stdint.h> + +#include <compiler.h> + +#include "../../ccan/list/list.c" + +void _prlog(int log_level __attribute__((unused)), const char* fmt, ...) __attribute__((format (printf, 2, 3))); + +#ifndef pr_fmt +#define pr_fmt(fmt) fmt +#endif +#define prlog(l, f, ...) do { _prlog(l, pr_fmt(f), ##__VA_ARGS__); } while(0) + +void _prlog(int log_level __attribute__((unused)), const char* fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + if (log_level <= 7) + vfprintf(stderr, fmt, ap); + va_end(ap); +} + +/* + * Skiboot malloc stubs + * + * The actual prototypes for these are defined in mem_region-malloc.h, + * but that file also #defines malloc, and friends so we don't pull that in + * directly. + */ + +#define DEFAULT_ALIGN __alignof__(long) + +void *__memalign(size_t blocksize, size_t bytes, const char *location __unused); +void *__memalign(size_t blocksize, size_t bytes, const char *location __unused) +{ + return memalign(blocksize, bytes); +} + +void *__malloc(size_t bytes, const char *location); +void *__malloc(size_t bytes, const char *location) +{ + return __memalign(DEFAULT_ALIGN, bytes, location); +} + +void __free(void *p, const char *location __unused); +void __free(void *p, const char *location __unused) +{ + free(p); +} + +void *__realloc(void *ptr, size_t size, const char *location __unused); +void *__realloc(void *ptr, size_t size, const char *location __unused) +{ + return realloc(ptr, size); +} + +void *__zalloc(size_t bytes, const char *location); +void *__zalloc(size_t bytes, const char *location) +{ + void *p = __malloc(bytes, location); + + if (p) + memset(p, 0, bytes); + return p; +} + +struct cpu_thread; + +struct cpu_job *__cpu_queue_job(struct cpu_thread *cpu, + const char *name, + void (*func)(void *data), void *data, + bool no_return); + +struct cpu_job *cpu_queue_job_on_node(uint32_t chip_id, + const char *name, + void (*func)(void *data), void *data); + +struct cpu_job *cpu_queue_job_on_node(uint32_t chip_id, + const char *name, + void (*func)(void *data), void *data) +{ + (void)chip_id; + return __cpu_queue_job(NULL, name, func, data, false); +} + +struct cpu_job *__cpu_queue_job(struct cpu_thread *cpu, + const char *name, + void (*func)(void *data), void *data, + bool no_return) +{ + (void)cpu; + (void)name; + (func)(data); + (void)no_return; + return NULL; +} + +void cpu_wait_job(struct cpu_job *job, bool free_it); +void cpu_wait_job(struct cpu_job *job, bool free_it) +{ + (void)job; + (void)free_it; + return; +} + +void cpu_process_local_jobs(void); +void cpu_process_local_jobs(void) +{ +} + +/* Add any stub functions required for linking here. */ +static void stub_function(void) +{ + abort(); +} + +#define STUB(fnname) \ + void fnname(void) __attribute__((weak, alias ("stub_function"))) + +STUB(fsp_preload_lid); +STUB(fsp_wait_lid_loaded); +STUB(fsp_adjust_lid_side); + +/* Add HW specific stubs here */ +static bool true_stub(void) { return true; } +static bool false_stub(void) { return false; } + +#define TRUE_STUB(fnname) \ + bool fnname(void) __attribute__((weak, alias ("true_stub"))) +#define FALSE_STUB(fnname) \ + bool fnname(void) __attribute__((weak, alias ("false_stub"))) +#define NOOP_STUB FALSE_STUB + +TRUE_STUB(lock_held_by_me); +NOOP_STUB(lock_caller); +NOOP_STUB(unlock); +NOOP_STUB(early_uart_init); +NOOP_STUB(mem_reserve_fw); +NOOP_STUB(mem_reserve_hwbuf); +NOOP_STUB(add_chip_dev_associativity); +NOOP_STUB(enable_mambo_console); +NOOP_STUB(backtrace); + diff --git a/roms/skiboot/hdata/tpmrel.c b/roms/skiboot/hdata/tpmrel.c new file mode 100644 index 000000000..4be3f81c4 --- /dev/null +++ b/roms/skiboot/hdata/tpmrel.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2018 IBM Corp. */ + +#ifndef pr_fmt +#define pr_fmt(fmt) "TPMREL: " fmt +#endif + +#include <skiboot.h> +#include <device.h> + +#include "spira.h" +#include "hdata.h" +#include "hdif.h" + +static void tpmrel_add_firmware_event_log(const struct HDIF_common_hdr *hdif_hdr) +{ + const struct secureboot_tpm_info *stinfo; + struct dt_node *xscom, *node; + uint64_t addr; + int count, i; + unsigned int asize; + + /* Are the hdat values populated? */ + if (!HDIF_get_idata(hdif_hdr, TPMREL_IDATA_SECUREBOOT_TPM_INFO, &asize)) + return; + if (asize < sizeof(struct HDIF_array_hdr)) { + prlog(PR_ERR, "secureboot_tpm_info idata not populated\n"); + return; + } + + count = HDIF_get_iarray_size(hdif_hdr, TPMREL_IDATA_SECUREBOOT_TPM_INFO); + if (count > 1) { + prlog(PR_ERR, "multiple TPM not supported, count=%d\n", count); + return; + } + + /* + * There can be multiple secureboot_tpm_info entries with each entry + * corresponding to a master processor that has a tpm device. + * This looks for the tpm node that supposedly exists under the xscom + * node associated with the respective chip_id. + */ + for (i = 0; i < count; i++) { + + stinfo = HDIF_get_iarray_item(hdif_hdr, + TPMREL_IDATA_SECUREBOOT_TPM_INFO, + i, NULL); + + /* + * If tpm is not present, hostboot creates an empty + * secureboot_tpm_info entry, but setting + * tpm_status=TPM_NOT_PRESENT + */ + if (stinfo->tpm_status == TPM_NOT_PRESENT) + continue; + + xscom = find_xscom_for_chip(be32_to_cpu(stinfo->chip_id)); + if (xscom) { + dt_for_each_node(xscom, node) { + if (dt_has_node_property(node, "label", "tpm")) + break; + } + + if (node) { + addr = (uint64_t) stinfo + + be32_to_cpu(stinfo->srtm_log_offset); + dt_add_property_u64s(node, "linux,sml-base", addr); + dt_add_property_cells(node, "linux,sml-size", + be32_to_cpu(stinfo->srtm_log_size)); + + if (stinfo->tpm_status == TPM_PRESENT_AND_NOT_FUNCTIONAL) + dt_add_property_string(node, "status", "disabled"); + } else { + /** + * @fwts-label HDATNoTpmForChipId + * @fwts-advice HDAT secureboot_tpm_info + * structure described a chip id, but no tpm + * node was found under that xscom chip id. + * This is most certainly a hostboot bug. + */ + prlog(PR_ERR, "TPM node not found for " + "chip_id=%d (HB bug)\n", stinfo->chip_id); + continue; + } + } else { + /** + * @fwts-label HDATBadChipIdForTPM + * @fwts-advice HDAT secureboot_tpm_info structure + * described a chip id, but the xscom node for the + * chip_id was not found. + * This is most certainly a firmware bug. + */ + prlog(PR_ERR, "xscom node not found for chip_id=%d\n", + stinfo->chip_id); + continue; + } + } +} + +static struct dt_node *get_hb_reserved_memory(const char *label) +{ + struct dt_node *node, *hb_reserved_mem; + + hb_reserved_mem = dt_find_by_path(dt_root, "/ibm,hostboot/reserved-memory"); + if (!hb_reserved_mem) { + prlog(PR_DEBUG, "/ibm,hostboot/reserved-memory node not found\n"); + return NULL; + } + + dt_for_each_node(hb_reserved_mem, node) { + const char *prd_label; + if (!dt_find_property(node, "ibm,prd-label")) + continue; + prd_label = dt_prop_get(node, "ibm,prd-label"); + if (!strcmp(prd_label, label)) + return node; + } + return NULL; +} + +static struct { + uint32_t type; + const char *compat; +} cvc_services[] = { + { TPMREL_HV_SHA512, "ibm,cvc-sha512" }, + { TPMREL_HV_VERIFY, "ibm,cvc-verify" }, +}; + +static const char* cvc_service_map_compat(uint32_t type) { + int i; + for (i = 0; i < ARRAY_SIZE(cvc_services); i++) { + if (cvc_services[i].type == type) + return cvc_services[i].compat; + } + return NULL; +} + +static void tpmrel_cvc_init(struct HDIF_common_hdr *hdif_hdr) +{ + struct dt_node *cvc_reserved_mem, *node, *parent; + int count, i; + unsigned int asize; + + /* Are the hdat values populated? */ + if (!HDIF_get_idata(hdif_hdr, TPMREL_IDATA_HASH_VERIF_OFFSETS, &asize)) + return; + if (asize < sizeof(struct HDIF_array_hdr)) { + prlog(PR_ERR, "hash_and_verification idata not populated\n"); + return; + } + + node = dt_find_by_path(dt_root, "/ibm,secureboot"); + if (!node) + return; + + cvc_reserved_mem = get_hb_reserved_memory("secure-crypt-algo-code"); + if (!cvc_reserved_mem) { + /* Fallback to old style ibm,prd-label */ + cvc_reserved_mem = get_hb_reserved_memory("ibm,secure-crypt-algo-code"); + if (!cvc_reserved_mem) { + prlog(PR_ERR, "CVC reserved memory not found\n"); + return; + } + } + + parent = dt_new(node, "ibm,cvc"); + assert(parent); + dt_add_property_cells(parent, "#address-cells", 1); + dt_add_property_cells(parent, "#size-cells", 0); + dt_add_property_strings(parent, "compatible", "ibm,container-verification-code"); + dt_add_property_cells(parent, "memory-region", cvc_reserved_mem->phandle); + + /* + * Initialize each service provided by the container verification code + */ + count = HDIF_get_iarray_size(hdif_hdr, TPMREL_IDATA_HASH_VERIF_OFFSETS); + if (count <= 0 ) { + prlog(PR_ERR, "no CVC service found\n"); + return; + } + + for (i = 0; i < count; i++) { + const struct hash_and_verification *hv; + uint32_t type, offset, version; + const char *compat; + + hv = HDIF_get_iarray_item(hdif_hdr, + TPMREL_IDATA_HASH_VERIF_OFFSETS, + i, NULL); + type = be32_to_cpu(hv->type); + offset = be32_to_cpu(hv->offset); + version = be32_to_cpu(hv->version); + + compat = cvc_service_map_compat(type); + + if (!compat) { + prlog(PR_WARNING, "CVC service type 0x%x unknown\n", type); + continue; + } + + node = dt_new_addr(parent, "ibm,cvc-service", offset); + dt_add_property_strings(node, "compatible", compat); + dt_add_property_cells(node, "reg", offset); + dt_add_property_cells(node, "version", version); + } +} + +void node_stb_parse(void) +{ + struct HDIF_common_hdr *hdif_hdr; + + hdif_hdr = get_hdif(&spira.ntuples.node_stb_data, STB_HDIF_SIG); + if (!hdif_hdr) { + prlog(PR_DEBUG, "TPMREL data not found\n"); + return; + } + + tpmrel_add_firmware_event_log(hdif_hdr); + tpmrel_cvc_init(hdif_hdr); +} diff --git a/roms/skiboot/hdata/vpd-common.c b/roms/skiboot/hdata/vpd-common.c new file mode 100644 index 000000000..c91fccaa2 --- /dev/null +++ b/roms/skiboot/hdata/vpd-common.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later +/* Copyright 2013-2017 IBM Corp. */ + +#include <skiboot.h> +#include <vpd.h> +#include <string.h> +#include <device.h> + +static const struct machine_info machine_table[] = { + {"8247-21L", "IBM Power System S812L"}, + {"8247-22L", "IBM Power System S822L"}, + {"8247-24L", "IBM Power System S824L"}, + {"8286-41A", "IBM Power System S814"}, + {"8286-22A", "IBM Power System S822"}, + {"8286-42A", "IBM Power System S824"}, +}; + +const struct machine_info *machine_info_lookup(const char *mtm) +{ + int i; + for(i = 0; i < ARRAY_SIZE(machine_table); i++) + if (!strcmp(machine_table[i].mtm, mtm)) + return &machine_table[i]; + return NULL; +} diff --git a/roms/skiboot/hdata/vpd.c b/roms/skiboot/hdata/vpd.c new file mode 100644 index 000000000..c778de346 --- /dev/null +++ b/roms/skiboot/hdata/vpd.c @@ -0,0 +1,767 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2013-2019 IBM Corp. */ + +#include <skiboot.h> +#include <vpd.h> +#include <string.h> +#include "spira.h" +#include "hdata.h" +#include <device.h> +#include "hdata.h" +#include <inttypes.h> +#include <mem_region-malloc.h> + +struct card_info { + const char *ccin; /* Customer card identification number */ + const char *description; +}; + +static const struct card_info card_table[] = { + {"2B06", "System planar 2S4U"}, + {"2B07", "System planar 1S4U"}, + {"2B2E", "System planar 2S2U"}, + {"2B2F", "System planar 1S2U"}, + {"2CD4", "System planar 2S4U"}, + {"2CD5", "System planar 1S4U"}, + {"2CD6", "System planar 2S2U"}, + {"2CD7", "System planar 1S2U"}, + {"2CD7", "System planar 1S2U"}, + {"2B09", "Base JBOD, RAID and Backplane HD"}, + {"57D7", "Split JBOD, RAID Card"}, + {"2B0B", "Native I/O Card"}, + + /* Anchor cards */ + {"52FE", "System Anchor Card - IBM Power 824"}, + {"52F2", "System Anchor Card - IBM Power 814"}, + {"52F5", "System Anchor Card - IBM Power 822"}, + {"561A", "System Anchor Card - IBM Power 824L"}, + {"524D", "System Anchor Card - IBM Power 822L"}, + {"560F", "System Anchor Card - IBM Power 812L"}, + {"561C", "System Anchor Card - DS8870"}, + + /* Memory DIMMs */ + {"31E0", "16GB CDIMM"}, + {"31E8", "16GB CDIMM"}, + {"31E1", "32GB CDIMM"}, + {"31E9", "32GB CDIMM"}, + {"31E2", "64GB CDIMM"}, + {"31EA", "64GB CDIMM"}, + + /* Power supplies */ + {"2B1D", "Power Supply 900W AC"}, + {"2B1E", "Power Supply 1400W AC"}, + {"2B75", "Power Supply 1400W HVDC"}, + + /* Fans */ + {"2B1F", "Fan 4U (A1, A2, A3, A4)"}, + {"2B29", "Fan 2U (A1, A2, A3, A4, A5, A6)"}, + + /* Other cards */ +}; + +struct vpd_key_map { + const char *keyword; /* 2 char keyword */ + const char *description; +}; + +static const struct vpd_key_map vpd_key_table[] = { + {"AA", "ac-power-supply"}, + {"AM", "air-mover"}, + {"AV", "anchor-card"}, + + {"BA", "bus-adapter-card"}, + {"BC", "battery-charger"}, + {"BD", "bus-daughter-card"}, + {"BE", "bus-expansion-card"}, + {"BP", "backplane"}, + {"BR", "backplane-riser"}, + {"BX", "backplane-extender"}, + + {"CA", "calgary-bridge"}, + {"CB", "infiniband-connector"}, + {"CC", "clock-card"}, + {"CD", "card-connector"}, + {"CE", "ethernet-connector"}, + {"CL", "calgary-phb"}, + {"CI", "capacity-card"}, + {"CO", "sma-connector"}, + {"CP", "processor-capacity-card"}, + {"CR", "rio-connector"}, + {"CS", "serial-connector"}, + {"CU", "usb-connector"}, + + {"DB", "dasd-backplane"}, + {"DC", "drawer-card"}, + {"DE", "drawer-extension"}, + {"DI", "drawer-interposer"}, + {"DL", "p7ih-dlink-connector"}, + {"DT", "legacy-pci-card"}, + {"DV", "media-drawer-led"}, + + {"EI", "enclosure-led"}, + {"EF", "enclosure-fault-led"}, + {"ES", "embedded-sas"}, + {"ET", "ethernet-riser"}, + {"EV", "enclosure"}, + + {"FM", "frame"}, + {"FN", "fru-stocking-part-number"}, + + {"HB", "host-rio-pci-card"}, + {"HD", "high-speed-card"}, + {"HM", "hmc-connector"}, + + {"IB", "io-backplane"}, + {"IC", "io-card"}, + {"ID", "ide-connector"}, + {"II", "io-drawer-led"}, + {"IP", "interplane-card"}, + {"IS", "smp-vbus-cable"}, + {"IT", "enclosure-cable"}, + {"IV", "io-enclosure"}, + + {"KV", "keyboard-led"}, + + {"L2", "l2-cache-module"}, + {"L3", "l3-cache-module"}, + {"LC", "squadrons-light-connector"}, + {"LR", "p7ih-connector"}, + {"LO", "system-locate-led"}, + {"LT", "squadrons-light-strip"}, + + {"MB", "media-backplane"}, + {"ME", "map-extension"}, + {"MM", "mip-meter"}, + {"MS", "ms-dimm"}, + + {"NB", "nvram-battery"}, + {"NC", "sp-node-controller"}, + {"ND", "numa-dimm"}, + + {"OD", "cuod-card"}, + {"OP", "op-panel"}, + {"OS", "oscillator"}, + + {"P2", "ioc"}, + {"P5", "ioc-bridge"}, + {"PB", "io-drawer-backplane"}, + {"PC", "power-capacitor"}, + {"PD", "processor-card"}, + {"PF", "processor"}, + {"PI", "ioc-phb"}, + {"PO", "spcn"}, + {"PN", "spcn-connector"}, + {"PR", "pci-riser-card"}, + {"PS", "power-supply"}, + {"PT", "pass-through-card"}, + {"PX", "psc-sync-card"}, + {"PW", "power-connector"}, + + {"RG", "regulator"}, + {"RI", "riser"}, + {"RK", "rack-indicator"}, + {"RW", "riscwatch-connector"}, + + {"SA", "sys-attn-led"}, + {"SB", "backup-sysvpd"}, + {"SC", "scsi-connector"}, + {"SD", "sas-connector"}, + {"SI", "scsi-ide-converter"}, + {"SL", "phb-slot"}, + {"SN", "smp-cable-connector"}, + {"SP", "service-processor"}, + {"SR", "service-card"}, + {"SS", "soft-switch"}, + {"SV", "system-vpd"}, + {"SY", "legacy-sysvpd"}, + + {"TD", "tod-clock"}, + {"TI", "torrent-pcie-phb"}, + {"TL", "torrent-riser"}, + {"TM", "thermal-sensor"}, + {"TP", "tpmd-adapter"}, + {"TR", "torrent-bridge"}, + + {"VV", "root-node-vpd"}, + + {"WD", "water_device"}, +}; + +static const char *vpd_map_name(const char *vpd_name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vpd_key_table); i++) + if (!strcmp(vpd_key_table[i].keyword, vpd_name)) + return vpd_key_table[i].description; + + prlog(PR_WARNING, "VPD: Could not map FRU ID %s to a known name\n", + vpd_name); + + return "Unknown"; +} + +static const struct card_info *card_info_lookup(char *ccin) +{ + int i; + for(i = 0; i < ARRAY_SIZE(card_table); i++) + /* CCIN is always 4 bytes in size */ + if (!strncmp(card_table[i].ccin, ccin, 4)) + return &card_table[i]; + return NULL; +} + +/* Discard trailing spaces and populate device tree */ +static struct dt_property *dt_add_prop_sanitize_val(struct dt_node *node, + const char *name, const char *val, int vlen) +{ + char *prop = zalloc(vlen + 1); + int i; + struct dt_property *p = NULL; + + if (!prop) + return p; + + memcpy(prop, val, vlen); + for (i = vlen - 1; i >= 0; i--) { + if (prop[i] != 0x20) { + prop[i + 1] = '\0'; + break; + } + } + + if (i >= 0 && !dt_find_property(node, name)) + p = dt_add_property_string(node, name, prop); + + free(prop); + return p; +} + +/* + * OpenPower system does not provide processor vendor name under FRU VPD. + * Parse processor module VPD to get vendor detail + */ +void dt_add_proc_vendor(struct dt_node *proc_node, + const void *mvpd, unsigned int mvpd_sz) +{ + const void *kw; + uint8_t sz; + + kw = vpd_find(mvpd, mvpd_sz, "VINI", "VN", &sz); + if (kw) + dt_add_prop_sanitize_val(proc_node, "vendor", kw, sz); +} + +/* + * For OpenPOWER, we only decipher OPFR records. While OP HDAT have VINI + * records too, populating the fields in there is optional. Also, there + * is an overlap in the fields contained therein. + */ +static void vpd_opfr_parse(struct dt_node *node, + const void *fruvpd, unsigned int fruvpd_sz) +{ + const void *kw; + uint8_t sz; + + /* Vendor Name */ + kw = vpd_find(fruvpd, fruvpd_sz, "OPFR", "VN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "vendor", kw, sz); + + /* FRU Description */ + kw = vpd_find(fruvpd, fruvpd_sz, "OPFR", "DR", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "description", kw, sz); + + /* Part number */ + kw = vpd_find(fruvpd, fruvpd_sz, "OPFR", "VP", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "part-number", kw, sz); + + /* Serial number */ + kw = vpd_find(fruvpd, fruvpd_sz, "OPFR", "VS", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "serial-number", kw, sz); + + /* Build date in BCD */ + kw = vpd_find(fruvpd, fruvpd_sz, "OPFR", "MB", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "build-date", kw, sz); + + return; +} + +/* + * For CPUs, parse the VRML data. + */ +static void vpd_vrml_parse(struct dt_node *node, + const void *fruvpd, unsigned int fruvpd_sz) +{ + const void *kw; + uint8_t sz; + + /* Part number */ + kw = vpd_find(fruvpd, fruvpd_sz, "VRML", "PN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "part-number", kw, sz); + + /* Serial number */ + kw = vpd_find(fruvpd, fruvpd_sz, "VRML", "SN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "serial-number", kw, sz); + + return; +} + +static void vpd_vini_parse(struct dt_node *node, + const void *fruvpd, unsigned int fruvpd_sz) +{ + const void *kw; + const char *desc; + uint8_t sz; + const struct card_info *cinfo; + + /* FRU Stocking Part Number */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "FN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "fru-number", kw, sz); + + /* Serial Number */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "SN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "serial-number", kw, sz); + + /* Part Number */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "PN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "part-number", kw, sz); + + /* Vendor Name */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "VN", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "vendor", kw, sz); + + /* CCIN Extension */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "CE", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "ccin-extension", kw, sz); + + /* HW Version info */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "HW", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "hw-version", kw, sz); + + /* Card type info */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "CT", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "card-type", kw, sz); + + /* HW characteristics info */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "B3", &sz); + if (kw) + dt_add_prop_sanitize_val(node, "hw-characteristics", kw, sz); + + /* Customer Card Identification Number (CCIN) */ + kw = vpd_find(fruvpd, fruvpd_sz, "VINI", "CC", &sz); + if (kw) { + dt_add_prop_sanitize_val(node, "ccin", kw, sz); + + cinfo = card_info_lookup((char *)kw); + if (cinfo) { + dt_add_property_string(node, + "description", cinfo->description); + } else { + desc = vpd_find(fruvpd, fruvpd_sz, "VINI", "DR", &sz); + if (desc) { + dt_add_prop_sanitize_val(node, + "description", desc, sz); + } else { + dt_add_property_string(node, "description", "Unknown"); + prlog(PR_WARNING, + "VPD: CCIN desc not available for: %s\n", + (char*)kw); + } + } + } + + return; +} + +static bool valid_child_entry(const struct slca_entry *entry) +{ + if ((entry->install_indic == SLCA_INSTALL_INSTALLED) && + (entry->vpd_collected == SLCA_VPD_COLLECTED)) + return true; + + return false; +} + +void vpd_data_parse(struct dt_node *node, const void *fruvpd, u32 fruvpd_sz) +{ + if (vpd_find_record(fruvpd, fruvpd_sz, "OPFR", NULL)) + vpd_opfr_parse(node, fruvpd, fruvpd_sz); + else if (vpd_find_record(fruvpd, fruvpd_sz, "VRML", NULL)) + vpd_vrml_parse(node, fruvpd, fruvpd_sz); + else + vpd_vini_parse(node, fruvpd, fruvpd_sz); +} + +/* Create the /vpd node and add its children */ +void dt_init_vpd_node(void) +{ + const char *name, *p_name; + int count, index; + uint64_t addr, p_addr; + struct dt_node *dt_vpd; + struct HDIF_common_hdr *slca_hdr; + struct dt_node *parent, *node; + const struct slca_entry *entry, *p_entry; + + dt_vpd = dt_new(dt_root, "vpd"); + assert(dt_vpd); + dt_add_property_string(dt_vpd, "compatible", "ibm,opal-v3-vpd"); + dt_add_property_cells(dt_vpd, "#size-cells", 0); + dt_add_property_cells(dt_vpd, "#address-cells", 1); + + slca_hdr = get_hdif(&spira.ntuples.slca, SLCA_HDIF_SIG); + if (!slca_hdr) { + prerror("SLCA Invalid\n"); + return; + } + + count = HDIF_get_iarray_size(slca_hdr, SLCA_IDATA_ARRAY); + if (count < 0) { + prerror("SLCA: Can't find SLCA array size!\n"); + return; + } + + for (index = 0; index < count; index++) { + /* Get SLCA entry */ + entry = slca_get_entry(index); + if (!entry) + continue; + + /* + * A child entry is valid if all of the following criteria is met + * a. SLCA_INSTALL_INSTALLED is set in s_entry->install_indic + * b. SLCA_VPD_COLLECTED is set in s_entry->vpd_collected + * c. The SLCA is not a duplicate entry. + */ + if (!valid_child_entry(entry)) + goto next_entry; + + name = vpd_map_name(entry->fru_id); + addr = be16_to_cpu(entry->rsrc_id); + /* Check node is already created or not */ + if (dt_find_by_name_addr(dt_vpd, name, addr)) + goto next_entry; + + /* Get parent node */ + if (index == SLCA_ROOT_INDEX) { + parent = dt_vpd; + } else { + p_entry = slca_get_entry(be16_to_cpu(entry->parent_index)); + if (!p_entry) + goto next_entry; + p_name = vpd_map_name(p_entry->fru_id); + p_addr = be16_to_cpu(p_entry->rsrc_id); + parent = dt_find_by_name_addr(dt_vpd, p_name, p_addr); + } + if (!parent) + goto next_entry; + + node = dt_new_addr(parent, name, addr); + if (!node) { + prerror("VPD: Creating node at %s@%"PRIx64" failed\n", + name, addr); + goto next_entry; + } + + /* Add location code */ + slca_vpd_add_loc_code(node, be16_to_cpu(entry->my_index)); + /* Add FRU label */ + dt_add_property(node, "fru-type", entry->fru_id, 2); + dt_add_property_cells(node, "reg", addr); + dt_add_property_cells(node, "#size-cells", 0); + dt_add_property_cells(node, "#address-cells", 1); + +next_entry: + /* Skip dups -- dups are contiguous */ + index += entry->nr_dups; + } +} + +struct dt_node *dt_add_vpd_node(const struct HDIF_common_hdr *hdr, + int indx_fru, int indx_vpd) +{ + const struct spira_fru_id *fru_id; + unsigned int fruvpd_sz, fru_id_sz; + const struct slca_entry *entry; + struct dt_node *dt_vpd, *node; + const void *fruvpd; + const char *name; + uint64_t addr; + + fru_id = HDIF_get_idata(hdr, indx_fru, &fru_id_sz); + if (!fru_id) + return NULL; + + fruvpd = HDIF_get_idata(hdr, indx_vpd, &fruvpd_sz); + if (!CHECK_SPPTR(fruvpd)) + return NULL; + + dt_vpd = dt_find_by_path(dt_root, "/vpd"); + if (!dt_vpd) + return NULL; + + entry = slca_get_entry(be16_to_cpu(fru_id->slca_index)); + if (!entry) + return NULL; + + name = vpd_map_name(entry->fru_id); + addr = be16_to_cpu(entry->rsrc_id); + /* Get the node already created */ + node = dt_find_by_name_addr(dt_vpd, name, addr); + /* + * It is unlikely that node not found because vpd nodes have the + * corresponding slca entry which we would have used to populate the vpd + * tree during the 'first' pass above so that we just need to perform + * VINI parse and add the vpd data.. + */ + if (!node) + return NULL; + + /* Parse VPD fields, ensure that it has not been added already */ + if (vpd_valid(fruvpd, fruvpd_sz) + && !dt_find_property(node, "ibm,vpd")) { + dt_add_property(node, "ibm,vpd", fruvpd, fruvpd_sz); + vpd_data_parse(node, fruvpd, fruvpd_sz); + } + + return node; +} + +static void dt_add_model_name(void) +{ + const char *model_name = NULL; + const struct machine_info *mi; + const struct iplparams_sysparams *p; + const struct HDIF_common_hdr *iplp; + const struct dt_property *model; + + model = dt_find_property(dt_root, "model"); + + iplp = get_hdif(&spira.ntuples.ipl_parms, "IPLPMS"); + if (!iplp) + goto def_model; + + p = HDIF_get_idata(iplp, IPLPARAMS_SYSPARAMS, NULL); + if (!CHECK_SPPTR(p)) + goto def_model; + + if (be16_to_cpu(iplp->version) >= 0x60) + model_name = p->sys_type_str; + +def_model: + if ((!model_name || model_name[0] == '\0') && model) { + mi = machine_info_lookup(model->prop); + if (mi) + model_name = mi->name; + } + + if(model_name) + dt_add_property_string(dt_root, "model-name", model_name); +} + +static void sysvpd_parse_opp(const void *sysvpd, unsigned int sysvpd_sz) +{ + const char *v; + uint8_t sz; + + v = vpd_find(sysvpd, sysvpd_sz, "OSYS", "MM", &sz); + if (v) + dt_add_prop_sanitize_val(dt_root, "model", v, sz); + else + dt_add_property_string(dt_root, "model", "Unknown"); + + v = vpd_find(sysvpd, sysvpd_sz, "OSYS", "SS", &sz); + if (v) + dt_add_prop_sanitize_val(dt_root, "system-id", v, sz); + else + dt_add_property_string(dt_root, "system-id", "Unknown"); +} + + +static void sysvpd_parse_legacy(const void *sysvpd, unsigned int sysvpd_sz) +{ + const char *model; + const char *system_id; + const char *brand; + uint8_t sz; + + model = vpd_find(sysvpd, sysvpd_sz, "VSYS", "TM", &sz); + if (model) + dt_add_prop_sanitize_val(dt_root, "model", model, sz); + else + dt_add_property_string(dt_root, "model", "Unknown"); + + system_id = vpd_find(sysvpd, sysvpd_sz, "VSYS", "SE", &sz); + if (system_id) + dt_add_prop_sanitize_val(dt_root, "system-id", system_id, sz); + else + dt_add_property_string(dt_root, "system-id", "Unknown"); + + brand = vpd_find(sysvpd, sysvpd_sz, "VSYS", "BR", &sz); + if (brand) + dt_add_prop_sanitize_val(dt_root, "system-brand", brand, sz); + else + dt_add_property_string(dt_root, "brand", "Unknown"); +} + +static void sysvpd_parse(void) +{ + const void *sysvpd; + unsigned int sysvpd_sz; + unsigned int fru_id_sz; + struct dt_node *dt_vpd; + const struct spira_fru_id *fru_id; + struct HDIF_common_hdr *sysvpd_hdr; + + sysvpd_hdr = get_hdif(&spira.ntuples.system_vpd, SYSVPD_HDIF_SIG); + if (!sysvpd_hdr) + return; + + fru_id = HDIF_get_idata(sysvpd_hdr, SYSVPD_IDATA_FRU_ID, &fru_id_sz); + if (!fru_id) + return; + + sysvpd = HDIF_get_idata(sysvpd_hdr, SYSVPD_IDATA_KW_VPD, &sysvpd_sz); + if (!CHECK_SPPTR(sysvpd)) + return; + + /* Add system VPD */ + dt_vpd = dt_find_by_path(dt_root, "/vpd"); + if (dt_vpd) { + dt_add_property(dt_vpd, "ibm,vpd", sysvpd, sysvpd_sz); + slca_vpd_add_loc_code(dt_vpd, be16_to_cpu(fru_id->slca_index)); + } + + /* Look for the new OpenPower "OSYS" first */ + if (vpd_find_record(sysvpd, sysvpd_sz, "OSYS", NULL)) + sysvpd_parse_opp(sysvpd, sysvpd_sz); + else + sysvpd_parse_legacy(sysvpd, sysvpd_sz); + + dt_add_model_name(); +} + +static void iokid_vpd_parse(const struct HDIF_common_hdr *iohub_hdr) +{ + const struct HDIF_child_ptr *iokids; + const struct HDIF_common_hdr *iokid; + unsigned int i; + + iokids = HDIF_child_arr(iohub_hdr, CECHUB_CHILD_IO_KIDS); + if (!CHECK_SPPTR(iokids)) { + prerror("VPD: No IOKID child array\n"); + return; + } + + for (i = 0; i < be32_to_cpu(iokids->count); i++) { + iokid = HDIF_child(iohub_hdr, iokids, i, + IOKID_FRU_HDIF_SIG); + /* IO KID VPD structure layout is similar to FRUVPD */ + if (iokid) + dt_add_vpd_node(iokid, + FRUVPD_IDATA_FRU_ID, FRUVPD_IDATA_KW_VPD); + } +} + +static void iohub_vpd_parse(void) +{ + const struct HDIF_common_hdr *iohub_hdr; + const struct cechub_hub_fru_id *fru_id_data; + unsigned int i, vpd_sz, fru_id_sz; + + if (!get_hdif(&spira.ntuples.cec_iohub_fru, CECHUB_FRU_HDIF_SIG)) { + prerror("VPD: Could not find IO HUB FRU data\n"); + return; + } + + for_each_ntuple_idx(&spira.ntuples.cec_iohub_fru, iohub_hdr, + i, CECHUB_FRU_HDIF_SIG) { + + fru_id_data = HDIF_get_idata(iohub_hdr, + CECHUB_FRU_ID_DATA_AREA, + &fru_id_sz); + + /* P8, IO HUB is on processor card and we have a + * daughter card array + */ + if (fru_id_data && + be32_to_cpu(fru_id_data->card_type) == CECHUB_FRU_TYPE_CPU_CARD) { + iokid_vpd_parse(iohub_hdr); + continue; + } + + if (HDIF_get_idata(iohub_hdr, + CECHUB_ASCII_KEYWORD_VPD, &vpd_sz)) + dt_add_vpd_node(iohub_hdr, CECHUB_FRU_ID_DATA, + CECHUB_ASCII_KEYWORD_VPD); + } +} + +static void _vpd_parse(struct spira_ntuple tuple) +{ + const struct HDIF_common_hdr *fruvpd_hdr; + unsigned int i; + + if (!get_hdif(&tuple, FRUVPD_HDIF_SIG)) + return; + + for_each_ntuple_idx(&tuple, fruvpd_hdr, i, FRUVPD_HDIF_SIG) + dt_add_vpd_node(fruvpd_hdr, + FRUVPD_IDATA_FRU_ID, FRUVPD_IDATA_KW_VPD); +} + +void vpd_parse(void) +{ + const struct HDIF_common_hdr *fruvpd_hdr; + + /* System VPD uses the VSYS record, so its special */ + sysvpd_parse(); + + /* Enclosure */ + _vpd_parse(spira.ntuples.nt_enclosure_vpd); + + /* Backplane */ + _vpd_parse(spira.ntuples.backplane_vpd); + + /* clock card -- does this use the FRUVPD sig? */ + _vpd_parse(spira.ntuples.clock_vpd); + + /* Anchor card */ + _vpd_parse(spira.ntuples.anchor_vpd); + + /* Op panel -- does this use the FRUVPD sig? */ + _vpd_parse(spira.ntuples.op_panel_vpd); + + /* External cache FRU vpd -- does this use the FRUVPD sig? */ + _vpd_parse(spira.ntuples.ext_cache_fru_vpd); + + /* Misc CEC FRU */ + _vpd_parse(spira.ntuples.misc_cec_fru_vpd); + + /* CEC IO HUB FRU */ + iohub_vpd_parse(); + + /* + * SP subsystem -- while the rest of the SPINFO structure is + * different, the FRU ID data and pointer pair to keyword VPD + * are the same offset as a FRUVPD entry. So reuse it + */ + fruvpd_hdr = get_hdif(&spira.ntuples.sp_subsys, SPSS_HDIF_SIG); + if (fruvpd_hdr) + dt_add_vpd_node(fruvpd_hdr, + FRUVPD_IDATA_FRU_ID, FRUVPD_IDATA_KW_VPD); +} |