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-rw-r--r--roms/u-boot/arch/arc/dts/Makefile19
-rw-r--r--roms/u-boot/arch/arc/dts/abilis_tb100.dts31
-rw-r--r--roms/u-boot/arch/arc/dts/axc001.dtsi18
-rw-r--r--roms/u-boot/arch/arc/dts/axc003.dtsi18
-rw-r--r--roms/u-boot/arch/arc/dts/axs101.dts18
-rw-r--r--roms/u-boot/arch/arc/dts/axs103.dts18
-rw-r--r--roms/u-boot/arch/arc/dts/axs10x_mb.dtsi123
-rw-r--r--roms/u-boot/arch/arc/dts/emsdp.dts58
-rw-r--r--roms/u-boot/arch/arc/dts/hsdk-4xd.dts12
-rw-r--r--roms/u-boot/arch/arc/dts/hsdk-common.dtsi160
-rw-r--r--roms/u-boot/arch/arc/dts/hsdk.dts12
-rw-r--r--roms/u-boot/arch/arc/dts/iot_devkit.dts67
-rw-r--r--roms/u-boot/arch/arc/dts/nsim.dts57
-rw-r--r--roms/u-boot/arch/arc/dts/skeleton.dtsi30
14 files changed, 641 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arc/dts/Makefile b/roms/u-boot/arch/arc/dts/Makefile
new file mode 100644
index 000000000..515fe1fe5
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/Makefile
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+dtb-$(CONFIG_TARGET_AXS101) += axs101.dtb
+dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
+dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
+dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
+dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
+dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
+dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
+
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/roms/u-boot/arch/arc/dts/abilis_tb100.dts b/roms/u-boot/arch/arc/dts/abilis_tb100.dts
new file mode 100644
index 000000000..19e45b9c6
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/abilis_tb100.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "abilis,tb100";
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial@ff100000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff100000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+};
diff --git a/roms/u-boot/arch/arc/dts/axc001.dtsi b/roms/u-boot/arch/arc/dts/axc001.dtsi
new file mode 100644
index 000000000..412580a38
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/axc001.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <750000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
diff --git a/roms/u-boot/arch/arc/dts/axc003.dtsi b/roms/u-boot/arch/arc/dts/axc003.dtsi
new file mode 100644
index 000000000..75a9de61d
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/axc003.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
diff --git a/roms/u-boot/arch/arc/dts/axs101.dts b/roms/u-boot/arch/arc/dts/axs101.dts
new file mode 100644
index 000000000..fc9fa93b7
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/axs101.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+/include/ "axc001.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+ model = "snps,axs101";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
diff --git a/roms/u-boot/arch/arc/dts/axs103.dts b/roms/u-boot/arch/arc/dts/axs103.dts
new file mode 100644
index 000000000..6e2dd00fc
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/axs103.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+/include/ "axc003.dtsi"
+/include/ "axs10x_mb.dtsi"
+
+
+/ {
+ model = "snps,axs103";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
diff --git a/roms/u-boot/arch/arc/dts/axs10x_mb.dtsi b/roms/u-boot/arch/arc/dts/axs10x_mb.dtsi
new file mode 100644
index 000000000..d4ff4f703
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/axs10x_mb.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
+
+ axs10x_mb@e0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0xe0000000 0x10000000>;
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ compatible = "simple-bus";
+ u-boot,dm-pre-reloc;
+
+ apbclk: apbclk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ uartclk: uartclk {
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ /*
+ * DW sdio controller has external ciu clock divider
+ * controlled via register in SDIO IP. It divides
+ * sdio_ref_clk (which comes from CGU) by 16 for
+ * default. So default mmcclk clock (which comes
+ * to sdk_in) is 25000000 Hz.
+ */
+ clock-frequency = <25000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_biu: mmcclk-biu {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ ethernet@18000 {
+ compatible = "snps,arc-dwmac-3.70a";
+ reg = < 0x18000 0x2000 >;
+ phy-mode = "gmii";
+ snps,pbl = < 32 >;
+ clocks = <&apbclk>;
+ clock-names = "stmmaceth";
+ max-speed = <100>;
+ };
+
+ ehci@40000 {
+ compatible = "generic-ehci";
+ reg = < 0x40000 0x100 >;
+ };
+
+ ohci@60000 {
+ compatible = "generic-ohci";
+ reg = < 0x60000 0x100 >;
+ };
+
+ mmc: mmc@15000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x15000 0x400>;
+ bus-width = <4>;
+ clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <25000000>;
+ };
+
+ uart0: serial0@22000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x22000 0x100>;
+ clocks = <&uartclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ spi0: spi@0 {
+ compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&apbclk>;
+ clock-names = "spi_clk";
+ num-cs = <1>;
+ cs-gpios = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@11218 {
+ compatible = "snps,creg-gpio";
+ reg = <0x11218 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "axs-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <1>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
+ };
+};
diff --git a/roms/u-boot/arch/arc/dts/emsdp.dts b/roms/u-boot/arch/arc/dts/emsdp.dts
new file mode 100644
index 000000000..dbebdb4e7
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/emsdp.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "snps,emsdp";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial0@f0004000 {
+ compatible = "snps,dw-apb-uart";
+ clock-frequency = <100000000>;
+ reg = <0xf0004000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ mmcclk_biu: mmcclk-biu {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ #clock-cells = <0>;
+ };
+
+ mmc: mmc0@f0010000 {
+ compatible = "snps,dw-mshc";
+ reg = <0xf0010000 0x400>;
+ bus-width = <4>;
+ fifo-depth = <256>;
+ clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <25000000>;
+ };
+
+};
diff --git a/roms/u-boot/arch/arc/dts/hsdk-4xd.dts b/roms/u-boot/arch/arc/dts/hsdk-4xd.dts
new file mode 100644
index 000000000..b245eea76
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/hsdk-4xd.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+/dts-v1/;
+
+#include "hsdk-common.dtsi"
+
+/ {
+ model = "snps,hsdk-4xd";
+};
diff --git a/roms/u-boot/arch/arc/dts/hsdk-common.dtsi b/roms/u-boot/arch/arc/dts/hsdk-common.dtsi
new file mode 100644
index 000000000..3fc82e57d
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/hsdk-common.dtsi
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
+#include "dt-bindings/reset/snps,hsdk-reset.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ spi0 = &spi0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clk-fmeas {
+ clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+ <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+ <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+ <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+ <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+ <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+ <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+ <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
+ <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
+ <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
+ <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+ <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
+ <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>,
+ <&cgu_clk CLK_TUN_TIMER>;
+ clock-names = "cpu-pll", "sys-pll",
+ "tun-pll", "ddr-clk",
+ "cpu-clk", "hdmi-pll",
+ "tun-clk", "hdmi-clk",
+ "apb-clk", "axi-clk",
+ "eth-clk", "usb-clk",
+ "sdio-clk", "hdmi-sys-clk",
+ "gfx-core-clk", "gfx-dma-clk",
+ "gfx-cfg-clk", "dmac-core-clk",
+ "dmac-cfg-clk", "sdio-ref-clk",
+ "spi-clk", "i2c-clk",
+ "uart-clk", "ebi-clk",
+ "rom-clk", "pwm-clk",
+ "timer-clk";
+ };
+
+ cgu_clk: cgu-clk@f0000000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
+ cgu_rst: reset-controller@f00008a0 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
+ };
+
+ uart0: serial0@f0005000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf0005000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ ethernet@f0008000 {
+ #interrupt-cells = <1>;
+ compatible = "snps,arc-dwmac-3.70a";
+ reg = <0xf0008000 0x2000>;
+ phy-mode = "gmii";
+ };
+
+ ehci@f0040000 {
+ compatible = "generic-ehci";
+ reg = <0xf0040000 0x100>;
+
+ /*
+ * OHCI and EHCI have reset line shared so we don't add
+ * reset property to OHCI node as it is probed later and
+ * it will reset sucessfuly probed and configured EHCI HW.
+ */
+ resets = <&cgu_rst HSDK_USB_RESET>;
+ };
+
+ ohci@f0060000 {
+ compatible = "generic-ohci";
+ reg = <0xf0060000 0x100>;
+ };
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ /*
+ * DW sdio controller has external ciu clock divider
+ * controlled via register in SDIO IP. Due to its
+ * unexpected default value (it should divide by 1
+ * but it divides by 8) SDIO IP uses wrong clock and
+ * works unstable (see STAR 9001204800)
+ * We switched to the minimum possible value of the
+ * divisor (div-by-2) in HSDK platform code.
+ * So default mmcclk ciu clock is 50000000 Hz.
+ */
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ mmc: mmc0@f000a000 {
+ compatible = "snps,dw-mshc";
+ reg = <0xf000a000 0x400>;
+ bus-width = <4>;
+ fifo-depth = <256>;
+ clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <25000000>;
+ };
+
+ spi0: spi@f0020000 {
+ compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
+ reg = <0xf0020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+ clock-names = "spi_clk";
+ num-cs = <1>;
+ cs-gpios = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@f00014b0 {
+ compatible = "snps,creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "hsdk-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
+};
diff --git a/roms/u-boot/arch/arc/dts/hsdk.dts b/roms/u-boot/arch/arc/dts/hsdk.dts
new file mode 100644
index 000000000..1a2e3d432
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/hsdk.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ */
+/dts-v1/;
+
+#include "hsdk-common.dtsi"
+
+/ {
+ model = "snps,hsdk";
+};
diff --git a/roms/u-boot/arch/arc/dts/iot_devkit.dts b/roms/u-boot/arch/arc/dts/iot_devkit.dts
new file mode 100644
index 000000000..212282752
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/iot_devkit.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <144000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial0@80014000 {
+ compatible = "snps,dw-apb-uart";
+ clock-frequency = <16000000>;
+ reg = <0x80014000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ usb: usb@f0040000 {
+ compatible = "snps,dwc2";
+ reg = <0xf0040000 0x10000>;
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
+ };
+
+ usbphy: phy {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ mmcclk_biu: mmcclk-biu {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
+ mmc: mmc0@f000b000 {
+ compatible = "snps,dw-mshc";
+ reg = <0xf000b000 0x400>;
+ bus-width = <4>;
+ fifo-depth = <128>;
+ clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <25000000>;
+ };
+};
diff --git a/roms/u-boot/arch/arc/dts/nsim.dts b/roms/u-boot/arch/arc/dts/nsim.dts
new file mode 100644
index 000000000..c2899ef2e
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/nsim.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016, 2020 Synopsys, Inc. (www.synopsys.com)
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ model = "snps,nsim";
+
+ aliases {
+ console = &uart0;
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <70000000>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ uart0: serial@f0000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf0000000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <70000000>;
+ };
+
+ virtio0: virtio@f0100000 {
+ compatible = "virtio,mmio";
+ reg = <0xf0100000 0x2000>;
+ };
+
+ virtio1: virtio@f0102000 {
+ compatible = "virtio,mmio";
+ reg = <0xf0102000 0x2000>;
+ };
+
+ virtio2: virtio@f0104000 {
+ compatible = "virtio,mmio";
+ reg = <0xf0104000 0x2000>;
+ };
+
+ virtio3: virtio@f0106000 {
+ compatible = "virtio,mmio";
+ reg = <0xf0106000 0x2000>;
+ };
+
+ virtio4: virtio@f0108000 {
+ compatible = "virtio,mmio";
+ reg = <0xf0108000 0x2000>;
+ };
+};
diff --git a/roms/u-boot/arch/arc/dts/skeleton.dtsi b/roms/u-boot/arch/arc/dts/skeleton.dtsi
new file mode 100644
index 000000000..279fc6cac
--- /dev/null
+++ b/roms/u-boot/arch/arc/dts/skeleton.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+ aliases { };
+
+ cpu_card {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ timer@0 {
+ compatible = "snps,arc-timer";
+ clocks = <&core_clk>;
+ reg = <0 1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256M */
+ };
+};