diff options
Diffstat (limited to 'roms/u-boot/arch/arc/include')
21 files changed, 779 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arc/include/asm/arc-bcr.h b/roms/u-boot/arch/arc/include/asm/arc-bcr.h new file mode 100644 index 000000000..823906d94 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/arc-bcr.h @@ -0,0 +1,77 @@ +/* + * ARC Build Configuration Registers, with encoded hardware config + * + * Copyright (C) 2018 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARC_BCR_H +#define __ARC_BCR_H +#ifndef __ASSEMBLY__ + +#include <config.h> + +union bcr_di_cache { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; +#else + unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; +#endif + } fields; + unsigned int word; +}; + +union bcr_slc_cfg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, way:2, lsz:2, sz:4; +#else + unsigned int sz:4, lsz:2, way:2, pad:24; +#endif + } fields; + unsigned int word; +}; + +union bcr_generic { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:24, ver:8; +#else + unsigned int ver:8, pad:24; +#endif + } fields; + unsigned int word; +}; + +union bcr_clust_cfg { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8; +#else + unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7; +#endif + } fields; + unsigned int word; +}; + +union bcr_mmu_4 { + struct { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, + n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; +#else + /* DTLB ITLB JES JE JA */ + unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, + pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; +#endif + } fields; + unsigned int word; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ARC_BCR_H */ diff --git a/roms/u-boot/arch/arc/include/asm/arcregs.h b/roms/u-boot/arch/arc/include/asm/arcregs.h new file mode 100644 index 000000000..a9f54f61e --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/arcregs.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + */ + +#ifndef _ASM_ARC_ARCREGS_H +#define _ASM_ARC_ARCREGS_H + +#include <asm/cache.h> +#include <config.h> + +/* + * ARC architecture has additional address space - auxiliary registers. + * These registers are mostly used for configuration purposes. + * These registers are not memory mapped and special commands are used for + * access: "lr"/"sr". + */ + +/* + * Typically 8 least significant bits of Build Configuration Register (BCR) + * describe version of the HW block in question. Moreover if decoded version + * is 0 this means given HW block is absent - this is especially useful because + * we may safely read BRC regardless HW block existence while an attempt to + * access any other AUX regs associated with this HW block lead to imediate + * "instruction error" exception. + * + * I.e. before using any cofigurable HW block it's required to make sure it + * exists at all, and for that we introduce a special macro below. + */ +#define ARC_BCR_VERSION_MASK GENMASK(7, 0) +#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK) + +#define ARC_AUX_IDENTITY 0x04 +#define ARC_AUX_STATUS32 0x0a + +/* STATUS32 Bits Positions */ +#define STATUS_AD_BIT 19 /* Enable unaligned access */ + +/* Instruction cache related auxiliary registers */ +#define ARC_AUX_IC_IVIC 0x10 +#define ARC_AUX_IC_CTRL 0x11 +#define ARC_AUX_IC_IVIL 0x19 +#if (CONFIG_ARC_MMU_VER == 3) +#define ARC_AUX_IC_PTAG 0x1E +#endif +#define ARC_BCR_IC_BUILD 0x77 +#define AUX_AUX_CACHE_LIMIT 0x5D +#define ARC_AUX_NON_VOLATILE_LIMIT 0x5E + +/* ICCM and DCCM auxiliary registers */ +#define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */ +#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */ + +/* CSM auxiliary registers */ +#define ARC_AUX_CSM_ENABLE 0x9A0 + +/* Timer related auxiliary registers */ +#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ +#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ +#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ + +#define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */ +#define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */ +#define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */ + +#define ARC_AUX_INTR_VEC_BASE 0x25 + +/* Data cache related auxiliary registers */ +#define ARC_AUX_DC_IVDC 0x47 +#define ARC_AUX_DC_CTRL 0x48 + +#define ARC_AUX_DC_IVDL 0x4A +#define ARC_AUX_DC_FLSH 0x4B +#define ARC_AUX_DC_FLDL 0x4C +#if (CONFIG_ARC_MMU_VER == 3) +#define ARC_AUX_DC_PTAG 0x5C +#endif +#define ARC_BCR_DC_BUILD 0x72 +#define ARC_BCR_SLC 0xce +#define ARC_AUX_SLC_CONFIG 0x901 +#define ARC_AUX_SLC_CTRL 0x903 +#define ARC_AUX_SLC_FLUSH 0x904 +#define ARC_AUX_SLC_INVALIDATE 0x905 +#define ARC_AUX_SLC_IVDL 0x910 +#define ARC_AUX_SLC_FLDL 0x912 +#define ARC_AUX_SLC_RGN_START 0x914 +#define ARC_AUX_SLC_RGN_START1 0x915 +#define ARC_AUX_SLC_RGN_END 0x916 +#define ARC_AUX_SLC_RGN_END1 0x917 +#define ARC_BCR_CLUSTER 0xcf + +/* MMU Management regs */ +#define ARC_AUX_MMU_BCR 0x6f + +/* IO coherency related auxiliary registers */ +#define ARC_AUX_IO_COH_ENABLE 0x500 +#define ARC_AUX_IO_COH_PARTIAL 0x501 +#define ARC_AUX_IO_COH_AP0_BASE 0x508 +#define ARC_AUX_IO_COH_AP0_SIZE 0x509 + +/* XY-memory related */ +#define ARC_AUX_XY_BUILD 0x79 + +/* DSP-extensions related auxiliary registers */ +#define ARC_AUX_DSP_BUILD 0x7A +#define ARC_AUX_DSP_CTRL 0x59F + +/* ARC Subsystems related auxiliary registers */ +#define ARC_AUX_SUBSYS_BUILD 0xF0 + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> + +/* Accessors for auxiliary registers */ +#define read_aux_reg(reg) __builtin_arc_lr(reg) + +/* gcc builtin sr needs reg param to be long immediate */ +#define write_aux_reg(reg_immed, val) \ + __builtin_arc_sr((unsigned int)val, reg_immed) + +/* ARCNUM [15:8] - field to identify each core in a multi-core system */ +#define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8) + +static const inline int is_isa_arcv2(void) +{ + return IS_ENABLED(CONFIG_ISA_ARCV2); +} + +static const inline int is_isa_arcompact(void) +{ + return IS_ENABLED(CONFIG_ISA_ARCOMPACT); +} +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARC_ARCREGS_H */ diff --git a/roms/u-boot/arch/arc/include/asm/bitops.h b/roms/u-boot/arch/arc/include/asm/bitops.h new file mode 100644 index 000000000..c6dd28ece --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/bitops.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_BITOPS_H +#define __ASM_ARC_BITOPS_H + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + +#endif /* __ASM_ARC_BITOPS_H */ diff --git a/roms/u-boot/arch/arc/include/asm/byteorder.h b/roms/u-boot/arch/arc/include/asm/byteorder.h new file mode 100644 index 000000000..8c171bb29 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/byteorder.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_BYTEORDER_H +#define __ASM_ARC_BYTEORDER_H + +#include <asm/types.h> + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) + #define __BYTEORDER_HAS_U64__ + #define __SWAB_64_THRU_32__ +#endif + +#ifdef __LITTLE_ENDIAN__ + #include <linux/byteorder/little_endian.h> +#else + #include <linux/byteorder/big_endian.h> +#endif /* CONFIG_SYS_BIG_ENDIAN */ + +#endif /* ASM_ARC_BYTEORDER_H */ diff --git a/roms/u-boot/arch/arc/include/asm/cache.h b/roms/u-boot/arch/arc/include/asm/cache.h new file mode 100644 index 000000000..ab61846b5 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/cache.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_CACHE_H +#define __ASM_ARC_CACHE_H + +#include <config.h> + +/* + * As of today we may handle any L1 cache line length right in software. + * For that essentially cache line length is a variable not constant. + * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length + * that may exist in either L1 or L2 (AKA SLC) caches on ARC. + */ +#define ARCH_DMA_MINALIGN 128 + +/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */ +#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN + +#if defined(ARC_MMU_ABSENT) +#define CONFIG_ARC_MMU_VER 0 +#elif defined(CONFIG_ARC_MMU_V2) +#define CONFIG_ARC_MMU_VER 2 +#elif defined(CONFIG_ARC_MMU_V3) +#define CONFIG_ARC_MMU_VER 3 +#elif defined(CONFIG_ARC_MMU_V4) +#define CONFIG_ARC_MMU_VER 4 +#endif + +#ifndef __ASSEMBLY__ + +void cache_init(void); +void flush_n_invalidate_dcache_all(void); +void sync_n_cleanup_cache_all(void); + +static const inline int is_ioc_enabled(void) +{ + return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE); +} + +/* + * We export SLC control functions to use them in platform configuration code. + * They maust not be used in any generic code! + */ +void slc_enable(void); +void slc_disable(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARC_CACHE_H */ diff --git a/roms/u-boot/arch/arc/include/asm/config.h b/roms/u-boot/arch/arc/include/asm/config.h new file mode 100644 index 000000000..46e94be14 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/config.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_CONFIG_H_ +#define __ASM_ARC_CONFIG_H_ + +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#endif /*__ASM_ARC_CONFIG_H_ */ diff --git a/roms/u-boot/arch/arc/include/asm/dma-mapping.h b/roms/u-boot/arch/arc/include/asm/dma-mapping.h new file mode 100644 index 000000000..853b0877b --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/dma-mapping.h @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/roms/u-boot/arch/arc/include/asm/global_data.h b/roms/u-boot/arch/arc/include/asm/global_data.h new file mode 100644 index 000000000..e35a26f1e --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/global_data.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_GLOBAL_DATA_H +#define __ASM_ARC_GLOBAL_DATA_H + +#ifndef __ASSEMBLY__ +/* Architecture-specific global data */ +struct arch_global_data { + int l1_line_sz; +#if defined(CONFIG_ISA_ARCV2) + int slc_line_sz; +#endif +}; +#endif /* __ASSEMBLY__ */ + +#include <asm-generic/global_data.h> + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25") + +#endif /* __ASM_ARC_GLOBAL_DATA_H */ diff --git a/roms/u-boot/arch/arc/include/asm/gpio.h b/roms/u-boot/arch/arc/include/asm/gpio.h new file mode 100644 index 000000000..306ab4c9f --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/gpio.h @@ -0,0 +1 @@ +#include <asm-generic/gpio.h> diff --git a/roms/u-boot/arch/arc/include/asm/io.h b/roms/u-boot/arch/arc/include/asm/io.h new file mode 100644 index 000000000..6adc0ed42 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/io.h @@ -0,0 +1,254 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_IO_H +#define __ASM_ARC_IO_H + +#include <linux/types.h> +#include <asm/byteorder.h> + +/* + * Compiler barrier. It prevents compiler from reordering instructions before + * and after it. It doesn't prevent HW (CPU) from any reordering though. + */ +#define __comp_b() asm volatile("" : : : "memory") + +#ifdef __ARCHS__ + +/* + * ARCv2 based HS38 cores are in-order issue, but still weakly ordered + * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ... + * + * Explicit barrier provided by DMB instruction + * - Operand supports fine grained load/store/load+store semantics + * - Ensures that selected memory operation issued before it will complete + * before any subsequent memory operation of same type + * - DMB guarantees SMP as well as local barrier semantics + * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e. + * UP: barrier(), SMP: smp_*mb == *mb) + * - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed + * in the general case. Plus it only provides full barrier. + */ + +#define mb() asm volatile("dmb 3\n" : : : "memory") +#define rmb() asm volatile("dmb 1\n" : : : "memory") +#define wmb() asm volatile("dmb 2\n" : : : "memory") + +#else + +/* + * ARCompact based cores (ARC700) only have SYNC instruction which is super + * heavy weight as it flushes the pipeline as well. + * There are no real SMP implementations of such cores. + */ + +#define mb() asm volatile("sync\n" : : : "memory") +#endif + +#ifdef __ARCHS__ +#define __iormb() rmb() +#define __iowmb() wmb() +#else +#define __iormb() __comp_b() +#define __iowmb() __comp_b() +#endif + +static inline void sync(void) +{ + /* Not yet implemented */ +} + +/* + * We must use 'volatile' in C-version read/write IO accessors implementation + * to avoid merging several reads (writes) into one read (write), or optimizing + * them out by compiler. + * We must use compiler barriers before and after operation (read or write) so + * it won't be reordered by compiler. + */ +#define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8 *)(a); __comp_b(); __v; }) +#define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; }) +#define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; }) +#define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; }) + +#define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v); __comp_b(); }) +#define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); }) +#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); }) +#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); }) + + +/* + * We add memory barriers for __raw_readX / __raw_writeX accessors same way as + * it is done for readX and writeX accessors as lots of U-boot driver uses + * __raw_readX / __raw_writeX instead of proper accessor with barrier. + */ +#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) +#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); }) +#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); }) +#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); }) + +#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) +#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) +#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) +#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) + + +static inline void __raw_writesb(unsigned long addr, const void *data, + int bytelen) +{ + u8 *buf = (uint8_t *)data; + + __iowmb(); + + while (bytelen--) + __arch_putb(*buf++, addr); +} + +static inline void __raw_writesw(unsigned long addr, const void *data, + int wordlen) +{ + u16 *buf = (uint16_t *)data; + + __iowmb(); + + while (wordlen--) + __arch_putw(*buf++, addr); +} + +static inline void __raw_writesl(unsigned long addr, const void *data, + int longlen) +{ + u32 *buf = (uint32_t *)data; + + __iowmb(); + + while (longlen--) + __arch_putl(*buf++, addr); +} + +static inline void __raw_readsb(unsigned long addr, void *data, int bytelen) +{ + u8 *buf = (uint8_t *)data; + + while (bytelen--) + *buf++ = __arch_getb(addr); + + __iormb(); +} + +static inline void __raw_readsw(unsigned long addr, void *data, int wordlen) +{ + u16 *buf = (uint16_t *)data; + + while (wordlen--) + *buf++ = __arch_getw(addr); + + __iormb(); +} + +static inline void __raw_readsl(unsigned long addr, void *data, int longlen) +{ + u32 *buf = (uint32_t *)data; + + while (longlen--) + *buf++ = __arch_getl(addr); + + __iormb(); +} + +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__arch_putb((v), (c))) +#define writew_relaxed(v, c) ((void)__arch_putw((__force u16)cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__arch_putq((__force u64)cpu_to_le64(v), (c))) + +/* + * MMIO can also get buffered/optimized in micro-arch, so barriers needed + * Based on ARM model for the typical use case + * + * <ST [DMA buffer]> + * <writel MMIO "go" reg> + * or: + * <readl MMIO "status" reg> + * <LD [DMA buffer]> + * + * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com + */ +#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) +#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; }) + +#define writeb(v, c) ({ __iowmb(); writeb_relaxed(v, c); }) +#define writew(v, c) ({ __iowmb(); writew_relaxed(v, c); }) +#define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); }) +#define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); }) + +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) + +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) + +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) + +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) + +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) + +/* + * Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + +#include <asm-generic/io.h> + +#endif /* __ASM_ARC_IO_H */ diff --git a/roms/u-boot/arch/arc/include/asm/linkage.h b/roms/u-boot/arch/arc/include/asm/linkage.h new file mode 100644 index 000000000..2d42ed409 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/linkage.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_LINKAGE_H +#define __ASM_ARC_LINKAGE_H + +#define ASM_NL ` /* use '`' to mark new line in macro */ + +#endif /* __ASM_ARC_LINKAGE_H */ diff --git a/roms/u-boot/arch/arc/include/asm/posix_types.h b/roms/u-boot/arch/arc/include/asm/posix_types.h new file mode 100644 index 000000000..13838cbc1 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/posix_types.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_POSIX_TYPES_H +#define __ASM_ARC_POSIX_TYPES_H + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +#ifdef __GNUC__ +typedef __SIZE_TYPE__ __kernel_size_t; +#else +typedef unsigned int __kernel_size_t; +#endif +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +#endif /* __ASM_ARC_POSIX_TYPES_H */ diff --git a/roms/u-boot/arch/arc/include/asm/processor.h b/roms/u-boot/arch/arc/include/asm/processor.h new file mode 100644 index 000000000..03e31fb4e --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/processor.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Synopsys, Inc. All rights reserved. + */ + +#ifndef _ASM_ARC_PROCESSOR_H +#define _ASM_ARC_PROCESSOR_H + +/* This file is required by some generic code like USB etc */ + +#endif /* _ASM_ARC_PROCESSOR_H */ diff --git a/roms/u-boot/arch/arc/include/asm/ptrace.h b/roms/u-boot/arch/arc/include/asm/ptrace.h new file mode 100644 index 000000000..6965e8936 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/ptrace.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_PTRACE_H +#define __ASM_ARC_PTRACE_H + +struct pt_regs { + long bta; + long lp_start; + long lp_end; + long lp_count; + long status32; + long ret; + long blink; + long fp; + long r26; /* gp */ + long r25; + long r24; + long r23; + long r22; + long r21; + long r20; + long r19; + long r18; + long r17; + long r16; + long r15; + long r14; + long r13; + long r12; + long r11; + long r10; + long r9; + long r8; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long sp; + long ecr; +}; + +#endif /* __ASM_ARC_PTRACE_H */ diff --git a/roms/u-boot/arch/arc/include/asm/sections.h b/roms/u-boot/arch/arc/include/asm/sections.h new file mode 100644 index 000000000..1c9c9db13 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/sections.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_SECTIONS_H +#define __ASM_ARC_SECTIONS_H + +#include <asm-generic/sections.h> + +extern ulong __ivt_start; +extern ulong __ivt_end; + +#endif /* __ASM_ARC_SECTIONS_H */ diff --git a/roms/u-boot/arch/arc/include/asm/spl.h b/roms/u-boot/arch/arc/include/asm/spl.h new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/spl.h diff --git a/roms/u-boot/arch/arc/include/asm/string.h b/roms/u-boot/arch/arc/include/asm/string.h new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/string.h @@ -0,0 +1 @@ + diff --git a/roms/u-boot/arch/arc/include/asm/types.h b/roms/u-boot/arch/arc/include/asm/types.h new file mode 100644 index 000000000..f31dcdf28 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/types.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_TYPES_H +#define __ASM_ARC_TYPES_H + +#include <asm-generic/int-ll64.h> + +typedef unsigned short umode_t; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __ASM_ARC_TYPES_H */ diff --git a/roms/u-boot/arch/arc/include/asm/u-boot-arc.h b/roms/u-boot/arch/arc/include/asm/u-boot-arc.h new file mode 100644 index 000000000..dd2c0949c --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/u-boot-arc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_U_BOOT_ARC_H__ +#define __ASM_ARC_U_BOOT_ARC_H__ + +int arch_early_init_r(void); + +void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); +void board_init_f_r(void) __attribute__ ((noreturn)); + +#endif /* __ASM_ARC_U_BOOT_ARC_H__ */ diff --git a/roms/u-boot/arch/arc/include/asm/u-boot.h b/roms/u-boot/arch/arc/include/asm/u-boot.h new file mode 100644 index 000000000..36c220745 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/u-boot.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + */ + +#ifndef __ASM_ARC_U_BOOT_H__ +#define __ASM_ARC_U_BOOT_H__ + +#include <asm-generic/u-boot.h> +#include <asm/u-boot-arc.h> + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_ARC + +#endif /* __ASM_ARC_U_BOOT_H__ */ diff --git a/roms/u-boot/arch/arc/include/asm/unaligned.h b/roms/u-boot/arch/arc/include/asm/unaligned.h new file mode 100644 index 000000000..6cecbbb21 --- /dev/null +++ b/roms/u-boot/arch/arc/include/asm/unaligned.h @@ -0,0 +1 @@ +#include <asm-generic/unaligned.h> |