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-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/Makefile15
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/cache.c58
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/config.mk18
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c145
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c295
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/relocate.S22
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/start.S205
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/timer.c16
-rw-r--r--roms/u-boot/arch/arm/cpu/pxa/usb.c89
9 files changed, 863 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/cpu/pxa/Makefile b/roms/u-boot/arch/arm/cpu/pxa/Makefile
new file mode 100644
index 000000000..263d9ddb4
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+extra-y = start.o
+
+obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o
+obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
+
+obj-y += cpuinfo.o
+obj-y += timer.o
+obj-y += usb.o
+obj-y += relocate.o
+obj-y += cache.o
diff --git a/roms/u-boot/arch/arm/cpu/pxa/cache.c b/roms/u-boot/arch/arm/cpu/pxa/cache.c
new file mode 100644
index 000000000..a2ec5e28c
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/cache.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
+ */
+
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <linux/types.h>
+#include <common.h>
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void invalidate_dcache_all(void)
+{
+ /* Flush/Invalidate I cache */
+ asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
+ /* Flush/Invalidate D cache */
+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+ return invalidate_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+ while (start <= stop) {
+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ return invalidate_dcache_range(start, stop);
+}
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+
+__weak void l2_cache_disable(void) {}
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+__weak void invalidate_l2_cache(void) {}
+#endif
diff --git a/roms/u-boot/arch/arm/cpu/pxa/config.mk b/roms/u-boot/arch/arm/cpu/pxa/config.mk
new file mode 100644
index 000000000..e7b183674
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/config.mk
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+
+#
+# !WARNING!
+# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
+# really small OneNAND memories where the mmap'd window is only 1KiB big. The
+# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
+# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
+# they are not discarded.
+#
+
+#ifdef CONFIG_SPL_BUILD
+OBJCOPYFLAGS += -j .text.0 -j .text.1
+#endif
diff --git a/roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c b/roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c
new file mode 100644
index 000000000..0d9542f99
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/cpuinfo.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PXA CPU information display
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <linux/compiler.h>
+
+#ifdef CONFIG_CPU_PXA25X
+#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
+#error "Init SP address must be set to 0xfffff800 for PXA250"
+#endif
+#endif
+
+#define CPU_MASK_PXA_PRODID 0x000003f0
+#define CPU_MASK_PXA_REVID 0x0000000f
+
+#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
+
+#define CPU_VALUE_PXA25X 0x100
+#define CPU_VALUE_PXA27X 0x110
+
+static uint32_t pxa_get_cpuid(void)
+{
+ uint32_t cpuid;
+ asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
+ return cpuid;
+}
+
+int cpu_is_pxa25x(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ id &= CPU_MASK_PXA_PRODID;
+ return id == CPU_VALUE_PXA25X;
+}
+
+int cpu_is_pxa27x(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ id &= CPU_MASK_PXA_PRODID;
+ return id == CPU_VALUE_PXA27X;
+}
+
+int cpu_is_pxa27xm(void)
+{
+ uint32_t id = pxa_get_cpuid();
+ return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
+ ((id & CPU_MASK_PXA_REVID) == 8);
+}
+
+uint32_t pxa_get_cpu_revision(void)
+{
+ return pxa_get_cpuid() & CPU_MASK_PRODREV;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static const char *pxa25x_get_revision(void)
+{
+ static __maybe_unused const char * const revs_25x[] = { "A0" };
+ static __maybe_unused const char * const revs_26x[] = {
+ "A0", "B0", "B1"
+ };
+ static const char *unknown = "Unknown";
+ uint32_t id;
+
+ if (!cpu_is_pxa25x())
+ return unknown;
+
+ id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
+#ifdef CONFIG_CPU_PXA26X
+ switch (id) {
+ case 3: return revs_26x[0];
+ case 5: return revs_26x[1];
+ case 6: return revs_26x[2];
+ }
+#else
+ if (id == 6)
+ return revs_25x[0];
+#endif
+ return unknown;
+}
+
+static const char *pxa27x_get_revision(void)
+{
+ static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
+ static const char *unknown = "Unknown";
+ uint32_t id;
+
+ if (!cpu_is_pxa27x())
+ return unknown;
+
+ id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
+
+ if ((id == 5) || (id == 6) || (id > 8))
+ return unknown;
+
+ /* Cap the special PXA270 C5 case. */
+ if (id == 7)
+ id = 5;
+
+ /* Cap the special PXA270M A1 case. */
+ if (id == 8)
+ id = 1;
+
+ return rev[id];
+}
+
+static int print_cpuinfo_pxa2xx(void)
+{
+ if (cpu_is_pxa25x()) {
+ puts("Marvell PXA25x rev. ");
+ puts(pxa25x_get_revision());
+ } else if (cpu_is_pxa27x()) {
+ puts("Marvell PXA27x");
+ if (cpu_is_pxa27xm()) puts("M");
+ puts(" rev. ");
+ puts(pxa27x_get_revision());
+ } else
+ return -EINVAL;
+
+ puts("\n");
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ int ret;
+
+ puts("CPU: ");
+
+ ret = print_cpuinfo_pxa2xx();
+ if (!ret)
+ return ret;
+
+ return ret;
+}
+#endif
diff --git a/roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c b/roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c
new file mode 100644
index 000000000..c7efb6775
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/pxa2xx.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <irq_func.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <command.h>
+
+/* Flush I/D-cache */
+static void cache_flush(void)
+{
+ unsigned long i = 0;
+
+ asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
+}
+
+int cleanup_before_linux(void)
+{
+ /*
+ * This function is called just before we call Linux. It prepares
+ * the processor for Linux by just disabling everything that can
+ * disturb booting Linux.
+ */
+
+ disable_interrupts();
+ icache_disable();
+ dcache_disable();
+ cache_flush();
+
+ return 0;
+}
+
+inline void writelrb(uint32_t val, uint32_t addr)
+{
+ writel(val, addr);
+ asm volatile("" : : : "memory");
+ readl(addr);
+ asm volatile("" : : : "memory");
+}
+
+void pxa2xx_dram_init(void)
+{
+ uint32_t tmp;
+ int i;
+ /*
+ * 1) Initialize Asynchronous static memory controller
+ */
+
+ writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
+ writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
+ writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
+ /*
+ * 2) Initialize Card Interface
+ */
+
+ /* MECR: Memory Expansion Card Register */
+ writelrb(CONFIG_SYS_MECR_VAL, MECR);
+ /* MCMEM0: Card Interface slot 0 timing */
+ writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
+ /* MCMEM1: Card Interface slot 1 timing */
+ writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
+
+ /*
+ * 3) Configure Fly-By DMA register
+ */
+
+ writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
+
+ /*
+ * 4) Initialize Timing for Sync Memory (SDCLK0)
+ */
+
+ /*
+ * Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+
+ /* Read current MDREFR config and zero out DRI */
+ tmp = readl(MDREFR) & ~0xfff;
+ /* Add user-specified DRI */
+ tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
+ /* Configure important bits */
+ tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
+ tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
+
+ /* Write MDREFR back */
+ writelrb(tmp, MDREFR);
+
+ /*
+ * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+ */
+
+ /* Initialize SXCNFG register. Assert the enable bits.
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+ writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
+
+ /*
+ * 6) Initialize SDRAM
+ */
+
+ writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
+ writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
+
+ /*
+ * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+ * but not enable each SDRAM partition pair.
+ */
+
+ writelrb(CONFIG_SYS_MDCNFG_VAL &
+ ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+
+ /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+ writel(0, OSCR);
+ while (readl(OSCR) < 0x300)
+ asm volatile("" : : : "memory");
+
+ /*
+ * 8) Trigger a number (usually 8) refresh cycles by attempting
+ * non-burst read or write accesses to disabled SDRAM, as commonly
+ * specified in the power up sequence documented in SDRAM data
+ * sheets. The address(es) used for this purpose must not be
+ * cacheable.
+ */
+ for (i = 9; i >= 0; i--) {
+ writel(i, 0xa0000000);
+ asm volatile("" : : : "memory");
+ }
+ /*
+ * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+ */
+
+ tmp = CONFIG_SYS_MDCNFG_VAL &
+ (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
+ tmp |= readl(MDCNFG);
+ writelrb(tmp, MDCNFG);
+
+ /*
+ * 10) Write MDMRS.
+ */
+
+ writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
+
+ /*
+ * 11) Enable APD
+ */
+
+ if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
+ tmp = readl(MDREFR);
+ tmp |= MDREFR_APD;
+ writelrb(tmp, MDREFR);
+ }
+}
+
+void pxa_gpio_setup(void)
+{
+ writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
+ writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
+ writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
+#if defined(CONFIG_CPU_PXA27X)
+ writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
+#endif
+
+ writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
+ writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
+ writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
+#if defined(CONFIG_CPU_PXA27X)
+ writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
+#endif
+
+ writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
+ writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
+ writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
+#if defined(CONFIG_CPU_PXA27X)
+ writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
+#endif
+
+ writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
+ writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
+ writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
+ writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
+ writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
+ writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
+#if defined(CONFIG_CPU_PXA27X)
+ writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
+ writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
+#endif
+
+ writel(CONFIG_SYS_PSSR_VAL, PSSR);
+}
+
+void pxa_interrupt_setup(void)
+{
+ writel(0, ICLR);
+ writel(0, ICMR);
+#if defined(CONFIG_CPU_PXA27X)
+ writel(0, ICLR2);
+ writel(0, ICMR2);
+#endif
+}
+
+void pxa_clock_setup(void)
+{
+ writel(CONFIG_SYS_CKEN, CKEN);
+ writel(CONFIG_SYS_CCCR, CCCR);
+ asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
+
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ writel(OSCC_OON, OSCC);
+ while (!(readl(OSCC) & OSCC_OOK))
+ asm volatile("" : : : "memory");
+}
+
+void pxa_wakeup(void)
+{
+ uint32_t rcsr;
+
+ rcsr = readl(RCSR);
+ writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
+
+ /* Wakeup */
+ if (rcsr & RCSR_SMR) {
+ writel(PSSR_PH, PSSR);
+ pxa2xx_dram_init();
+ icache_disable();
+ dcache_disable();
+ asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
+ }
+}
+
+int arch_cpu_init(void)
+{
+ pxa_gpio_setup();
+ pxa_wakeup();
+ pxa_interrupt_setup();
+ pxa_clock_setup();
+ return 0;
+}
+
+void i2c_clk_enable(void)
+{
+ /* Set the global I2C clock on */
+ writel(readl(CKEN) | CKEN14_I2C, CKEN);
+}
+
+void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
+
+void reset_cpu(void)
+{
+ uint32_t tmp;
+
+ setbits_le32(OWER, OWER_WME);
+
+ tmp = readl(OSCR);
+ tmp += 0x1000;
+ writel(tmp, OSMR3);
+ writel(MDREFR_SLFRSH, MDREFR);
+
+ for (;;)
+ ;
+}
+
+void enable_caches(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+ icache_enable();
+#endif
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+ dcache_enable();
+#endif
+}
diff --git a/roms/u-boot/arch/arm/cpu/pxa/relocate.S b/roms/u-boot/arch/arm/cpu/pxa/relocate.S
new file mode 100644
index 000000000..778cd45e9
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/relocate.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * relocate - PXA270 vector relocation
+ *
+ * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The PXA SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+ .section .text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+ bx lr
+
+ENDPROC(relocate_vectors)
diff --git a/roms/u-boot/arch/arm/cpu/pxa/start.S b/roms/u-boot/arch/arm/cpu/pxa/start.S
new file mode 100644
index 000000000..575abac09
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/start.S
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * armboot - Startup Code for XScale CPU-core
+ *
+ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
+ * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
+ * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
+ * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
+ * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ * Copyright (C) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+ .globl reset
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ bl cpu_init_crit
+#endif
+
+#ifdef CONFIG_CPU_PXA25X
+ bl lock_cache_for_stack
+#endif
+#ifdef CONFIG_CPU_PXA27X
+ /*
+ * enable clock for SRAM
+ */
+ ldr r0,=CKEN
+ ldr r1,[r0]
+ orr r1,r1,#(1 << 20)
+ str r1,[r0]
+#endif
+ bl _main
+
+/*------------------------------------------------------------------------------*/
+
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+#ifdef CONFIG_CPU_PXA25X
+ /*
+ * Unlock (actually, disable) the cache now that board_init_f
+ * is done. We could do this earlier but we would need to add
+ * a new C runtime hook, whereas c_runtime_cpu_setup already
+ * exists.
+ * As this routine is just a call to cpu_init_crit, let us
+ * tail-optimize and do a simple branch here.
+ */
+ b cpu_init_crit
+#else
+ bx lr
+#endif
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
+cpu_init_crit:
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 1 (A) Align
+ mcr p15, 0, r0, c1, c0, 0
+
+ mov pc, lr /* back to my caller */
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
+
+/*
+ * Enable MMU to use DCache as DRAM.
+ *
+ * This is useful on PXA25x and PXA26x in early bootstages, where there is no
+ * other possible memory available to hold stack.
+ */
+#ifdef CONFIG_CPU_PXA25X
+.macro CPWAIT reg
+ mrc p15, 0, \reg, c2, c0, 0
+ mov \reg, \reg
+ sub pc, pc, #4
+.endm
+lock_cache_for_stack:
+ /* Domain access -- enable for all CPs */
+ ldr r0, =0x0000ffff
+ mcr p15, 0, r0, c3, c0, 0
+
+ /* Point TTBR to MMU table */
+ ldr r0, =mmutable
+ mcr p15, 0, r0, c2, c0, 0
+
+ /* Kick in MMU, ICache, DCache, BTB */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, #0x1b00
+ bic r0, #0x0087
+ orr r0, #0x1800
+ orr r0, #0x0005
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
+
+ /* Unlock Icache, Dcache */
+ mcr p15, 0, r0, c9, c1, 1
+ mcr p15, 0, r0, c9, c2, 1
+
+ /* Flush Icache, Dcache, BTB */
+ mcr p15, 0, r0, c7, c7, 0
+
+ /* Unlock I-TLB, D-TLB */
+ mcr p15, 0, r0, c10, c4, 1
+ mcr p15, 0, r0, c10, c8, 1
+
+ /* Flush TLB */
+ mcr p15, 0, r0, c8, c7, 0
+
+ /* Allocate 4096 bytes of Dcache as RAM */
+
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+
+ mov r4, #0x00
+ mov r5, #0x00
+ mov r2, #0x01
+ mcr p15, 0, r0, c9, c2, 0
+ CPWAIT r0
+
+ /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+ mov r0, #128
+ ldr r1, =0xfffff000
+
+alloc:
+ mcr p15, 0, r1, c7, c2, 5
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ subs r0, #0x01
+ bne alloc
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ mov r2, #0x00
+ mcr p15, 0, r2, c9, c2, 0
+ CPWAIT r0
+
+ mov pc, lr
+
+.section .mmutable, "a"
+mmutable:
+ .align 14
+ /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
+ .set __base, 0
+ .rept 0xfff
+ .word (__base << 20) | 0xc12
+ .set __base, __base + 1
+ .endr
+
+ /* 0xfff00000 : 1:1, cached mapping */
+ .word (0xfff << 20) | 0x1c1e
+#endif /* CONFIG_CPU_PXA25X */
diff --git a/roms/u-boot/arch/arm/cpu/pxa/timer.c b/roms/u-boot/arch/arm/cpu/pxa/timer.c
new file mode 100644
index 000000000..8e9d61044
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/timer.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell PXA2xx/3xx timer driver
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+
+int timer_init(void)
+{
+ writel(0, CONFIG_SYS_TIMER_COUNTER);
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/cpu/pxa/usb.c b/roms/u-boot/arch/arm/cpu/pxa/usb.c
new file mode 100644
index 000000000..13e010d91
--- /dev/null
+++ b/roms/u-boot/arch/arm/cpu/pxa/usb.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
+ */
+
+#include <common.h>
+#include <linux/delay.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <usb.h>
+
+int usb_cpu_init(void)
+{
+#if defined(CONFIG_CPU_MONAHANS)
+ /* Enable USB host clock. */
+ writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
+ udelay(100);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+ /* Enable USB host clock. */
+ writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+#endif
+
+#if defined(CONFIG_CPU_MONAHANS)
+ /* Configure Port 2 for Host (USB Client Registers) */
+ writel(0x3000c, UP2OCR);
+#endif
+
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ mdelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ udelay(1);
+
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+ writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+ writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
+#endif
+ writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
+
+ return 0;
+}
+
+int usb_cpu_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
+ udelay(10);
+
+#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+ writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+ writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
+#endif
+ writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
+
+#if defined(CONFIG_CPU_MONAHANS)
+ /* Disable USB host clock. */
+ writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+ udelay(100);
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+ /* Disable USB host clock. */
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+#endif
+
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
+
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */