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-rw-r--r--roms/u-boot/arch/arm/dts/fsl-lx2160a.dtsi573
1 files changed, 573 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/dts/fsl-lx2160a.dtsi b/roms/u-boot/arch/arm/dts/fsl-lx2160a.dtsi
new file mode 100644
index 000000000..a6f0e9bc5
--- /dev/null
+++ b/roms/u-boot/arch/arm/dts/fsl-lx2160a.dtsi
@@ -0,0 +1,573 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP lx2160a SOC common device tree source
+ *
+ * Copyright 2018-2020 NXP
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "fsl,lx2160a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ /* DRAM space - 1, size : 2 GB DRAM */
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,ls2080a-clockgen";
+ reg = <0 0x1300000 0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06200000 0 0x100000>; /* GICR */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <1 9 0x4>;
+ };
+
+ gic_lpi_base: syscon@0x80000000 {
+ compatible = "gic-lpi-base";
+ reg = <0x0 0x80000000 0x0 0x200000>;
+ max-gic-redistributors = <16>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+ <1 14 0x8>, /* Physical NS PPI, active-low */
+ <1 11 0x8>, /* Virtual PPI, active-low */
+ <1 10 0x8>; /* Hypervisor PPI, active-low */
+ };
+
+ fspi: flexspi@20c0000 {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "fspi_en", "fspi";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 4>;
+ scl-gpio = <&gpio2 15 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 4>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <0 74 4>;
+ scl-gpio = <&gpio2 16 0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <0 74 4>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <0 75 4>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <0 75 4>;
+ status = "disabled";
+ };
+
+ uart0: serial@21c0000 {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21c0000 0x0 0x1000>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ uart1: serial@21d0000 {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21d0000 0x0 0x1000>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ uart2: serial@21e0000 {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21e0000 0x0 0x1000>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ uart3: serial@21f0000 {
+ compatible = "arm,pl011";
+ reg = <0x0 0x21f0000 0x0 0x1000>;
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 26 0x4>; /* Level high type */
+ num-cs = <6>;
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 26 0x4>; /* Level high type */
+ num-cs = <6>;
+ };
+
+ dspi2: dspi@2120000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2120000 0x0 0x10000>;
+ interrupts = <0 241 0x4>; /* Level high type */
+ num-cs = <6>;
+ };
+
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 36 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 37 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 37 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog@23a0000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x23a0000 0 0x1000>,
+ <0x0 0x2390000 0 0x1000>;
+ timeout-sec = <30>;
+ };
+
+ usb0: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <0 63 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ non-removable;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ sata0: sata@3200000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 133 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata1: sata@3210000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3210000 0x0 0x10000>;
+ interrupts = <0 136 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata2: sata@3220000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3220000 0x0 0x10000>;
+ interrupts = <0 97 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata3: sata@3230000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3230000 0x0 0x10000>;
+ interrupts = <0 100 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ pcie1: pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03480000 0x0 0x40000 /* LUT registers */
+ 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
+ 0x80 0x00000000 0x0 0x2000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie2: pcie@3500000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03580000 0x0 0x40000 /* LUT registers */
+ 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
+ 0x88 0x00000000 0x0 0x2000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie3: pcie@3600000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03680000 0x0 0x40000 /* LUT registers */
+ 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
+ 0x90 0x00000000 0x0 0x2000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie4: pcie@3700000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03780000 0x0 0x40000 /* LUT registers */
+ 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
+ 0x98 0x00000000 0x0 0x2000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie5: pcie@3800000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03880000 0x0 0x40000 /* LUT registers */
+ 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
+ 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie6: pcie@3900000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
+ 0x00 0x03980000 0x0 0x40000 /* LUT registers */
+ 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
+ 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
+ reg-names = "ccsr", "lut", "pf_ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ fsl_mc: fsl-mc@80c000000 {
+ compatible = "fsl,qoriq-mc", "simple-mfd";
+ reg = <0x00000008 0x0c000000 0 0x40>,
+ <0x00000000 0x08340000 0 0x40000>;
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+ /*
+ * Region type 0x0 - MC portals
+ * Region type 0x1 - QBMAN portals
+ */
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+ dpmacs {
+ compatible = "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpmac1: dpmac@1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ dpmac2: dpmac@2 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ dpmac3: dpmac@3 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ dpmac4: dpmac@4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ dpmac5: dpmac@5 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ dpmac6: dpmac@6 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x6>;
+ status = "disabled";
+ };
+
+ dpmac7: dpmac@7 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x7>;
+ status = "disabled";
+ };
+
+ dpmac8: dpmac@8 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x8>;
+ status = "disabled";
+ };
+
+ dpmac9: dpmac@9 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x9>;
+ status = "disabled";
+ };
+
+ dpmac10: dpmac@a {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xa>;
+ status = "disabled";
+ };
+
+ dpmac11: dpmac@b {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xb>;
+ status = "disabled";
+ };
+
+ dpmac12: dpmac@c {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xc>;
+ status = "disabled";
+ };
+
+ dpmac13: dpmac@d {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xd>;
+ status = "disabled";
+ };
+
+ dpmac14: dpmac@e {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xe>;
+ status = "disabled";
+ };
+
+ dpmac15: dpmac@f {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xf>;
+ status = "disabled";
+ };
+
+ dpmac16: dpmac@10 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x10>;
+ status = "disabled";
+ };
+
+ dpmac17: dpmac@11 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x11>;
+ status = "disabled";
+ };
+
+ dpmac18: dpmac@12 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x12>;
+ status = "disabled";
+ };
+ };
+ };
+
+ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
+ emdio1: mdio@8b96000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8b96000 0x0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
+ emdio2: mdio@8b97000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8b97000 0x0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};