diff options
Diffstat (limited to 'roms/u-boot/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi')
| -rw-r--r-- | roms/u-boot/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/roms/u-boot/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi new file mode 100644 index 000000000..d1e4a8567 --- /dev/null +++ b/roms/u-boot/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17 + * + * Some assumptions are made: + * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) + * + * Copyright 2020-2021 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy2>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy3>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; + + inphi_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x2>; + }; + + inphi_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x3>; + }; +}; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; |