diff options
Diffstat (limited to 'roms/u-boot/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi')
-rw-r--r-- | roms/u-boot/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/roms/u-boot/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi new file mode 100644 index 000000000..264fb7adf --- /dev/null +++ b/roms/u-boot/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + */ + +#include "rk3368-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = &emmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = <DMC_MSCH_CBRD>; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = <DDR3_1600K>; + + status = "okay"; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&sgrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&emmc { + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; + u-boot,dm-pre-reloc; +}; + +&timer0 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; + status = "okay"; +}; |