1 files changed, 110 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/roms/u-boot/arch/arm/dts/socfpga_cyclone5_sr1500.dts
new file mode 100644
index 000000000..bb29da6d6
--- /dev/null
+++ b/roms/u-boot/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
+
+/ {
+	model = "SoCFPGA Cyclone V SR1500";
+	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		/*
+		 * This allows the ethaddr uboot environment variable
+		 * contents to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&porta {
+	bank-name = "porta";
+};
+
+&portb {
+	bank-name = "portb";
+};
+
+&portc {
+	bank-name = "portc";
+};
+
+&i2c0 {
+	status = "okay";
+	speed-mode = <0>;
+};
+
+&i2c1 {
+	status = "okay";
+	speed-mode = <0>;
+};
+
+&mmc0 {
+	status = "okay";
+	bus-width = <8>;
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	flash0: n25q00@0 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00", "jedec,spi-nor";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <100000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+	};
+};