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Diffstat (limited to 'roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h')
-rw-r--r--roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
new file mode 100644
index 000000000..5cd6553d0
--- /dev/null
+++ b/roms/u-boot/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#ifndef __STM32_PWR_H_
+#define __STM32_PWR_H_
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN BIT(16)
+#define PWR_CR1_ODSWEN BIT(17)
+#define PWR_CSR1_ODRDY BIT(16)
+#define PWR_CSR1_ODSWRDY BIT(17)
+
+struct stm32_pwr_regs {
+ u32 cr1; /* power control register 1 */
+ u32 csr1; /* power control/status register 2 */
+ u32 cr2; /* power control register 2 */
+ u32 csr2; /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */