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-rw-r--r--roms/u-boot/arch/arm/mach-aspeed/ast2500/Kconfig16
-rw-r--r--roms/u-boot/arch/arm/mach-aspeed/ast2500/Makefile3
-rw-r--r--roms/u-boot/arch/arm/mach-aspeed/ast2500/board_common.c60
-rw-r--r--roms/u-boot/arch/arm/mach-aspeed/ast2500/clk_ast2500.c45
-rw-r--r--roms/u-boot/arch/arm/mach-aspeed/ast2500/lowlevel_init.S41
5 files changed, 165 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-aspeed/ast2500/Kconfig b/roms/u-boot/arch/arm/mach-aspeed/ast2500/Kconfig
new file mode 100644
index 000000000..b815153bf
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-aspeed/ast2500/Kconfig
@@ -0,0 +1,16 @@
+if ASPEED_AST2500
+
+config SYS_CPU
+ default "arm1176"
+
+config TARGET_EVB_AST2500
+ bool "Evb-AST2500"
+ help
+ Evb-AST2500 is Aspeed evaluation board for AST2500 chip.
+ It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
+ 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot,
+ 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs.
+
+source "board/aspeed/evb_ast2500/Kconfig"
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-aspeed/ast2500/Makefile b/roms/u-boot/arch/arm/mach-aspeed/ast2500/Makefile
new file mode 100644
index 000000000..db70432ad
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-aspeed/ast2500/Makefile
@@ -0,0 +1,3 @@
+obj-y += lowlevel_init.o
+obj-y += board_common.o
+obj-y += clk_ast2500.o
diff --git a/roms/u-boot/arch/arm/mach-aspeed/ast2500/board_common.c b/roms/u-boot/arch/arm/mach-aspeed/ast2500/board_common.c
new file mode 100644
index 000000000..aca200223
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-aspeed/ast2500/board_common.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <timer.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+#include <dm/uclass.h>
+
+/*
+ * Second Watchdog Timer by default is configured
+ * to trigger secondary boot source.
+ */
+#define AST_2ND_BOOT_WDT 1
+
+/*
+ * Third Watchdog Timer by default is configured
+ * to toggle Flash address mode switch before reset.
+ */
+#define AST_FLASH_ADDR_DETECT_WDT 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct udevice *dev;
+ struct ram_info ram;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM FAIL1\r\n");
+ return ret;
+ }
+
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("DRAM FAIL2\r\n");
+ return ret;
+ }
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/roms/u-boot/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
new file mode 100644
index 000000000..02bd3f67c
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Google, Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+#include <linux/err.h>
+
+int ast_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(aspeed_ast2500_scu), devp);
+}
+
+void *ast_get_scu(void)
+{
+ struct ast2500_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = ast_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->scu;
+}
+
+void ast_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+void ast_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
diff --git a/roms/u-boot/arch/arm/mach-aspeed/ast2500/lowlevel_init.S b/roms/u-boot/arch/arm/mach-aspeed/ast2500/lowlevel_init.S
new file mode 100644
index 000000000..9ec3dd46b
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-aspeed/ast2500/lowlevel_init.S
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <asm/arch/scu_ast2500.h>
+
+/* registers for low level init */
+#define SCU_PROT_KEY 0x1e6e2000
+#define SCU_VGA_HANDSHAKE 0x1e6e2040
+#define SCU_HW_STRAP 0x1e6e2070
+#define SCU_HW_STRAP_CLR 0x1e6e207c
+#define WDT3_CTRL 0x1e78504c
+
+.global lowlevel_init
+lowlevel_init:
+
+ /* unlock SCU */
+ ldr r0, =SCU_PROT_KEY
+ ldr r1, =SCU_UNLOCK_VALUE
+ str r1, [r0]
+
+ /* set BMC FW as DRAM initializer */
+ ldr r0, =SCU_VGA_HANDSHAKE
+ ldr r1, [r0]
+ orr r1, #0x80
+ str r1, [r0]
+
+ /* set PERST# as LPC reset source if eSPI mode is enabled*/
+ ldr r0, =SCU_HW_STRAP
+ ldr r1, [r0]
+ tst r1, #(0x1 << 25)
+ ldrne r0, =SCU_HW_STRAP_CLR
+ movne r1, #(0x1 << 14)
+ strne r1, [r0]
+
+ /* disable WDT3 for SPI 3/4 bytes auto-detection */
+ ldr r0, =WDT3_CTRL
+ mov r1, #0x0
+ str r1, [r0]
+
+ mov pc, lr