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-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/Kconfig110
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/Makefile7
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/clock.c1139
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/clock_slice.c756
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/ddr.c230
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/psci-mx7.c690
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/psci-suspend.S67
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/snvs.c21
-rw-r--r--roms/u-boot/arch/arm/mach-imx/mx7/soc.c438
9 files changed, 3458 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/Kconfig b/roms/u-boot/arch/arm/mach-imx/mx7/Kconfig
new file mode 100644
index 000000000..adedc0116
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/Kconfig
@@ -0,0 +1,110 @@
+if ARCH_MX7
+
+config MX7
+ bool
+ default y
+ select ARCH_SUPPORT_PSCI
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ROM_UNIFIED_SECTIONS
+ select SYSCOUNTER_TIMER
+ imply CMD_FUSE
+
+config MX7D
+ bool
+ select HAS_CAAM
+ select ROM_UNIFIED_SECTIONS
+ imply CMD_FUSE
+
+config SYS_TEXT_BASE
+ default 0x87800000
+
+config SPL_TEXT_BASE
+ depends on SPL
+ default 0x00912000
+
+choice
+ prompt "MX7 board select"
+ optional
+
+config TARGET_CL_SOM_IMX7
+ bool "CL-SOM-iMX7"
+ select DM
+ select DM_THERMAL
+ select MX7D
+ select SUPPORT_SPL
+ imply CMD_DM
+
+config TARGET_IMX7_CM
+ bool "Ronetix iMX7-CM"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX7D
+ select SUPPORT_SPL
+ imply CMD_DM
+
+config TARGET_MEERKAT96
+ bool "NovTech Meerkat96 board"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+ select MX7D
+ imply CMD_DM
+
+config TARGET_MX7DSABRESD
+ bool "mx7dsabresd"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX7D
+ imply CMD_DM
+
+config TARGET_PICO_IMX7D
+ bool "pico-imx7d"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX7D
+ select SUPPORT_SPL
+ imply CMD_DM
+
+config TARGET_SMEGW01
+ bool "smegw01"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX7D
+ imply CMD_DM
+
+config TARGET_WARP7
+ bool "warp7"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX7D
+ imply CMD_DM
+
+config TARGET_COLIBRI_IMX7
+ bool "Support Colibri iMX7S/iMX7D modules"
+ select DM
+ select DM_SERIAL
+ select DM_THERMAL
+ imply CMD_DM
+
+endchoice
+
+config SYS_SOC
+ default "mx7"
+
+source "board/compulab/cl-som-imx7/Kconfig"
+source "board/ronetix/imx7-cm/Kconfig"
+source "board/freescale/mx7dsabresd/Kconfig"
+source "board/novtech/meerkat96/Kconfig"
+source "board/storopack/smegw01/Kconfig"
+source "board/technexion/pico-imx7d/Kconfig"
+source "board/toradex/colibri_imx7/Kconfig"
+source "board/warp7/Kconfig"
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/Makefile b/roms/u-boot/arch/arm/mach-imx/mx7/Makefile
new file mode 100644
index 000000000..f1436e2d0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+
+obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o
+obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o psci-suspend.o
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/clock.c b/roms/u-boot/arch/arm/mach-imx/mx7/clock.c
new file mode 100644
index 000000000..304a03031
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/clock.c
@@ -0,0 +1,1139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
+#include <div64.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+ return 0;
+}
+
+u32 get_ahb_clk(void)
+{
+ return get_root_clk(AHB_CLK_ROOT);
+}
+
+static u32 get_ipg_clk(void)
+{
+ /*
+ * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
+ * each other.
+ */
+ return get_ahb_clk() / 2;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_root_clk(UART_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, enable);
+}
+
+void enable_thermal_clk(void)
+{
+ enable_ocotp_clk(1);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 target;
+
+ if (enable) {
+ /* disable the clock gate first */
+ clock_enable(CCGR_USB_HSIC, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON |
+ USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(USB_HSIC_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USB_CTRL, 1);
+ clock_enable(CCGR_USB_HSIC, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ } else {
+ clock_enable(CCGR_USB_CTRL, 0);
+ clock_enable(CCGR_USB_HSIC, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ }
+}
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 reg, div_sel;
+ u32 num, denom;
+
+ /*
+ * Alought there are four choices for the bypass src,
+ * we choose OSC_24M which is the default set in ROM.
+ */
+ switch (pll) {
+ case PLL_CORE:
+ reg = readl(&ccm_anatop->pll_arm);
+
+ if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
+
+ return (infreq * div_sel) / 2;
+
+ case PLL_SYS:
+ reg = readl(&ccm_anatop->pll_480);
+
+ if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
+ return MXC_HCLK;
+
+ if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
+ return 480000000u;
+ else
+ return 528000000u;
+
+ case PLL_ENET:
+ reg = readl(&ccm_anatop->pll_enet);
+
+ if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
+ return MXC_HCLK;
+
+ return 1000000000u;
+
+ case PLL_DDR:
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
+ return 0;
+
+ num = ccm_anatop->pll_ddr_num;
+ denom = ccm_anatop->pll_ddr_denom;
+
+ if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
+
+ return infreq * (div_sel + num / denom);
+
+ case PLL_USB:
+ return 480000000u;
+
+ default:
+ printf("Unsupported pll clocks %d\n", pll);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_sys_derive(int derive)
+{
+ u32 freq, div, frac;
+ u32 reg;
+
+ div = 1;
+ reg = readl(&ccm_anatop->pll_480);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+ switch (derive) {
+ case PLL_SYS_MAIN_480M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
+ return 0;
+ else
+ return freq;
+ case PLL_SYS_MAIN_240M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 2;
+ case PLL_SYS_MAIN_120M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 4;
+ case PLL_SYS_PFD0_392M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD0_196M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD1_332M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD1_166M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD2_270M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD2_135M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD3_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD4_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD5_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD6_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD7_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
+ break;
+ default:
+ printf("Error derived pll_sys clock %d\n", derive);
+ return 0;
+ }
+
+ return ((freq / frac) * 18) / div;
+}
+
+static u32 mxc_get_pll_enet_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_enet);
+
+ switch (derive) {
+ case PLL_ENET_MAIN_500M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
+ return freq / 2;
+ break;
+ case PLL_ENET_MAIN_250M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
+ return freq / 4;
+ break;
+ case PLL_ENET_MAIN_125M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
+ return freq / 8;
+ break;
+ case PLL_ENET_MAIN_100M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
+ return freq / 10;
+ break;
+ case PLL_ENET_MAIN_50M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
+ return freq / 20;
+ break;
+ case PLL_ENET_MAIN_40M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
+ return freq / 25;
+ break;
+ case PLL_ENET_MAIN_25M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
+ return freq / 40;
+ break;
+ default:
+ printf("Error derived pll_enet clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_ddr_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_DDR, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ switch (derive) {
+ case PLL_DRAM_MAIN_1066M_CLK:
+ return freq;
+ case PLL_DRAM_MAIN_533M_CLK:
+ if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
+ return freq / 2;
+ break;
+ default:
+ printf("Error derived pll_ddr clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
+{
+ switch (pll) {
+ case PLL_SYS:
+ return mxc_get_pll_sys_derive(derive);
+ case PLL_ENET:
+ return mxc_get_pll_enet_derive(derive);
+ case PLL_DDR:
+ return mxc_get_pll_ddr_derive(derive);
+ default:
+ printf("Error pll.\n");
+ return 0;
+ }
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_24M_CLK:
+ return 24000000u;
+ case PLL_ARM_MAIN_800M_CLK:
+ return decode_pll(PLL_CORE, MXC_HCLK);
+
+ case PLL_SYS_MAIN_480M_CLK:
+ case PLL_SYS_MAIN_240M_CLK:
+ case PLL_SYS_MAIN_120M_CLK:
+ case PLL_SYS_PFD0_392M_CLK:
+ case PLL_SYS_PFD0_196M_CLK:
+ case PLL_SYS_PFD1_332M_CLK:
+ case PLL_SYS_PFD1_166M_CLK:
+ case PLL_SYS_PFD2_270M_CLK:
+ case PLL_SYS_PFD2_135M_CLK:
+ case PLL_SYS_PFD3_CLK:
+ case PLL_SYS_PFD4_CLK:
+ case PLL_SYS_PFD5_CLK:
+ case PLL_SYS_PFD6_CLK:
+ case PLL_SYS_PFD7_CLK:
+ return mxc_get_pll_derive(PLL_SYS, root_src);
+
+ case PLL_ENET_MAIN_500M_CLK:
+ case PLL_ENET_MAIN_250M_CLK:
+ case PLL_ENET_MAIN_125M_CLK:
+ case PLL_ENET_MAIN_100M_CLK:
+ case PLL_ENET_MAIN_50M_CLK:
+ case PLL_ENET_MAIN_40M_CLK:
+ case PLL_ENET_MAIN_25M_CLK:
+ return mxc_get_pll_derive(PLL_ENET, root_src);
+
+ case PLL_DRAM_MAIN_1066M_CLK:
+ case PLL_DRAM_MAIN_533M_CLK:
+ return mxc_get_pll_derive(PLL_DDR, root_src);
+
+ case PLL_AUDIO_MAIN_CLK:
+ return decode_pll(PLL_AUDIO, MXC_HCLK);
+ case PLL_VIDEO_MAIN_CLK:
+ return decode_pll(PLL_VIDEO, MXC_HCLK);
+
+ case PLL_USB_MAIN_480M_CLK:
+ return decode_pll(PLL_USB, MXC_HCLK);
+
+ case REF_1M_CLK:
+ return 1000000;
+ case OSC_32K_CLK:
+ return MXC_CLK32;
+
+ case EXT_CLK_1:
+ case EXT_CLK_2:
+ case EXT_CLK_3:
+ case EXT_CLK_4:
+ printf("No EXT CLK supported??\n");
+ break;
+ };
+
+ return 0;
+}
+
+u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, auto_podf, root_src_clk;
+ int auto_en;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
+ return 0;
+
+ if (auto_en == 0)
+ auto_podf = 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ /*
+ * bypass clk is ignored.
+ */
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
+ (auto_podf + 1);
+}
+
+static u32 get_ddrc_clk(void)
+{
+ u32 reg, freq;
+ enum root_post_div post_div;
+
+ reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
+ if (reg & CLK_ROOT_MUX_MASK)
+ /* DRAM_ALT_CLK_ROOT */
+ freq = get_root_clk(DRAM_ALT_CLK_ROOT);
+ else
+ /* PLL_DRAM_MAIN_1066M_CLK */
+ freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
+
+ post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
+
+ return freq / (post_div + 1) / 2;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_root_clk(ARM_A7_CLK_ROOT);
+ case MXC_AXI_CLK:
+ return get_root_clk(MAIN_AXI_CLK_ROOT);
+ case MXC_AHB_CLK:
+ return get_root_clk(AHB_CLK_ROOT);
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
+ case MXC_DDR_CLK:
+ return get_ddrc_clk();
+ case MXC_ESDHC_CLK:
+ return get_root_clk(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return get_root_clk(USDHC3_CLK_ROOT);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 target;
+
+ if (i2c_num >= 4)
+ return -EINVAL;
+
+ if (enable) {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+
+ /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
+
+ target = CLK_ROOT_ON |
+ I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
+
+ clock_enable(CCGR_I2C1 + i2c_num, 1);
+ } else {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+ }
+
+ return 0;
+}
+#endif
+
+static void init_clk_esdhc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_USDHC1, 0);
+ clock_enable(CCGR_USDHC2, 0);
+ clock_enable(CCGR_USDHC3, 0);
+
+ /* 196: 392/2 */
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC3_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USDHC1, 1);
+ clock_enable(CCGR_USDHC2, 1);
+ clock_enable(CCGR_USDHC3, 1);
+}
+
+static void init_clk_uart(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_UART1, 0);
+ clock_enable(CCGR_UART2, 0);
+ clock_enable(CCGR_UART3, 0);
+ clock_enable(CCGR_UART4, 0);
+ clock_enable(CCGR_UART5, 0);
+ clock_enable(CCGR_UART6, 0);
+ clock_enable(CCGR_UART7, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART4_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART5_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART6_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART7_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_UART1, 1);
+ clock_enable(CCGR_UART2, 1);
+ clock_enable(CCGR_UART3, 1);
+ clock_enable(CCGR_UART4, 1);
+ clock_enable(CCGR_UART5, 1);
+ clock_enable(CCGR_UART6, 1);
+ clock_enable(CCGR_UART7, 1);
+}
+
+static void init_clk_weim(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WEIM, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(EIM_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WEIM, 1);
+}
+
+static void init_clk_ecspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_ECSPI1, 0);
+ clock_enable(CCGR_ECSPI2, 0);
+ clock_enable(CCGR_ECSPI3, 0);
+ clock_enable(CCGR_ECSPI4, 0);
+
+ /* 60Mhz: 240/4 */
+ target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI4_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_ECSPI1, 1);
+ clock_enable(CCGR_ECSPI2, 1);
+ clock_enable(CCGR_ECSPI3, 1);
+ clock_enable(CCGR_ECSPI4, 1);
+}
+
+static void init_clk_wdog(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_enable(CCGR_WDOG4, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(WDOG_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+ clock_enable(CCGR_WDOG4, 1);
+}
+
+#ifdef CONFIG_MXC_EPDC
+static void init_clk_epdc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_EPDC, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
+ clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_EPDC, 1);
+}
+#endif
+
+static int enable_pll_enet(void)
+{
+ u32 reg;
+ s32 timeout = 100000;
+
+ reg = readl(&ccm_anatop->pll_enet);
+ /* If pll_enet powered up, no need to set it again */
+ if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
+ reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
+ writel(reg, &ccm_anatop->pll_enet);
+
+ while (timeout--) {
+ if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
+ break;
+ }
+
+ if (timeout <= 0) {
+ /* If timeout, we set pwdn for pll_enet. */
+ reg |= ANADIG_PLL_ENET_PWDN_MASK;
+ return -ETIME;
+ }
+ }
+
+ /* Clear bypass */
+ writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
+
+ writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
+ &ccm_anatop->pll_enet_set);
+
+ return 0;
+}
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+ u32 post_div)
+{
+ u32 reg = 0;
+ ulong start;
+
+ debug("pll5 div = %d, num = %d, denom = %d\n",
+ pll_div, pll_num, pll_denom);
+
+ /* Power up PLL5 video and disable its output */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
+ &ccm_anatop->pll_video_clr);
+
+ /* Set div, num and denom */
+ switch (post_div) {
+ case 1:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 2:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 3:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 4:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 0:
+ default:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ }
+
+ writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
+ &ccm_anatop->pll_video_num);
+
+ writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
+ &ccm_anatop->pll_video_denom);
+
+ /* Wait PLL5 lock */
+ start = get_timer(0); /* Get current timestamp */
+
+ do {
+ reg = readl(&ccm_anatop->pll_video);
+ if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
+ /* Enable PLL out */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
+ &ccm_anatop->pll_video_set);
+ return 0;
+ }
+ } while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+ printf("Lock PLL5 timeout\n");
+
+ return 1;
+}
+
+int set_clk_qspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_QSPI, 0);
+
+ /* 49M: 392/2/4 */
+ target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(QSPI_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+int set_clk_nand(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_RAWNAND, 0);
+
+ enable_pll_enet();
+ /* 100: 500/5 */
+ target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
+ clock_set_target_val(NAND_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_RAWNAND, 1);
+
+ return 0;
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
+{
+ u32 hck = MXC_HCLK/1000;
+ u32 min = hck * 27;
+ u32 max = hck * 54;
+ u32 temp, best = 0;
+ u32 i, j, pred = 1, postd = 1;
+ u32 pll_div, pll_num, pll_denom, post_div = 0;
+ u32 target;
+
+ debug("mxs_set_lcdclk, freq = %d\n", freq);
+
+ clock_enable(CCGR_LCDIF, 0);
+
+ temp = (freq * 8 * 8);
+ if (temp < min) {
+ for (i = 1; i <= 4; i++) {
+ if ((temp * (1 << i)) > min) {
+ post_div = i;
+ freq = (freq * (1 << i));
+ break;
+ }
+ }
+
+ if (5 == i) {
+ printf("Fail to set rate to %u kHz", freq);
+ return;
+ }
+ }
+
+ for (i = 1; i <= 8; i++) {
+ for (j = 1; j <= 8; j++) {
+ temp = freq * i * j;
+ if (temp > max || temp < min)
+ continue;
+
+ if (best == 0 || temp < best) {
+ best = temp;
+ pred = i;
+ postd = j;
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Fail to set rate to %u kHz", freq);
+ return;
+ }
+
+ debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+ pll_div = best / hck;
+ pll_denom = 1000000;
+ pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
+ CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
+ clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
+
+ clock_enable(CCGR_LCDIF, 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ int ret;
+ u32 enet1_ref, enet2_ref;
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_ENET2, 0);
+
+ switch (type) {
+ case ENET_125MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = enable_pll_enet();
+ if (ret != 0)
+ return ret;
+
+ /* set enet axi clock 196M: 392/2 */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET1_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet2_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET2_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ target = CLK_ROOT_ON |
+ ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
+#endif
+ /* enable clock */
+ clock_enable(CCGR_ENET1, 1);
+ clock_enable(CCGR_ENET2, 1);
+
+ return 0;
+}
+#endif
+
+/* Configure PLL/PFD freq */
+void clock_init(void)
+{
+/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
+ * In u-boot, we have to:
+ * 1. Configure PFD3- PFD7 for freq we needed in u-boot
+ * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
+ * interface. The clocks for these peripherals are enabled after this intialization.
+ * 3. Other peripherals with set clock rate interface does not be set in this function.
+ */
+ u32 reg;
+
+ /*
+ * Configure PFD4 to 392M
+ * 480M * 18 / 0x16 = 392M
+ */
+ reg = readl(&ccm_anatop->pfd_480b);
+
+ reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
+ CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
+ reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
+
+ writel(reg, &ccm_anatop->pfd_480b);
+
+ init_clk_esdhc();
+ init_clk_uart();
+ init_clk_weim();
+ init_clk_ecspi();
+ init_clk_wdog();
+#ifdef CONFIG_MXC_EPDC
+ init_clk_epdc();
+#endif
+
+ enable_usboh3_clk(1);
+
+ clock_enable(CCGR_SNVS, 1);
+
+#ifdef CONFIG_NAND_MXS
+ clock_enable(CCGR_RAWNAND, 1);
+#endif
+
+ if (IS_ENABLED(CONFIG_IMX_RDC)) {
+ clock_enable(CCGR_RDC, 1);
+ clock_enable(CCGR_SEMA1, 1);
+ clock_enable(CCGR_SEMA2, 1);
+ }
+}
+
+#ifdef CONFIG_IMX_HAB
+void hab_caam_clock_enable(unsigned char enable)
+{
+ if (enable)
+ clock_enable(CCGR_CAAM, 1);
+ else
+ clock_enable(CCGR_CAAM, 0);
+}
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+void epdc_clock_enable(void)
+{
+ clock_enable(CCGR_EPDC, 1);
+}
+void epdc_clock_disable(void)
+{
+ clock_enable(CCGR_EPDC, 0);
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Dump some core clockes.
+ */
+int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 freq;
+ freq = decode_pll(PLL_CORE, MXC_HCLK);
+ printf("PLL_CORE %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+ printf("PLL_SYS %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ printf("PLL_NET %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+
+ printf("IPG %8u kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("UART %8u kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8u kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+ printf("AHB %8u kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("AXI %8u kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ printf("DDR %8u kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ printf("USDHC1 %8u kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ printf("USDHC2 %8u kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ printf("USDHC3 %8u kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
+ "display clocks",
+ ""
+);
+#endif
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/clock_slice.c b/roms/u-boot/arch/arm/mach-imx/mx7/clock_slice.c
new file mode 100644
index 000000000..dd731d949
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/clock_slice.c
@@ -0,0 +1,756 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+static struct clk_root_map root_array[] = {
+ {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
+ {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
+ PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
+ },
+ {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
+ },
+ {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
+ },
+ {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
+ },
+ {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
+ },
+ {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
+ PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
+ EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
+ },
+ {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
+ },
+ {EIM_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {NAND_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {UART1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART5_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART6_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART7_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
+ },
+ {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
+ },
+ {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {IPP_DO_CLKO1, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
+ },
+ {IPP_DO_CLKO2, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
+ },
+};
+
+/* select which entry of root_array */
+static int select(enum clk_root_index clock_id)
+{
+ int i, size;
+ struct clk_root_map *p = root_array;
+
+ size = ARRAY_SIZE(root_array);
+
+ for (i = 0; i < size; i++, p++) {
+ if (clock_id == p->entry)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int src_supported(int entry, enum clk_root_src clock_src)
+{
+ int i, size;
+ struct clk_root_map *p = &root_array[entry];
+
+ if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
+ size = 2;
+ else
+ size = 8;
+
+ for (i = 0; i < size; i++) {
+ if (p->src_mux[i] == clock_src)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+/* Set src for clock root slice. */
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
+{
+ int root_entry, src_entry;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_MUX_MASK;
+ reg |= src_entry << CLK_ROOT_MUX_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Get src of a clock root slice. */
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_MUX_MASK;
+ val >>= CLK_ROOT_MUX_SHIFT;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+ *p_clock_src = p->src_mux[val];
+
+ return 0;
+}
+
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
+{
+ int root_entry;
+ struct clk_root_map *p;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_PRE_DIV_MASK;
+ reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ *pre_div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_PRE_DIV_MASK;
+ val >>= CLK_ROOT_PRE_DIV_SHIFT;
+
+ *pre_div = val;
+
+ return 0;
+}
+
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
+{
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ if (div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_POST_DIV_MASK;
+ reg |= div << CLK_ROOT_POST_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if (clock_id == DRAM_CLK_ROOT)
+ val &= DRAM_CLK_ROOT_POST_DIV_MASK;
+ else
+ val &= CLK_ROOT_POST_DIV_MASK;
+ val >>= CLK_ROOT_POST_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+ int auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ printf("Auto postdiv not supported.!\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Each time only one filed can be changed, no use target_root_set.
+ */
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= ~CLK_ROOT_AUTO_DIV_MASK;
+ val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
+
+ if (auto_en)
+ val |= CLK_ROOT_AUTO_EN;
+ else
+ val &= ~CLK_ROOT_AUTO_EN;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+ int *auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ /*
+ * Only bus/ahb channel supports auto div.
+ * If unsupported, just set auto_en and div with 0.
+ */
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ *auto_en = 0;
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
+ *auto_en = 0;
+ else
+ *auto_en = 1;
+
+ val &= CLK_ROOT_AUTO_DIV_MASK;
+ val >>= CLK_ROOT_AUTO_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_set_target_val(enum clk_root_index clock_id, u32 val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Auto_div and auto_en is ignored, they are rarely used. */
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src)
+{
+ u32 val;
+ int root_entry, src_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if (p->type == CCM_DRAM_CHANNEL) {
+ if (post_div > CLK_ROOT_POST_DIV7) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ if (p->type == CCM_DRAM_PHYM_CHANNEL) {
+ if (post_div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
+ post_div << CLK_ROOT_POST_DIV_SHIFT |
+ src_entry << CLK_ROOT_MUX_SHIFT;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_root_enabled(enum clk_root_index clock_id)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ /*
+ * No enable bit for DRAM controller and PHY. Just return enabled.
+ */
+ if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
+ return 1;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
+}
+
+/* CCGR gate operation */
+int clock_enable(enum clk_ccgr_index index, bool enable)
+{
+ if (index >= CCGR_MAX)
+ return -EINVAL;
+
+ if (enable)
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_set);
+ else
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_clr);
+
+ return 0;
+}
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/ddr.c b/roms/u-boot/arch/arm/mach-imx/mx7/ddr.c
new file mode 100644
index 000000000..cf2556976
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/ddr.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DDR controller configuration for the i.MX7 architecture
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx7-ddr.h>
+#include <common.h>
+#include <linux/delay.h>
+
+/*
+ * Routine: mx7_dram_cfg
+ * Description: DDR controller configuration
+ *
+ * @ddrc_regs_val: DDRC registers value
+ * @ddrc_mp_val: DDRC_MP registers value
+ * @ddr_phy_regs_val: DDR_PHY registers value
+ * @calib_param: calibration parameters
+ *
+ */
+void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
+ struct ddr_phy *ddr_phy_regs_val,
+ struct mx7_calibration *calib_param)
+{
+ struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
+ struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
+ struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
+ struct ddr_phy *const ddr_phy_regs =
+ (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
+ struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+ int i;
+
+ /*
+ * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
+ * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
+ * aresetn_n = 0, presetn = 0. That means reset everything.
+ */
+ writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
+ &src_regs->ddrc_rcr);
+
+ /*
+ * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
+ * If we assume this is 30 cycles at 100 MHz (about the rate of a
+ * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
+ */
+ udelay(10);
+
+ /* De-assert DDR Controller 'preset' and DDR PHY reset */
+ clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
+
+ /* DDR controller configuration */
+ writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
+ writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
+ writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
+ writel(ddrc_regs_val->init1, &ddrc_regs->init1);
+ writel(ddrc_regs_val->init0, &ddrc_regs->init0);
+ writel(ddrc_regs_val->init3, &ddrc_regs->init3);
+ writel(ddrc_regs_val->init4, &ddrc_regs->init4);
+ writel(ddrc_regs_val->init5, &ddrc_regs->init5);
+ writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
+ writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
+ writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
+ writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
+ writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
+ writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
+ writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
+ writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
+ writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
+ writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);
+ writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
+ writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
+ writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
+ writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
+ writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
+ writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
+ writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
+ writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
+ writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
+ writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
+ writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
+ writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
+
+ /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
+ clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
+
+ /* PHY configuration */
+ writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
+ writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
+ writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
+ writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
+ writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
+ writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
+ writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
+ writel(ddr_phy_regs_val->cmd_sdll_con0 |
+ DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
+ &ddr_phy_regs->cmd_sdll_con0);
+ writel(ddr_phy_regs_val->cmd_sdll_con0 &
+ ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
+ &ddr_phy_regs->cmd_sdll_con0);
+ writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
+ writel(ddr_phy_regs_val->cmd_deskew_con0,
+ &ddr_phy_regs->cmd_deskew_con0);
+ writel(ddr_phy_regs_val->cmd_deskew_con1,
+ &ddr_phy_regs->cmd_deskew_con1);
+ writel(ddr_phy_regs_val->cmd_deskew_con2,
+ &ddr_phy_regs->cmd_deskew_con2);
+ writel(ddr_phy_regs_val->cmd_deskew_con3,
+ &ddr_phy_regs->cmd_deskew_con3);
+ writel(ddr_phy_regs_val->cmd_lvl_con0, &ddr_phy_regs->cmd_lvl_con0);
+
+ /* calibration */
+ for (i = 0; i < calib_param->num_val; i++)
+ writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
+
+ /* Wake_up DDR PHY */
+ HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
+ writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
+ IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
+ &iomuxc_gpr_regs->gpr[8]);
+ HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
+}
+
+/*
+ * Routine: imx_ddr_size
+ * Description: extract the current DRAM size from the DDRC registers
+ *
+ * @return: DRAM size
+ */
+unsigned int imx_ddr_size(void)
+{
+ struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
+ u32 reg_val, field_val;
+ int bits = 0;/* Number of address bits */
+
+ /* Count data bus width bits */
+ reg_val = readl(&ddrc_regs->mstr);
+ field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
+ bits += 2 - field_val;
+ /* Count rank address bits */
+ field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
+ if (field_val > 1)
+ bits += field_val - 1;
+ /* Count column address bits */
+ bits += 2;/* Column address 0 and 1 are fixed mapped */
+ reg_val = readl(&ddrc_regs->addrmap2);
+ field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ reg_val = readl(&ddrc_regs->addrmap3);
+ field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ reg_val = readl(&ddrc_regs->addrmap4);
+ field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
+ if (field_val <= 7)
+ bits++;
+ /* Count row address bits */
+ reg_val = readl(&ddrc_regs->addrmap5);
+ field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
+ if (field_val <= 11)
+ bits += 9;
+ field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ reg_val = readl(&ddrc_regs->addrmap6);
+ field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
+ if (field_val <= 11)
+ bits++;
+ /* Count bank bits */
+ reg_val = readl(&ddrc_regs->addrmap1);
+ field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
+ if (field_val <= 30)
+ bits++;
+ field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
+ if (field_val <= 30)
+ bits++;
+ field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
+ if (field_val <= 29)
+ bits++;
+
+ /* cap to max 2 GB */
+ if (bits > 31)
+ bits = 31;
+
+ return 1 << bits;
+}
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/psci-mx7.c b/roms/u-boot/arch/arm/mach-imx/mx7/psci-mx7.c
new file mode 100644
index 000000000..f32945ea3
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <linux/bitops.h>
+#include <common.h>
+#include <fsl_wdog.h>
+
+#define GPC_LPCR_A7_BSC 0x0
+#define GPC_LPCR_A7_AD 0x4
+#define GPC_SLPCR 0x14
+#define GPC_PGC_ACK_SEL_A7 0x24
+#define GPC_IMR1_CORE0 0x30
+#define GPC_SLOT0_CFG 0xb0
+#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
+#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
+#define GPC_PGC_C0 0x800
+#define GPC_PGC_C0 0x800
+#define GPC_PGC_C1 0x840
+#define GPC_PGC_SCU 0x880
+
+#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
+#define BM_LPCR_A7_BSC_LPM1 0xc
+#define BM_LPCR_A7_BSC_LPM0 0x3
+#define BP_LPCR_A7_BSC_LPM0 0
+#define BM_SLPCR_EN_DSM 0x80000000
+#define BM_SLPCR_RBC_EN 0x40000000
+#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
+#define BM_SLPCR_VSTBY 0x4
+#define BM_SLPCR_SBYOS 0x2
+#define BM_SLPCR_BYPASS_PMIC_READY 0x1
+#define BM_LPCR_A7_AD_L2PGE 0x10000
+#define BM_LPCR_A7_AD_EN_C1_PUP 0x800
+#define BM_LPCR_A7_AD_EN_C0_PUP 0x200
+#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10
+#define BM_LPCR_A7_AD_EN_C1_PDN 0x8
+#define BM_LPCR_A7_AD_EN_C0_PDN 0x2
+
+#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1
+#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
+
+#define BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK 0x8000
+#define BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK 0x80000000
+
+#define MAX_SLOT_NUMBER 10
+#define A7_LPM_WAIT 0x5
+#define A7_LPM_STOP 0xa
+
+#define BM_SYS_COUNTER_CNTCR_FCR1 0x200
+#define BM_SYS_COUNTER_CNTCR_FCR0 0x100
+
+#define REG_SET 0x4
+#define REG_CLR 0x8
+
+#define ANADIG_ARM_PLL 0x60
+#define ANADIG_DDR_PLL 0x70
+#define ANADIG_SYS_PLL 0xb0
+#define ANADIG_ENET_PLL 0xe0
+#define ANADIG_AUDIO_PLL 0xf0
+#define ANADIG_VIDEO_PLL 0x130
+#define BM_ANATOP_ARM_PLL_OVERRIDE BIT(20)
+#define BM_ANATOP_DDR_PLL_OVERRIDE BIT(19)
+#define BM_ANATOP_SYS_PLL_OVERRIDE (0x1ff << 17)
+#define BM_ANATOP_ENET_PLL_OVERRIDE BIT(13)
+#define BM_ANATOP_AUDIO_PLL_OVERRIDE BIT(24)
+#define BM_ANATOP_VIDEO_PLL_OVERRIDE BIT(24)
+
+#define DDRC_STAT 0x4
+#define DDRC_PWRCTL 0x30
+#define DDRC_PSTAT 0x3fc
+
+#define SRC_GPR1_MX7D 0x074
+#define SRC_GPR2_MX7D 0x078
+#define SRC_A7RCR0 0x004
+#define SRC_A7RCR1 0x008
+
+#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
+#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+
+#define SNVS_LPCR 0x38
+#define BP_SNVS_LPCR_DP_EN 0x20
+#define BP_SNVS_LPCR_TOP 0x40
+
+#define CCM_CCGR_SNVS 0x4250
+
+#define CCM_ROOT_WDOG 0xbb80
+#define CCM_CCGR_WDOG1 0x49c0
+
+#define MPIDR_AFF0 GENMASK(7, 0)
+
+#define IMX7D_PSCI_NR_CPUS 2
+#if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
+#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
+#endif
+
+#define imx_cpu_gpr_entry_offset(cpu) \
+ (SRC_BASE_ADDR + SRC_GPR1_MX7D + cpu * 8)
+#define imx_cpu_gpr_para_offset(cpu) \
+ (imx_cpu_gpr_entry_offset(cpu) + 4)
+
+#define IMX_CPU_SYNC_OFF ~0
+#define IMX_CPU_SYNC_ON 0
+
+u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = {
+ PSCI_AFFINITY_LEVEL_ON,
+ PSCI_AFFINITY_LEVEL_OFF};
+
+enum imx_gpc_slot {
+ CORE0_A7,
+ CORE1_A7,
+ SCU_A7,
+ FAST_MEGA_MIX,
+ MIPI_PHY,
+ PCIE_PHY,
+ USB_OTG1_PHY,
+ USB_OTG2_PHY,
+ USB_HSIC_PHY,
+ CORE0_M4,
+};
+
+enum mxc_cpu_pwr_mode {
+ RUN,
+ WAIT,
+ STOP,
+};
+
+extern void psci_system_resume(void);
+
+static inline void psci_set_state(int cpu, u8 state)
+{
+ psci_state[cpu] = state;
+ dsb();
+ isb();
+}
+
+static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
+{
+ writel(enable, GPC_IPS_BASE_ADDR + offset);
+}
+
+__secure void imx_gpcv2_set_core_power(int cpu, bool pdn)
+{
+ u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
+ u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0;
+ u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 :
+ BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7;
+ u32 val;
+
+ imx_gpcv2_set_m_core_pgc(true, pgc);
+
+ val = readl(GPC_IPS_BASE_ADDR + reg);
+ val |= pdn_pup_req;
+ writel(val, GPC_IPS_BASE_ADDR + reg);
+
+ while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0)
+ ;
+
+ imx_gpcv2_set_m_core_pgc(false, pgc);
+}
+
+__secure void imx_enable_cpu_ca7(int cpu, bool enable)
+{
+ u32 mask, val;
+
+ mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
+ val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
+ val = enable ? val | mask : val & ~mask;
+ writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
+}
+
+__secure void psci_arch_cpu_entry(void)
+{
+ u32 cpu = psci_get_cpu_id();
+
+ psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
+}
+
+__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep,
+ u32 context_id)
+{
+ u32 cpu = mpidr & MPIDR_AFF0;
+
+ if (mpidr & ~MPIDR_AFF0)
+ return ARM_PSCI_RET_INVAL;
+
+ if (cpu >= IMX7D_PSCI_NR_CPUS)
+ return ARM_PSCI_RET_INVAL;
+
+ if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
+ return ARM_PSCI_RET_ALREADY_ON;
+
+ if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
+ return ARM_PSCI_RET_ON_PENDING;
+
+ psci_save(cpu, ep, context_id);
+
+ writel((u32)psci_cpu_entry, imx_cpu_gpr_entry_offset(cpu));
+
+ psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
+
+ imx_gpcv2_set_core_power(cpu, true);
+ imx_enable_cpu_ca7(cpu, true);
+
+ return ARM_PSCI_RET_SUCCESS;
+}
+
+__secure s32 psci_cpu_off(void)
+{
+ int cpu;
+
+ cpu = psci_get_cpu_id();
+
+ psci_cpu_off_common();
+ psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
+
+ imx_enable_cpu_ca7(cpu, false);
+ imx_gpcv2_set_core_power(cpu, false);
+ /*
+ * We use the cpu jumping argument register to sync with
+ * psci_affinity_info() which is running on cpu0 to kill the cpu.
+ */
+ writel(IMX_CPU_SYNC_OFF, imx_cpu_gpr_para_offset(cpu));
+
+ while (1)
+ wfi();
+}
+
+__secure void psci_system_reset(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ /* make sure WDOG1 clock is enabled */
+ writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
+ writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
+ writew(WCR_WDE, &wdog->wcr);
+
+ while (1)
+ wfi();
+}
+
+__secure void psci_system_off(void)
+{
+ u32 val;
+
+ /* make sure SNVS clock is enabled */
+ writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
+
+ val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
+ val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
+ writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
+
+ while (1)
+ wfi();
+}
+
+__secure u32 psci_version(void)
+{
+ return ARM_PSCI_VER_1_0;
+}
+
+__secure s32 psci_cpu_suspend(u32 __always_unused function_id, u32 power_state,
+ u32 entry_point_address,
+ u32 context_id)
+{
+ return ARM_PSCI_RET_INVAL;
+}
+
+__secure s32 psci_affinity_info(u32 __always_unused function_id,
+ u32 target_affinity,
+ u32 lowest_affinity_level)
+{
+ u32 cpu = target_affinity & MPIDR_AFF0;
+
+ if (lowest_affinity_level > 0)
+ return ARM_PSCI_RET_INVAL;
+
+ if (target_affinity & ~MPIDR_AFF0)
+ return ARM_PSCI_RET_INVAL;
+
+ if (cpu >= IMX7D_PSCI_NR_CPUS)
+ return ARM_PSCI_RET_INVAL;
+
+ /* CPU is waiting for killed */
+ if (readl(imx_cpu_gpr_para_offset(cpu)) == IMX_CPU_SYNC_OFF) {
+ imx_enable_cpu_ca7(cpu, false);
+ imx_gpcv2_set_core_power(cpu, false);
+ writel(IMX_CPU_SYNC_ON, imx_cpu_gpr_para_offset(cpu));
+ }
+
+ return psci_state[cpu];
+}
+
+__secure u32 psci_migrate_info_type(void)
+{
+ /* Trusted OS is either not present or does not require migration */
+ return 2;
+}
+
+__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
+{
+ switch (psci_fid) {
+ case ARM_PSCI_0_2_FN_PSCI_VERSION:
+ case ARM_PSCI_0_2_FN_CPU_OFF:
+ case ARM_PSCI_0_2_FN_CPU_ON:
+ case ARM_PSCI_0_2_FN_AFFINITY_INFO:
+ case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
+ case ARM_PSCI_0_2_FN_SYSTEM_OFF:
+ case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+ case ARM_PSCI_1_0_FN_PSCI_FEATURES:
+ case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
+ return 0x0;
+ }
+ return ARM_PSCI_RET_NI;
+}
+
+static __secure void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode)
+{
+ u32 val1, val2, val3;
+
+ val1 = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
+ val2 = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /* all cores' LPM settings must be same */
+ val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1);
+ val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
+
+ val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
+ BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY);
+ /*
+ * GPC: When improper low-power sequence is used,
+ * the SoC enters low power mode before the ARM core executes WFI.
+ *
+ * Software workaround:
+ * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+ * by setting IOMUX_GPR1_IRQ.
+ * 2) Software should then unmask IRQ #32 in GPC before setting GPC
+ * Low-Power mode.
+ * 3) Software should mask IRQ #32 right after GPC Low-Power mode
+ * is set.
+ */
+ switch (mode) {
+ case RUN:
+ val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
+ val3 &= ~0x1;
+ writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
+ break;
+ case WAIT:
+ val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0;
+ val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
+ val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
+ val3 &= ~0x1;
+ writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
+ break;
+ case STOP:
+ val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0;
+ val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
+ val2 |= BM_SLPCR_EN_DSM;
+ val2 |= BM_SLPCR_SBYOS;
+ val2 |= BM_SLPCR_VSTBY;
+ val2 |= BM_SLPCR_BYPASS_PMIC_READY;
+ val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
+ val3 |= 0x1;
+ writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0);
+ break;
+ default:
+ return;
+ }
+ writel(val1, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
+ writel(val2, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+}
+
+static __secure void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn)
+{
+ u32 val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
+
+ val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE);
+ if (pdn)
+ val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE;
+
+ writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
+}
+
+static __secure void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn)
+{
+ u32 val;
+
+ val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
+ if (cpu == 0) {
+ if (pdn)
+ val |= BM_LPCR_A7_AD_EN_C0_PDN |
+ BM_LPCR_A7_AD_EN_C0_PUP;
+ else
+ val &= ~(BM_LPCR_A7_AD_EN_C0_PDN |
+ BM_LPCR_A7_AD_EN_C0_PUP);
+ }
+ if (cpu == 1) {
+ if (pdn)
+ val |= BM_LPCR_A7_AD_EN_C1_PDN |
+ BM_LPCR_A7_AD_EN_C1_PUP;
+ else
+ val &= ~(BM_LPCR_A7_AD_EN_C1_PDN |
+ BM_LPCR_A7_AD_EN_C1_PUP);
+ }
+ writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_AD);
+}
+
+static __secure void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core,
+ bool mode, bool ack)
+{
+ u32 val;
+
+ if (index >= MAX_SLOT_NUMBER)
+ return;
+
+ /* set slot */
+ writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) |
+ ((mode + 1) << (m_core * 2)),
+ GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4);
+
+ if (ack) {
+ /* set ack */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
+ /* clear dummy ack */
+ val &= ~(mode ? BM_GPC_PGC_ACK_SEL_A7_PU_DUMMY_ACK :
+ BM_GPC_PGC_ACK_SEL_A7_PD_DUMMY_ACK);
+ val |= 1 << (m_core + (mode ? 16 : 0));
+ writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
+ }
+}
+
+static __secure void imx_system_counter_resume(void)
+{
+ u32 val;
+
+ val = readl(SYSCNT_CTRL_IPS_BASE_ADDR);
+ val &= ~BM_SYS_COUNTER_CNTCR_FCR1;
+ val |= BM_SYS_COUNTER_CNTCR_FCR0;
+ writel(val, SYSCNT_CTRL_IPS_BASE_ADDR);
+}
+
+static __secure void imx_system_counter_suspend(void)
+{
+ u32 val;
+
+ val = readl(SYSCNT_CTRL_IPS_BASE_ADDR);
+ val &= ~BM_SYS_COUNTER_CNTCR_FCR0;
+ val |= BM_SYS_COUNTER_CNTCR_FCR1;
+ writel(val, SYSCNT_CTRL_IPS_BASE_ADDR);
+}
+
+static __secure void gic_resume(void)
+{
+ u32 itlinesnr, i;
+ u32 gic_dist_addr = GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET;
+
+ /* enable the GIC distributor */
+ writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
+ gic_dist_addr + GICD_CTLR);
+
+ /* TYPER[4:0] contains an encoded number of available interrupts */
+ itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
+
+ /* set all bits in the GIC group registers to one to allow access
+ * from non-secure state. The first 32 interrupts are private per
+ * CPU and will be set later when enabling the GIC for each core
+ */
+ for (i = 1; i <= itlinesnr; i++)
+ writel((u32)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+}
+
+static inline void imx_pll_suspend(void)
+{
+ writel(BM_ANATOP_ARM_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_SET);
+ writel(BM_ANATOP_DDR_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_SET);
+ writel(BM_ANATOP_SYS_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_SET);
+ writel(BM_ANATOP_ENET_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_SET);
+ writel(BM_ANATOP_AUDIO_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_SET);
+ writel(BM_ANATOP_VIDEO_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_SET);
+}
+
+static inline void imx_pll_resume(void)
+{
+ writel(BM_ANATOP_ARM_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_ARM_PLL + REG_CLR);
+ writel(BM_ANATOP_DDR_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_DDR_PLL + REG_CLR);
+ writel(BM_ANATOP_SYS_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_SYS_PLL + REG_CLR);
+ writel(BM_ANATOP_ENET_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_ENET_PLL + REG_CLR);
+ writel(BM_ANATOP_AUDIO_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_AUDIO_PLL + REG_CLR);
+ writel(BM_ANATOP_VIDEO_PLL_OVERRIDE,
+ ANATOP_BASE_ADDR + ANADIG_VIDEO_PLL + REG_CLR);
+}
+
+static inline void imx_udelay(u32 usec)
+{
+ u32 freq;
+ u64 start, end;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
+ do {
+ asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
+ if ((end - start) > usec * (freq / 1000000))
+ break;
+ } while (1);
+}
+
+static inline void imx_ddrc_enter_self_refresh(void)
+{
+ writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
+ while (readl(DDRC_IPS_BASE_ADDR + DDRC_PSTAT) & 0x10001)
+ ;
+
+ writel(0x20, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
+ while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x23) != 0x23)
+ ;
+ writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x8,
+ DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
+}
+
+static inline void imx_ddrc_exit_self_refresh(void)
+{
+ writel(0, DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
+ while ((readl(DDRC_IPS_BASE_ADDR + DDRC_STAT) & 0x3) == 0x3)
+ ;
+ writel(readl(DDRC_IPS_BASE_ADDR + DDRC_PWRCTL) | 0x1,
+ DDRC_IPS_BASE_ADDR + DDRC_PWRCTL);
+}
+
+__secure void imx_system_resume(void)
+{
+ unsigned int i, val, imr[4], entry;
+
+ entry = psci_get_target_pc(0);
+ imx_ddrc_exit_self_refresh();
+ imx_system_counter_resume();
+ imx_gpcv2_set_lpm_mode(RUN);
+ imx_gpcv2_set_cpu_power_gate_by_lpm(0, false);
+ imx_gpcv2_set_plat_power_gate_by_lpm(false);
+ imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0);
+ imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU);
+
+ /*
+ * need to mask all interrupts in GPC before
+ * operating RBC configurations
+ */
+ for (i = 0; i < 4; i++) {
+ imr[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+ }
+
+ /* configure RBC enable bit */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+ val &= ~BM_SLPCR_RBC_EN;
+ writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /* configure RBC count */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+ val &= ~BM_SLPCR_REG_BYPASS_COUNT;
+ writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /*
+ * need to delay at least 2 cycles of CKIL(32K)
+ * due to hardware design requirement, which is
+ * ~61us, here we use 65us for safe
+ */
+ imx_udelay(65);
+
+ /* restore GPC interrupt mask settings */
+ for (i = 0; i < 4; i++)
+ writel(imr[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+
+ /* initialize gic distributor */
+ gic_resume();
+ _nonsec_init();
+
+ /* save cpu0 entry */
+ psci_save(0, entry, 0);
+ psci_cpu_entry();
+}
+
+__secure void psci_system_suspend(u32 __always_unused function_id,
+ u32 ep, u32 context_id)
+{
+ u32 gpc_mask[4];
+ u32 i, val;
+
+ psci_save(0, ep, context_id);
+ /* overwrite PLL to be controlled by low power mode */
+ imx_pll_suspend();
+ imx_system_counter_suspend();
+ /* set CA7 platform to enter STOP mode */
+ imx_gpcv2_set_lpm_mode(STOP);
+ /* enable core0/scu power down/up with low power mode */
+ imx_gpcv2_set_cpu_power_gate_by_lpm(0, true);
+ imx_gpcv2_set_plat_power_gate_by_lpm(true);
+ /* time slot settings for core0 and scu */
+ imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false);
+ imx_gpcv2_set_slot_ack(1, SCU_A7, false, true);
+ imx_gpcv2_set_slot_ack(5, SCU_A7, true, false);
+ imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true);
+ imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0);
+ imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU);
+ psci_v7_flush_dcache_all();
+
+ imx_ddrc_enter_self_refresh();
+
+ /*
+ * e10133: ARM: Boot failure after A7 enters into
+ * low-power idle mode
+ *
+ * Workaround:
+ * If both CPU0/CPU1 are IDLE, the last IDLE CPU should
+ * disable GIC first, then REG_BYPASS_COUNTER is used
+ * to mask wakeup INT, and then execute “wfi” is used to
+ * bring the system into power down processing safely.
+ * The counter must be enabled as close to the “wfi” state
+ * as possible. The following equation can be used to
+ * determine the RBC counter value:
+ * RBC_COUNT * (1/32K RTC frequency) >=
+ * (46 + PDNSCR_SW + PDNSCR_SW2ISO ) ( 1/IPG_CLK frequency ).
+ */
+
+ /* disable GIC distributor */
+ writel(0, GIC400_ARB_BASE_ADDR + GIC_DIST_OFFSET);
+
+ for (i = 0; i < 4; i++)
+ gpc_mask[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+
+ /*
+ * enable the RBC bypass counter here
+ * to hold off the interrupts. RBC counter
+ * = 8 (240us). With this setting, the latency
+ * from wakeup interrupt to ARM power up
+ * is ~250uS.
+ */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+ val &= ~(0x3f << 24);
+ val |= (0x8 << 24);
+ writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /* enable the counter. */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+ val |= (1 << 30);
+ writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /* unmask all the GPC interrupts. */
+ for (i = 0; i < 4; i++)
+ writel(gpc_mask[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+
+ /*
+ * now delay for a short while (3usec)
+ * ARM is at 1GHz at this point
+ * so a short loop should be enough.
+ * this delay is required to ensure that
+ * the RBC counter can start counting in
+ * case an interrupt is already pending
+ * or in case an interrupt arrives just
+ * as ARM is about to assert DSM_request.
+ */
+ imx_udelay(3);
+
+ /* save resume entry and sp in CPU0 GPR registers */
+ asm volatile("mov %0, sp" : "=r" (val));
+ writel((u32)psci_system_resume, SRC_BASE_ADDR + SRC_GPR1_MX7D);
+ writel(val, SRC_BASE_ADDR + SRC_GPR2_MX7D);
+
+ /* sleep */
+ while (1)
+ wfi();
+}
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/psci-suspend.S b/roms/u-boot/arch/arm/mach-imx/mx7/psci-suspend.S
new file mode 100644
index 000000000..a21403f73
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/psci-suspend.S
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+ .arch_extension sec
+
+.globl v7_invalidate_l1
+v7_invalidate_l1:
+ mov r0, #0
+ mcr p15, 2, r0, c0, c0, 0
+ mrc p15, 1, r0, c0, c0, 0
+
+ movw r1, #0x7fff
+ and r2, r1, r0, lsr #13
+
+ movw r1, #0x3ff
+
+ and r3, r1, r0, lsr #3 @ NumWays - 1
+ add r2, r2, #1 @ NumSets
+
+ and r0, r0, #0x7
+ add r0, r0, #4 @ SetShift
+
+ clz r1, r3 @ WayShift
+ add r4, r3, #1 @ NumWays
+1:
+ sub r2, r2, #1 @ NumSets--
+ mov r3, r4 @ Temp = NumWays
+2:
+ subs r3, r3, #1 @ Temp--
+ mov r5, r3, lsl r1
+ mov r6, r2, lsl r0
+ orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+ mcr p15, 0, r5, c7, c6, 2
+ bgt 2b
+ cmp r2, #0
+ bgt 1b
+ dsb st
+ isb
+ mov pc, lr
+
+.globl psci_system_resume
+psci_system_resume:
+ mov sp, r0
+
+ /* invalidate L1 I-cache first */
+ mov r6, #0x0
+ mcr p15, 0, r6, c7, c5, 0
+ mcr p15, 0, r6, c7, c5, 6
+ /* enable the Icache and branch prediction */
+ mov r6, #0x1800
+ mcr p15, 0, r6, c1, c0, 0
+ isb
+
+ bl v7_invalidate_l1
+ b imx_system_resume
+
+ .popsection
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/snvs.c b/roms/u-boot/arch/arm/mach-imx/mx7/snvs.c
new file mode 100644
index 000000000..359bbbb41
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/snvs.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Linaro
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/bitops.h>
+
+#define SNVS_HPCOMR 0x04
+#define SNVS_HPCOMR_NPSWA_EN BIT(31)
+
+void init_snvs(void)
+{
+ u32 val;
+
+ /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */
+ val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR);
+ val |= SNVS_HPCOMR_NPSWA_EN;
+ writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR);
+}
diff --git a/roms/u-boot/arch/arm/mach-imx/mx7/soc.c b/roms/u-boot/arch/arm/mach-imx/mx7/soc.c
new file mode 100644
index 000000000..fda25ba66
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-imx/mx7/soc.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <env.h>
+#include <imx_thermal.h>
+#include <fsl_sec.h>
+#include <asm/setup.h>
+#include <linux/delay.h>
+
+#define IOMUXC_GPR1 0x4
+#define BM_IOMUXC_GPR1_IRQ 0x1000
+
+#define GPC_LPCR_A7_BSC 0x0
+#define GPC_LPCR_M4 0x8
+#define GPC_SLPCR 0x14
+#define GPC_PGC_ACK_SEL_A7 0x24
+#define GPC_IMR1_CORE0 0x30
+#define GPC_IMR1_CORE1 0x40
+#define GPC_IMR1_M4 0x50
+#define GPC_PGC_CPU_MAPPING 0xec
+#define GPC_PGC_C0_PUPSCR 0x804
+#define GPC_PGC_SCU_TIMING 0x890
+#define GPC_PGC_C1_PUPSCR 0x844
+
+#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
+#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
+#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
+#define BM_SLPCR_EN_DSM 0x80000000
+#define BM_SLPCR_RBC_EN 0x40000000
+#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
+#define BM_SLPCR_VSTBY 0x4
+#define BM_SLPCR_SBYOS 0x2
+#define BM_SLPCR_BYPASS_PMIC_READY 0x1
+#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
+
+#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
+#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
+
+#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
+
+#if defined(CONFIG_IMX_THERMAL)
+static const struct imx_thermal_plat imx7_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 3,
+ .fuse_word = 3,
+};
+
+U_BOOT_DRVINFO(imx7_thermal) = {
+ .name = "imx_thermal",
+ .plat = &imx7_thermal_plat,
+};
+#endif
+
+#if CONFIG_IS_ENABLED(IMX_RDC)
+/*
+ * In current design, if any peripheral was assigned to both A7 and M4,
+ * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
+ * low power mode. So M4 sleep will cause some peripherals fail to work
+ * at A7 core side. At default, all resources are in domain 0 - 3.
+ *
+ * There are 26 peripherals impacted by this IC issue:
+ * SIM2(sim2/emvsim2)
+ * SIM1(sim1/emvsim1)
+ * UART1/UART2/UART3/UART4/UART5/UART6/UART7
+ * SAI1/SAI2/SAI3
+ * WDOG1/WDOG2/WDOG3/WDOG4
+ * GPT1/GPT2/GPT3/GPT4
+ * PWM1/PWM2/PWM3/PWM4
+ * ENET1/ENET2
+ * Software Workaround:
+ * Here we setup some resources to domain 0 where M4 codes will move
+ * the M4 out of this domain. Then M4 is not able to access them any longer.
+ * This is a workaround for ic issue. So the peripherals are not shared
+ * by them. This way requires the uboot implemented the RDC driver and
+ * set the 26 IPs above to domain 0 only. M4 code will assign resource
+ * to its own domain, if it want to use the resource.
+ */
+static rdc_peri_cfg_t const resources[] = {
+ (RDC_PER_SIM1 | RDC_DOMAIN(0)),
+ (RDC_PER_SIM2 | RDC_DOMAIN(0)),
+ (RDC_PER_UART1 | RDC_DOMAIN(0)),
+ (RDC_PER_UART2 | RDC_DOMAIN(0)),
+ (RDC_PER_UART3 | RDC_DOMAIN(0)),
+ (RDC_PER_UART4 | RDC_DOMAIN(0)),
+ (RDC_PER_UART5 | RDC_DOMAIN(0)),
+ (RDC_PER_UART6 | RDC_DOMAIN(0)),
+ (RDC_PER_UART7 | RDC_DOMAIN(0)),
+ (RDC_PER_SAI1 | RDC_DOMAIN(0)),
+ (RDC_PER_SAI2 | RDC_DOMAIN(0)),
+ (RDC_PER_SAI3 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
+ (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT1 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT2 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT3 | RDC_DOMAIN(0)),
+ (RDC_PER_GPT4 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM1 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM2 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM3 | RDC_DOMAIN(0)),
+ (RDC_PER_PWM4 | RDC_DOMAIN(0)),
+ (RDC_PER_ENET1 | RDC_DOMAIN(0)),
+ (RDC_PER_ENET2 | RDC_DOMAIN(0)),
+};
+
+static void isolate_resource(void)
+{
+ imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
+}
+#endif
+
+#if defined(CONFIG_IMX_HAB)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 1,
+ .word = 3,
+};
+#endif
+
+static bool is_mx7d(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ int val;
+
+ val = readl(&fuse->tester4);
+ if (val & 1)
+ return false;
+ else
+ return true;
+}
+
+u32 get_cpu_rev(void)
+{
+ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+ u32 reg = readl(&ccm_anatop->digprog);
+ u32 type = (reg >> 16) & 0xff;
+
+ if (!is_mx7d())
+ type = MXC_CPU_MX7S;
+
+ reg &= 0xff;
+ return (type << 12) | reg;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
+static void imx_enet_mdio_fixup(void)
+{
+ struct iomuxc_gpr_base_regs *gpr_regs =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /*
+ * The management data input/output (MDIO) requires open-drain,
+ * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
+ * this feature. So to TO1.1, need to enable open drain by setting
+ * bits GPR0[8:7].
+ */
+
+ if (soc_rev() >= CHIP_REV_1_1) {
+ setbits_le32(&gpr_regs->gpr[0],
+ IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
+ }
+}
+
+static void init_cpu_basic(void)
+{
+ imx_enet_mdio_fixup();
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+}
+
+#ifdef CONFIG_IMX_BOOTAUX
+/*
+ * Table of mappings of physical mem regions in both
+ * Cortex-A7 and Cortex-M4 address spaces.
+ *
+ * For additional details check sections 2.1.2 and 2.1.3 in
+ * i.MX7Dual Applications Processor Reference Manual
+ *
+ */
+const struct rproc_att hostmap[] = {
+ /* aux core , host core, size */
+ { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
+ { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
+ { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
+ { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
+ { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
+ { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
+ { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
+ { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
+ { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
+ { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
+ { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
+ { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
+ { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
+ { /* sentinel */ }
+};
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/* enable all periherial can be accessed in nosec mode */
+static void init_csu(void)
+{
+ int i = 0;
+
+ for (i = 0; i < CSU_NUM_REGS; i++)
+ writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
+}
+
+static void imx_gpcv2_init(void)
+{
+ u32 val, i;
+
+ /*
+ * Force IOMUXC irq pending, so that the interrupt to GPC can be
+ * used to deassert dsm_request signal when the signal gets
+ * asserted unexpectedly.
+ */
+ val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
+ val |= BM_IOMUXC_GPR1_IRQ;
+ writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
+
+ /* Initially mask all interrupts */
+ for (i = 0; i < 4; i++) {
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
+ writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
+ }
+
+ /* set SCU timing */
+ writel((0x59 << 10) | 0x5B | (0x2 << 20),
+ GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
+
+ /* only external IRQs to wake up LPM and core 0/1 */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
+ val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
+ writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
+
+ /* set C0 power up timming per design requirement */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
+ val &= ~BM_GPC_PGC_CORE_PUPSCR;
+ val |= (0x1A << 7);
+ writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
+
+ /* set C1 power up timming per design requirement */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
+ val &= ~BM_GPC_PGC_CORE_PUPSCR;
+ val |= (0x1A << 7);
+ writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
+
+ /* dummy ack for time slot by default */
+ writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
+ BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
+ GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
+
+ /* mask M4 DSM trigger */
+ writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
+ BM_LPCR_M4_MASK_DSM_TRIGGER,
+ GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
+
+ /* set mega/fast mix in A7 domain */
+ writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
+
+ /* DSM related settings */
+ val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
+ val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
+ BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
+ BM_SLPCR_REG_BYPASS_COUNT);
+ val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
+ writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
+
+ /*
+ * disabling RBC need to delay at least 2 cycles of CKIL(32K)
+ * due to hardware design requirement, which is
+ * ~61us, here we use 65us for safe
+ */
+ udelay(65);
+}
+
+int arch_cpu_init(void)
+{
+ init_aips();
+
+ init_csu();
+ /* Disable PDE bit of WMCR register */
+ imx_wdog_disable_powerdown();
+
+ init_cpu_basic();
+
+#if CONFIG_IS_ENABLED(IMX_RDC)
+ isolate_resource();
+#endif
+
+ init_snvs();
+
+ imx_gpcv2_init();
+
+ return 0;
+}
+#else
+int arch_cpu_init(void)
+{
+ init_cpu_basic();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (is_mx7d())
+ env_set("soc", "imx7d");
+ else
+ env_set("soc", "imx7s");
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+/*
+ * OCOTP_TESTER
+ * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+ * OCOTP_TESTER describes a unique ID based on silicon wafer
+ * and die X/Y position
+ *
+ * OCOTOP_TESTER offset 0x410
+ * 31:0 fuse 0
+ * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
+ *
+ * OCOTP_TESTER1 offset 0x420
+ * 31:24 fuse 1
+ * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
+ * 23:16 fuse 1
+ * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
+ * 15:11 fuse 1
+ * The wafer number of the wafer on which the device was fabricated/SJC
+ * CHALLENGE/ Unique ID
+ * 10:0 fuse 1
+ * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ serialnr->low = fuse->tester0;
+ serialnr->high = fuse->tester1;
+}
+#endif
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+ u32 reg = readw(&wdog->wcr);
+ /*
+ * Output WDOG_B signal to reset external pmic or POR_B decided by
+ * the board desgin. Without external reset, the peripherals/DDR/
+ * PMIC are not reset, that may cause system working abnormal.
+ */
+ reg = readw(&wdog->wcr);
+ reg |= 1 << 3;
+ /*
+ * WDZST bit is write-once only bit. Align this bit in kernel,
+ * otherwise kernel code will have no chance to set this bit.
+ */
+ reg |= 1 << 0;
+ writew(reg, &wdog->wcr);
+}
+
+void s_init(void)
+{
+ /* clock configuration. */
+ clock_init();
+
+ return;
+}
+
+#ifndef CONFIG_SPL_BUILD
+const struct boot_mode soc_boot_modes[] = {
+ {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
+ {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
+ {NULL, 0},
+};
+
+int boot_mode_getprisec(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+
+ return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
+}
+#endif
+
+void reset_misc(void)
+{
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
+ lcdif_power_down();
+#endif
+#endif
+}
+