diff options
Diffstat (limited to 'roms/u-boot/arch/arm/mach-mediatek')
24 files changed, 1087 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-mediatek/Kconfig b/roms/u-boot/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 000000000..e067604d9 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,91 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +config MT8512 + bool "MediaTek MT8512 SoC" + default n + +choice + prompt "MediaTek board select" + +config TARGET_MT7622 + bool "MediaTek MT7622 SoC" + select ARM64 + help + The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB3.0, SD and MMC cards, NAND, SNFI, PWM, PCIe, + Gigabit Ethernet, I2C, built-in Wi-Fi, and PCIe. + +config TARGET_MT7623 + bool "MediaTek MT7623 SoC" + select CPU_V7A + help + The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-450 graphics, several DDR3 options, + crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder, + video interfaces supporting HDMI and MIPI, and video codec support. + Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe, + I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM. + +config TARGET_MT7629 + bool "MediaTek MT7629 SoC" + select CPU_V7A + select SPL + help + The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7 + including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, + switch, USB3.0, PCIe, UART, SPI, I2C and PWM. + +config TARGET_MT8183 + bool "MediaTek MT8183 SoC" + select ARM64 + help + The MediaTek MT8183 is a ARM64-based SoC with a quad-core Cortex-A73 and + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 dual role, + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 + and LPDDR4 options. + +config TARGET_MT8512 + bool "MediaTek MT8512 M1 Board" + select ARM64 + select MT8512 + help + The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital + and several LPDDR3 and LPDDR4 options. + +config TARGET_MT8516 + bool "MediaTek MT8516 SoC" + select ARM64 + help + The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + +config TARGET_MT8518 + bool "MediaTek MT8518 SoC" + select ARM64 + help + The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + +endchoice + +source "board/mediatek/mt7622/Kconfig" +source "board/mediatek/mt7623/Kconfig" +source "board/mediatek/mt7629/Kconfig" +source "board/mediatek/mt8183/Kconfig" +source "board/mediatek/mt8512/Kconfig" +source "board/mediatek/mt8516/Kconfig" +source "board/mediatek/mt8518/Kconfig" + +endif diff --git a/roms/u-boot/arch/arm/mach-mediatek/Makefile b/roms/u-boot/arch/arm/mach-mediatek/Makefile new file mode 100644 index 000000000..0f5b0c16d --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += cpu.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +obj-$(CONFIG_MT8512) += mt8512/ +obj-$(CONFIG_TARGET_MT7622) += mt7622/ +obj-$(CONFIG_TARGET_MT7623) += mt7623/ +obj-$(CONFIG_TARGET_MT7629) += mt7629/ +obj-$(CONFIG_TARGET_MT8183) += mt8183/ +obj-$(CONFIG_TARGET_MT8516) += mt8516/ +obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/roms/u-boot/arch/arm/mach-mediatek/cpu.c b/roms/u-boot/arch/arm/mach-mediatek/cpu.c new file mode 100644 index 000000000..c329e7cc9 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/cpu.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <init.h> +#include <wdt.h> +#include <dm/uclass-internal.h> + +int arch_cpu_init(void) +{ + icache_enable(); + + return 0; +} + +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} diff --git a/roms/u-boot/arch/arm/mach-mediatek/init.h b/roms/u-boot/arch/arm/mach-mediatek/init.h new file mode 100644 index 000000000..1d896fbbf --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/init.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_INIT_H_ +#define __MEDIATEK_INIT_H_ + +extern int mtk_soc_early_init(void); + +#endif /* __MEDIATEK_INIT_H_ */ diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7622/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt7622/Makefile new file mode 100644 index 000000000..886ab7e4e --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7622/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7622/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt7622/init.c new file mode 100644 index 000000000..e501907b5 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7622/init.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/cache.h> + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT7622\n"); + return 0; +} + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + return fdtdec_setup_mem_size_base(); + +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +static struct mm_region mt7622_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; +struct mm_region *mem_map = mt7622_mem_map; diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7623/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt7623/Makefile new file mode 100644 index 000000000..007eb4a36 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7623/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7623/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt7623/init.c new file mode 100644 index 000000000..5d837e059 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7623/init.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <common.h> +#include <init.h> +#include <asm/global_data.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <asm/arch/misc.h> + +#include "preloader.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct boot_argument *preloader_param; + +int mtk_soc_early_init(void) +{ + return 0; +} + +int dram_init(void) +{ + u32 i; + + if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + ((size_t)preloader_param % sizeof(size_t) == 0) && + preloader_param->magic == BOOT_ARGUMENT_MAGIC && + preloader_param->dram_rank_num <= + ARRAY_SIZE(preloader_param->dram_rank_size)) { + gd->ram_size = 0; + + for (i = 0; i < preloader_param->dram_rank_num; i++) + gd->ram_size += preloader_param->dram_rank_size[i]; + } else { + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + SZ_2G); + } + + return 0; +} + +int print_cpuinfo(void) +{ + void __iomem *chipid; + u32 swver; + + chipid = ioremap(VER_BASE, VER_SIZE); + swver = readl(chipid + APSW_VER); + + printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1); + + return 0; +} diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7623/lowlevel_init.S b/roms/u-boot/arch/arm/mach-mediatek/mt7623/lowlevel_init.S new file mode 100644 index 000000000..afb94767e --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7623/lowlevel_init.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <linux/linkage.h> + +.extern preloader_param + +ENTRY(save_boot_params) + ldr r6, =preloader_param + str r4, [r6] + b save_boot_params_ret +ENDPROC(save_boot_params) + +ENTRY(lowlevel_init) + /* enable SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7623/preloader.h b/roms/u-boot/arch/arm/mach-mediatek/mt7623/preloader.h new file mode 100644 index 000000000..2d2c71ad4 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7623/preloader.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __PRELOADER_H_ +#define __PRELOADER_H_ + +enum forbidden_mode { + F_FACTORY_MODE = 0x0001 +}; + +union lk_hdr { + struct { + u32 magic; + u32 size; + char name[32]; + u32 loadaddr; + }; + + u8 data[512]; +}; + +struct sec_limit { + unsigned int magic_num; + enum forbidden_mode forbid_mode; +}; + +enum bootmode { + NORMAL_BOOT = 0, + META_BOOT = 1, + RECOVERY_BOOT = 2, + SW_REBOOT = 3, + FACTORY_BOOT = 4, + ADVMETA_BOOT = 5, + ATE_FACTORY_BOOT = 6, + ALARM_BOOT = 7, + + KERNEL_POWER_OFF_CHARGING_BOOT = 8, + LOW_POWER_OFF_CHARGING_BOOT = 9, + + FAST_BOOT = 99, + DOWNLOAD_BOOT = 100, + UNKNOWN_BOOT +}; + +enum boot_reason { + BR_POWER_KEY = 0, + BR_USB, + BR_RTC, + BR_WDT, + BR_WDT_BY_PASS_PWK, + BR_TOOL_BY_PASS_PWK, + BR_2SEC_REBOOT, + BR_UNKNOWN +}; + +enum meta_com_type { + META_UNKNOWN_COM = 0, + META_UART_COM, + META_USB_COM +}; + +struct da_info_t { + u32 addr; + u32 arg1; + u32 arg2; + u32 len; + u32 sig_len; +}; + +struct boot_argument { + u32 magic; + enum bootmode boot_mode; + u32 e_flag; + u32 log_port; + u32 log_baudrate; + u8 log_enable; + u8 part_num; + u8 reserved[2]; + u32 dram_rank_num; + u32 dram_rank_size[4]; + u32 boot_reason; + enum meta_com_type meta_com_type; + u32 meta_com_id; + u32 boot_time; + struct da_info_t da_info; + struct sec_limit sec_limit; + union lk_hdr *part_info; + u8 md_type[4]; + u32 ddr_reserve_enable; + u32 ddr_reserve_success; + u32 chip_ver; + char pl_version[8]; +}; + +#define BOOT_ARGUMENT_MAGIC 0x504c504c + +#endif /* __PRELOADER_H_ */ diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7629/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt7629/Makefile new file mode 100644 index 000000000..007eb4a36 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7629/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7629/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt7629/init.c new file mode 100644 index 000000000..0130554ff --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7629/init.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <init.h> +#include <log.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> + +#include <dt-bindings/clock/mt7629-clk.h> + +#define L2_CFG_BASE 0x10200000 +#define L2_CFG_SIZE 0x1000 +#define L2_SHARE_CFG_MP0 0x7f0 +#define L2_SHARE_MODE_OFF BIT(8) + +DECLARE_GLOBAL_DATA_PTR; + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1250000000, + [CLK_APMIXED_MAINPLL] = 1120000000, + [CLK_APMIXED_UNIV2PLL] = 1200000000, + [CLK_APMIXED_ETH1PLL] = 500000000, + [CLK_APMIXED_ETH2PLL] = 700000000, + [CLK_APMIXED_SGMIPLL] = 650000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + /* setup mcu bus */ + ret = uclass_get_device_by_driver(UCLASS_SYSCON, + DM_DRIVER_GET(mtk_mcucfg), &dev); + if (ret) + return ret; + + return 0; +} + +int mtk_soc_early_init(void) +{ + struct udevice *dev; + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + ret = uclass_first_device_err(UCLASS_RAM, &dev); + if (ret) + return ret; + + return 0; +} + +int mach_cpu_init(void) +{ + void __iomem *base; + + base = ioremap(L2_CFG_BASE, L2_CFG_SIZE); + + /* disable L2C shared mode */ + writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0); + + return 0; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_RAM, &dev); + if (ret) + return ret; + + ret = ram_get_info(dev, &ram); + if (ret) + return ret; + + debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} + +int print_cpuinfo(void) +{ + void __iomem *chipid; + u32 hwcode, swver; + + chipid = ioremap(VER_BASE, VER_SIZE); + hwcode = readl(chipid + APHW_CODE); + swver = readl(chipid + APSW_VER); + + printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1); + + return 0; +} diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/roms/u-boot/arch/arm/mach-mediatek/mt7629/lowlevel_init.S new file mode 100644 index 000000000..0a0672cbe --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt7629/lowlevel_init.S @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#include <linux/linkage.h> +#include <asm/proc-armv/ptrace.h> + +#define WAIT_CODE_SRAM_BASE 0x0010ff00 + +#define SLAVE_JUMP_REG 0x10202034 +#define SLAVE1_MAGIC_REG 0x10202038 +#define SLAVE1_MAGIC_NUM 0x534c4131 + +#define GIC_CPU_BASE 0x10320000 + +ENTRY(lowlevel_init) + +#ifndef CONFIG_SPL_BUILD + /* Return to U-Boot via saved link register */ + mov pc, lr +#else + /* + * Arch timer : + * set CNTFRQ = 20Mhz, set CNTVOFF = 0 + */ + movw r0, #0x2d00 + movt r0, #0x131 + mcr p15, 0, r0, c14, c0, 0 + + cps #MON_MODE + mrc p15, 0, r1, c1, c1, 0 @ Get Secure Config + orr r0, r1, #1 + mcr p15, 0, r0, c1, c1, 0 @ Set Non Secure bit + isb + mov r0, #0 + mcrr p15, 4, r0, r0, c14 @ CNTVOFF = 0 + isb + mcr p15, 0, r1, c1, c1, 0 @ Set Secure bit + isb + cps #SVC_MODE + + /* enable SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + + /* if MP core, handle secondary cores */ + mrc p15, 0, r0, c0, c0, 5 + ands r1, r0, #0x40000000 + bne go @ Go if UP + /* read slave CPU number */ + ands r0, r0, #0x0f + beq go @ Go if core0 on primary core tile + b secondary + +go: + /* master CPU */ + mov pc, lr + +secondary: + /* enable GIC as cores will be waken up by IPI */ + ldr r2, =GIC_CPU_BASE + mov r1, #0xf0 + str r1, [r2, #4] + mov r1, #1 + str r1, [r2, #0] + + ldr r1, [r2] + orr r1, #1 + str r1, [r2] + + /* copy wait code into SRAM */ + ldr r0, =slave_cpu_wait + ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns + ldr r0, =WAIT_CODE_SRAM_BASE + stm r0, {r1 - r8} + + /* pass args to slave_cpu_wait */ + ldr r0, =SLAVE1_MAGIC_REG + ldr r1, =SLAVE1_MAGIC_NUM + + /* jump to wait code in SRAM */ + ldr pc, =WAIT_CODE_SRAM_BASE + +#endif +ENDPROC(lowlevel_init) + +/* This function will be copied into SRAM */ +ENTRY(slave_cpu_wait) + wfi + ldr r2, [r0] + cmp r2, r1 + bne slave_cpu_wait + movw r0, #:lower16:SLAVE_JUMP_REG + movt r0, #:upper16:SLAVE_JUMP_REG + ldr r1, [r0] + mov pc, r1 +ENDPROC(slave_cpu_wait) diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8183/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt8183/Makefile new file mode 100644 index 000000000..886ab7e4e --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8183/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8183/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt8183/init.c new file mode 100644 index 000000000..877f38710 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8183/init.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + * Copyright (C) 2021 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <asm/system.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8516-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + return 0; +} + +int mtk_soc_early_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8183\n"); + return 0; +} + +static struct mm_region mt8183_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; +struct mm_region *mem_map = mt8183_mem_map; diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8512/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt8512/Makefile new file mode 100644 index 000000000..007eb4a36 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8512/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8512/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt8512/init.c new file mode 100644 index 000000000..b7050dfc3 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8512/init.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Configuration for MediaTek MT8512 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <init.h> +#include <log.h> +#include <ram.h> +#include <wdt.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8512-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +phys_size_t get_effective_memsize(void) +{ + /* limit stack below tee reserve memory */ + return gd->ram_size - 6 * SZ_1M; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = get_effective_memsize(); + + return 0; +} + +void reset_cpu(void) +{ + struct udevice *watchdog_dev = NULL; + + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) + psci_system_reset(); + + wdt_expire_now(watchdog_dev, 0); +} + +int print_cpuinfo(void) +{ + debug("CPU: MediaTek MT8512\n"); + return 0; +} + +static struct mm_region mt8512_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8512_mem_map; diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8512/lowlevel_init.S b/roms/u-boot/arch/arm/mach-mediatek/mt8512/lowlevel_init.S new file mode 100644 index 000000000..ad392120f --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8512/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + /* Define in src\bsp\trustzone\atf\v1.2\ */ + /* mt8xxx\plat\mediatek\common\sip_svc.h */ + /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/ + ldr x0, =0xC2000200 + SMC #0 + ret diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8516/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt8516/Makefile new file mode 100644 index 000000000..886ab7e4e --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8516/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8516/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt8516/init.c new file mode 100644 index 000000000..3460dcc24 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8516/init.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <clk.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdtdec.h> +#include <init.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8516-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1300000000, + [CLK_APMIXED_MAINPLL] = 1501000000, + [CLK_APMIXED_UNIVPLL] = 1248000000, + [CLK_APMIXED_MMPLL] = 380000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + return 0; +} + +int mtk_soc_early_init(void) +{ + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + return 0; +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8516\n"); + return 0; +} + +static struct mm_region mt8516_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; +struct mm_region *mem_map = mt8516_mem_map; diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8518/Makefile b/roms/u-boot/arch/arm/mach-mediatek/mt8518/Makefile new file mode 100644 index 000000000..007eb4a36 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8518/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8518/init.c b/roms/u-boot/arch/arm/mach-mediatek/mt8518/init.c new file mode 100644 index 000000000..f7e03de36 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8518/init.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Configuration for MediaTek MT8518 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdtdec.h> +#include <init.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8518-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8518\n"); + return 0; +} + +static struct mm_region mt8518_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8518_mem_map; diff --git a/roms/u-boot/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/roms/u-boot/arch/arm/mach-mediatek/mt8518/lowlevel_init.S new file mode 100644 index 000000000..ad392120f --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/mt8518/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + /* Define in src\bsp\trustzone\atf\v1.2\ */ + /* mt8xxx\plat\mediatek\common\sip_svc.h */ + /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/ + ldr x0, =0xC2000200 + SMC #0 + ret diff --git a/roms/u-boot/arch/arm/mach-mediatek/spl.c b/roms/u-boot/arch/arm/mach-mediatek/spl.c new file mode 100644 index 000000000..927175c5a --- /dev/null +++ b/roms/u-boot/arch/arm/mach-mediatek/spl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <hang.h> +#include <init.h> +#include <spl.h> + +#include "init.h" + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + hang(); + + /* enable console uart printing */ + preloader_console_init(); + + /* soc early initialization */ + ret = mtk_soc_early_init(); + if (ret) + hang(); +} + +u32 spl_boot_device(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + return BOOT_DEVICE_SPI; +#elif defined(CONFIG_SPL_MMC_SUPPORT) + return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_SPL_NAND_SUPPORT) + return BOOT_DEVICE_NAND; +#elif defined(CONFIG_SPL_NOR_SUPPORT) + return BOOT_DEVICE_NOR; +#else + return BOOT_DEVICE_NONE; +#endif +} |