diff options
Diffstat (limited to 'roms/u-boot/arch/arm/mach-rmobile/include')
20 files changed, 3650 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/boot0.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/boot0.h new file mode 100644 index 000000000..1d8c3eea9 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/boot0.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Specialty padding for the RCar Gen2 SPL JTAG loading + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + +_start: + ARM_VECTORS + +#ifdef CONFIG_SPL_BUILD + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; +#endif + +#endif /* __BOOT0_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h new file mode 100644 index 000000000..ca8c5f370 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + */ + +#ifndef __EHCI_RMOBILE_H__ +#define __EHCI_RMOBILE_H__ + +/* Register offset */ +#define OHCI_OFFSET 0x00 +#define OHCI_SIZE 0x1000 +#define EHCI_OFFSET 0x1000 +#define EHCI_SIZE 0x1000 + +#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) + +/* USBCTR */ +#define DIRPD (1 << 8) +#define PLL_RST (1 << 2) +#define PCICLK_MASK (1 << 1) +#define USBH_RST (1 << 0) + +/* CMND_STS */ +#define SERREN (1 << 8) +#define PERREN (1 << 6) +#define MASTEREN (1 << 2) +#define MEMEN (1 << 1) + +/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ +#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) + +/* AHBPCI_WIN1_CTR */ +#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) +#define AHB_CFG_AHBPCI 0x40000000 +#define AHB_CFG_HOST 0x80000000 + +/* AHBPCI_WIN2_CTR */ +#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) + +/* PCI_INT_ENABLE */ +#define USBH_PMEEN (1 << 19) +#define USBH_INTBEN (1 << 17) +#define USBH_INTAEN (1 << 16) + +/* AHB_BUS_CTR */ +#define SMODE_READY_CTR (1 << 17) +#define SMODE_READ_BURST (1 << 16) +#define MMODE_HBUSREQ (1 << 7) +#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) +#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) +#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) +#define MMODE_WR_INCR (1 << 2) +#define MMODE_BYTE_BURST (1 << 1) +#define MMODE_HTRANS (1 << 0) + +/* PCI_ARBITER_CTR */ +#define PCIBUS_PARK_TIMER 0x00FF0000 +#define PCIBUS_PARK_TIMER_SET 0x00070000 +#define PCIBP_MODE (1 << 12) +#define PCIREQ7 (1 << 7) +#define PCIREQ6 (1 << 6) +#define PCIREQ5 (1 << 5) +#define PCIREQ4 (1 << 4) +#define PCIREQ3 (1 << 3) +#define PCIREQ2 (1 << 2) +#define PCIREQ1 (1 << 1) +#define PCIREQ0 (1 << 0) + +#define SMSTPCR7 0xE615014C +#define SMSTPCR703 (1 << 3) + +/* Init AHB master and slave functions of the host logic */ +#define AHB_BUS_CTR_INIT \ + (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ + MMODE_BYTE_BURST | MMODE_HTRANS) + +#define USBCTR_WIN_SIZE_1GB 0x800 + +/* PCI Configuration Registers */ +#define PCI_CONF_OHCI_OFFSET 0x10000 +#define PCI_CONF_EHCI_OFFSET 0x10100 +struct ahb_pciconf { + u32 vid_did; + u32 cmnd_sts; + u32 rev; + u32 cache_line; + u32 basead; +}; + +/* PCI Configuration Registers for AHB-PCI Bridge Registers */ +#define PCI_CONF_AHBPCI_OFFSET 0x10000 +struct ahbconf_pci_bridge { + u32 vid_did; /* 0x00 */ + u32 cmnd_sts; + u32 revid_cc; + u32 cls_lt_ht_bist; + u32 basead; /* 0x10 */ + u32 win1_basead; + u32 win2_basead; + u32 dummy0[5]; + u32 ssvdi_ssid; /* 0x2C */ + u32 dummy1[4]; + u32 intr_line_pin; +}; + +/* AHB-PCI Bridge PCI Communication Registers */ +#define AHBPCI_OFFSET 0x10800 +struct ahbcom_pci_bridge { + u32 pciahb_win1_ctr; /* 0x00 */ + u32 pciahb_win2_ctr; + u32 pciahb_dct_ctr; + u32 dummy0; + u32 ahbpci_win1_ctr; /* 0x10 */ + u32 ahbpci_win2_ctr; + u32 dummy1; + u32 ahbpci_dct_ctr; + u32 pci_int_enable; /* 0x20 */ + u32 pci_int_status; + u32 dummy2[2]; + u32 ahb_bus_ctr; /* 0x30 */ + u32 usbctr; + u32 dummy3[2]; + u32 pci_arbiter_ctr; /* 0x40 */ + u32 dummy4; + u32 pci_unit_rev; /* 0x48 */ +}; + +struct rmobile_ehci_reg { + u32 hciversion; /* hciversion/caplength */ + u32 hcsparams; /* hcsparams */ + u32 hccparams; /* hccparams */ + u32 hcsp_portroute; /* hcsp_portroute */ + u32 usbcmd; /* usbcmd */ + u32 usbsts; /* usbsts */ + u32 usbintr; /* usbintr */ + u32 frindex; /* frindex */ + u32 ctrldssegment; /* ctrldssegment */ + u32 periodiclistbase; /* periodiclistbase */ + u32 asynclistaddr; /* asynclistaddr */ + u32 dummy[9]; + u32 configflag; /* configflag */ + u32 portsc; /* portsc */ +}; + +#endif /* __EHCI_RMOBILE_H__ */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/gpio.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/gpio.h new file mode 100644 index 000000000..6b5e4ed4e --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/gpio.h @@ -0,0 +1,12 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#if defined(CONFIG_SH73A0) +#include "sh73a0-gpio.h" +void sh73a0_pinmux_init(void); +#elif defined(CONFIG_R8A7740) +#include "r8a7740-gpio.h" +void r8a7740_pinmux_init(void); +#endif + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/irqs.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/irqs.h new file mode 100644 index 000000000..dcb714f4d --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/irqs.h @@ -0,0 +1,18 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#define NR_IRQS 1024 + +/* GIC */ +#define gic_spi(nr) ((nr) + 32) + +/* INTCA */ +#define evt2irq(evt) (((evt) >> 5) - 16) +#define irq2evt(irq) (((irq) + 16) << 5) + +/* INTCS */ +#define INTCS_VECT_BASE 0x2200 +#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) +#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/mmc.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/mmc.h new file mode 100644 index 000000000..7a0e6f0f7 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/mmc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas SuperH MMCIF driver. + * + * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2014 Renesas Electronics Corporation + */ +#ifndef _RMOBILE_MMC_H_ +#define _RMOBILE_MMC_H_ + +int mmcif_mmc_init(void); + +#endif /* _RMOBILE_MMC_H_ */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h new file mode 100644 index 000000000..125b3b4ff --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h @@ -0,0 +1,572 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ + +#ifndef __ASM_R8A7740_H__ +#define __ASM_R8A7740_H__ + +/* + * MD_CKx pin + */ +#define MD_CK2 (1 << 2) +#define MD_CK1 (1 << 1) +#define MD_CK0 (1 << 0) + +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, + + /* IRQ */ + GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, + GPIO_FN_IRQ1, + GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, + GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, + GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, + GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, + GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, + GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, + GPIO_FN_IRQ8, + GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, + GPIO_FN_IRQ10, + GPIO_FN_IRQ11, + GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, + GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, + GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, + GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, + GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, + GPIO_FN_IRQ17, + GPIO_FN_IRQ18, + GPIO_FN_IRQ19, + GPIO_FN_IRQ20, + GPIO_FN_IRQ21, + GPIO_FN_IRQ22, + GPIO_FN_IRQ23, + GPIO_FN_IRQ24, + GPIO_FN_IRQ25, + GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, + GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, + GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, + GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, + GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, + GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, + + /* Function */ + + /* DBGT */ + GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, + GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, + GPIO_FN_DBGMD21, + + /* FSI */ + GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ + GPIO_FN_FSIAISLD_PORT5, + GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ + GPIO_FN_FSIASPDIF_PORT18, + GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, + GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, + GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, + GPIO_FN_FSIACK, GPIO_FN_FSIAILR, + GPIO_FN_FSIAIBT, + + /* FMSI */ + GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ + GPIO_FN_FMSISLD_PORT6, + GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, + GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, + GPIO_FN_FMSICK, GPIO_FN_FMSOILR, + GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, + GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOCK, + + /* SCIFA0 */ + GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, + GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_TXD, + + /* SCIFA1 */ + GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, + GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, + GPIO_FN_SCIFA1_RTS, + + /* SCIFA2 */ + GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ + GPIO_FN_SCIFA2_SCK_PORT199, + GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, + GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, + + /* SCIFA3 */ + GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ + GPIO_FN_SCIFA3_SCK_PORT116, + GPIO_FN_SCIFA3_CTS_PORT117, + GPIO_FN_SCIFA3_RXD_PORT174, + GPIO_FN_SCIFA3_TXD_PORT175, + + GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ + GPIO_FN_SCIFA3_SCK_PORT158, + GPIO_FN_SCIFA3_CTS_PORT162, + GPIO_FN_SCIFA3_RXD_PORT159, + GPIO_FN_SCIFA3_TXD_PORT160, + + /* SCIFA4 */ + GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ + GPIO_FN_SCIFA4_TXD_PORT13, + + GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ + GPIO_FN_SCIFA4_TXD_PORT203, + + GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ + GPIO_FN_SCIFA4_TXD_PORT93, + + GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ + GPIO_FN_SCIFA4_SCK_PORT205, + + /* SCIFA5 */ + GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ + GPIO_FN_SCIFA5_RXD_PORT10, + + GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ + GPIO_FN_SCIFA5_TXD_PORT208, + + GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ + GPIO_FN_SCIFA5_RXD_PORT92, + + GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ + GPIO_FN_SCIFA5_SCK_PORT206, + + /* SCIFA6 */ + GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, + + /* SCIFA7 */ + GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, + + /* SCIFAB */ + GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ + GPIO_FN_SCIFB_RXD_PORT191, + GPIO_FN_SCIFB_TXD_PORT192, + GPIO_FN_SCIFB_RTS_PORT186, + GPIO_FN_SCIFB_CTS_PORT187, + + GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ + GPIO_FN_SCIFB_RXD_PORT3, + GPIO_FN_SCIFB_TXD_PORT4, + GPIO_FN_SCIFB_RTS_PORT172, + GPIO_FN_SCIFB_CTS_PORT173, + + /* LCD0 */ + GPIO_FN_LCDC0_SELECT, + GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, + GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, + GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, + GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, + GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, + GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, + GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, + + GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ + GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ + + GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ + GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ + + GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, + GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, + GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, + GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ + + GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, + GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, + GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, + GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN_LCDC1_SELECT, + GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, + GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, + GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, + GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, + GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, + GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, + GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, + GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, + GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, + GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, + + GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ + GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ + + GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ + GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ + + /* RSPI */ + GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, + GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, + GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, + GPIO_FN_RSPI_CK_A, + + /* VIO CKO */ + GPIO_FN_VIO_CKO1, + GPIO_FN_VIO_CKO2, + GPIO_FN_VIO_CKO_1, + GPIO_FN_VIO_CKO, + + /* VIO0 */ + GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, + GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, + GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, + GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, + GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, + GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, + + GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ + GPIO_FN_VIO0_D14_PORT25, + GPIO_FN_VIO0_D15_PORT24, + + GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ + GPIO_FN_VIO0_D14_PORT95, + GPIO_FN_VIO0_D15_PORT96, + + /* VIO1 */ + GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, + GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, + GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, + GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, + + /* TPU0 */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO3, + GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ + GPIO_FN_TPU0TO2_PORT202, + + /* SSP1 0 */ + GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, + GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, + GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, + GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, + + /* SSP1 1 */ + GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, + GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, + GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, + + GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ + GPIO_FN_STP1_IPEN_PORT187, + + GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ + GPIO_FN_STP1_IPEN_PORT193, + + /* SIM */ + GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, + GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ + GPIO_FN_SIM_D_PORT199, + + /* SDHI0 */ + GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, + GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, + GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, + + /* SDHI1 */ + GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, + GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, + GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, + + /* SDHI2 */ + GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, + GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, + + GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ + GPIO_FN_SDHI2_WP_PORT25, + + GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ + GPIO_FN_SDHI2_CD_PORT202, + + /* MSIOF2 */ + GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, + GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_MSIOF2_RSCK, + + /* KEYSC */ + GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, + GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, + GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, + GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, + GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, + + GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ + GPIO_FN_KEYIN1_PORT44, + GPIO_FN_KEYIN2_PORT45, + GPIO_FN_KEYIN3_PORT46, + + GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ + GPIO_FN_KEYIN1_PORT57, + GPIO_FN_KEYIN2_PORT56, + GPIO_FN_KEYIN3_PORT55, + + /* VOU */ + GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, + GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, + GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, + GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, + GPIO_FN_DV_CLK, + GPIO_FN_DV_VSYNC, + GPIO_FN_DV_HSYNC, + + /* MEMC */ + GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, + GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, + GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, + GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, + GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, + GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, + GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, + + GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ + GPIO_FN_MEMC_ADV, + GPIO_FN_MEMC_WAIT, + GPIO_FN_MEMC_BUSCLK, + + GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ + GPIO_FN_MEMC_DREQ0, + GPIO_FN_MEMC_DREQ1, + GPIO_FN_MEMC_A0, + + /* MMC */ + GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, + GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, + GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, + GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, + GPIO_FN_MMC0_CLK_PORT66, + GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ + + GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, + GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, + GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, + GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, + GPIO_FN_MMC1_CLK_PORT103, + GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, + GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, + GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, + + /* MSIOF1 */ + GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + + GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, + GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, + GPIO_FN_MSIOF1_TSYNC_PORT120, + GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ + + GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, + GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, + GPIO_FN_MSIOF1_RXD_PORT75, + GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ + + /* GPIO */ + GPIO_FN_GPO0, GPIO_FN_GPI0, + GPIO_FN_GPO1, GPIO_FN_GPI1, + + /* USB0 */ + GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, + + /* USB1 */ + GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, + + /* BBIF1 */ + GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, + + /* BBIF2 */ + GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ + GPIO_FN_BBIF2_RXD2_PORT60, + GPIO_FN_BBIF2_TSYNC2_PORT6, + GPIO_FN_BBIF2_TSCK2_PORT59, + + GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ + GPIO_FN_BBIF2_TXD2_PORT183, + GPIO_FN_BBIF2_TSCK2_PORT89, + GPIO_FN_BBIF2_TSYNC2_PORT184, + + /* BSC / FLCTL / PCMCIA */ + GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, + GPIO_FN_CS5B, GPIO_FN_CS6A, + GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ + GPIO_FN_CS5A_PORT19, + GPIO_FN_IOIS16, /* ? */ + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, + GPIO_FN_A4_FOE, /* share with FLCTL */ + GPIO_FN_A5_FCDE, /* share with FLCTL */ + GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, + GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, + GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, + GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + + GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ + GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ + GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ + GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ + GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ + GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ + GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ + GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ + + GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, + GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, + GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, + GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, + + GPIO_FN_WE0_FWE, /* share with FLCTL */ + GPIO_FN_WE1, + GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ + GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ + GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, + GPIO_FN_RD_FSC, /* share with FLCTL */ + GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ + GPIO_FN_WAIT_PORT90, + + GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ + + /* IRDA */ + GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, + + /* ATAPI */ + GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, + GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, + GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, + GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, + GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, + GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, + GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, + GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, + GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, + GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, + + /* RMII */ + GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, + GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, + GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, + GPIO_FN_RMII_REF50CK, /* for RMII */ + GPIO_FN_RMII_REF125CK, /* for GMII */ + + /* GEther */ + GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, + GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, + GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ + GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ + GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, + GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, + GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, + GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, + GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ + GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ + GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, + GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, + GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, + GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, + + /* DMA0 */ + GPIO_FN_DREQ0, GPIO_FN_DACK0, + + /* DMA1 */ + GPIO_FN_DREQ1, GPIO_FN_DACK1, + + /* SYSC */ + GPIO_FN_RESETOUTS, + GPIO_FN_RESETP_PULLUP, + GPIO_FN_RESETP_PLAIN, + + /* SDENC */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, + + /* IRREM */ + GPIO_FN_IROUT, + + /* DEBUG */ + GPIO_FN_EDEBGREQ_PULLDOWN, + GPIO_FN_EDEBGREQ_PULLUP, + + GPIO_FN_TRACEAUD_FROM_VIO, + GPIO_FN_TRACEAUD_FROM_LCDC0, + GPIO_FN_TRACEAUD_FROM_MEMC, +}; + +#endif /* __ASM_R8A7740_H__ */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7740.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7740.h new file mode 100644 index 000000000..f1fcfe19e --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7740.h @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + */ + +#ifndef __ASM_ARCH_R8A7740_H +#define __ASM_ARCH_R8A7740_H + +/* + * R8A7740 I/O Addresses + */ + +#define MERAM_BASE 0xE5580000 +#define DDRP_BASE 0xC12A0000 +#define HPB_BASE 0xE6000000 +#define RWDT0_BASE 0xE6020000 +#define RWDT1_BASE 0xE6030000 +#define GPIO_BASE 0xE6050000 +#define CMT1_BASE 0xE6138000 +#define CPG_BASE 0xE6150000 +#define SYSC_BASE 0xE6180000 +#define SDHI0_BASE 0xE6850000 +#define SDHI1_BASE 0xE6860000 +#define MMCIF_BASE 0xE6BD0000 +#define SCIF5_BASE 0xE6CB0000 +#define SCIF6_BASE 0xE6CC0000 +#define DBSC_BASE 0xFE400000 +#define BSC_BASE 0xFEC10000 +#define I2C0_BASE 0xFFF20000 +#define I2C1_BASE 0xE6C20000 +#define TMU_BASE 0xFFF80000 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct r8a7740_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 dummy0; /* 0x02 */ + u16 rwtcsra0; /* 0x04 */ + u16 dummy1; /* 0x06 */ + u16 rwtcsrb0; /* 0x08 */ + u16 dummy2; /* 0x0A */ +}; + +/* HPB Semaphore Control Registers */ +struct r8a7740_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; +}; + +/* CPG */ +struct r8a7740_cpg { + u32 frqcra; + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 fmsickcr; + u32 fmsockcr; + u32 fsiackcr; + u32 dummy0; /* 0x1c */ + u32 rtstbcr; + u32 systbcr; + u32 pllc01cr; + u32 pllc2cr; + u32 mstpsr0; + u32 dummy1; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy2; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy3; /* 0x50 */ + u32 astat; + u32 dummy4[4]; /* 0x58 .. 0x64 */ + u32 ztrckcr; + u32 dummy5[5]; /* 0x6c .. 0x7c */ + u32 subckcr; + u32 spuckcr; + u32 vouckcr; + u32 usbckcr; + u32 dummy6[3]; /* 0x90 .. 0x98 */ + u32 stprckcr; + u32 srcr0; + u32 dummy7; /* 0xa4 */ + u32 srcr1; + u32 dummy8; /* 0xac */ + u32 srcr2; + u32 dummy9; /* 0xb4 */ + u32 srcr3; + u32 srcr4; + u32 dummy10; /* 0xc0 */ + u32 srcr5; + u32 pllc01stpcr; + u32 dummy11[5]; /* 0xcc .. 0xdc */ + u32 frqcrc; + u32 frqcrd; + u32 dummy12[10]; /* 0xe8 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy13[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; +}; + +/* BSC */ +struct r8a7740_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0c */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 dummy1; /* 0x20 */ + u32 cs0wcr; + u32 cs2wcr; + u32 dummy2; /* 0x2c */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 dummy3[5]; /* 0x40 .. 0x50 */ + u32 rbwtcnt; + u32 busycr; + u32 dummy4[5]; /* 0x5c .. 0x6c */ + u32 bromtimcr; + u32 dummy5[7]; /* 0x74 .. 0x8c */ + u32 bptcr00; + u32 bptcr01; + u32 bptcr02; + u32 bptcr03; + u32 bptcr04; + u32 bptcr05; + u32 bptcr06; + u32 bptcr07; + u32 bptcr08; + u32 bptcr09; + u32 bptcr10; + u32 bptcr11; + u32 bptcr12; + u32 bptcr13; + u32 bptcr14; + u32 bptcr15; + u32 bptcr16; + u32 bptcr17; + u32 bptcr18; + u32 bptcr19; + u32 bptcr20; + u32 bptcr21; + u32 bptcr22; + u32 bptcr23; + u32 bptcr24; + u32 bptcr25; + u32 bptcr26; + u32 bptcr27; + u32 bptcr28; + u32 bptcr29; + u32 bptcr30; + u32 bptcr31; + u32 bswcr; + u32 dummy6[68]; /* 0x114 .. 0x220 */ + u32 cs0wcr2; + u32 cs2wcr2; + u32 dummy7; /* 0x22c */ + u32 cs4wcr2; +}; + +#define CS0WCR2 0xFEC10224 +#define CS2WCR2 0xFEC10228 +#define CS4WCR2 0xFEC10230 + +/* DDRP */ +struct r8a7740_ddrp { + u32 funcctrl; + u32 dllctrl; + u32 zqcalctrl; + u32 zqodtctrl; + u32 rdctrl; + u32 rdtmg; + u32 fifoinit; + u32 outctrl; + u32 dummy0[50]; /* 0x20 .. 0xe4 */ + u32 dqcalofs1; + u32 dqcalofs2; + u32 dummy1[2]; /* 0xf0 .. 0xf4 */ + u32 dqcalexp; +}; + +#define DDRPNCNT 0xE605803C +#define DDRVREFCNT 0xE61500EC + +/* DBSC */ +struct r8a7740_dbsc { + u32 dummy0; + u32 dbsvcr; + u32 dbstate0; + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2c */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3c */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4c */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xac */ + u32 dbbl; + u32 dummy5[3]; /* 0xb4 .. 0xbc */ + u32 dbadj0; + u32 dbadj1; + u32 dbadj2; + u32 dummy6[5]; /* 0xcc .. 0xdc */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dbrfcnf3; + u32 dummy7; /* 0xf0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy8; /* 0xfc */; + u32 dbrnk0; + u32 dummy9[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy10[7]; /* 0x184 .. 0x19C */ + u32 dbmrrdr; + u32 dummy11[39]; /* 0x1A4 .. 0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[46]; /* 0x248 .. 0x2FC */ + u32 dbbs0cnt0; + u32 dbbs0cnt1; +}; + +#endif + +#endif /* __ASM_ARCH_R8A7740_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7790.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7790.h new file mode 100644 index 000000000..f3fbf77b0 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/r8a7790.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_R8A7790_H +#define __ASM_ARCH_R8A7790_H + +#include "rcar-base.h" + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0xDB6E9BDF +#define MSTP2_BITS 0x300DA1FC +#define MSTP3_BITS 0xF08CF831 +#define MSTP4_BITS 0x80000184 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x07F30718 +#define MSTP8_BITS 0x01F0FF84 +#define MSTP9_BITS 0xF5979FCF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x00000000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 + +#define R8A7790_CUT_ES2X 2 +#define IS_R8A7790_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7790_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7791.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7791.h new file mode 100644 index 000000000..fec9f7bf5 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/r8a7791.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_R8A7791_H +#define __ASM_ARCH_R8A7791_H + +#include "rcar-base.h" +/* + * R-Car (R8A7791) I/O Addresses + */ + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + +#define DBSC3_1_QOS_R0_BASE 0xE67A1000 +#define DBSC3_1_QOS_R1_BASE 0xE67A1100 +#define DBSC3_1_QOS_R2_BASE 0xE67A1200 +#define DBSC3_1_QOS_R3_BASE 0xE67A1300 +#define DBSC3_1_QOS_R4_BASE 0xE67A1400 +#define DBSC3_1_QOS_R5_BASE 0xE67A1500 +#define DBSC3_1_QOS_R6_BASE 0xE67A1600 +#define DBSC3_1_QOS_R7_BASE 0xE67A1700 +#define DBSC3_1_QOS_R8_BASE 0xE67A1800 +#define DBSC3_1_QOS_R9_BASE 0xE67A1900 +#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 +#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 +#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 +#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 +#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 +#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 +#define DBSC3_1_QOS_W0_BASE 0xE67A2000 +#define DBSC3_1_QOS_W1_BASE 0xE67A2100 +#define DBSC3_1_QOS_W2_BASE 0xE67A2200 +#define DBSC3_1_QOS_W3_BASE 0xE67A2300 +#define DBSC3_1_QOS_W4_BASE 0xE67A2400 +#define DBSC3_1_QOS_W5_BASE 0xE67A2500 +#define DBSC3_1_QOS_W6_BASE 0xE67A2600 +#define DBSC3_1_QOS_W7_BASE 0xE67A2700 +#define DBSC3_1_QOS_W8_BASE 0xE67A2800 +#define DBSC3_1_QOS_W9_BASE 0xE67A2900 +#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 +#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 +#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 +#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 +#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 +#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 +#define DBSC3_1_DBADJ2 0xE67A00C8 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0x9B6C9B5A +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xF08CD810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x05BFE618 +#define MSTP8_BITS 0x40C0FE85 +#define MSTP9_BITS 0xFF979FFF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +#define R8A7791_CUT_ES2X 2 +#define IS_R8A7791_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7791_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7792.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7792.h new file mode 100644 index 000000000..8acd7ba75 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/r8a7792.h + * + * Copyright (C) 2016 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_R8A7792_H +#define __ASM_ARCH_R8A7792_H + +#include "rcar-base.h" + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00400801 +#define MSTP1_BITS 0x9B6F987F +#define MSTP2_BITS 0x108CE100 +#define MSTP3_BITS 0x20004010 +#define MSTP4_BITS 0x80000184 +#define MSTP5_BITS 0x44C00004 +#define MSTP7_BITS 0x01BF0000 +#define MSTP8_BITS 0x1FE01FB0 +#define MSTP9_BITS 0xFE2BFFB2 +#define MSTP10_BITS 0x00001820 +#define MSTP11_BITS 0x00000008 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 + +#endif /* __ASM_ARCH_R8A7792_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7793.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7793.h new file mode 100644 index 000000000..278c7768d --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/r8a7793.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_R8A7793_H +#define __ASM_ARCH_R8A7793_H + +#include "rcar-base.h" + +/* + * R8A7793 I/O Addresses + */ + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + +#define DBSC3_1_QOS_R0_BASE 0xE67A1000 +#define DBSC3_1_QOS_R1_BASE 0xE67A1100 +#define DBSC3_1_QOS_R2_BASE 0xE67A1200 +#define DBSC3_1_QOS_R3_BASE 0xE67A1300 +#define DBSC3_1_QOS_R4_BASE 0xE67A1400 +#define DBSC3_1_QOS_R5_BASE 0xE67A1500 +#define DBSC3_1_QOS_R6_BASE 0xE67A1600 +#define DBSC3_1_QOS_R7_BASE 0xE67A1700 +#define DBSC3_1_QOS_R8_BASE 0xE67A1800 +#define DBSC3_1_QOS_R9_BASE 0xE67A1900 +#define DBSC3_1_QOS_R10_BASE 0xE67A1A00 +#define DBSC3_1_QOS_R11_BASE 0xE67A1B00 +#define DBSC3_1_QOS_R12_BASE 0xE67A1C00 +#define DBSC3_1_QOS_R13_BASE 0xE67A1D00 +#define DBSC3_1_QOS_R14_BASE 0xE67A1E00 +#define DBSC3_1_QOS_R15_BASE 0xE67A1F00 +#define DBSC3_1_QOS_W0_BASE 0xE67A2000 +#define DBSC3_1_QOS_W1_BASE 0xE67A2100 +#define DBSC3_1_QOS_W2_BASE 0xE67A2200 +#define DBSC3_1_QOS_W3_BASE 0xE67A2300 +#define DBSC3_1_QOS_W4_BASE 0xE67A2400 +#define DBSC3_1_QOS_W5_BASE 0xE67A2500 +#define DBSC3_1_QOS_W6_BASE 0xE67A2600 +#define DBSC3_1_QOS_W7_BASE 0xE67A2700 +#define DBSC3_1_QOS_W8_BASE 0xE67A2800 +#define DBSC3_1_QOS_W9_BASE 0xE67A2900 +#define DBSC3_1_QOS_W10_BASE 0xE67A2A00 +#define DBSC3_1_QOS_W11_BASE 0xE67A2B00 +#define DBSC3_1_QOS_W12_BASE 0xE67A2C00 +#define DBSC3_1_QOS_W13_BASE 0xE67A2D00 +#define DBSC3_1_QOS_W14_BASE 0xE67A2E00 +#define DBSC3_1_QOS_W15_BASE 0xE67A2F00 + +#define DBSC3_1_DBADJ2 0xE67A00C8 + +/* + * R8A7793 I/O Product Information + */ + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00640801 +#define MSTP1_BITS 0x9B6C9B5A +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xF08CD810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x44C00046 +#define MSTP7_BITS 0x05BFE618 +#define MSTP8_BITS 0x40C0FE85 +#define MSTP9_BITS 0xFF979FFF +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +#define R8A7793_CUT_ES2X 2 +#define IS_R8A7793_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X) + +#endif /* __ASM_ARCH_R8A7793_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7794.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7794.h new file mode 100644 index 000000000..73259c7ec --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/r8a7794.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_R8A7794_H +#define __ASM_ARCH_R8A7794_H + +#include "rcar-base.h" + +/* SH-I2C */ +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00440801 +#define MSTP1_BITS 0x936899DA +#define MSTP2_BITS 0x100D21FC +#define MSTP3_BITS 0xE084D810 +#define MSTP4_BITS 0x800001C4 +#define MSTP5_BITS 0x40C00044 +#define MSTP7_BITS 0x013FE618 +#define MSTP8_BITS 0x40803C05 +#define MSTP9_BITS 0xFB879FEE +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000001C0 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 + +#define R8A7794_CUT_ES2 2 +#define IS_R8A7794_ES2() \ + (rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2) + +#endif /* __ASM_ARCH_R8A7794_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-base.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-base.h new file mode 100644 index 000000000..a20740679 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -0,0 +1,1046 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/rcar-base.h + * + * Copyright (C) 2013,2014 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_RCAR_BASE_H +#define __ASM_ARCH_RCAR_BASE_H + +/* + * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xFEC00200 +#define DBSC3_0_BASE 0xE6790000 +#define DBSC3_1_BASE 0xE67A0000 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 +#define SH_QSPI_BASE 0xE6B10000 + +/* SCIF */ +#define SCIF0_BASE 0xE6E60000 +#define SCIF1_BASE 0xE6E68000 +#define SCIF2_BASE 0xE6E58000 +#define SCIF3_BASE 0xE6EA8000 +#define SCIF4_BASE 0xE6EE0000 +#define SCIF5_BASE 0xE6EE8000 +#define SCIFA0_BASE 0xE6C40000 +#define SCIFA1_BASE 0xE6C50000 +#define SCIFA2_BASE 0xE6C60000 + +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + +/* + * SH-I2C + * Ch2 and ch3 are different address. These are defined + * in the header of each SoCs. + */ +#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 + +/* RCAR-I2C */ +#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 +#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 +#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 +#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 + +#define S3C_BASE 0xE6784000 +#define S3C_INT_BASE 0xE6784A00 +#define S3C_MEDIA_BASE 0xE6784B00 + +#define S3C_QOS_DCACHE_BASE 0xE6784BDC +#define S3C_QOS_CCI0_BASE 0xE6784C00 +#define S3C_QOS_CCI1_BASE 0xE6784C24 +#define S3C_QOS_MXI_BASE 0xE6784C48 +#define S3C_QOS_AXI_BASE 0xE6784C6C + +#define DBSC3_0_QOS_R0_BASE 0xE6791000 +#define DBSC3_0_QOS_R1_BASE 0xE6791100 +#define DBSC3_0_QOS_R2_BASE 0xE6791200 +#define DBSC3_0_QOS_R3_BASE 0xE6791300 +#define DBSC3_0_QOS_R4_BASE 0xE6791400 +#define DBSC3_0_QOS_R5_BASE 0xE6791500 +#define DBSC3_0_QOS_R6_BASE 0xE6791600 +#define DBSC3_0_QOS_R7_BASE 0xE6791700 +#define DBSC3_0_QOS_R8_BASE 0xE6791800 +#define DBSC3_0_QOS_R9_BASE 0xE6791900 +#define DBSC3_0_QOS_R10_BASE 0xE6791A00 +#define DBSC3_0_QOS_R11_BASE 0xE6791B00 +#define DBSC3_0_QOS_R12_BASE 0xE6791C00 +#define DBSC3_0_QOS_R13_BASE 0xE6791D00 +#define DBSC3_0_QOS_R14_BASE 0xE6791E00 +#define DBSC3_0_QOS_R15_BASE 0xE6791F00 +#define DBSC3_0_QOS_W0_BASE 0xE6792000 +#define DBSC3_0_QOS_W1_BASE 0xE6792100 +#define DBSC3_0_QOS_W2_BASE 0xE6792200 +#define DBSC3_0_QOS_W3_BASE 0xE6792300 +#define DBSC3_0_QOS_W4_BASE 0xE6792400 +#define DBSC3_0_QOS_W5_BASE 0xE6792500 +#define DBSC3_0_QOS_W6_BASE 0xE6792600 +#define DBSC3_0_QOS_W7_BASE 0xE6792700 +#define DBSC3_0_QOS_W8_BASE 0xE6792800 +#define DBSC3_0_QOS_W9_BASE 0xE6792900 +#define DBSC3_0_QOS_W10_BASE 0xE6792A00 +#define DBSC3_0_QOS_W11_BASE 0xE6792B00 +#define DBSC3_0_QOS_W12_BASE 0xE6792C00 +#define DBSC3_0_QOS_W13_BASE 0xE6792D00 +#define DBSC3_0_QOS_W14_BASE 0xE6792E00 +#define DBSC3_0_QOS_W15_BASE 0xE6792F00 +#define DBSC3_0_DBADJ2 0xE67900C8 + +#define CCI_400_MAXOT_1 0xF0091110 +#define CCI_400_MAXOT_2 0xF0092110 +#define CCI_400_QOSCNTL_1 0xF009110C +#define CCI_400_QOSCNTL_2 0xF009210C + +#define MXI_BASE 0xFE960000 +#define MXI_QOS_BASE 0xFE960300 + +#define SYS_AXI_SYX64TO128_BASE 0xFF800300 +#define SYS_AXI_AVB_BASE 0xFF800340 +#define SYS_AXI_AX2M_BASE 0xFF800380 +#define SYS_AXI_CC50_BASE 0xFF8003C0 +#define SYS_AXI_CCI_BASE 0xFF800440 +#define SYS_AXI_CS_BASE 0xFF800480 +#define SYS_AXI_DDM_BASE 0xFF8004C0 +#define SYS_AXI_ETH_BASE 0xFF800500 +#define SYS_AXI_G2D_BASE 0xFF800540 +#define SYS_AXI_IMP0_BASE 0xFF800580 +#define SYS_AXI_IMP1_BASE 0xFF8005C0 +#define SYS_AXI_IMUX0_BASE 0xFF800600 +#define SYS_AXI_IMUX1_BASE 0xFF800640 +#define SYS_AXI_IMUX2_BASE 0xFF800680 +#define SYS_AXI_LBS_BASE 0xFF8006C0 +#define SYS_AXI_MMUDS_BASE 0xFF800700 +#define SYS_AXI_MMUM_BASE 0xFF800740 +#define SYS_AXI_MMUR_BASE 0xFF800780 +#define SYS_AXI_MMUS0_BASE 0xFF8007C0 +#define SYS_AXI_MMUS1_BASE 0xFF800800 +#define SYS_AXI_MPXM_BASE 0xFF800840 +#define SYS_AXI_MTSB0_BASE 0xFF800880 +#define SYS_AXI_MTSB1_BASE 0xFF8008C0 +#define SYS_AXI_PCI_BASE 0xFF800900 +#define SYS_AXI_RTX_BASE 0xFF800940 +#define SYS_AXI_SAT0_BASE 0xFF800980 +#define SYS_AXI_SAT1_BASE 0xFF8009C0 +#define SYS_AXI_SDM0_BASE 0xFF800A00 +#define SYS_AXI_SDM1_BASE 0xFF800A40 +#define SYS_AXI_SDS0_BASE 0xFF800A80 +#define SYS_AXI_SDS1_BASE 0xFF800AC0 +#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */ +#define SYS_AXI_UDM0_BASE 0xFF800B80 +#define SYS_AXI_UDM1_BASE 0xFF800BC0 +#define SYS_AXI_USB20_BASE 0xFF800C00 +#define SYS_AXI_USB21_BASE 0xFF800C40 +#define SYS_AXI_USB22_BASE 0xFF800C80 +#define SYS_AXI_USB30_BASE 0xFF800CC0 +#define SYS_AXI_ADM_BASE 0xFF800D00 +#define SYS_AXI_ADS_BASE 0xFF800D40 +#define SYS_AXI_SYX_BASE 0xFF800FB8 + +#define SYS_AXI_AXI64TO128W_BASE 0xFF801300 +#define SYS_AXI_AVBW_BASE 0xFF801340 +#define SYS_AXI_CC50W_BASE 0xFF8013C0 +#define SYS_AXI_CCIW_BASE 0xFF801440 +#define SYS_AXI_CSW_BASE 0xFF801480 +#define SYS_AXI_G2DW_BASE 0xFF801540 +#define SYS_AXI_IMUX0W_BASE 0xFF801600 +#define SYS_AXI_IMUX1W_BASE 0xFF801640 +#define SYS_AXI_IMUX2W_BASE 0xFF801680 +#define SYS_AXI_LBSW_BASE 0xFF8016C0 +#define SYS_AXI_RTXW_BASE 0xFF801940 +#define SYS_AXI_SDM0W_BASE 0xFF801A00 +#define SYS_AXI_SDM1W_BASE 0xFF801A40 +#define SYS_AXI_SDS0W_BASE 0xFF801A80 +#define SYS_AXI_SDS1W_BASE 0xFF801AC0 +#define SYS_AXI_TRABW_BASE 0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */ +#define SYS_AXI_UDM0W_BASE 0xFF801B80 +#define SYS_AXI_UDM1W_BASE 0xFF801BC0 +#define SYS_AXI_ADMW_BASE 0xFF801D00 +#define SYS_AXI_ADSW_BASE 0xFF801D40 +#define SYS_AXI_SYXW_BASE 0xFF801FB8 + +#define RT_AXI_SHX_BASE 0xFF810100 +#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */ +#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */ +#define RT_AXI_RDS_BASE 0xFF8101C0 +#define RT_AXI_RTX64TO128_BASE 0xFF810200 +#define RT_AXI_STPRO_BASE 0xFF810240 +#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */ +#define RT_AXI_RT_BASE 0xFF810FC0 +#define RT_AXI_SHXW_BASE 0xFF811100 +#define RT_AXI_DBGW_BASE 0xFF811140 +#define RT_AXI_RTX64TO128W_BASE 0xFF811200 +#define RT_AXI_RTW_BASE 0xFF811FC0 + +#define MP_AXI_ADSP_BASE 0xFF820100 +#define MP_AXI_ASDS0_BASE 0xFF8201C0 +#define MP_AXI_ASDS1_BASE 0xFF820200 +#define MP_AXI_MLP_BASE 0xFF820240 +#define MP_AXI_MMUMP_BASE 0xFF820280 +#define MP_AXI_SPU_BASE 0xFF8202C0 +#define MP_AXI_SPUC_BASE 0xFF820300 + +#define SYS_AXI256_AXI128TO256_BASE 0xFF860100 +#define SYS_AXI256_SYX_BASE 0xFF860140 +#define SYS_AXI256_AXM_BASE 0xFF860140 +#define SYS_AXI256_MPX_BASE 0xFF860180 +#define SYS_AXI256_MXI_BASE 0xFF8601C0 +#define SYS_AXI256_IMP0_BASE 0xFF860580 +#define SYS_AXI256_SY2_BASE 0xFF860FC0 +#define SYS_AXI256_AXI128TO256W_BASE 0xFF861100 +#define SYS_AXI256_AXMW_BASE 0xFF861140 +#define SYS_AXI256_MXIW_BASE 0xFF8611C0 +#define SYS_AXI256_IMP0W_BASE 0xFF861580 +#define SYS_AXI256_SY2W_BASE 0xFF861FC0 + +#define CCI_AXI_MMUS0_BASE 0xFF880100 +#define CCI_AXI_SYX2_BASE 0xFF880140 +#define CCI_AXI_MMUR_BASE 0xFF880180 +#define CCI_AXI_MMUDS_BASE 0xFF8801C0 +#define CCI_AXI_MMUM_BASE 0xFF880200 +#define CCI_AXI_MXI_BASE 0xFF880240 +#define CCI_AXI_MMUS1_BASE 0xFF880280 +#define CCI_AXI_MMUMP_BASE 0xFF8802C0 + +#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */ +#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */ +#define MEDIA_AXI_JPR_BASE 0xFE964100 +#define MEDIA_AXI_JPW_BASE 0xFE966100 +#define MEDIA_AXI_GCU0R_BASE 0xFE964140 +#define MEDIA_AXI_GCU0W_BASE 0xFE966140 +#define MEDIA_AXI_GCU1R_BASE 0xFE964180 +#define MEDIA_AXI_GCU1W_BASE 0xFE966180 +#define MEDIA_AXI_TDMR_BASE 0xFE964500 +#define MEDIA_AXI_TDMW_BASE 0xFE966500 +#define MEDIA_AXI_VSP0CR_BASE 0xFE964540 +#define MEDIA_AXI_VSP0CW_BASE 0xFE966540 +#define MEDIA_AXI_VSP1CR_BASE 0xFE964580 +#define MEDIA_AXI_VSP1CW_BASE 0xFE966580 +#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0 +#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0 +#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600 +#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600 +#define MEDIA_AXI_FDP0R_BASE 0xFE964D40 +#define MEDIA_AXI_FDP0W_BASE 0xFE966D40 +#define MEDIA_AXI_IMSR_BASE 0xFE964D80 +#define MEDIA_AXI_IMSW_BASE 0xFE966D80 +#define MEDIA_AXI_VSP1R_BASE 0xFE965100 +#define MEDIA_AXI_VSP1W_BASE 0xFE967100 +#define MEDIA_AXI_FDP1R_BASE 0xFE965140 +#define MEDIA_AXI_FDP1W_BASE 0xFE967140 +#define MEDIA_AXI_IMRR_BASE 0xFE965180 +#define MEDIA_AXI_IMRW_BASE 0xFE967180 +#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0 +#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0 +#define MEDIA_AXI_DU1R_BASE 0xFE9655C0 +#define MEDIA_AXI_DU1W_BASE 0xFE9675C0 +#define MEDIA_AXI_VCP0CR_BASE 0xFE965900 +#define MEDIA_AXI_VCP0CW_BASE 0xFE967900 +#define MEDIA_AXI_VCP0VR_BASE 0xFE965940 +#define MEDIA_AXI_VCP0VW_BASE 0xFE967940 +#define MEDIA_AXI_VPC0R_BASE 0xFE965980 +#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00 +#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00 +#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40 +#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40 +#define MEDIA_AXI_VPC1R_BASE 0xFE965D80 + +#if defined (CONFIG_R8A7792) +#define MEDIA_AXI_VCTU0R_BASE 0xFE964500 /* R8A7792 */ +#define MEDIA_AXI_VCTU0W_BASE 0xFE966500 +#define MEDIA_AXI_VDCTU0R_BASE 0xFE964540 +#define MEDIA_AXI_VDCTU0W_BASE 0xFE966540 +#define MEDIA_AXI_VDCTU1R_BASE 0xFE964580 +#define MEDIA_AXI_VDCTU1W_BASE 0xFE966580 +#define MEDIA_AXI_VIN0W_BASE 0xFE967580 +#define MEDIA_AXI_VIN1W_BASE 0xFE966D80 +#define MEDIA_AXI_RDRW_BASE 0xFE9675C0 +#define MEDIA_AXI_IMS01R_BASE 0xFE965500 +#define MEDIA_AXI_IMS01W_BASE 0xFE967500 +#define MEDIA_AXI_IMS23R_BASE 0xFE965540 /* FIXME */ +#define MEDIA_AXI_IMS23W_BASE 0xFE967540 +#define MEDIA_AXI_IMS45R_BASE 0xFE964D00 +#define MEDIA_AXI_IMS45W_BASE 0xFE966D00 +#define MEDIA_AXI_ROTCE4R_BASE 0xFE965100 +#define MEDIA_AXI_ROTCE4W_BASE 0xFE967100 +#define MEDIA_AXI_ROTVLC4R_BASE 0xFE965140 +#define MEDIA_AXI_ROTVLC4W_BASE 0xFE965140 +#define MEDIA_AXI_VSPD0R_BASE 0xFE964900 +#define MEDIA_AXI_VSPD0W_BASE 0xFE966900 +#define MEDIA_AXI_VSPD1R_BASE 0xFE964940 +#define MEDIA_AXI_VSPD1W_BASE 0xFE966940 +#define MEDIA_AXI_DU0R_BASE 0xFE964980 +#define MEDIA_AXI_DU0W_BASE 0xFE966980 +#define MEDIA_AXI_VSP0R_BASE 0xFE9649C0 +#define MEDIA_AXI_VSP0W_BASE 0xFE9669C0 +#define MEDIA_AXI_ROTCE0R_BASE 0xFE965900 +#define MEDIA_AXI_ROTCE0W_BASE 0xFE967900 +#define MEDIA_AXI_ROTVLC0R_BASE 0xFE965940 +#define MEDIA_AXI_ROTVLC0W_BASE 0xFE967940 +#define MEDIA_AXI_ROTCE1R_BASE 0xFE965980 +#define MEDIA_AXI_ROTCE1W_BASE 0xFE967980 +#define MEDIA_AXI_ROTVLC1R_BASE 0xFE9659C0 +#define MEDIA_AXI_ROTVLC1W_BASE 0xFE9679C0 +#define MEDIA_AXI_ROTCE2R_BASE 0xFE965D00 +#define MEDIA_AXI_ROTCE2W_BASE 0xFE967D00 +#define MEDIA_AXI_ROTVLC2R_BASE 0xFE965D40 +#define MEDIA_AXI_ROTVLC2W_BASE 0xFE967D40 +#define MEDIA_AXI_ROTCE3R_BASE 0xFE965D80 +#define MEDIA_AXI_ROTCE3W_BASE 0xFE967D80 +#define MEDIA_AXI_ROTVLC3R_BASE 0xFE965DC0 +#define MEDIA_AXI_ROTVLC3W_BASE 0xFE967DC0 +#else /* R8A7792 */ +#define MEDIA_AXI_VIN0W_BASE 0xFE966900 +#define MEDIA_AXI_VSPD0R_BASE 0xFE965500 +#define MEDIA_AXI_VSPD0W_BASE 0xFE967500 +#define MEDIA_AXI_VSPD1R_BASE 0xFE965540 +#define MEDIA_AXI_VSPD1W_BASE 0xFE967540 +#define MEDIA_AXI_DU0R_BASE 0xFE965580 +#define MEDIA_AXI_DU0W_BASE 0xFE967580 +#define MEDIA_AXI_VSP0R_BASE 0xFE964D00 +#define MEDIA_AXI_VSP0W_BASE 0xFE966D00 +#endif /* R8A7792 */ + + +#define SYS_AXI_AVBDMSCR 0xFF802000 +#define SYS_AXI_SYX2DMSCR 0xFF802004 +#define SYS_AXI_AX2MDMSCR 0xFF802004 +#define SYS_AXI_CC50DMSCR 0xFF802008 +#define SYS_AXI_CC51DMSCR 0xFF80200C +#define SYS_AXI_CCIDMSCR 0xFF802010 +#define SYS_AXI_CSDMSCR 0xFF802014 +#define SYS_AXI_DDMDMSCR 0xFF802018 +#define SYS_AXI_ETHDMSCR 0xFF80201C +#define SYS_AXI_G2DDMSCR 0xFF802020 +#define SYS_AXI_IMP0DMSCR 0xFF802024 +#define SYS_AXI_IMP1DMSCR 0xFF802028 +#define SYS_AXI_LBSDMSCR 0xFF80202C +#define SYS_AXI_MMUDSDMSCR 0xFF802030 +#define SYS_AXI_MMUMXDMSCR 0xFF802034 +#define SYS_AXI_MMURDDMSCR 0xFF802038 +#define SYS_AXI_MMUS0DMSCR 0xFF80203C +#define SYS_AXI_MMUS1DMSCR 0xFF802040 +#define SYS_AXI_MPXDMSCR 0xFF802044 +#define SYS_AXI_MTSB0DMSCR 0xFF802048 +#define SYS_AXI_MTSB1DMSCR 0xFF80204C +#define SYS_AXI_PCIDMSCR 0xFF802050 +#define SYS_AXI_RTXDMSCR 0xFF802054 +#define SYS_AXI_SAT0DMSCR 0xFF802058 +#define SYS_AXI_SAT1DMSCR 0xFF80205C +#define SYS_AXI_SDM0DMSCR 0xFF802060 +#define SYS_AXI_SDM1DMSCR 0xFF802064 +#define SYS_AXI_SDS0DMSCR 0xFF802068 +#define SYS_AXI_SDS1DMSCR 0xFF80206C +#define SYS_AXI_ETRABDMSCR 0xFF802070 +#define SYS_AXI_ETRKFDMSCR 0xFF802074 +#define SYS_AXI_UDM0DMSCR 0xFF802078 +#define SYS_AXI_UDM1DMSCR 0xFF80207C +#define SYS_AXI_USB20DMSCR 0xFF802080 +#define SYS_AXI_USB21DMSCR 0xFF802084 +#define SYS_AXI_USB22DMSCR 0xFF802088 +#define SYS_AXI_USB30DMSCR 0xFF80208C +#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100 +#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104 +#define SYS_AXI_AVBSLVDMSCR 0xFF802108 +#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C +#define SYS_AXI_AX2SLVDMSCR 0xFF80210C +#define SYS_AXI_ETHSLVDMSCR 0xFF802110 +#define SYS_AXI_GICSLVDMSCR 0xFF802114 +#define SYS_AXI_IMPSLVDMSCR 0xFF802118 +#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C +#define SYS_AXI_IMX1SLVDMSCR 0xFF802120 +#define SYS_AXI_IMX2SLVDMSCR 0xFF802124 +#define SYS_AXI_LBSSLVDMSCR 0xFF802128 +#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C +#define SYS_AXI_MMC1SLVDMSCR 0xFF802130 +#define SYS_AXI_MPXSLVDMSCR 0xFF802134 +#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138 +#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C +#define SYS_AXI_MXTSLVDMSCR 0xFF802140 +#define SYS_AXI_PCISLVDMSCR 0xFF802144 +#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148 +#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C +#define SYS_AXI_RTXSLVDMSCR 0xFF802150 +#define SYS_AXI_SAPC1SLVDMSCR 0xFF802154 +#define SYS_AXI_SAPC2SLVDMSCR 0xFF802158 +#define SYS_AXI_SAPC3SLVDMSCR 0xFF80215C +#define SYS_AXI_SAPC65SLVDMSCR 0xFF802160 +#define SYS_AXI_SAPC8SLVDMSCR 0xFF802164 +#define SYS_AXI_SAT0SLVDMSCR 0xFF802168 +#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C +#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170 +#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174 +#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178 +#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C +#define SYS_AXI_SGXSLVDMSCR 0xFF802180 +#define SYS_AXI_SGXSLV1SLVDMSCR 0xFF802184 +#define SYS_AXI_STBSLVDMSCR 0xFF802188 +#define SYS_AXI_STMSLVDMSCR 0xFF80218C +#define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR 0xFF802190 +#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194 +#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198 +#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C +#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0 +#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4 +#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8 +#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC +#define SYS_AXI_UTLBDSSLVDMSCR 0xFF8021B0 +#define SYS_AXI_UTLBS0SLVDMSCR 0xFF8021B4 +#define SYS_AXI_UTLBS1SLVDMSCR 0xFF8021B8 +#define SYS_AXI_ROT0DMSCR 0xFF802320 +#define SYS_AXI_ROT1DMSCR 0xFF802324 +#define SYS_AXI_ROT2DMSCR 0xFF802328 +#define SYS_AXI_ROT3DMSCR 0xFF80232C +#define SYS_AXI_ROT4DMSCR 0xFF802330 +#define SYS_AXI_IMUX3SLVDMSCR 0xFF802334 +#define SYS_AXI_STBR0SLVDMSCR 0xFF803200 +#define SYS_AXI_STBR0PSLVDMSCR 0xFF803204 +#define SYS_AXI_STBR0XSLVDMSCR 0xFF803208 +#define SYS_AXI_STBR1SLVDMSCR 0xFF803210 +#define SYS_AXI_STBR1PSLVDMSCR 0xFF803214 +#define SYS_AXI_STBR1XSLVDMSCR 0xFF803218 +#define SYS_AXI_STBR2SLVDMSCR 0xFF803220 +#define SYS_AXI_STBR2PSLVDMSCR 0xFF803224 +#define SYS_AXI_STBR2XSLVDMSCR 0xFF803228 +#define SYS_AXI_STBR3SLVDMSCR 0xFF803230 +#define SYS_AXI_STBR3PSLVDMSCR 0xFF803234 +#define SYS_AXI_STBR3XSLVDMSCR 0xFF803238 +#define SYS_AXI_STBR4SLVDMSCR 0xFF803240 +#define SYS_AXI_STBR4PSLVDMSCR 0xFF803244 +#define SYS_AXI_STBR4XSLVDMSCR 0xFF803248 +#define SYS_AXI_ADM_DMSCR 0xFF803260 +#define SYS_AXI_ADS_DMSCR 0xFF803264 + +#define RT_AXI_CBMDMSCR 0xFF812000 +#define RT_AXI_DBDMSCR 0xFF812004 +#define RT_AXI_RDMDMSCR 0xFF812008 +#define RT_AXI_RDSDMSCR 0xFF81200C +#define RT_AXI_STRDMSCR 0xFF812010 +#define RT_AXI_SY2RTDMSCR 0xFF812014 +#define RT_AXI_CBSSLVDMSCR 0xFF812100 +#define RT_AXI_DBSSLVDMSCR 0xFF812104 +#define RT_AXI_RTAP1SLVDMSCR 0xFF812108 +#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C +#define RT_AXI_RTAP3SLVDMSCR 0xFF812110 +#define RT_AXI_RT2SYSLVDMSCR 0xFF812114 +#define RT_AXI_A128TO64SLVDMSCR 0xFF812118 +#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C +#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120 +#define RT_AXI_UTLBRSLVDMSCR 0xFF812128 + +#define MP_AXI_ADSPDMSCR 0xFF822000 +#define MP_AXI_ASDM0DMSCR 0xFF822004 +#define MP_AXI_ASDM1DMSCR 0xFF822008 +#define MP_AXI_ASDS0DMSCR 0xFF82200C +#define MP_AXI_ASDS1DMSCR 0xFF822010 +#define MP_AXI_MLPDMSCR 0xFF822014 +#define MP_AXI_MMUMPDMSCR 0xFF822018 +#define MP_AXI_SPUDMSCR 0xFF82201C +#define MP_AXI_SPUCDMSCR 0xFF822020 +#define MP_AXI_SY2MPDMSCR 0xFF822024 +#define MP_AXI_ADSPSLVDMSCR 0xFF822100 +#define MP_AXI_MLMSLVDMSCR 0xFF822104 +#define MP_AXI_MPAP4SLVDMSCR 0xFF822108 +#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C +#define MP_AXI_MPAP6SLVDMSCR 0xFF822110 +#define MP_AXI_MPAP7SLVDMSCR 0xFF822114 +#define MP_AXI_MP2SYSLVDMSCR 0xFF822118 +#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C +#define MP_AXI_MPXAPSLVDMSCR 0xFF822124 +#define MP_AXI_SPUSLVDMSCR 0xFF822128 +#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C + +#define ADM_AXI_ASDM0DMSCR 0xFF842000 +#define ADM_AXI_ASDM1DMSCR 0xFF842004 +#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104 +#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108 +#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C + +#define DM_AXI_DMAXICONF 0xFF850000 +#define DM_AXI_DMAPBCONF 0xFF850004 +#define DM_AXI_DMADMCONF 0xFF850020 +#define DM_AXI_DMSDM0CONF 0xFF850024 +#define DM_AXI_DMSDM1CONF 0xFF850028 +#define DM_AXI_DMQSPAPSLVCONF 0xFF850030 +#define DM_AXI_RAPD4SLVCONF 0xFF850034 +#define DM_AXI_SAPD4SLVCONF 0xFF85003C +#define DM_AXI_SAPD5SLVCONF 0xFF850040 +#define DM_AXI_SAPD6SLVCONF 0xFF850044 +#define DM_AXI_SAPD65DSLVCONF 0xFF850048 +#define DM_AXI_SDAP0SLVCONF 0xFF85004C +#define DM_AXI_MAPD2SLVCONF 0xFF850050 +#define DM_AXI_MAPD3SLVCONF 0xFF850054 +#define DM_AXI_DMXXDEFAULTSLAVESLVCONF 0xFF850058 +#define DM_AXI_DMADMRQOSCONF 0xFF850100 +#define DM_AXI_DMADMRQOSCTSET0 0xFF850104 +#define DM_AXI_DMADMRQOSREQCTR 0xFF850114 +#define DM_AXI_DMADMRQOSQON 0xFF850124 +#define DM_AXI_DMADMRQOSIN 0xFF850128 +#define DM_AXI_DMADMRQOSSTAT 0xFF85012C +#define DM_AXI_DMSDM0RQOSCONF 0xFF850140 +#define DM_AXI_DMSDM0RQOSCTSET0 0xFF850144 +#define DM_AXI_DMSDM0RQOSREQCTR 0xFF850154 +#define DM_AXI_DMSDM0RQOSQON 0xFF850164 +#define DM_AXI_DMSDM0RQOSIN 0xFF850168 +#define DM_AXI_DMSDM0RQOSSTAT 0xFF85016C +#define DM_AXI_DMSDM1RQOSCONF 0xFF850180 +#define DM_AXI_DMSDM1RQOSCTSET0 0xFF850184 +#define DM_AXI_DMSDM1RQOSREQCTR 0xFF850194 +#define DM_AXI_DMSDM1RQOSQON 0xFF8501A4 +#define DM_AXI_DMSDM1RQOSIN 0xFF8501A8 +#define DM_AXI_DMSDM1RQOSSTAT 0xFF8501AC +#define DM_AXI_DMRQOSCTSET1 0xFF850FC0 +#define DM_AXI_DMRQOSCTSET2 0xFF850FC4 +#define DM_AXI_DMRQOSCTSET3 0xFF850FC8 +#define DM_AXI_DMRQOSTHRES0 0xFF850FCC +#define DM_AXI_DMRQOSTHRES1 0xFF850FD0 +#define DM_AXI_DMRQOSTHRES2 0xFF850FD4 +#define DM_AXI_DMADMWQOSCONF 0xFF851100 +#define DM_AXI_DMADMWQOSCTSET0 0xFF851104 +#define DM_AXI_DMADMWQOSREQCTR 0xFF851114 +#define DM_AXI_DMADMWQOSQON 0xFF851124 +#define DM_AXI_DMADMWQOSIN 0xFF851128 +#define DM_AXI_DMADMWQOSSTAT 0xFF85112C +#define DM_AXI_DMSDM0WQOSCONF 0xFF851140 +#define DM_AXI_DMSDM0WQOSCTSET0 0xFF851144 +#define DM_AXI_DMSDM0WQOSREQCTR 0xFF851154 +#define DM_AXI_DMSDM0WQOSQON 0xFF851164 +#define DM_AXI_DMSDM0WQOSIN 0xFF851168 +#define DM_AXI_DMSDM0WQOSSTAT 0xFF85116C +#define DM_AXI_DMSDM1WQOSCONF 0xFF851180 +#define DM_AXI_DMSDM1WQOSCTSET0 0xFF851184 +#define DM_AXI_DMSDM1WQOSREQCTR 0xFF851194 +#define DM_AXI_DMSDM1WQOSQON 0xFF8511A4 +#define DM_AXI_DMSDM1WQOSIN 0xFF8511A8 +#define DM_AXI_DMSDM1WQOSSTAT 0xFF8511AC +#define DM_AXI_DMWQOSCTSET1 0xFF851FC0 +#define DM_AXI_DMWQOSCTSET2 0xFF851FC4 +#define DM_AXI_DMWQOSCTSET3 0xFF851FC8 +#define DM_AXI_DMWQOSTHRES0 0xFF851FCC +#define DM_AXI_DMWQOSTHRES1 0xFF851FD0 +#define DM_AXI_DMWQOSTHRES2 0xFF851FD4 + +#define DM_AXI_RDMDMSCR 0xFF852000 +#define DM_AXI_SDM0DMSCR 0xFF852004 +#define DM_AXI_SDM1DMSCR 0xFF852008 +#if defined(CONFIG_R8A7792) +#define DM_AXI_DMQSPAPSLVDMSCR 0xFF852104 +#define DM_AXI_RAPD4SLVDMSCR 0xFF852108 +#define DM_AXI_SAPD4SLVDMSCR 0xFF852110 +#define DM_AXI_SAPD5SLVDMSCR 0xFF852114 +#define DM_AXI_SAPD6SLVDMSCR 0xFF852118 +#define DM_AXI_SAPD65DSLVDMSCR 0xFF85211C +#define DM_AXI_SDAP0SLVDMSCR 0xFF852120 +#define DM_AXI_MAPD2SLVDMSCR 0xFF852124 +#define DM_AXI_MAPD3SLVDMSCR 0xFF852128 +#define DM_AXI_DMXXDEFAULTSLAVESLVDMSCR 0xFF85212C +#define DM_AXI_DMXREGDMSENN 0xFF852200 +#else +#define DM_AXI_MMAP0SLVDMSCR 0xFF852100 +#define DM_AXI_MMAP1SLVDMSCR 0xFF852104 +#define DM_AXI_QSPAPSLVDMSCR 0xFF852108 +#define DM_AXI_RAP4SLVDMSCR 0xFF85210C +#define DM_AXI_RAP5SLVDMSCR 0xFF852110 +#define DM_AXI_SAP4SLVDMSCR 0xFF852114 +#define DM_AXI_SAP5SLVDMSCR 0xFF852118 +#define DM_AXI_SAP6SLVDMSCR 0xFF85211C +#define DM_AXI_SAP65SLVDMSCR 0xFF852120 +#define DM_AXI_SDAP0SLVDMSCR 0xFF852124 +#define DM_AXI_SDAP1SLVDMSCR 0xFF852128 +#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C +#define DM_AXI_SDAP3SLVDMSCR 0xFF852130 +#endif + +#define SYS_AXI256_SYXDMSCR 0xFF862000 +#define SYS_AXI256_MPXDMSCR 0xFF862004 +#define SYS_AXI256_MXIDMSCR 0xFF862008 +#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100 +#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104 +#define SYS_AXI256_SYXSLVDMSCR 0xFF862108 +#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C +#define SYS_AXI256_S3CSLVDMSCR 0xFF862110 + +#define MXT_SYXDMSCR 0xFF872000 +#if defined(CONFIG_R8A7792) +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VSP1SLVDMSCR 0xFF87211C +#define MXT_VSPD0SLVDMSCR 0xFF872120 +#define MXT_VSPD1SLVDMSCR 0xFF872124 +#define MXT_MAP1SLVDMSCR 0xFF872128 +#define MXT_MAP2SLVDMSCR 0xFF87212C +#define MXT_MAP2BSLVDMSCR 0xFF872134 +#else /* R8A7792 */ +#define MXT_CMM0SLVDMSCR 0xFF872100 +#define MXT_CMM1SLVDMSCR 0xFF872104 +#define MXT_CMM2SLVDMSCR 0xFF872108 +#define MXT_FDPSLVDMSCR 0xFF87210C +#define MXT_IMRSLVDMSCR 0xFF872110 +#define MXT_VINSLVDMSCR 0xFF872114 +#define MXT_VPC0SLVDMSCR 0xFF872118 +#define MXT_VPC1SLVDMSCR 0xFF87211C +#define MXT_VSP0SLVDMSCR 0xFF872120 +#define MXT_VSP1SLVDMSCR 0xFF872124 +#define MXT_VSPD0SLVDMSCR 0xFF872128 +#define MXT_VSPD1SLVDMSCR 0xFF87212C +#define MXT_MAP1SLVDMSCR 0xFF872130 +#define MXT_MAP2SLVDMSCR 0xFF872134 +#endif /* R8A7792 */ + +/* DMS Register (MXI) */ +#if defined(CONFIG_R8A7792) +#define MXI_JPURDMSCR 0xFE964200 +#define MXI_JPUWDMSCR 0xFE966200 +#define MXI_VCTU0RDMSCR 0xFE964600 +#define MXI_VCTU0WDMSCR 0xFE966600 +#define MXI_VDCTU0RDMSCR 0xFE964604 +#define MXI_VDCTU0WDMSCR 0xFE966604 +#define MXI_VDCTU1RDMSCR 0xFE964608 +#define MXI_VDCTU1WDMSCR 0xFE966608 +#define MXI_VIN0WDMSCR 0xFE967608 +#define MXI_VIN1WDMSCR 0xFE966E08 +#define MXI_RDRWDMSCR 0xFE96760C +#define MXI_IMS01RDMSCR 0xFE965600 +#define MXI_IMS01WDMSCR 0xFE967600 +#define MXI_IMS23RDMSCR 0xFE965604 +#define MXI_IMS23WDMSCR 0xFE967604 +#define MXI_IMS45RDMSCR 0xFE964E00 +#define MXI_IMS45WDMSCR 0xFE966E00 +#define MXI_IMRRDMSCR 0xFE964E04 +#define MXI_IMRWDMSCR 0xFE966E04 +#define MXI_ROTCE4RDMSCR 0xFE965200 +#define MXI_ROTCE4WDMSCR 0xFE967200 +#define MXI_ROTVLC4RDMSCR 0xFE965204 +#define MXI_ROTVLC4WDMSCR 0xFE967204 +#define MXI_VSPD0RDMSCR 0xFE964A00 +#define MXI_VSPD0WDMSCR 0xFE966A00 +#define MXI_VSPD1RDMSCR 0xFE964A04 +#define MXI_VSPD1WDMSCR 0xFE966A04 +#define MXI_DU0RDMSCR 0xFE964A08 +#define MXI_DU0WDMSCR 0xFE966A08 +#define MXI_VSP0RDMSCR 0xFE964A0C +#define MXI_VSP0WDMSCR 0xFE966A0C +#define MXI_ROTCE0RDMSCR 0xFE965A00 +#define MXI_ROTCE0WDMSCR 0xFE967A00 +#define MXI_ROTVLC0RDMSCR 0xFE965A04 +#define MXI_ROTVLC0WDMSCR 0xFE967A04 +#define MXI_ROTCE1RDMSCR 0xFE965A08 +#define MXI_ROTCE1WDMSCR 0xFE967A08 +#define MXI_ROTVLC1RDMSCR 0xFE965A0C +#define MXI_ROTVLC1WDMSCR 0xFE967A0C +#define MXI_ROTCE2RDMSCR 0xFE965E00 +#define MXI_ROTCE2WDMSCR 0xFE967E00 +#define MXI_ROTVLC2RDMSCR 0xFE965E04 +#define MXI_ROTVLC2WDMSCR 0xFE967E04 +#define MXI_ROTCE3RDMSCR 0xFE965E08 +#define MXI_ROTCE3WDMSCR 0xFE967E08 +#define MXI_ROTVLC3RDMSCR 0xFE965E0C +#define MXI_ROTVLC3WDMSCR 0xFE967E0C +#endif /* R8A7792 */ + +#define CCI_AXI_MMUS0DMSCR 0xFF882000 +#define CCI_AXI_SYX2DMSCR 0xFF882004 +#define CCI_AXI_MMURDMSCR 0xFF882008 +#define CCI_AXI_MMUDSDMSCR 0xFF88200C +#define CCI_AXI_MMUMDMSCR 0xFF882010 +#define CCI_AXI_MXIDMSCR 0xFF882014 +#define CCI_AXI_MMUS1DMSCR 0xFF882018 +#define CCI_AXI_MMUMPDMSCR 0xFF88201C +#define CCI_AXI_DVMDMSCR 0xFF882020 +#define CCI_AXI_CCISLVDMSCR 0xFF882100 + +#define CCI_AXI_IPMMUIDVMCR 0xFF880400 +#define CCI_AXI_IPMMURDVMCR 0xFF880404 +#define CCI_AXI_IPMMUS0DVMCR 0xFF880408 +#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C +#define CCI_AXI_IPMMUMPDVMCR 0xFF880410 +#define CCI_AXI_IPMMUDSDVMCR 0xFF880414 +#define CCI_AXI_AX2ADDRMASK 0xFF88041C + +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_BIT 24 +#define PLLECR 0xE61500D0 +#define PLL0ST 0x100 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct rcar_rwdt { + u32 rwtcnt; /* 0x00 */ + u32 rwtcsra; /* 0x04 */ + u16 rwtcsrb; /* 0x08 */ +}; + +/* SWDT */ +struct rcar_swdt { + u32 swtcnt; /* 0x00 */ + u32 swtcsra; /* 0x04 */ + u16 swtcsrb; /* 0x08 */ +}; + +/* LBSC */ +struct rcar_lbsc { + u32 cs0ctrl; + u32 cs1ctrl; + u32 ecs0ctrl; + u32 ecs1ctrl; + u32 ecs2ctrl; + u32 ecs3ctrl; + u32 ecs4ctrl; + u32 ecs5ctrl; + u32 dummy0[4]; /* 0x20 .. 0x2C */ + u32 cswcr0; + u32 cswcr1; + u32 ecswcr0; + u32 ecswcr1; + u32 ecswcr2; + u32 ecswcr3; + u32 ecswcr4; + u32 ecswcr5; + u32 exdmawcr0; + u32 exdmawcr1; + u32 exdmawcr2; + u32 dummy1[9]; /* 0x5C .. 0x7C */ + u32 cspwcr0; + u32 cspwcr1; + u32 ecspwcr0; + u32 ecspwcr1; + u32 ecspwcr2; + u32 ecspwcr3; + u32 ecspwcr4; + u32 ecspwcr5; + u32 exwtsync; + u32 dummy2[3]; /* 0xA4 .. 0xAC */ + u32 cs0bstctl; + u32 cs0btph; + u32 dummy3[2]; /* 0xB8 .. 0xBC */ + u32 cs1gdst; + u32 ecs0gdst; + u32 ecs1gdst; + u32 ecs2gdst; + u32 ecs3gdst; + u32 ecs4gdst; + u32 ecs5gdst; + u32 dummy4[5]; /* 0xDC .. 0xEC */ + u32 exdmaset0; + u32 exdmaset1; + u32 exdmaset2; + u32 dummy5[5]; /* 0xFC .. 0x10C */ + u32 exdmcr0; + u32 exdmcr1; + u32 exdmcr2; + u32 dummy6[5]; /* 0x11C .. 0x12C */ + u32 bcintsr; + u32 bcintcr; + u32 bcintmr; + u32 dummy7; /* 0x13C */ + u32 exbatlv; + u32 exwtsts; + u32 dummy8[14]; /* 0x148 .. 0x17C */ + u32 atacsctrl; + u32 dummy9[15]; /* 0x184 .. 0x1BC */ + u32 exbct; + u32 extct; +}; + +/* DBSC3 */ +struct rcar_dbsc3 { + u32 dummy0[3]; /* 0x00 .. 0x08 */ + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2C */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3C */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4C */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xAC */ + u32 dbbl; + u32 dummy5[3]; /* 0xB4 .. 0xBC */ + u32 dbadj0; + u32 dummy6; /* 0xC4 */ + u32 dbadj2; + u32 dummy7[5]; /* 0xCC .. 0xDC */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dummy8[2]; /* 0xEC .. 0xF0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy9; /* 0xFC */ + u32 dbrnk0; + u32 dummy10[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy11[47]; /* 0x184 ..0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[14]; /* 0x248 .. 0x27C */ + u32 dbpdlck; + u32 dummy13[3]; /* 0x284 .. 0x28C */ + u32 dbpdrga; + u32 dummy14[3]; /* 0x294 .. 0x29C */ + u32 dbpdrgd; + u32 dummy15[24]; /* 0x2A4 .. 0x300 */ + u32 dbbs0cnt1; + u32 dummy16[30]; /* 0x308 .. 0x37C */ + u32 dbwt0cnf0; + u32 dbwt0cnf1; + u32 dbwt0cnf2; + u32 dbwt0cnf3; + u32 dbwt0cnf4; + u32 dummy17[27]; /* 0x394 .. 0x3FC */ + u32 dbeccmode; + u32 dummy18[3]; /* 0x404 .. 0x40C */ + u32 dbeccarea0; + u32 dbeccarea1; + u32 dbeccarea2; + u32 dbeccarea3; + u32 dummy19[4]; /* 0x420 .. 0x42C */ + u32 dbeccintenable; + u32 dbeccintdetect; + u32 dummy20[22]; /* 0x438 .. 0x48C */ + u32 dbeccmodulcnt; + u32 dummy21[27]; /* 0x494 .. 0x4FC */ + u32 dbschecnt0; + u32 dummy22[63]; /* 0x504 .. 0x5FC */ + u32 dbreradr0; + u32 dbreblane0; + u32 dbrerid0; + u32 dbrerinfo0; + u32 dbureradr0; + u32 dbureblane0; + u32 dburerid0; + u32 dburerinfo0; + u32 dbreradr1; + u32 dbreblane1; + u32 dbrerid1; + u32 dbrerinfo1; + u32 dbureradr1; + u32 dbureblane1; + u32 dburerid1; + u32 dburerinfo1; + u32 dbreradr2; + u32 dbreblane2; + u32 dbrerid2; + u32 dbrerinfo2; + u32 dbureradr2; + u32 dbureblane2; + u32 dburerid2; + u32 dburerinfo2; + u32 dbreradr3; + u32 dbreblane3; + u32 dbrerid3; + u32 dbrerinfo3; + u32 dbureradr3; + u32 dbureblane3; + u32 dburerid3; + u32 dburerinfo3; + u32 dummy23[160]; /* 0x680 .. 0x8FC */ + u32 dbpccr; + u32 dbpeier; + u32 dbpeisr; + u32 dummy24; + u32 dbwdpesr0; + u32 dbwspesr0; + u32 dbpwear0; + u32 dbpweid0; + u32 dbpweinfo0; + u32 dummy25[3]; /* 0x924 .. 0x92C */ + u32 dbwdpesr1; + u32 dbwspesr1; + u32 dbpwear1; + u32 dbpweid1; + u32 dbpweinfo1; + u32 dummy26[3]; /* 0x944 .. 0x94C */ + u32 dbwdpesr2; + u32 dbwspesr2; + u32 dbpwear2; + u32 dbpweid2; + u32 dbpweinfo2; + u32 dummy27[3]; /* 0x964 .. 0x96C */ + u32 dbwdpesr3; + u32 dbwspesr3; + u32 dbpwear3; + u32 dbpweid3; + u32 dbpweinfo3; +}; + +/* GPIO */ +struct rcar_gpio { + u32 iointsel; + u32 inoutsel; + u32 outdt; + u32 indt; + u32 intdt; + u32 intclr; + u32 intmsk; + u32 posneg; + u32 edglevel; + u32 filonoff; + u32 intmsks; + u32 mskclrs; + u32 outdtsel; + u32 outdth; + u32 outdtl; + u32 bothedge; +}; + +/* S3C(QoS) */ +struct rcar_s3c { + u32 s3cexcladdmsk; + u32 s3cexclidmsk; + u32 s3cadsplcr; + u32 s3cmaar; + u32 s3carcr11; + u32 s3crorr; + u32 s3cworr; + u32 s3carcr22; + u32 dummy1[2]; /* 0x20 .. 0x24 */ + u32 s3cmctr; + u32 dummy2; /* 0x2C */ + u32 cconf0; + u32 cconf1; + u32 cconf2; + u32 cconf3; +}; + +struct rcar_s3c_qos { + u32 s3cqos0; + u32 s3cqos1; + u32 s3cqos2; + u32 s3cqos3; + u32 s3cqos4; + u32 s3cqos5; + u32 s3cqos6; + u32 s3cqos7; + u32 s3cqos8; +}; + +/* DBSC(QoS) */ +struct rcar_dbsc3_qos { + u32 dblgcnt; + u32 dbtmval0; + u32 dbtmval1; + u32 dbtmval2; + u32 dbtmval3; + u32 dbrqctr; + u32 dbthres0; + u32 dbthres1; + u32 dbthres2; + u32 dummy0; /* 0x24 */ + u32 dblgqon; +}; + +/* MXI(QoS) */ +struct rcar_mxi { + u32 mxsaar0; + u32 mxsaar1; + u32 dummy0[7]; /* 0x08 .. 0x20 */ + u32 mxaxiracr; /* R8a7790 only */ + u32 mxs3cracr; + u32 dummy1[2]; /* 0x2C .. 0x30 */ + u32 mxaxiwacr; /* R8a7790 only */ + u32 mxs3cwacr; + u32 dummy2; /* 0x3C */ + u32 mxrtcr; + u32 mxwtcr; + u32 mxaxirtcr; /* R8a7792 only */ + u32 mxaxiwtcr; + u32 mxs3crtcr; + u32 mxs3cwtcr; +}; + +struct rcar_mxi_qos { + u32 vspdu0; + u32 vspdu1; + u32 du0; + u32 du1; +}; + +/* AXI(QoS) */ +struct rcar_axi_qos { + u32 qosconf; + u32 qosctset0; + u32 qosctset1; + u32 qosctset2; + u32 qosctset3; + u32 qosreqctr; + u32 qosthres0; + u32 qosthres1; + u32 qosthres2; + u32 qosqon; + u32 qosin; +}; + +#endif + +#endif /* __ASM_ARCH_RCAR_BASE_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h new file mode 100644 index 000000000..5cd8a8c78 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h + * + * Copyright (C) 2015 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H +#define __ASM_ARCH_RCAR_GEN3_BASE_H + +/* + * R-Car (R8A7750) I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xEE220200 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 + +/* SCIF */ +#define SCIF0_BASE 0xE6E60000 +#define SCIF1_BASE 0xE6E68000 +#define SCIF2_BASE 0xE6E88000 +#define SCIF3_BASE 0xE6C50000 +#define SCIF4_BASE 0xE6C40000 +#define SCIF5_BASE 0xE6F30000 + +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR6 0xE61501C0 +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR6 0xE6150128 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR6 0xE6150148 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + +/* PFC */ +#define PFC_PUEN5 0xE6060414 +#define PUEN_SSI_SDATA4 BIT(17) +#define PFC_PUEN6 0xE6060418 +#define PUEN_USB1_OVC (1 << 2) +#define PUEN_USB1_PWEN (1 << 1) + +/* IICDVFS (I2C) */ +#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <linux/bitops.h> + +/* RWDT */ +struct rcar_rwdt { + u32 rwtcnt; + u32 rwtcsra; + u32 rwtcsrb; +}; + +/* SWDT */ +struct rcar_swdt { + u32 swtcnt; + u32 swtcsra; + u32 swtcsrb; +}; +#endif + +#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-mstp.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-mstp.h new file mode 100644 index 000000000..f2f8ce959 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rcar-mstp.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/arch-rmobile/rcar-mstp.h + * + * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * Copyright (C) 2013, 2014 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_RCAR_MSTP_H +#define __ASM_ARCH_RCAR_MSTP_H + +#define mstp_setbits(type, addr, saddr, set) \ + out_##type((saddr), in_##type(addr) | (set)) +#define mstp_clrbits(type, addr, saddr, clear) \ + out_##type((saddr), in_##type(addr) & ~(clear)) +#define mstp_setclrbits(type, addr, set, clear) \ + out_##type((addr), (in_##type(addr) | (set)) & ~(clear)) +#define mstp_setbits_le32(addr, saddr, set) \ + mstp_setbits(le32, addr, saddr, set) +#define mstp_clrbits_le32(addr, saddr, clear) \ + mstp_clrbits(le32, addr, saddr, clear) +#define mstp_setclrbits_le32(addr, set, clear) \ + mstp_setclrbits(le32, addr, set, clear) + +#ifndef CONFIG_SMSTP0_ENA +#define CONFIG_SMSTP0_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP1_ENA +#define CONFIG_SMSTP1_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP2_ENA +#define CONFIG_SMSTP2_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP3_ENA +#define CONFIG_SMSTP3_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP4_ENA +#define CONFIG_SMSTP4_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP5_ENA +#define CONFIG_SMSTP5_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP6_ENA +#define CONFIG_SMSTP6_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP7_ENA +#define CONFIG_SMSTP7_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP8_ENA +#define CONFIG_SMSTP8_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP9_ENA +#define CONFIG_SMSTP9_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP10_ENA +#define CONFIG_SMSTP10_ENA 0x00 +#endif +#ifndef CONFIG_SMSTP11_ENA +#define CONFIG_SMSTP11_ENA 0x00 +#endif + +#ifndef CONFIG_RMSTP0_ENA +#define CONFIG_RMSTP0_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP1_ENA +#define CONFIG_RMSTP1_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP2_ENA +#define CONFIG_RMSTP2_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP3_ENA +#define CONFIG_RMSTP3_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP4_ENA +#define CONFIG_RMSTP4_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP5_ENA +#define CONFIG_RMSTP5_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP6_ENA +#define CONFIG_RMSTP6_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP7_ENA +#define CONFIG_RMSTP7_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP8_ENA +#define CONFIG_RMSTP8_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP9_ENA +#define CONFIG_RMSTP9_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP10_ENA +#define CONFIG_RMSTP10_ENA 0x00 +#endif +#ifndef CONFIG_RMSTP11_ENA +#define CONFIG_RMSTP11_ENA 0x00 +#endif + +struct mstp_ctl { + u32 s_addr; + u32 s_dis; + u32 s_ena; + u32 r_addr; + u32 r_dis; + u32 r_ena; +}; + +#endif /* __ASM_ARCH_RCAR_MSTP_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/rmobile.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rmobile.h new file mode 100644 index 000000000..a68863614 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -0,0 +1,50 @@ +#ifndef __ASM_ARCH_RMOBILE_H +#define __ASM_ARCH_RMOBILE_H + +#if defined(CONFIG_ARCH_RMOBILE) +#if defined(CONFIG_SH73A0) +#include <asm/arch/sh73a0.h> +#elif defined(CONFIG_R8A7740) +#include <asm/arch/r8a7740.h> +#elif defined(CONFIG_R8A7790) +#include <asm/arch/r8a7790.h> +#elif defined(CONFIG_R8A7791) +#include <asm/arch/r8a7791.h> +#elif defined(CONFIG_R8A7792) +#include <asm/arch/r8a7792.h> +#elif defined(CONFIG_R8A7793) +#include <asm/arch/r8a7793.h> +#elif defined(CONFIG_R8A7794) +#include <asm/arch/r8a7794.h> +#elif defined(CONFIG_RCAR_GEN3) +#include <asm/arch/rcar-gen3-base.h> +#elif defined(CONFIG_R7S72100) +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_ARCH_RMOBILE */ + +/* PRR CPU IDs */ +#define RMOBILE_CPU_TYPE_SH73A0 0x37 +#define RMOBILE_CPU_TYPE_R8A7740 0x40 +#define RMOBILE_CPU_TYPE_R8A7790 0x45 +#define RMOBILE_CPU_TYPE_R8A7791 0x47 +#define RMOBILE_CPU_TYPE_R8A7792 0x4A +#define RMOBILE_CPU_TYPE_R8A7793 0x4B +#define RMOBILE_CPU_TYPE_R8A7794 0x4C +#define RMOBILE_CPU_TYPE_R8A7795 0x4F +#define RMOBILE_CPU_TYPE_R8A7796 0x52 +#define RMOBILE_CPU_TYPE_R8A77965 0x55 +#define RMOBILE_CPU_TYPE_R8A77970 0x54 +#define RMOBILE_CPU_TYPE_R8A77980 0x56 +#define RMOBILE_CPU_TYPE_R8A77990 0x57 +#define RMOBILE_CPU_TYPE_R8A77995 0x58 + +#ifndef __ASSEMBLY__ +const u8 *rzg_get_cpu_name(void); +u32 rmobile_get_cpu_type(void); +u32 rmobile_get_cpu_rev_integer(void); +u32 rmobile_get_cpu_rev_fraction(void); +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h new file mode 100644 index 000000000..398e2c109 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h @@ -0,0 +1,553 @@ +#ifndef __ASM_SH73A0_H__ +#define __ASM_SH73A0_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function and MSEL switch + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* Hardware manual Table 25-1 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, + GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, + + GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, + + GPIO_PORT288, GPIO_PORT289, + + GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, + GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, + + GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, + GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, + + /* Table 25-1 (Function 0-7) */ + GPIO_FN_VBUS_0, + GPIO_FN_GPI0, + GPIO_FN_GPI1, + GPIO_FN_GPI2, + GPIO_FN_GPI3, + GPIO_FN_GPI4, + GPIO_FN_GPI5, + GPIO_FN_GPI6, + GPIO_FN_GPI7, + GPIO_FN_SCIFA7_RXD, + GPIO_FN_SCIFA7_CTS_, + GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, + GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, + GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ + GPIO_FN_PORT16_VIO_CKOR, + GPIO_FN_SCIFA0_TXD, + GPIO_FN_SCIFA7_TXD, + GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_GPO0, + GPIO_FN_GPO1, + GPIO_FN_GPO2, GPIO_FN_STATUS0, + GPIO_FN_GPO3, GPIO_FN_STATUS1, + GPIO_FN_GPO4, GPIO_FN_STATUS2, + GPIO_FN_VINT, + GPIO_FN_TCKON, + GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ + GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, + GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ + GPIO_FN_PORT28_TPU1TO1, + GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, + GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, + GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, + GPIO_FN_SCIFA4_TXD, + GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_SCIFA4_RTS_, + GPIO_FN_SCIFA4_CTS_, + GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, + GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIBISLD, + GPIO_FN_VACK, + GPIO_FN_XTAL1L, + GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, + GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, + GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, + GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, + GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, + GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ + GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + + GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, + GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ + GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, + GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ + GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, + GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, + GPIO_FN_A0, GPIO_FN_BS_, + GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, + GPIO_FN_A14, GPIO_FN_KEYOUT5, + GPIO_FN_A15, GPIO_FN_KEYOUT4, + GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_KEYIN6, + GPIO_FN_KEYIN7, + GPIO_FN_D0_NAF0, + GPIO_FN_D1_NAF1, + GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, + GPIO_FN_D4_NAF4, + GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, + GPIO_FN_D7_NAF7, + GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, + GPIO_FN_D10_NAF10, + GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, + GPIO_FN_D13_NAF13, + GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + GPIO_FN_CS4_, + GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, + GPIO_FN_CS5B_, GPIO_FN_FCE1_, + GPIO_FN_CS6B_, GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_CS6A_, + GPIO_FN_WAIT_, GPIO_FN_DREQ0, + GPIO_FN_RD__FSC, + GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, + GPIO_FN_WE1_, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT_, + GPIO_FN_NBRST_, + GPIO_FN_BBIF2_TXD, + GPIO_FN_BBIF2_RXD, + GPIO_FN_BBIF2_SYNC, + GPIO_FN_BBIF2_SCK, + GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, + GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_TXD, + GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, + GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, + GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ + GPIO_FN_PORT115_I2C_SCL3, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ + GPIO_FN_PORT116_I2C_SDA3, + GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, + GPIO_FN_HSI_TX_FLAG, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ + GPIO_FN_LCD2D0, + + GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ + GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ + GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ + GPIO_FN_LCD2D6, + GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_LCD2D7, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ + GPIO_FN_LCD2D2, + GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_LCD2D4, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ + GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, + GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ + GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, + GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, + GPIO_FN_VIO_CKO, + GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_PORT149_KEYOUT9, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, + GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, + GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, + GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ + GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_LCDD8, GPIO_FN_D16, + GPIO_FN_LCDD9, GPIO_FN_D17, + GPIO_FN_LCDD10, GPIO_FN_D18, + GPIO_FN_LCDD11, GPIO_FN_D19, + GPIO_FN_LCDD12, GPIO_FN_D20, + GPIO_FN_LCDD13, GPIO_FN_D21, + GPIO_FN_LCDD14, GPIO_FN_D22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_LCDD17, GPIO_FN_D25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, + GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ + GPIO_FN_PORT218_VIO_CKOR, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ + GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ + GPIO_FN_LCD2DCK_2, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ + GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ + GPIO_FN_PORT221_LCD2HSYN, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_LCD2D20, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ + GPIO_FN_LCD2D21, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ + GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, + GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ + GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ + GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_SDHICLK0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, + GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, + GPIO_FN_SDHID0_3, + GPIO_FN_SDHICMD0, + GPIO_FN_SDHIWP0, + GPIO_FN_SDHICLK1, + GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, + GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, + GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, + GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, + GPIO_FN_SDHICMD1, + GPIO_FN_SDHICLK2, + GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, + GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, + GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, + GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, + GPIO_FN_SDHICMD2, + GPIO_FN_MMCCLK0, + GPIO_FN_MMCD0_0, + GPIO_FN_MMCD0_1, + GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, + GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, + GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, + GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, + GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, + GPIO_FN_MMCCMD0, + GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, + GPIO_FN_MCP_WAIT__MCP_FRB, + GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, + GPIO_FN_MCP_D15_MCP_NAF15, + GPIO_FN_MCP_D14_MCP_NAF14, + GPIO_FN_MCP_D13_MCP_NAF13, + GPIO_FN_MCP_D12_MCP_NAF12, + GPIO_FN_MCP_D11_MCP_NAF11, + GPIO_FN_MCP_D10_MCP_NAF10, + GPIO_FN_MCP_D9_MCP_NAF9, + GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, + GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, + + GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, + GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, + GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, + GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, + GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, + GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, + GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, + GPIO_FN_MCP_NBRSTOUT_, + GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, + + /* MSEL2 special case */ + GPIO_FN_TSIF2_TS_XX1, + GPIO_FN_TSIF2_TS_XX2, + GPIO_FN_TSIF2_TS_XX3, + GPIO_FN_TSIF2_TS_XX4, + GPIO_FN_TSIF2_TS_XX5, + GPIO_FN_TSIF1_TS_XX1, + GPIO_FN_TSIF1_TS_XX2, + GPIO_FN_TSIF1_TS_XX3, + GPIO_FN_TSIF1_TS_XX4, + GPIO_FN_TSIF1_TS_XX5, + GPIO_FN_TSIF0_TS_XX1, + GPIO_FN_TSIF0_TS_XX2, + GPIO_FN_TSIF0_TS_XX3, + GPIO_FN_TSIF0_TS_XX4, + GPIO_FN_TSIF0_TS_XX5, + GPIO_FN_MST1_TS_XX1, + GPIO_FN_MST1_TS_XX2, + GPIO_FN_MST1_TS_XX3, + GPIO_FN_MST1_TS_XX4, + GPIO_FN_MST1_TS_XX5, + GPIO_FN_MST0_TS_XX1, + GPIO_FN_MST0_TS_XX2, + GPIO_FN_MST0_TS_XX3, + GPIO_FN_MST0_TS_XX4, + GPIO_FN_MST0_TS_XX5, + + /* MSEL3 special cases */ + GPIO_FN_SDHI0_VCCQ_MC0_ON, + GPIO_FN_SDHI0_VCCQ_MC0_OFF, + GPIO_FN_DEBUG_MON_VIO, + GPIO_FN_DEBUG_MON_LCDD, + GPIO_FN_LCDC_LCDC0, + GPIO_FN_LCDC_LCDC1, + + /* MSEL4 special cases */ + GPIO_FN_IRQ9_MEM_INT, + GPIO_FN_IRQ9_MCP_INT, + GPIO_FN_A11, + GPIO_FN_KEYOUT8, + GPIO_FN_TPU4TO3, + GPIO_FN_RESETA_N_PU_ON, + GPIO_FN_RESETA_N_PU_OFF, + GPIO_FN_EDBGREQ_PD, + GPIO_FN_EDBGREQ_PU, + + /* Functions with pull-ups */ + GPIO_FN_KEYIN0_PU, + GPIO_FN_KEYIN1_PU, + GPIO_FN_KEYIN2_PU, + GPIO_FN_KEYIN3_PU, + GPIO_FN_KEYIN4_PU, + GPIO_FN_KEYIN5_PU, + GPIO_FN_KEYIN6_PU, + GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHICD0_PU, + GPIO_FN_SDHID0_0_PU, + GPIO_FN_SDHID0_1_PU, + GPIO_FN_SDHID0_2_PU, + GPIO_FN_SDHID0_3_PU, + GPIO_FN_SDHICMD0_PU, + GPIO_FN_SDHIWP0_PU, + GPIO_FN_SDHID1_0_PU, + GPIO_FN_SDHID1_1_PU, + GPIO_FN_SDHID1_2_PU, + GPIO_FN_SDHID1_3_PU, + GPIO_FN_SDHICMD1_PU, + GPIO_FN_SDHID2_0_PU, + GPIO_FN_SDHID2_1_PU, + GPIO_FN_SDHID2_2_PU, + GPIO_FN_SDHID2_3_PU, + GPIO_FN_SDHICMD2_PU, + GPIO_FN_MMCCMD0_PU, + GPIO_FN_MMCCMD1_PU, + GPIO_FN_MMCD0_0_PU, + GPIO_FN_MMCD0_1_PU, + GPIO_FN_MMCD0_2_PU, + GPIO_FN_MMCD0_3_PU, + GPIO_FN_MMCD0_4_PU, + GPIO_FN_MMCD0_5_PU, + GPIO_FN_MMCD0_6_PU, + GPIO_FN_MMCD0_7_PU, + GPIO_FN_FSIACK_PU, + GPIO_FN_FSIAILR_PU, + GPIO_FN_FSIAIBT_PU, + GPIO_FN_FSIAISLD_PU, + + /* end of GPIO */ + GPIO_NR, +}; + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_SCIF7_TX, + SHDMA_SLAVE_SCIF7_RX, + SHDMA_SLAVE_SCIF8_TX, + SHDMA_SLAVE_SCIF8_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, +}; + +/* + * SH73A0 IRQ LOCATION TABLE + * + * 416 ----------------------------------------- + * IRQ0-IRQ15 + * 431 ----------------------------------------- + * ... + * 448 ----------------------------------------- + * sh73a0-intcs + * sh73a0-intca-irq-pins + * 680 ----------------------------------------- + * ... + * 700 ----------------------------------------- + * sh73a0-pint0 + * 731 ----------------------------------------- + * 732 ----------------------------------------- + * sh73a0-pint1 + * 739 ----------------------------------------- + * ... + * 800 ----------------------------------------- + * IRQ16-IRQ31 + * 815 ----------------------------------------- + * ... + * 928 ----------------------------------------- + * sh73a0-intca-irq-pins + * 943 ----------------------------------------- + */ + +/* PINT interrupts are located at Linux IRQ 700 and up */ +#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) +#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) + +#endif /* __ASM_SH73A0_H__ */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh73a0.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh73a0.h new file mode 100644 index 000000000..bdbb40864 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh73a0.h @@ -0,0 +1,289 @@ +#ifndef __ASM_ARCH_RMOBILE_SH73A0_H +#define __ASM_ARCH_RMOBILE_SH73A0_H + +/* Global Timer */ +#define GLOBAL_TIMER_BASE_ADDR (0xF0000200) +#define MERAM_BASE (0xE5580000) + +/* GIC */ +#define GIC_BASE (0xF0000100) +#define ICCICR GIC_BASE + +/* Secure control register */ +#define LIFEC_SEC_SRC (0xE6110008) + +/* RWDT */ +#define RWDT_BASE (0xE6020000) + +/* HPB Semaphore Control Registers */ +#define HPB_BASE (0xE6001010) + +/* Bus Semaphore Control Registers */ +#define HPBSCR_BASE (0xE6001600) + +/* SBSC1 */ +#define SBSC1_BASE (0xFE400000) +#define SDMRA1A (SBSC1_BASE + 0x100000) +#define SDMRA2A (SBSC1_BASE + 0x1C0000) +#define SDMRA3A (SBSC1_BASE + 0x104000) + +/* SBSC2 */ +#define SBSC2_BASE (0xFB400000) +#define SDMRA1B (SBSC2_BASE + 0x100000) +#define SDMRA2B (SBSC2_BASE + 0x1C0000) +#define SDMRA3B (SBSC2_BASE + 0x104000) + +/* CPG */ +#define CPG_BASE (0xE6150000) +#define CPG_SRCR_BASE (CPG_BASE + 0x80A0) +#define WUPCR (CPG_BASE + 0x1010) +#define SRESCR (CPG_BASE + 0x1018) +#define PCLKCR (CPG_BASE + 0x1020) + +/* SYSC */ +#define SYSC_BASE (0xE6180000) +#define RESCNT2 (SYSC_BASE + 0x8020) + +/* BSC */ +#define BSC_BASE (0xFEC10000) + +/* SCIF */ +#define SCIF0_BASE (0xE6C40000) +#define SCIF1_BASE (0xE6C50000) +#define SCIF2_BASE (0xE6C60000) +#define SCIF3_BASE (0xE6C70000) +#define SCIF4_BASE (0xE6C80000) +#define SCIF5_BASE (0xE6CB0000) +#define SCIF6_BASE (0xE6CC0000) +#define SCIF7_BASE (0xE6CD0000) + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct sh73a0_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 dummy0; /* 0x02 */ + u16 rwtcsra0; /* 0x04 */ + u16 dummy1; /* 0x06 */ + u16 rwtcsrb0; /* 0x08 */ +}; + +/* HPB Semaphore Control Registers */ +struct sh73a0_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; + u32 dummy1; /* 0x2C */ + u32 hpbctrl6; +}; + +/* Bus Semaphore Control Registers */ +struct sh73a0_hpb_bscr { + u32 mpsrc; /* 0x00 */ + u32 mpacctl; /* 0x04 */ + u32 dummy0[6]; + u32 smgpiosrc; /* 0x20 */ + u32 smgpioerr; + u32 smgpiotime; + u32 smgpiocnt; + u32 dummy1[4]; /* 0x30 .. 0x3C */ + u32 smcmt2src; + u32 smcmt2err; + u32 smcmt2time; + u32 smcmt2cnt; + u32 smcpgsrc; + u32 smcpgerr; + u32 smcpgtime; + u32 smcpgcnt; + u32 dummy2[4]; /* 0x60 - 0x6C */ + u32 smsyscsrc; + u32 smsyscerr; + u32 smsysctime; + u32 smsysccnt; +}; + +/* SBSC */ +struct sh73a0_sbsc { + u32 dummy0[2]; /* 0x00, 0x04 */ + u32 sdcr0; + u32 sdcr1; + u32 sdpcr; + u32 dummy1; /* 0x14 */ + u32 sdcr0s; + u32 sdcr1s; + u32 rtcsr; + u32 dummy2; /* 0x24 */ + u32 rtcor; + u32 rtcorh; + u32 rtcors; + u32 rtcorsh; + u32 dummy3[2]; /* 0x38, 0x3C */ + u32 sdwcrc0; + u32 sdwcrc1; + u32 sdwcr00; + u32 sdwcr01; + u32 sdwcr10; + u32 sdwcr11; + u32 sdpdcr0; + u32 dummy4; /* 0x5C */ + u32 sdwcr2; + u32 sdwcrc2; + u32 zqccr; + u32 dummy5[6]; /* 0x6C .. 0x80 */ + u32 sdmracr0; + u32 dummy6; /* 0x88 */ + u32 sdmrtmpcr; + u32 dummy7; /* 0x90 */ + u32 sdmrtmpmsk; + u32 dummy8; /* 0x98 */ + u32 sdgencnt; + u32 dphycnt0; + u32 dphycnt1; + u32 dphycnt2; + u32 dummy9[2]; /* 0xAC .. 0xB0 */ + u32 sddrvcr0; + u32 dummy10[14]; /* 0xB8 .. 0xEC */ + u32 dptdivcr0; + u32 dptdivcr1; + u32 dptdivcr2; + u32 dummy11; /* 0xFC */ + u32 sdptcr0; + u32 sdptcr1; + u32 sdptcr2; + u32 sdptcr3; /* 0x10C */ + u32 dummy12[145]; /* 0x110 .. 0x350 */ + u32 dllcnt0; /* 0x354 */ + u32 sbscmon0; +}; + +/* CPG */ +struct sh73a0_sbsc_cpg { + u32 frqcra; /* 0x00 */ + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 zbckcr; + u32 flckcr; + u32 fsiackcr; + u32 vclkcr3; + u32 rtstbcr; + u32 systbcr; + u32 pll1cr; + u32 pll2cr; + u32 mstpsr0; + u32 dummy0; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy1; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy2; /* 0x50 */ + u32 astat; + u32 dvfscr0; + u32 dvfscr1; + u32 dsitckcr; + u32 dsi0pckcr; + u32 dsi1pckcr; + u32 dsi0phycr; + u32 dsi1phycr; + u32 sd0ckcr; + u32 sd1ckcr; + u32 sd2ckcr; + u32 subckcr; + u32 spuackcr; + u32 msuckcr; + u32 hsickcr; + u32 fsibckcr; + u32 spuvckcr; + u32 mfck1cr; + u32 mfck2cr; + u32 dummy3[8]; /* 0xA0 .. 0xBC */ + u32 ckscr; + u32 dummy4; /* 0xC4 */ + u32 pll1stpcr; + u32 mpmode; + u32 pllecr; + u32 dummy5; /* 0xD4 */ + u32 pll0cr; + u32 pll3cr; + u32 dummy6; /* 0xE0 */ + u32 frqcrd; + u32 dummyi7; /* 0xE8 */ + u32 vrefcr; + u32 pll0stpcr; + u32 dummy8; /* 0xF4 */ + u32 pll2stpcr; + u32 pll3stpcr; + u32 dummy9[4]; /* 0x100 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy10[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; + u32 dummy11[2]; /* 0x148 .. 0x14c */ + u32 cpgxxcs4; + u32 dummy12[7]; /* 0x154 .. 0x16c */ + u32 dvfscr2; + u32 dvfscr3; + u32 dvfscr4; + u32 dvfscr5; /* 0x17C */ +}; + +/* CPG SRCR part OK */ +struct sh73a0_sbsc_cpg_srcr { + u32 srcr0; + u32 dummy0; /* 0xA4 */ + u32 srcr1; + u32 dummy1; /* 0xAC */ + u32 srcr2; + u32 dummy2; /* 0xB4 */ + u32 srcr3; + u32 srcr4; + u32 dummy3; /* 0xC0 */ + u32 srcr5; +}; + +/* BSC */ +struct sh73a0_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0C */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 cs6bbcr; + u32 cs0wcr; + u32 cs2wcr; + u32 dummy1; /* 0x2C */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 cs6bwcr; + u32 rbwtcnt; + u32 busycr; + u32 dummy2; /* 0x5c */ + u32 cs7abcr; + u32 cs7awcr; + u32 dummy3[2]; /* 0x68, 0x6C */ + u32 bromtimcr; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh_sdhi.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh_sdhi.h new file mode 100644 index 000000000..7741718be --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sh_sdhi.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * drivers/mmc/sh-sdhi.h + * + * SD/MMC driver for Renesas rmobile ARM SoCs + * + * Copyright (C) 2013-2017 Renesas Electronics Corporation + * Copyright (C) 2008-2009 Renesas Solutions Corp. + */ + +#ifndef _SH_SDHI_H +#define _SH_SDHI_H + +#include <linux/bitops.h> +#define SDHI_CMD (0x0000 >> 1) +#define SDHI_PORTSEL (0x0004 >> 1) +#define SDHI_ARG0 (0x0008 >> 1) +#define SDHI_ARG1 (0x000C >> 1) +#define SDHI_STOP (0x0010 >> 1) +#define SDHI_SECCNT (0x0014 >> 1) +#define SDHI_RSP00 (0x0018 >> 1) +#define SDHI_RSP01 (0x001C >> 1) +#define SDHI_RSP02 (0x0020 >> 1) +#define SDHI_RSP03 (0x0024 >> 1) +#define SDHI_RSP04 (0x0028 >> 1) +#define SDHI_RSP05 (0x002C >> 1) +#define SDHI_RSP06 (0x0030 >> 1) +#define SDHI_RSP07 (0x0034 >> 1) +#define SDHI_INFO1 (0x0038 >> 1) +#define SDHI_INFO2 (0x003C >> 1) +#define SDHI_INFO1_MASK (0x0040 >> 1) +#define SDHI_INFO2_MASK (0x0044 >> 1) +#define SDHI_CLK_CTRL (0x0048 >> 1) +#define SDHI_SIZE (0x004C >> 1) +#define SDHI_OPTION (0x0050 >> 1) +#define SDHI_ERR_STS1 (0x0058 >> 1) +#define SDHI_ERR_STS2 (0x005C >> 1) +#define SDHI_BUF0 (0x0060 >> 1) +#define SDHI_SDIO_MODE (0x0068 >> 1) +#define SDHI_SDIO_INFO1 (0x006C >> 1) +#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1) +#define SDHI_CC_EXT_MODE (0x01B0 >> 1) +#define SDHI_SOFT_RST (0x01C0 >> 1) +#define SDHI_VERSION (0x01C4 >> 1) +#define SDHI_HOST_MODE (0x01C8 >> 1) +#define SDHI_SDIF_MODE (0x01CC >> 1) +#define SDHI_EXT_SWAP (0x01E0 >> 1) +#define SDHI_SD_DMACR (0x0324 >> 1) + +/* SDHI CMD VALUE */ +#define CMD_MASK 0x0000ffff + +/* SDHI_PORTSEL */ +#define USE_1PORT (1 << 8) /* 1 port */ + +/* SDHI_ARG */ +#define ARG0_MASK 0x0000ffff +#define ARG1_MASK 0x0000ffff + +/* SDHI_STOP */ +#define STOP_SEC_ENABLE (1 << 8) + +/* SDHI_INFO1 */ +#define INFO1_RESP_END (1 << 0) +#define INFO1_ACCESS_END (1 << 2) +#define INFO1_CARD_RE (1 << 3) +#define INFO1_CARD_IN (1 << 4) +#define INFO1_ISD0CD (1 << 5) +#define INFO1_WRITE_PRO (1 << 7) +#define INFO1_DATA3_CARD_RE (1 << 8) +#define INFO1_DATA3_CARD_IN (1 << 9) +#define INFO1_DATA3 (1 << 10) + +/* SDHI_INFO2 */ +#define INFO2_CMD_ERROR (1 << 0) +#define INFO2_CRC_ERROR (1 << 1) +#define INFO2_END_ERROR (1 << 2) +#define INFO2_TIMEOUT (1 << 3) +#define INFO2_BUF_ILL_WRITE (1 << 4) +#define INFO2_BUF_ILL_READ (1 << 5) +#define INFO2_RESP_TIMEOUT (1 << 6) +#define INFO2_SDDAT0 (1 << 7) +#define INFO2_BRE_ENABLE (1 << 8) +#define INFO2_BWE_ENABLE (1 << 9) +#define INFO2_CBUSY (1 << 14) +#define INFO2_ILA (1 << 15) +#define INFO2_ALL_ERR (0x807f) + +/* SDHI_INFO1_MASK */ +#define INFO1M_RESP_END (1 << 0) +#define INFO1M_ACCESS_END (1 << 2) +#define INFO1M_CARD_RE (1 << 3) +#define INFO1M_CARD_IN (1 << 4) +#define INFO1M_DATA3_CARD_RE (1 << 8) +#define INFO1M_DATA3_CARD_IN (1 << 9) +#define INFO1M_ALL (0xffff) +#define INFO1M_SET (INFO1M_RESP_END | \ + INFO1M_ACCESS_END | \ + INFO1M_DATA3_CARD_RE | \ + INFO1M_DATA3_CARD_IN) + +/* SDHI_INFO2_MASK */ +#define INFO2M_CMD_ERROR (1 << 0) +#define INFO2M_CRC_ERROR (1 << 1) +#define INFO2M_END_ERROR (1 << 2) +#define INFO2M_TIMEOUT (1 << 3) +#define INFO2M_BUF_ILL_WRITE (1 << 4) +#define INFO2M_BUF_ILL_READ (1 << 5) +#define INFO2M_RESP_TIMEOUT (1 << 6) +#define INFO2M_BRE_ENABLE (1 << 8) +#define INFO2M_BWE_ENABLE (1 << 9) +#define INFO2M_ILA (1 << 15) +#define INFO2M_ALL (0xffff) +#define INFO2M_ALL_ERR (0x807f) + +/* SDHI_CLK_CTRL */ +#define CLK_ENABLE (1 << 8) + +/* SDHI_OPTION */ +#define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */ +#define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */ +#define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */ +#define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */ + +/* SDHI_ERR_STS1 */ +#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \ + (1 << 8) | (1 << 5)) +#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \ + (1 << 1) | (1 << 0)) + +/* SDHI_ERR_STS2 */ +#define ERR_STS2_RES_TIMEOUT (1 << 0) +#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1)) +#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \ + (1 << 3) | (1 << 2) | (1 << 1) | \ + (1 << 0)) + +/* SDHI_SDIO_MODE */ +#define SDIO_MODE_ON (1 << 0) +#define SDIO_MODE_OFF (0 << 0) + +/* SDHI_SDIO_INFO1 */ +#define SDIO_INFO1_IOIRQ (1 << 0) +#define SDIO_INFO1_EXPUB52 (1 << 14) +#define SDIO_INFO1_EXWT (1 << 15) + +/* SDHI_SDIO_INFO1_MASK */ +#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2)) +#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \ + (1 << 1) | (1 << 0)) + +/* SDHI_EXT_SWAP */ +#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */ + +/* SDHI_SOFT_RST */ +#define SOFT_RST_ON (0 << 0) +#define SOFT_RST_OFF (1 << 0) + +#define CLKDEV_SD_DATA 25000000 /* 25 MHz */ +#define CLKDEV_HS_DATA 50000000 /* 50 MHz */ +#define CLKDEV_MMC_DATA 20000000 /* 20MHz */ +#define CLKDEV_INIT 400000 /* 100 - 400 KHz */ + +/* For quirk */ +#define SH_SDHI_QUIRK_16BIT_BUF BIT(0) +#define SH_SDHI_QUIRK_64BIT_BUF BIT(1) + +int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks); + +#endif /* _SH_SDHI_H */ diff --git a/roms/u-boot/arch/arm/mach-rmobile/include/mach/sys_proto.h b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sys_proto.h new file mode 100644 index 000000000..ec8036a35 --- /dev/null +++ b/roms/u-boot/arch/arm/mach-rmobile/include/mach/sys_proto.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#endif |