5 files changed, 281 insertions, 0 deletions
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3188/Kconfig b/roms/u-boot/arch/arm/mach-rockchip/rk3188/Kconfig
new file mode 100644
index 000000000..e24e68ea5
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -0,0 +1,38 @@
+if ROCKCHIP_RK3188
+
+config TARGET_ROCK
+	bool "Radxa Rock"
+	help
+	  Rock is a RK3188-based development board with 2 USB and 1 otg
+	  ports, HDMI, TV-out, micro-SD card, audio, WiFi  and 100MBit
+	  Ethernet, It also includes on-board nand and 1GB of SDRAM.
+	  Expansion connectors provide access to display pins, I2C, SPI,
+	  UART and GPIOs.
+
+config ROCKCHIP_BOOT_MODE_REG
+	default 0x20004040
+
+config SYS_SOC
+	default "rk3188"
+
+config SYS_MALLOC_F_LEN
+	default 0x0800
+
+config SPL_LIBCOMMON_SUPPORT
+	default y
+
+config SPL_LIBGENERIC_SUPPORT
+	default y
+
+config SPL_SERIAL_SUPPORT
+	default y
+
+config TPL_LIBCOMMON_SUPPORT
+	default y
+
+config TPL_LIBGENERIC_SUPPORT
+	default y
+
+source "board/radxa/rock/Kconfig"
+
+endif
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3188/Makefile b/roms/u-boot/arch/arm/mach-rockchip/rk3188/Makefile
new file mode 100644
index 000000000..7dc123a3d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3188/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2015 Google, Inc
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifndef CONFIG_TPL_BUILD
+obj-y += clk_rk3188.o
+obj-y += rk3188.o
+obj-y += syscon_rk3188.o
+endif
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/roms/u-boot/arch/arm/mach-rockchip/rk3188/clk_rk3188.c
new file mode 100644
index 000000000..94d1d23e1
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3188/clk_rk3188.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3188.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_DRIVER_GET(rockchip_rk3188_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3188_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3188/rk3188.c b/roms/u-boot/arch/arm/mach-rockchip/rk3188/rk3188.c
new file mode 100644
index 000000000..ad8c6cd1d
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+#include <common.h>
+#include <dm.h>
+#include <hang.h>
+#include <init.h>
+#include <led.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/err.h>
+
+#define GRF_BASE	0x20008000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
+};
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	/* Enable early UART on the RK3188 */
+	struct rk3188_grf * const grf = (void *)GRF_BASE;
+	enum {
+		GPIO1B1_SHIFT		= 2,
+		GPIO1B1_MASK		= 3,
+		GPIO1B1_GPIO		= 0,
+		GPIO1B1_UART2_SOUT,
+		GPIO1B1_JTAG_TDO,
+
+		GPIO1B0_SHIFT		= 0,
+		GPIO1B0_MASK		= 3,
+		GPIO1B0_GPIO		= 0,
+		GPIO1B0_UART2_SIN,
+		GPIO1B0_JTAG_TDI,
+	};
+
+	rk_clrsetreg(&grf->gpio1b_iomux,
+		     GPIO1B1_MASK << GPIO1B1_SHIFT |
+		     GPIO1B0_MASK << GPIO1B0_SHIFT,
+		     GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
+		     GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+int arch_cpu_init(void)
+{
+	struct rk3188_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(grf)) {
+		pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
+		return 0;
+	}
+#ifdef CONFIG_ROCKCHIP_USB_UART
+	rk_clrsetreg(&grf->uoc0_con[0],
+		     SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
+		     1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
+		     1 << COMMON_ON_N_SHIFT);
+	rk_clrsetreg(&grf->uoc0_con[2],
+		     SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
+	rk_clrsetreg(&grf->uoc0_con[3],
+		     OPMODE_MASK | XCVRSELECT_MASK |
+		     TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
+		     OPMODE_NODRIVING << OPMODE_SHIFT |
+		     XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
+		     1 << TERMSEL_FULLSPEED_SHIFT |
+		     1 << SUSPENDN_SHIFT);
+	rk_clrsetreg(&grf->uoc0_con[0],
+		     BYPASSSEL_MASK | BYPASSDMEN_MASK,
+		     1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
+#endif
+	return 0;
+}
+#endif
+
+__weak int rk3188_board_late_init(void)
+{
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	struct rk3188_grf *grf;
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (IS_ERR(grf)) {
+		pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
+		return 0;
+	}
+
+	/* enable noc remap to mimic legacy loaders */
+	rk_clrsetreg(&grf->soc_con0,
+		     NOC_REMAP_MASK << NOC_REMAP_SHIFT,
+		     NOC_REMAP_MASK << NOC_REMAP_SHIFT);
+
+	return rk3188_board_late_init();
+}
+
+#ifdef CONFIG_SPL_BUILD
+DECLARE_GLOBAL_DATA_PTR;
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+	struct udevice *dev;
+	char *led_name;
+	int ret;
+
+	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+	if (!led_name)
+		return 0;
+	ret = led_get_by_label(led_name, &dev);
+	if (ret) {
+		debug("%s: get=%d\n", __func__, ret);
+		return ret;
+	}
+	ret = led_set_state(dev, LEDST_ON);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = setup_led();
+	if (ret) {
+		debug("LED ret=%d\n", ret);
+		hang();
+	}
+}
+#endif
diff --git a/roms/u-boot/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/roms/u-boot/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
new file mode 100644
index 000000000..917ff37c0
--- /dev/null
+++ b/roms/u-boot/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3188_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
+	{ .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3188-pmu", .data = ROCKCHIP_SYSCON_PMU },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3188) = {
+	.name = "rk3188_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3188_syscon_bind_of_plat(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3188_noc) = {
+	.name = "rockchip_rk3188_noc",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids,
+	.bind = rk3188_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3188_grf) = {
+	.name = "rockchip_rk3188_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids + 1,
+	.bind = rk3188_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
+	.name = "rockchip_rk3188_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids + 2,
+	.bind = rk3188_syscon_bind_of_plat,
+};
+#endif